Wafer reliability test system

Abstract

The wafer reliability test system provided by the application relates to the field of semiconductors. The wafer reliability test system comprises a test board, a controller and a test circuit are arranged on the test board, the test circuit comprises at least one of a dynamic high-temperature gate bias test circuit and a static high-temperature reverse bias test circuit; a probe card, a plurality of probes are arranged on the probe card away from the lower surface of the test board, and the probes are used for being connected with electrodes of transistors on a wafer, the probe card is further provided with a plurality of first conductive through holes penetrating through the upper and lower surfaces of the probe card, and the test circuit on the test board is electrically connected with the probes on the probe card through the plurality of first conductive through holes; a wafer tray is arranged on the side of the wafer away from the probe card to support the wafer; and a heater is arranged on the side of the wafer tray away from the wafer to provide a high-temperature test environment for the wafer through the wafer tray. The technical solution provided by the application can reduce the production cost of electronic devices.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, specifically to a wafer reliability testing system. Background Technology

[0002] With the development of electronic technology, the requirements for electronic devices (such as transistors or integrated circuits) that form the cornerstone of electronic technology are becoming increasingly stringent. High-speed, broadband, and high-reliability devices have become the focus of research.

[0003] In existing technologies, to improve the reliability of electronic devices, chips are typically packaged in encapsulation (such as plastic or metal casings). After encapsulation, reliability testing is required to screen out defective devices and improve overall reliability. However, with increasing demands for data rate and bandwidth in electronic devices, the industry has proposed using semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) to fabricate chips. However, the processes for fabricating chips using SiC and GaN are not yet mature enough, resulting in unstable chip performance and typically high failure rates. Therefore, testing and screening chips made from novel materials like SiC or GaN after encapsulation leads to wasted packaging space and higher costs. Thus, how to effectively test chips made from materials such as SiC and GaN while reducing costs has become a problem that needs to be solved. Summary of the Invention

[0004] The wafer reliability testing system provided in this application completes chip testing and screening before chip packaging, which can reduce the production cost of electronic devices.

[0005] In a first aspect, embodiments of this application provide a wafer reliability testing system, comprising: a test board, on which a controller and a test circuit are disposed, the test circuit including at least one of a dynamic high-temperature gate bias test circuit and a static high-temperature reverse bias test circuit; a probe card, on the lower surface of the probe card away from the test board, having a plurality of probes disposed for connection to electrodes of transistors on the wafer, the probe card also having a plurality of first conductive vias, the test circuit on the test board being electrically connected to the plurality of probes on the probe card through the plurality of first conductive vias; a wafer tray, disposed on the side of the wafer away from the probe card, for supporting the wafer; and a heater, disposed on the side of the wafer tray away from the wafer, for providing a high-temperature testing environment to the wafer through the wafer tray.

[0006] The wafer reliability testing system provided in this application embodiment, by setting up multiple test boards, probe cards, wafer trays and heaters, can perform wafer-level chip reliability testing before chip packaging, so as to screen out qualified chips before chip packaging, eliminating the need for further packaging of failed chips, thereby reducing packaging costs and thus reducing the production cost of electronic devices.

[0007] In one possible implementation, the wafer reliability testing system further includes an adapter board, a first insulating layer, and a second insulating layer. The adapter board is disposed between the test board and the probe card, and has multiple second conductive vias. The test circuit on the test board is electrically connected to multiple probes on the probe card through the multiple second conductive vias and the multiple first conductive vias. The first insulating layer is disposed between the wafer tray and the heater, and the first insulating layer is an insulating and thermally conductive material. The second insulating layer is disposed on the side of the heater away from the wafer tray to isolate the wafer reliability testing system from the external environment.

[0008] In one possible implementation, the reliability testing system further includes a wafer; the wafer includes multiple transistors, with gates and sources of the multiple transistors disposed on the upper surface of the wafer, and drains disposed on the lower surface of the wafer; the gates and sources of the multiple transistors are connected to multiple probes one-to-one; the drains are connected to a wafer tray and to a probe card through the wafer tray, wherein the wafer tray is conductive.

[0009] In one possible implementation, the test circuit includes a dynamic high-temperature gate bias test circuit, which includes a first test module, a first protection module, and a voltage conversion module. The first protection module is connected to the voltage conversion module to protect the voltage conversion module and the transistors on the wafer. The voltage conversion module is connected between the controller and the first test module and is used to convert the voltage transmitted from the first power supply terminal based on the control signal transmitted by the controller, and to input the voltage-converted signal to the first test module. The first test module includes multiple switches, which, based on the control of the controller, connect the test terminals of the transistors under test on the wafer to the voltage conversion module or to the controller.

[0010] In one possible implementation, the voltage conversion module includes a first transistor and a second transistor; the gate of the first transistor and the gate of the second transistor are connected to the control signal output terminal of the controller; the drain of the first transistor is connected to a first protection module, the source of the first transistor is connected to the drain of the second transistor to form a node, and the source of the second transistor is connected to a second power supply terminal.

[0011] In one possible implementation, the first test module includes a first switch, a second switch, a third switch, a fourth switch, and a signal source measurement unit. The first and second switches are single-pole double-throw switches. The first switch, based on controller control, selectively connects the gate of the transistor under test to a node or to the signal source measurement unit. The second switch, based on controller control, selectively connects the source of the transistor under test to a first common ground or to a second common ground, where the first common ground is the same ground terminal as the controller, and the second common ground is the same ground terminal as the first protection module. The third switch selectively connects or disconnects the gate and drain of the transistor under test. The fourth switch selectively connects or disconnects the source and drain of the transistor under test. The output of the signal source measurement unit is connected to the controller to output the counting result to the controller.

[0012] In one possible implementation, the first protection module includes a first fuse, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and a first operational amplifier; the drain of the first transistor is connected to a first terminal of the first resistor, the second terminal of the first resistor is connected to a first terminal of the first fuse, and the second terminal of the first fuse is connected to a first power supply terminal; the non-inverting input terminal of the first operational amplifier is connected to the drain of the first transistor through the second resistor, and the non-inverting input terminal of the first operational amplifier is connected to a first common ground through the third resistor; the inverting input terminal of the first operational amplifier is connected to the first terminal of the first fuse through the fourth resistor; the inverting input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier through the fifth resistor; and the drain of the first transistor is connected to a second power supply terminal through the sixth and seventh resistors.

[0013] In one possible implementation, the static high-temperature reverse bias test circuit includes a second test module, a second protection module, a current conversion module, and a fifth switch; the second test module is connected to the transistor under test on the wafer, and the fifth switch, based on the control of the driver, selectively connects the second test module to the current conversion module or to the common ground of the static high-temperature reverse bias test circuit; the second protection module is located between the second test module and the common ground.

[0014] In one possible implementation, the second test module includes a second resistance wire and a voltage source. The second resistance wire is disposed between the first power supply terminal and the source of the transistor under test. The negative terminal of the voltage source is connected to the gate of the transistor under test, and the positive terminal of the voltage source is connected to the drain of the transistor under test.

[0015] In one possible implementation, the static high-temperature reverse bias test circuit further includes a reading sampling circuit. The input terminal of the reading sampling circuit is connected to the fifth switch and the common ground, and the output terminal of the reading sampling circuit is connected to the controller. The reading sampling circuit is used to: collect the drain current of the transistor under test when the second test module is connected to the current conversion module, and transmit the collected drain current to the controller. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of the wafer reliability testing system 100 provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of the wafer reliability testing system 200 provided in an embodiment of this application; Figure 3 This is a schematic diagram of the dynamic high-temperature gate bias test circuit 300 provided in an embodiment of this application; Figure 4 The embodiments provided in this application are as follows Figure 3 A schematic diagram of a specific circuit structure of the dynamic high-temperature gate bias test circuit 300 is shown. Figures 5A-5C The embodiments provided in this application are as follows Figure 4 The diagram shows the working structure of the dynamic high-temperature gate bias test circuit 300. Figure 6 This is a schematic diagram of a static high-temperature reverse bias test circuit 400 provided in an embodiment of this application; Figure 7 The embodiments provided in this application are as follows Figure 6 The diagram shows a specific circuit structure of the static high-temperature reverse bias test circuit 400. Detailed Implementation

[0017] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0018] In the description of the embodiments of this application, the words "for example" or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design that is described as "for example" or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design options. Rather, the use of the words "for example" or "for instance" is intended to present the relevant concepts in a specific manner.

[0019] In the description of the embodiments of this application, the term "multiple" means two or more. For example, multiple transducers means two or more transducers. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0020] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of the wafer reliability testing system 100 provided in an embodiment of this application. Figure 1 As shown, the wafer reliability testing system 100 includes a test board 1, a test board n, a probe card 20, a wafer tray 30, and a heater 40. When the wafer reliability testing system 100 is used to test a wafer, the wafer is placed between the probe card 20 and the wafer tray 30. The test board is electrically connected to the wafer through the probe card 20.

[0021] In this embodiment of the application, the wafer reliability testing system 100 may include multiple test boards, for example, n, where n is an integer greater than or equal to 2. Figure 1 The diagram schematically illustrates two test boards, 1 and n. This application embodiment does not specifically limit the number of test boards; it can be set according to the needs of the application scenario. For example, the number of test boards can be the same as the number of chips on the wafer, with a one-to-one correspondence between the test boards and the chips on the wafer, and one test board used to test one chip. Alternatively, the number of test boards can be less than the number of chips on the wafer, and one test board can test multiple chips.

[0022] Each test board is equipped with a controller and test circuitry. The controller may include, but is not limited to, various control devices such as PLCs (Programmable Logic Controllers), FPGAs (Field-Programmable Gate Arrays), and microcontrollers. In addition, each test board is also equipped with test circuitry, which may include at least one of a dynamic high-temperature gate bias test circuit and a static high-temperature reverse bias test circuit. That is, a single test board may only have a dynamic high-temperature gate bias test circuit, only a static high-temperature reverse bias test circuit, or both; this application embodiment does not impose specific limitations. The dynamic high-temperature gate bias test circuitry is used to test the gate leakage current Igss and gate threshold voltage Vgsth of the transistor under test after aging under a high-temperature environment. The static high-temperature reverse bias test circuitry is used to test the drain cutoff current Idss of the transistor under test after aging under a high-temperature environment. The controller is connected to the test circuit and is used to input control signals to the test circuit or receive signals from the test circuit to detect the gate-biased gate leakage current Igss, the gate-biased gate threshold voltage Vgsth, and the reverse-biased drain cutoff current Idss of the transistor under test. The controller compares the gate-biased gate leakage current Igss with a preset gate-biased gate leakage current, compares the gate-biased gate threshold voltage Vgsth with a preset gate threshold voltage, and compares the reverse-biased drain cutoff current Idss with a preset reverse-biased drain cutoff current. If at least one of the gate-biased gate leakage current Igss, the gate-biased gate threshold voltage Vgsth, and the reverse-biased drain cutoff current Idss is higher than the corresponding preset value, the transistor under test is considered to be faulty.

[0023] Continue to refer to Figure 1The probe card 20 includes an upper surface S1 away from the wafer side and a lower surface S2 close to the wafer side. A test board is disposed on the upper surface S1 of the probe card 20, and a plurality of probes 21 are disposed on the lower surface of the probe card 20. The plurality of probes 21 are used to connect with the electrodes of the transistor under test on the wafer. In one possible implementation, the probes and electrodes on the transistors have a one-to-one correspondence, with one probe 21 connected to one of the electrodes on the transistor under test. In another possible implementation, the probe card 20 is a PCB board. The probe card 20 may also include at least one layer of patterned conductive lines and a plurality of first conductive vias. The conductive lines are connected to each other and to the probes 21 through the first conductive vias. Thus, the test board can be electrically connected to the transistor under test through the conductive lines, first conductive vias, and probes 21 on the probe card 20. The controller on the test board sends signals to the transistor under test and receives signals from the transistor under test through the test circuit to test the transistor under test.

[0024] like Figure 1 As shown, the wafer includes an upper surface S3 (i.e., the front side of the wafer) that contacts the probes 21 on the probe card 20, and a lower surface S4 (i.e., the back side of the wafer) that is away from the probe card 20. A wafer tray 30 is disposed on one side of the lower surface S4 and contacts the lower surface S4 to support the wafer. In one possible implementation, the wafer tray 30 has a groove for fixing the wafer; the wafer can be placed in the groove of the wafer tray 30 to fix the wafer and prevent it from moving. A heater 40 is disposed on the side of the wafer tray 30 away from the wafer. The heater 40 can provide a high-temperature testing environment to the wafer through the wafer tray 30.

[0025] In one optional implementation of this application, the upper surface S3 of the wafer serves as the gate and source of a transistor, and the lower surface S4 of the wafer serves as the drain of a transistor. Before the wafer is diced into individual bare chips, the gate and source of each transistor on the wafer are independent electrodes, and the drains of all transistors on the wafer are connected together. In this implementation, the wafer tray 30 is conductive, for example, made of a metallic material. The probes 21 on the probe card 20 are connected one-to-one to the gate and source of each transistor; the drains of the transistors on the wafer are connected to the wafer tray 30, and are connected to the probe card 20 through the wafer tray 30. Furthermore, a groove can be provided in the area on the lower surface S2 of the probe card 20 where no probes 21 are provided, and a strip-shaped structure perpendicular to the surface of the wafer tray 30 is also provided on the side of the wafer tray 30. The strip-shaped structure on the wafer tray 30 is embedded in the groove on the lower surface of the probe card 20, so that the wafer tray 30 is fixed to the probe card 20. Figure 1The diagram shows a case where the upper surface S3 of the wafer is the gate and source of the transistor, and the lower surface S4 of the wafer is the drain of the transistor. It should be noted that in other possible implementations, the drain of the transistor can also be located on the upper surface S3 of the wafer. In this case, the drain of the transistor can be connected to a probe on the probe card 20. Furthermore, in this case, the strip structure on the wafer tray 30 may not be provided; this embodiment does not impose specific limitations.

[0026] from Figure 1 As can be seen from the wafer reliability testing system 100 shown in the present application embodiment, the wafer reliability testing system 100, by setting up multiple test boards, probe cards 20, wafer trays 30 and heaters 40, can realize wafer-level chip reliability testing before chip packaging, so as to screen out qualified chips before chip packaging, eliminating the need for further packaging of failed chips, thereby reducing packaging costs and thus reducing the production cost of electronic devices.

[0027] Please continue to refer to this. Figure 2 , Figure 2 This is another structural schematic diagram of the wafer reliability testing system 200 provided in the embodiments of this application. Figure 1 The wafer reliability testing system 100 shown is different in that... Figure 2The wafer reliability testing system 100 shown includes, in addition to a test board, probe card 20, wafer tray 30, and heater 40, an adapter board 50, a first insulating layer 60, and a second insulating layer 70. The adapter board 50 is disposed between the test board and the probe card 20, and its projection onto the probe card 20 completely covers it. Typically, the surface area of ​​the probe card 20 is limited, and its upper surface S1 may not be able to accommodate all the test boards. By providing the adapter board 50, the test boards can be placed on it, and the test boards are electrically connected to the probes on the probe card 20 through the adapter board 50, thus effectively accommodating the test boards. The first insulating layer 60 is disposed between the wafer tray 30 and the heater 40. The first insulating layer 60 can be an insulating and thermally conductive material. The heater 40 provides a high-temperature environment to the wafer through the first insulating layer 60 and the wafer tray 30. The second insulating layer 70 is disposed on the side of the heater 40 away from the wafer tray 30. The second insulating layer 70 is used to isolate the wafer reliability testing system 200 from the external environment, thereby ensuring that the wafer reliability testing system 200 operates in a stable environment and ensuring the accuracy of the test. It should be noted that in other possible implementations, in addition to the test board, probe card 20, wafer tray 30 and heater 40, the wafer reliability testing system 200 may be provided with at least one of the following: adapter board 50, first insulating layer 60 and second insulating layer 70. For example, the wafer reliability testing system 200 may only provide adapter board 50 and not provide first insulating layer 60 and second insulating layer 70; or, for example, the wafer reliability testing system 200 may provide adapter board 50 and first insulating layer 60 and not provide second insulating layer 70. The embodiments of this application do not make specific limitations.

[0028] Based on the wafer reliability testing system described in any of the above embodiments, this application also provides the circuit structure of the test circuit on the test board. Please continue to refer to... Figure 3 , Figure 3 This is a schematic diagram of the dynamic high-temperature gate bias test circuit 300 provided in the embodiment of this application. Figure 3As shown, the dynamic high-temperature gate bias test circuit 300 includes a first test module 10, a first protection module 11, and a voltage conversion module 12. The first protection module 11 is connected to the voltage conversion module 12 to protect both the voltage conversion module 12 and the transistor under test (TUT) on the wafer. The voltage conversion module 12 is connected between the controller C and the first test module 10. Based on the PWM (Pulse Width Modulation) signal emitted by the controller C, the voltage conversion module 12 converts the power supply voltage and inputs the converted signal to the first test module 10. The voltage conversion module 12 can be, for example, a boost circuit, a buck circuit, or a buck-boost circuit. The first test module 10 includes multiple switches, which, based on the control of the controller C, connect the electrodes of the TUT on the wafer to the voltage conversion module 12 or to the controller C. When the first test module 10 is connected to the voltage conversion module 12, the transistor under test is in an aging state. When the first test module 10 is connected to the controller C, the controller C reads at least one of the gate-biased gate leakage current Igss and the gate-biased gate threshold voltage Vgsth of the transistor under test. In addition, the controller C is also used to connect to the first protection module 11, and the controller C is also used to read the current value and voltage value from the first protection module 11. The controller C detects whether the current or voltage in the circuit exceeds the threshold value by reading the current value and voltage value. When the threshold value is exceeded, the controller controls the voltage conversion module 12 to stop transmitting signals to the first test module 10.

[0029] based on Figure 3 Please refer to the schematic diagram of the dynamic high-temperature gate bias test circuit 300 shown below. Figure 4 , Figure 4 Is it like this? Figure 3 The diagram shows a specific circuit structure of the dynamic high-temperature gate bias test circuit 300. (See attached diagram.) Figure 4 As shown, the voltage conversion module 12 includes a first transistor G1 and a second transistor G2. The gates of both the first transistor G1 and the second transistor G2 are connected to the control signal output terminal of the controller C. The drain of the first transistor G1 is connected to the first protection module 11, and the source of the first transistor G1 is connected to the drain of the second transistor G2 to form node a. The source of the second transistor G2 is connected to the second power supply terminal -Vdd. In one possible implementation, a drive circuit 13 can also be provided between the controller C and the voltage conversion module 12. The gates of both the first transistor G1 and the second transistor G2 are connected to the drive circuit 13. The controller C outputs a PWM signal to the drive circuit 13, and the drive circuit 13 provides the PWM signal to the first transistor G1 and the second transistor G2 in a time-division multiplexing manner.

[0030] The first test module 10 includes a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, and a signal source measurement unit (SMU). The first switch K1 and the second switch K2 are single-pole double-throw switches; the third switch K3 and the fourth switch K4 are single-pole single-throw switches. The first switch K1, under the control of the controller C, selectively connects the gate of the transistor under test (G) to node a or to the signal source measurement unit (SMU). The second switch K2, under the control of the controller C, selectively connects the source of the transistor under test (G) to the first common ground (MGND) or to the second common ground (GND), where the first common ground (MGND) is the same ground terminal as the controller C, and the second common ground (GND) is the same ground terminal as the voltage conversion module 12 and the first protection module 11. The third switch K3, under the control of the controller C, selectively connects or disconnects the gate and drain of the transistor under test (G). The fourth switch K4, under the control of the controller C, selectively connects or disconnects the source and drain of the transistor under test (G).

[0031] In specific operations, during the aging stage of the transistor G under test, the first switch K1 connects the gate of the transistor G to node a, the second switch K2 connects the source of the transistor G to the second common ground GND, the third switch K3 is open, and the fourth switch is closed. At this time, the voltage input from the first power supply terminal +Vdd is provided to the voltage conversion module 12 through the first protection module 11. The voltage conversion module 12 boosts the voltage and applies it to the gate of the transistor G under test, thereby completing the aging process of the transistor G. Figure 5A As shown.

[0032] During the data reading phase of the transistor G under test, the first switch K1 connects the gate of the transistor G to the signal source measurement unit (SMU), the second switch K2 connects the source of the transistor G to the first common ground (MGND), the third switch K3 is open, and the fourth switch is closed. At this time, the controller C can read the gate leakage current Igss of the transistor G under test through the signal source measurement unit (SMU), such as... Figure 5B As shown.

[0033] During the data reading phase of the transistor G under test, the first switch K1 connects the gate of the transistor G to the signal source measurement unit (SMU), the second switch K2 connects the source of the transistor G to the first common ground (MGND), the third switch K3 is closed, and the fourth switch is open. At this time, the controller C can read the gate threshold voltage Vgsth of the transistor G through the signal source measurement unit (SMU), such as... Figure 5C As shown.

[0034] Continue to refer to Figure 4 ,like Figure 4As shown, the first protection module 11 includes a first fuse F1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a first integrated operational amplifier A1. The drain of the first transistor G1 is connected to the first terminal of the first resistor R1, the second terminal of the first resistor R1 is connected to the first terminal of the first fuse F1, and the second terminal of the first fuse F1 is connected to the first power supply terminal +Vdd, which is at a high level. The non-inverting input terminal of the first integrated operational amplifier A1 is connected to the drain of the first transistor G1 through the second resistor R2, and the non-inverting input terminal of the first integrated operational amplifier A1 is connected to the first common ground GND through the third resistor R3. The inverting input terminal of the first integrated operational amplifier A1 is connected to the first terminal of the first fuse F1 through the fourth resistor R4. The inverting input terminal of the first integrated operational amplifier A1 is connected to the output terminal of the first integrated operational amplifier A1 through the fifth resistor R5. The drain of the first transistor G1 is connected to the second power supply terminal -Vdd through the sixth transistor R6 and the seventh transistor R7. In this configuration, a node b is formed between the sixth transistor R6 and the seventh transistor R7. The controller C is also connected to node b and the output terminal of the first integrated operational amplifier A1. The controller C collects the voltage of node b and the current output by the first integrated operational amplifier A1. The controller C first compares the current output by the first integrated operational amplifier A1 with a preset current. If it is higher than a preset threshold, the controller C further detects whether the voltage of node b exceeds the preset threshold. If the voltage of node b also exceeds the preset threshold, the controller controls the first transistor G1 and the second transistor G2 to turn off.

[0035] Please continue to refer to this. Figure 6 , Figure 6 This is a schematic diagram of a static high-temperature reverse bias test circuit 400 provided in an embodiment of this application. For example... Figure 6 As shown, the static high-temperature reverse bias test circuit 400 includes a second test module 14, a current conversion module 15, and a second protection module 16. The second test module 14 is connected to the transistor under test (TUT). The current conversion module 15 is located between the fifth switch K5 and the common ground GND. Based on the control of the driver C, the fifth switch K5 selectively connects the second test module 14 to the current conversion module 15 or to the common ground GND of the static high-temperature reverse bias test circuit 400. Specifically, when aging the TUT, the fifth switch K5 is connected to the common ground GND; when reading the drain cutoff current of the TUT, the fifth switch K5 is connected to the current conversion module 15. The second protection module 16 is located between the second test module 14 and the common ground. The second protection module 16 is used to protect the current conversion module 15.

[0036] based on Figure 6 Please refer to the schematic diagram of the static high-temperature reverse bias test circuit 400 shown below. Figure 7 , Figure 7 Is it like this? Figure 6 The diagram shows a specific circuit structure of the static high-temperature reverse bias test circuit 400. (See attached diagram.) Figure 7 As shown, the second test module 14 includes a second resistance wire F2 and a voltage source U. The second resistance wire F2 is disposed between the second power supply terminal U and the source of the transistor under test G. The negative terminal of the voltage source U is connected to the gate of the transistor under test G, and the positive terminal of the voltage source U is connected to the source of the transistor under test G.

[0037] In one possible implementation of this application, the current conversion module 15 may include a plurality of shunt resistors and a plurality of switches connected in parallel. The plurality of shunt resistors and the plurality of switches are connected one-to-one. One end of each of the plurality of shunt resistors is connected to a fifth switch through a corresponding switch, and the other end of the plurality of shunt resistors is connected to the common ground GND.

[0038] In addition, such as Figure 7 The static high-temperature reverse bias test circuit 400 shown also includes a reading sampling circuit 17. The input terminal of the reading sampling circuit 17 is connected to the fifth switch K5 and the common ground GND, and the output terminal of the reading sampling circuit 17 is connected to the controller C.

[0039] In one possible implementation of this application, the second protection module 16 can be a clamping and warning circuit 161, which may include circuits such as Zener diodes, diodes, and integrated operational amplifiers. When the voltage across the drain and source terminals of the transistor under test G is too high, the clamping and warning circuit 161 clamps the source potential of the transistor under test G at a preset potential, thereby protecting the static high-temperature reverse bias test circuit 400 to prevent damage to components such as switch K5 in the circuit.

[0040] based on Figure 7 In the circuit structure shown, during the aging test of transistor G, switch K5, under the control of controller C, connects the source of transistor G to the common ground GND, and voltage source U provides reverse bias voltage to transistor G. When reading the reverse bias leakage current of transistor G, switch K5, under the control of controller C, connects the source of transistor G to node c. Controller C adjusts the current at node c by regulating current conversion module 15, thereby changing the current data output from the reading sampling circuit 17. Based on the current data read from the reading sampling circuit 17, controller C can determine the reverse bias leakage current Idss of transistor G.

[0041] The above description is merely an exemplary embodiment of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Other embodiments of this disclosure will be readily apparent to those skilled in the art upon consideration of the specification and the disclosure of practical truths.

[0042] This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described in this disclosure. The specification and embodiments are to be considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.

Claims

1. A wafer reliability testing system, characterized in that, include: A test board, wherein a controller (C) and a test circuit are provided on the test board, and the test circuit includes at least one of a dynamic high-temperature gate bias test circuit and a static high-temperature reverse bias test circuit; The probe card (20) has a plurality of probes (21) disposed on the lower surface away from the test board for connection with the electrodes of each transistor on the wafer. The probe card (20) also has a plurality of first conductive vias. The test circuit on the test board is electrically connected to the plurality of probes (21) on the probe card (20) through the plurality of first conductive vias. A wafer tray (30) is disposed on the side of the wafer away from the probe card (20) to support the wafer; A heater (40) is disposed on the side of the wafer tray (30) away from the wafer to provide a high-temperature testing environment to the wafer through the wafer tray (30); The test circuit includes a dynamic high-temperature gate bias test circuit, which includes a first test module (10), a first protection module (11), and a voltage conversion module (12). The first protection module (11) is connected to the voltage conversion module (12) to protect the voltage conversion module (12) and the transistor under test (G) on the wafer; The voltage conversion module (12) is connected between the controller (C) and the first test module (10) and is used to convert the voltage transmitted from the first power supply terminal (+Vdd) based on the control signal transmitted by the controller (C) and input the voltage-converted signal to the first test module (10). The first test module (10) includes multiple switches, which, based on the control of the controller (C), connect the test terminal of the transistor under test (G) to the voltage conversion module (12) or to the controller (C); The voltage conversion module (12) includes a first transistor (G1) and a second transistor (G2); The gates of the first transistor (G1) and the second transistor (G2) are connected to the control signal output terminal of the controller (C); The drain of the first transistor (G1) is connected to the first protection module (11), the source of the first transistor (G1) is connected to the drain of the second transistor (G2) to form a node (a), and the source of the second transistor (G2) is connected to the second power supply terminal (-Vdd).

2. The wafer reliability testing system according to claim 1, characterized in that, The wafer reliability testing system also includes an adapter board (50), a first insulating layer (60), and a second insulating layer (70). The adapter plate (50) is disposed between the test board and the probe card (20). The adapter plate (50) is provided with a plurality of second conductive through holes. The test circuit on the test board is electrically connected to a plurality of probes (21) on the probe card (20) through the plurality of second conductive through holes and the plurality of first conductive through holes. The first insulating layer (60) is disposed between the wafer tray (30) and the heater (40), and the first insulating layer (60) is an insulating and thermally conductive material; The second insulating layer (70) is disposed on the side of the heater (40) away from the wafer tray (30) to isolate the wafer reliability testing system from the external environment.

3. The wafer reliability testing system according to claim 1 or 2, characterized in that, The wafer reliability testing system also includes the wafer; The wafer includes a plurality of transistors, the upper surface of the wafer is provided with the gate and source of the plurality of transistors, and the lower surface of the wafer is provided with the drain. The gates and sources of the plurality of transistors are connected one-to-one with the plurality of probes (21); The drain is connected to the wafer tray (30) and is connected to the probe card (20) through the wafer tray (30), wherein the wafer tray (30) is conductive.

4. The wafer reliability testing system according to claim 1, characterized in that, The first test module (10) includes a first switch (K1), a second switch (K2), a third switch (K3), a fourth switch (K4), and a signal source measurement unit (SMU), wherein the first switch (K1) and the second switch (K2) are single-pole double-throw switches; The first switch (K1) selectively connects the gate of the transistor under test (G) to the node (a) or to the signal source measurement unit (SMU) based on the control of the controller (C). The second switch (K2) selectively connects the source of the transistor under test (G) to a first common ground (MGND) or a second common ground (GND) based on the control of the controller (C). The first common ground is the same ground terminal as the controller (C), and the second common ground is the same ground terminal as the first protection module (11). The third switch (K3) selectively connects or disconnects the gate and drain of the transistor under test (G); The fourth switch (K4) selectively connects or disconnects the source and drain of the transistor under test (G); The output of the signal source measurement unit (SMU) is connected to the controller (C) and is used to output the counting result to the controller (C).

5. The wafer reliability testing system according to claim 4, characterized in that, The first protection module (11) includes a first fuse (F1), a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5), a sixth resistor (R6), a seventh resistor (R7), and a first integrated operational amplifier (A1). The drain of the first transistor (G1) is connected to the first end of the first resistor (R1), the second end of the first resistor (R1) is connected to the first end of the first fuse (F1), and the second end of the first fuse (F1) is connected to the first power supply terminal (+Vdd). The non-inverting input terminal of the first integrated operational amplifier (A1) is connected to the drain of the first transistor (G1) through the second resistor (R2), and the non-inverting input terminal of the first integrated operational amplifier (A1) is connected to the second common ground (GND) through the third resistor (R3). The inverting input terminal of the first integrated operational amplifier (A1) is connected to the first terminal of the first fuse (F1) through the fourth resistor (R4); The inverting input terminal of the first integrated operational amplifier (A1) is connected to the output terminal of the first integrated operational amplifier (A1) through the fifth resistor (R5); The drain of the first transistor (G1) is connected to the second power supply terminal (-Vdd) through the sixth resistor (R6) and the seventh resistor (R7).

6. The wafer reliability testing system according to claim 1, characterized in that, The static high temperature reverse bias test circuit includes a second test module (14), a second protection module (16), a current conversion module (15), and a fifth switch (K5). The second test module (14) is connected to the transistor under test (G) on the wafer. The fifth switch (K5) selectively connects the second test module (14) to the current conversion module (15) or to the common ground of the static high temperature reverse bias test circuit based on the control of the controller (C). The second protection module (16) is located between the second test module (14) and the common ground.

7. The wafer reliability testing system according to claim 6, characterized in that, The second test module (14) includes a second resistance wire (F2) and a voltage source (U). The second resistance wire (F2) is disposed between the first power supply terminal (+Vdd) and the drain of the transistor under test (G). The negative terminal of the voltage source (U) is connected to the gate of the transistor under test (G), and the positive terminal of the voltage source (U) is connected to the source of the transistor under test (G).

8. The wafer reliability testing system according to claim 7, characterized in that, The static high-temperature reverse bias test circuit further includes a reading sampling circuit (17). The input terminal of the reading sampling circuit (17) is connected to the fifth switch (K5) and the common ground, and the output terminal of the reading sampling circuit (17) is connected to the controller (C). The reading sampling circuit (17) is used for: When the second test module (14) is connected to the current conversion module (15), the drain current of the transistor under test (G) is collected, and the collected drain current is transmitted to the controller (C).

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