Photovoltaic cell and method of manufacturing the same

Abstract

The application discloses a photovoltaic cell and a preparation method thereof. The preparation method comprises the following steps: providing a silicon wafer with amorphous silicon layers on both sides, wherein the two sides comprise a first side and a second side arranged oppositely; simultaneously growing a barrier layer on the first side and the second side of the silicon wafer to obtain a silicon wafer with a barrier layer; performing diffusion treatment on the silicon wafer with the barrier layer, so that the amorphous silicon layer of the silicon wafer with the barrier layer is converted into a polycrystalline silicon layer, and a silicon wafer with a polycrystalline silicon layer is obtained; and processing the silicon wafer with the polycrystalline silicon layer, removing the barrier layer and the polycrystalline silicon layer on the first side, and removing the barrier layer on the second side, to obtain a photovoltaic cell. The application keeps the diffusion rate of phosphorus atoms consistent through the barrier layer, improves the doping uniformity of phosphorus atoms in the polycrystalline silicon layer, and greatly improves the photoelectric conversion efficiency and the yield of the photovoltaic cell prepared by the method.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and more specifically, to photovoltaic cells and their preparation methods. Background Technology

[0002] Photovoltaic cells, also known as solar cells, are thin-film photovoltaic semiconductors that directly generate electricity using sunlight. Given sufficient illumination, they can instantly output voltage and, in the presence of a circuit, produce current. There are many types of photovoltaic cells, including PERC cells (passivated reflector and back-side cell structure) and TOPCon cells (tunneling oxide passivated contact structure). The back side of a photovoltaic cell includes a polycrystalline silicon layer doped with phosphorus atoms. The method for preparing the polycrystalline silicon layer typically involves first preparing an amorphous silicon layer, which is then subjected to phosphorus diffusion treatment and high-temperature annealing to transform into a polycrystalline silicon layer. However, in existing technologies, the uniformity of phosphorus doping in the polycrystalline silicon layer is generally poor. Therefore, this is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0003] In view of this, the present invention provides a method for preparing photovoltaic cells to solve the problem of general phosphorus atom doping uniformity in polycrystalline silicon layers.

[0004] In a first aspect, this application provides a method for preparing a photovoltaic cell, comprising the following steps:

[0005] A silicon wafer with amorphous silicon layers on both sides is provided, the two sides including a first side and a second side disposed opposite to each other;

[0006] A barrier layer is grown simultaneously on the first and second sides of a silicon wafer to obtain a silicon wafer with a barrier layer.

[0007] The silicon wafer forming the barrier layer is subjected to diffusion treatment, which transforms the amorphous silicon layer of the silicon wafer forming the barrier layer into a polycrystalline silicon layer, thus obtaining a silicon wafer with a polycrystalline silicon layer.

[0008] A silicon wafer with a polycrystalline silicon layer is processed by removing the barrier layer and polycrystalline silicon layer on the first side and removing the barrier layer on the second side to obtain a photovoltaic cell.

[0009] Optionally, the barrier layer is grown simultaneously on the first and second sides of the silicon wafer, including the growth of the barrier layer by diffusion method, wherein the oxygen flow rate is in the range of 10000sccm-30000sccm and the temperature is in the range of 600℃-700℃.

[0010] Optionally, in the diffusion process of the silicon wafer forming the barrier layer, the diffusion source is phosphorus oxychloride.

[0011] Optionally, processing a silicon wafer having a polycrystalline silicon layer includes the following steps:

[0012] The barrier layer on the first surface is removed using an acidic liquid;

[0013] The polycrystalline silicon layer on the first side is removed using an alkaline liquid;

[0014] The barrier layer on the second side is removed using an acidic liquid.

[0015] Optionally, the preparation method of a silicon wafer with amorphous silicon layers on both sides includes texturing, first diffusion, laser, second diffusion, etching, and growth of a protective layer.

[0016] Optionally, the growth protective layer includes the following steps:

[0017] A tunneling oxide layer is grown on the second side of the etched silicon wafer;

[0018] After growing the tunnel oxide layer, amorphous silicon layers are grown on both the first and second sides of the silicon wafer to obtain a silicon wafer with amorphous silicon layers on both sides.

[0019] Optionally, the process of processing a silicon wafer with a polycrystalline silicon layer includes the following steps: passivation, coating, screen printing, and sintering.

[0020] Optionally, growing a tunneling oxide layer on the second side of the etched silicon wafer includes growing the tunneling oxide layer using an oxidation method, wherein the oxygen flow rate is in the range of 30000 sccm-38000 sccm and the temperature is in the range of 580℃-620℃.

[0021] Optionally, growing an amorphous silicon layer on both the first and second sides of the silicon wafer after growing the tunnel oxide layer includes growing the amorphous silicon layer using a decomposition method, wherein the flow rate of silicon tetrahydrogen hydride is in the range of 1300 sccm-1700 sccm and the temperature is in the range of 590℃-610℃.

[0022] Secondly, this application provides a photovoltaic cell, including a photovoltaic cell prepared by any of the above-mentioned photovoltaic cell preparation methods.

[0023] Compared with the prior art, the photovoltaic cell and its preparation method provided by the present invention achieve at least the following beneficial effects:

[0024] The present invention provides a photovoltaic cell and a method for preparing the same. The method includes the following steps: providing a silicon wafer with amorphous silicon layers on both sides, the two sides including a first side and a second side disposed opposite to each other; simultaneously growing a barrier layer on the first side and the second side of the silicon wafer to obtain a silicon wafer with a barrier layer; subjecting the silicon wafer with the barrier layer to diffusion treatment, transforming the amorphous silicon layer of the silicon wafer with the barrier layer into a polycrystalline silicon layer, to obtain a silicon wafer with a polycrystalline silicon layer; processing the silicon wafer with the polycrystalline silicon layer to remove the barrier layer and the polycrystalline silicon layer on the first side, and removing the barrier layer on the second side to obtain a photovoltaic cell. By adopting the above scheme, the diffusion rate of phosphorus atoms is kept consistent through the barrier layer, improving the doping uniformity of phosphorus atoms in the polycrystalline silicon layer. At the same time, the photovoltaic cell prepared by this method has significantly improved photoelectric conversion efficiency and yield.

[0025] Of course, any product implementing this invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0026] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0028] Figure 1 This is a flowchart of the photovoltaic cell preparation method provided by the present invention;

[0029] Figure 2 This is a flowchart of an optional embodiment of a photovoltaic cell fabrication method provided by the present invention;

[0030] Figure 3 This is a flowchart of the process for processing a silicon wafer with a polycrystalline silicon layer provided by the present invention;

[0031] Figure 4 This is a flowchart of the chain device provided by the present invention;

[0032] Figure 5 This is a flowchart of the trough-type device provided by the present invention;

[0033] Figure 6 This is a flowchart of an optional implementation method for obtaining a silicon wafer with amorphous silicon layers on both sides, provided by the present invention;

[0034] Figure 7 This is a flowchart of the flocking process provided by the present invention;

[0035] Figure 8 yes Figure 6 The flowchart for obtaining a silicon wafer with amorphous silicon layers on both sides;

[0036] Figure 9 This is a flowchart of the etching process provided by the present invention;

[0037] Figure 10 This is a flowchart of the growth protective layer provided by the present invention;

[0038] Figure 11 This is a flowchart of the process of processing a silicon wafer with a polycrystalline silicon layer provided by the present invention;

[0039] Figure 12 yes Figure 11 The flowchart for obtaining photovoltaic cells is as follows;

[0040] Figure 13 This is a schematic diagram of the structure of the photovoltaic cell provided by the present invention. Detailed Implementation

[0041] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0042] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0043] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification.

[0044] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0045] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0046] Reference Figures 1-2 , Figure 1 This is a flowchart of the photovoltaic cell preparation method provided by the present invention; Figure 2 This is a flowchart of an optional embodiment of a photovoltaic cell fabrication method provided by the present invention. This embodiment provides a photovoltaic cell fabrication method, including the following steps:

[0047] S1: Provide a silicon wafer 00 with amorphous silicon layers 10 on both sides, the two sides including a first side 01 and a second side 02 arranged opposite to each other.

[0048] Specifically, in combination Figure 1and Figure 2 As shown, the silicon wafer 00 includes a first side 01 and a second side 02 disposed opposite to each other. In this embodiment, the first side 01 can be the front side, and the second side 02 can be the back side. The first side 01 includes a doped layer 40 and a first amorphous silicon layer 101, with the first amorphous silicon layer 101 located on the side of the doped layer 40 away from the first side 01. The second side 02 includes a tunneling oxide layer 30 and a second amorphous silicon layer 102, with the second amorphous silicon layer 102 located on the side of the tunneling oxide layer 30 away from the second side 02. A silicon wafer 00 with amorphous silicon layers 10 on both sides (the amorphous silicon layers 10 include the first amorphous silicon layer 101 and the second amorphous silicon layer 102) is as follows. Figure 2 As shown in (a).

[0049] S2: A barrier layer 20 is grown simultaneously on the first side 01 and the second side 02 of the silicon wafer 00 to obtain a silicon wafer 00 with the barrier layer 20 formed.

[0050] Specifically, in combination Figure 1 and Figure 2 As shown, the silicon wafer 00, with amorphous silicon layers 10 on both sides, requires subsequent diffusion treatment. During diffusion, a silicon dioxide (SiO2) layer automatically grows on the surface of the amorphous silicon layer 10. This generated silicon dioxide layer is unevenly distributed and cannot form a dense film. During diffusion, some phosphorus atoms need to pass through the silicon dioxide layer to enter the amorphous silicon layer 10, while others can directly enter. Because the doping rate of phosphorus atoms in the silicon dioxide layer is lower than that in the amorphous silicon layer 10, the amount of phosphorus atoms doped in the entire amorphous silicon layer 10 varies, ultimately affecting the uniformity of phosphorus doping. Therefore, as... Figure 2 As shown in (b), by simultaneously growing a barrier layer 20 on the first side 01 and the second side 02 of the silicon wafer 00, the barrier layer 20 includes a first barrier layer 201 and a second barrier layer 202. The first barrier layer 201 is grown on the first side 01 and the second barrier layer 202 is grown on the second side, resulting in a silicon wafer 00 with barrier layers 20 formed on both sides. The barrier layer 20 ensures that the diffusion rate of phosphorus atoms is consistent during the doping process, thus ensuring the uniformity of doping.

[0051] S3: The silicon wafer 00 forming the barrier layer 20 is subjected to diffusion treatment, and the amorphous silicon layer 10 of the silicon wafer 00 forming the barrier layer 20 is transformed into a polycrystalline silicon layer 11, thus obtaining a silicon wafer 00 with a polycrystalline silicon layer 11.

[0052] Specifically, in combination Figure 1 and Figure 2 As shown, the diffusion process for the silicon wafer 00 forming the barrier layer 20 includes placing the silicon wafer 00 in a diffusion furnace, where heat treatment and phosphorus diffusion are performed simultaneously, such as... Figure 2As shown in (c), the heat treatment transforms the first amorphous silicon layer 101 into the first polycrystalline silicon layer 111 and the second amorphous silicon layer 102 into the second polycrystalline silicon layer 112, completing crystallization. Phosphorus atoms diffuse through the first barrier layer 201 to the first polycrystalline silicon layer 111 and through the second barrier layer 202 to the second polycrystalline silicon layer 112, resulting in phosphorus atoms being doped in both the first polycrystalline silicon layer 111 and the second polycrystalline silicon layer 112, becoming n+ doped polycrystalline silicon. Since both the first barrier layer 201 and the second barrier layer 202 are dense and uniform structures, the diffusion rate of phosphorus atoms into the polycrystalline silicon can be slowed down, improving the doping uniformity of the first polycrystalline silicon layer 111 and the second polycrystalline silicon layer 112.

[0053] The temperature range for heat treatment is 850℃-950℃. If the temperature is below 850℃, the resulting polycrystalline silicon grain boundaries are small and thin, and the phosphorus doping effect is weak and low, leading to problems such as poor contact and passivation effects in photovoltaic cells. If the temperature is above 950℃, the resulting polycrystalline silicon doping effect is strong, the polycrystalline silicon doping concentration is low, the bulk doping concentration is high, and the photovoltaic cell contact and passivation effects are also poor. Therefore, setting the temperature range for heat treatment to 850℃-950℃ can not only avoid the problems of small and thin polycrystalline silicon grain boundaries, weak and low phosphorus doping effect, and poor contact and passivation effects in photovoltaic cells, but also avoid the problems of strong phosphorus doping effect, low polycrystalline silicon doping concentration, and high bulk doping concentration. Specifically, the heat treatment temperature can be 850℃, 870℃, 890℃, 910℃, 930℃, or 950℃.

[0054] The phosphorus doping concentration ranges from 2.0 × 10⁻⁶. 20 -5.0×10 20 If the phosphorus doping concentration is less than 2.0 × 10⁻⁶ 20 If the doping concentration is too low, problems such as bulk passivation, poor metal contact, and poor photovoltaic cell efficiency and yield will occur. If the phosphorus doping concentration is greater than 5.0 × 10⁻⁶, the doping concentration will be significantly lower. 20 Excessive doping concentration leads to problems such as high matrix doping concentration, increased recombination, and poor photovoltaic cell efficiency and yield. Therefore, the phosphorus doping concentration was set to 2.0 × 10⁻⁶. 20 -5.0×10 20 This not only avoids problems such as bulk passivation, poor metal contact, and low photovoltaic cell efficiency and yield, but also avoids problems such as high matrix doping concentration and increased recombination; specifically, the phosphorus doping concentration can be 2.0 × 10⁻⁶. 20 2.5×10 20 3.0×10 20 3.5×10 20 4.0×10 20 4.5×10 20 Or 5.0×1020 .

[0055] S4: Process the silicon wafer 00 with polycrystalline silicon layer 11, remove the barrier layer 20 and polycrystalline silicon layer 11 on the first side 01, remove the barrier layer 20 on the second side 02, and obtain a photovoltaic cell.

[0056] Specifically, in combination Figure 1 and Figure 2 As shown, by gradually removing the first barrier layer 201 and the first polysilicon layer 111 on the first surface 01, and removing the second barrier layer 202 on the second surface 02, the following can be obtained: Figure 2 (d) shows a photovoltaic cell, wherein the first side 01 of the photovoltaic cell includes a doped layer 40, and the second side 02 includes a tunneling oxide layer 30 and a second polycrystalline silicon layer 112.

[0057] The following is a comparison between a photovoltaic cell of one embodiment and a photovoltaic cell of a comparative example:

[0058] Example

[0059] (1) A silicon wafer 00 with amorphous silicon layers 10 on both sides is provided. The two sides include a first side 01 and a second side 02 arranged opposite to each other. The first side 01 is a first amorphous silicon layer 101, and the second side 02 is a second amorphous silicon layer 102. (2) A barrier layer 20 is grown simultaneously on the first side 01 and the second side 02 of the silicon wafer 00. The first barrier layer 201 is grown on the first amorphous silicon layer 101, and the second barrier layer 202 is grown on the second amorphous silicon layer 102, to obtain a silicon wafer 00 with barrier layers 20 on both sides. (3) The silicon wafer 00 with barrier layers 20 is subjected to diffusion treatment, and the first amorphous silicon layer 101 is transformed into a first polycrystalline silicon layer 111, and the second amorphous silicon layer 102 is transformed into a second polycrystalline silicon layer 112, to obtain a silicon wafer 00 with polycrystalline silicon layers 11 on both sides. The heating temperature is 850℃, and the phosphorus doping concentration is 2.0×10⁻⁶. 20 (4) Process the silicon wafer 00 with polycrystalline silicon layers 11 on both sides, remove the first barrier layer 201 and the first polycrystalline silicon layer 111 on the first side 01, and remove the second barrier layer 202 on the second side 02 to obtain a photovoltaic cell; (5) Perform electrical performance testing on the photovoltaic cell.

[0060] Comparative Example

[0061] (1) A silicon wafer 00 with amorphous silicon layers 10 on both sides is provided. The two sides include a first side 01 and a second side 02 arranged opposite to each other. The first side 01 is a first amorphous silicon layer 101, and the second side 02 is a second amorphous silicon layer 102. (2) The silicon wafer 00 with amorphous silicon layers 10 on both sides is directly subjected to diffusion treatment, so that the first amorphous silicon layer 101 is transformed into a first polycrystalline silicon layer 111, and the second amorphous silicon layer 102 is transformed into a second polycrystalline silicon layer 112, to obtain a silicon wafer 00 with polycrystalline silicon layers 11 on both sides. The heating treatment temperature is 850℃, and the phosphorus atom doping concentration is 2.0×10⁻⁶. 20 (3) Process the silicon wafer 00 with polycrystalline silicon layers 11 on both sides, remove the phosphosilicate glass, the first polycrystalline silicon layer 111 and borosilicate glass on the first side 01, and remove the phosphosilicate glass on the second side 02 to obtain a photovoltaic cell; (4) Perform electrical performance testing on the photovoltaic cell.

[0062] It should be noted that: (1) the electrical performance test can be performed using a battery performance tester to measure the relevant electrical performance parameters of the photovoltaic cell; (2) the comparative example is the photovoltaic cell preparation method in the prior art.

[0063] Table 1: Partial Electrical Performance and Electron Defects of Photovoltaic Cells in Examples and Comparative Examples

[0064] Grouping Example Comparative Example <![CDATA[E ta (%)]]> 25.75 25.72 <![CDATA[U oc (V)]]> 0.7305 0.7300 <![CDATA[I sc (A)]]> 13.750 13.745 FF (%) 85.10 85.10 <![CDATA[R s (Oh)]]> 0.95 0.90 <![CDATA[R sh (Oh)]]> 3000 3500 <![CDATA[I rev2 (A)]]> 0.08 0.05 EL defect rate 0.50％ 0.70％

[0065] (Note: (1)E ta For photoelectric conversion efficiency, U oc Open circuit voltage, I sc Where is the short-circuit current, FF is the fill factor, and R is the short-circuit current. s For series resistor, R sh For parallel resistors, I rev2 (2) The data in the table are the average values ​​of different electrical properties of a certain number of example photovoltaic cells and a certain number of comparative photovoltaic cells, respectively.

[0066] As can be seen from the results in Table 1, compared with the photovoltaic cells prepared by the photovoltaic cell preparation method in the comparative example, the photovoltaic cells prepared by the photovoltaic cell preparation method provided in this embodiment have lower data such as parallel resistance and EL defect rate than the comparative example, while the photoelectric conversion efficiency and reverse current are higher than the comparative example. This shows that the photovoltaic cell preparation method of this embodiment can effectively improve the photoelectric conversion efficiency and yield of photovoltaic cells.

[0067] Compared with the prior art, the photovoltaic cell fabrication method provided in this embodiment achieves at least the following beneficial effects:

[0068] The photovoltaic cell fabrication method provided in this embodiment includes the following steps: providing a silicon wafer with amorphous silicon layers on both sides, the two sides including a first side and a second side arranged opposite to each other; growing a barrier layer on both sides of the silicon wafer simultaneously to obtain a silicon wafer with a barrier layer; performing a diffusion treatment on the silicon wafer with the barrier layer to transform the amorphous silicon layer of the silicon wafer with the barrier layer into a polycrystalline silicon layer to obtain a silicon wafer with a polycrystalline silicon layer; processing the silicon wafer with the polycrystalline silicon layer to remove the barrier layer and the polycrystalline silicon layer on the first side, and removing the barrier layer on the second side to obtain a photovoltaic cell; by adopting the above scheme, the diffusion rate of phosphorus atoms is kept consistent through the barrier layer, improving the doping uniformity of phosphorus atoms in the polycrystalline silicon layer, and the photovoltaic cell prepared by this method has a significantly improved photoelectric conversion efficiency and yield.

[0069] In one optional embodiment, the barrier layer 20 is grown simultaneously on the first side 01 and the second side 02 of the silicon wafer 00, including the growth of the barrier layer 20 by diffusion method, wherein the oxygen flow rate is in the range of 10000sccm-30000sccm and the temperature range is 600℃-700℃.

[0070] Specifically, refer to Figure 2 As shown, a silicon wafer 00 with amorphous silicon layers 10 on both sides is placed in a diffusion furnace. The furnace tube is purged with a clean gas (such as nitrogen N2) to ensure that there is no residual gas from the previous step. Then, oxygen (O2) is introduced to simultaneously grow a barrier layer 20 on the first side 01 and the second side 02 of the silicon wafer 00. This includes growing a first barrier layer 201 on the first side 01 and a second barrier layer 202 on the second side 02. The barrier layer 20 is composed of silicon dioxide. The oxygen flow rate is in the range of 10000 sccm-30000 sccm, the temperature range is 600℃-700℃, and the pressure is 0.1 MPa (i.e., atmospheric pressure).

[0071] If the oxygen flow rate is less than 10,000 sccm, a dense barrier layer 20 of sufficient thickness cannot be formed. If the oxygen flow rate is greater than 30,000 sccm, there is no significant room for improvement in the atmosphere concentration inside the pipe, resulting in material waste. Therefore, setting the oxygen flow rate range to 10,000 sccm-30,000 sccm not only avoids the problem of not being able to form a dense barrier layer 20 of sufficient thickness, but also avoids the problems of no significant room for improvement in the atmosphere concentration inside the pipe and material waste. Specifically, the oxygen flow rate can be 10,000 sccm. The temperature range is 600℃-700℃. Temperatures below 600℃ can lead to incomplete reactions, while temperatures above 700℃ cannot guarantee the safety of the reaction. Therefore, setting the temperature range to 600℃-700℃ not only avoids incomplete reactions but also ensures the safety of the reaction. Specifically, the temperatures can be 600℃, 620℃, 640℃, 660℃, 680℃, or 700℃.

[0072] In one alternative embodiment, during the diffusion process of the silicon wafer 00 forming the barrier layer 20, the diffusion source is phosphorus oxychloride.

[0073] Specifically, refer to Figure 2 As shown, phosphorus oxychloride (POCl3) has strong volatility, which ensures a fast diffusion rate. In addition to phosphorus oxychloride, other diffusion sources containing phosphorus atoms can also be used, which are not limited here.

[0074] Figure 3 This is a flowchart of the process for processing a silicon wafer with a polycrystalline silicon layer provided by the present invention; Figure 4 This is a flowchart of the chain device provided by the present invention; Figure 5 This is a flowchart of the tank-type equipment provided by the present invention. In an optional embodiment, processing a silicon wafer 00 having a polysilicon layer 11 includes the following steps:

[0075] S4-1: Use acidic liquid to remove the barrier layer 20 on the first surface 01;

[0076] Specifically, in combination Figures 2-4As shown, the removal of the first barrier layer 201 on the first surface 01 can be carried out in a chain-type equipment. The production line of this equipment sequentially includes feeding, water film, pickling tank, washing tank, drying tank, and unloading. In the pickling tank, an acidic liquid is placed to remove the first barrier layer 201 on the first surface 01. The acidic liquid can be a hydrogen fluoride (HF) solution with a concentration range of 7%-10%. If the concentration of the hydrogen fluoride solution is less than 7%, the first barrier layer 201 on the first surface 01 cannot be completely removed. If the concentration of the hydrogen fluoride solution is greater than 10%, it is easy to damage the structure of the doped layer 40 on the first surface 01. Therefore, setting the concentration range of the hydrogen fluoride solution to 7%-10% not only avoids the problem of not being able to completely remove the first barrier layer 201 on the first surface 01, but also avoids the problem of damaging the structure of the doped layer 40 on the first surface 01. Specifically, the concentration of the hydrogen fluoride solution can be 7%, 7.5%, 8%, 8.5%, 9%, 9.5%, or 10%. The working conditions and materials used in other production lines are all existing technologies in this field and are not limited here.

[0077] S4-2: Use an alkaline liquid to remove the polycrystalline silicon layer 11 on the first surface 01.

[0078] S4-3: Use an acidic liquid to remove the barrier layer 20 on the second surface 02.

[0079] Specifically, in combination Figures 2-3 , Figure 5 As shown, steps S4-2 and S4-3 can be performed sequentially in a set of tank equipment. The production line of this equipment includes feeding, alkaline etching tank, first water washing tank, first alkaline washing tank, second water washing tank, first acid washing tank, third water washing tank, second alkaline washing tank, fourth water washing tank, second acid washing tank, fifth water washing tank, slow lifting, drying tank, and unloading.

[0080] Step S4-2 is performed in the alkaline etching bath: the first polycrystalline silicon layer 111 on the first surface 01 is removed using an alkaline liquid. The alkaline liquid includes sodium hydroxide (NaOH) solution and an etching additive (ADD). The concentration of the sodium hydroxide solution ranges from 8% to 12%. If the concentration of the sodium hydroxide solution is less than 8%, the first polycrystalline silicon layer 111 cannot be completely removed; if the concentration of the sodium hydroxide solution is greater than 12%, the reaction rate will be reduced. Therefore, setting the concentration range of the sodium hydroxide solution to 8%-12% not only avoids the problem of not being able to completely remove the first polycrystalline silicon layer 111, but also avoids the problem of reducing the reaction rate. Specifically, the concentration of the sodium hydroxide solution can be 8%, 9%, 10%, 11%, or 12%. The role of the etching additive ADD is to slow down the reaction, making the reaction between the silicon wafer 00 surface and the alkaline liquid more mild. The amount of etching additive ADD can be adjusted adaptively according to the concentration of the sodium hydroxide solution. In the first pickling tank, step S4-3 involves using an acidic liquid to remove the second barrier layer 202 on the second surface 02. The acidic liquid includes a hydrogen fluoride solution and an auxiliary agent (such as ADD). The concentration of the hydrogen fluoride solution ranges from 8% to 12%. If the concentration is less than 8%, the barrier layer 202 cannot be completely removed; if the concentration is greater than 12%, the second polycrystalline silicon layer 112 on the second surface 02 will be damaged. Therefore, setting the concentration range of the hydrogen fluoride solution to 8%-12% not only avoids the problem of not being able to completely remove the second barrier layer 202 but also avoids the problem of damaging the second polycrystalline silicon layer 112 on the second surface 02. Specifically, the concentration of the hydrogen fluoride solution can be 8%, 9%, 10%, 11%, or 12%. The auxiliary agent ADD slows down the reaction, making the reaction between the silicon wafer 00 surface and the acidic liquid more mild. The amount of auxiliary agent ADD can be adjusted adaptively according to the concentration of the hydrogen fluoride solution. Other operating conditions and materials used in other production lines are existing technologies in the field and are not limited here.

[0081] Figure 6 This is a flowchart of an optional implementation method for obtaining a silicon wafer with amorphous silicon layers on both sides, provided by the present invention; Figure 7 This is a flowchart of the flocking process provided by the present invention; Figure 8 yes Figure 6 The flowchart for obtaining a silicon wafer with amorphous silicon layers on both sides; Figure 9 This is a flowchart of the etching process provided by the present invention. In an optional embodiment, the method for preparing a silicon wafer 00 with amorphous silicon layers 10 on both sides includes texturing, first diffusion, laser treatment, second diffusion, etching, and growth of a protective layer.

[0082] Specifically, in combination Figures 6-8 As shown, S0-1: Texturing, including the following steps:

[0083] S0-1-1: Etching of silicon wafer 00: The method is to immerse silicon wafer 00 in a tank-type equipment. The process parameters include: potassium hydroxide (KOH) solution with a volume concentration of 8%-10%, additive with a volume of 4L-6L, temperature of 65℃, time range of 350s-400s, and volume ratio of potassium hydroxide solution to additive of 150:1.

[0084] Specifically, if the volume concentration of potassium hydroxide solution is less than 8%, a textured structure cannot be formed on the surface of silicon wafer 00. If the volume concentration of potassium hydroxide solution is greater than 10%, the textured structure formed is too high, affecting the light absorption of silicon wafer 00. Therefore, setting the volume concentration range of potassium hydroxide solution to 8%-10% not only avoids the problem of not being able to form a textured structure on the surface of silicon wafer 00, but also avoids the problem of the textured structure being too high, affecting the light absorption of silicon wafer 00. Specifically, the volume concentration of potassium hydroxide solution can be 8%, 8.5%, 9%, 9.5%, or 10%. If the volume of additive is less than 4L, it cannot accelerate the etching rate of silicon wafer 00. If the volume of additive is greater than 6L, it actually reduces the etching rate of silicon wafer 00. Therefore, setting the volume range of additive to 4L-6L not only avoids the problem of not being able to accelerate the etching rate of silicon wafer 00, but also avoids the problem of the etching rate of silicon wafer 00 decreasing. Specifically, the volume of additive can be 4L, 4L, or 6L. 5L, 5L, 5.5L, or 6L; if the time is less than 350s, there is not enough time to form a complete textured surface; if the time is greater than 400s, the textured surface will be too thick, affecting the light absorption of the silicon wafer 00. Therefore, setting the time range to 350s-400s can not only avoid the problem of insufficient time to form a complete textured surface, but also avoid the problem of the textured surface being too thick, affecting the light absorption of the silicon wafer 00. Specifically, the time can be 350s, 365s, 380s, 395s, or 400s; if the volume ratio of potassium hydroxide solution to additive is less than 150:1, the silicon wafer 00 is easily not cleaned properly; if the volume ratio of potassium hydroxide solution to additive is greater than 150:1, the additive cannot play a good desorption role. Therefore, setting the volume ratio of potassium hydroxide solution to additive to 150:1 can not only avoid the problem of the silicon wafer 00 not being cleaned properly, but also avoid the problem of the additive not playing a good desorption role.

[0085] Silicon wafer 00 refers to a clean N-type monocrystalline silicon wafer that has been free of surface metal contaminants, surface organic films, impurity ions, and other impurities. Its cleaning methods, structure, and dimensions are all existing technologies in this field and will not be described in detail here.

[0086] The silicon wafer 00 includes a first surface 01 and a second surface 02 arranged opposite to each other. After texturing, the silicon wafer 00 forms a pyramid-shaped texture on both the first surface 01 and the second surface 02, also known as a textured surface (not shown in the figure). The textured surface has a light-trapping effect, which can reduce the reflectivity of the first surface 01 and the second surface 02 of the silicon wafer 00 to below 10%, thereby improving the short-circuit current of the photovoltaic cell and its photoelectric conversion efficiency.

[0087] S0-1-2: First water wash of the etched silicon wafer 00: Immerse and rinse the silicon wafer 00 in the tank equipment with flowing deionized water to avoid residual liquid adhering to the silicon wafer 00 during the texturing process from affecting the normal operation of the next process.

[0088] S0-1-3: Post-cleaning of silicon wafer 00 after the first water wash: The silicon wafer 00 in the tank equipment is immersed and rinsed with a flowing chemical solution. The process parameters include: 3% hydrogen peroxide (H2O2) solution and 5% ozone (O3) solution.

[0089] S0-1-4: Acid washing of silicon wafer 00 after post-cleaning: Immerse and rinse silicon wafer 00 in the tank equipment using a flowing chemical solution. The process parameters include: 10% hydrogen fluoride solution and 7% hydrochloric acid (HCl) solution.

[0090] S0-1-5: Perform a second water wash on the pickled silicon wafer 00: Immerse and rinse the silicon wafer 00 in the tank equipment with flowing deionized water to avoid residual liquid adhering to the silicon wafer 00 during the pickling process from affecting the normal operation of the next process.

[0091] S0-1-6: Slowly lift the silicon wafer 00 after the second water wash: slowly lift the basket carrying the silicon wafer 00 out of the water washing tank so that the liquid adhering to the silicon wafer 00 flows out without residue, ensuring that there are no watermarks on the surface of the silicon wafer.

[0092] S0-1-7: Drying the silicon wafer 00 after slow pulling: The method is drying in a drying oven, and the process parameters include: temperature 80℃; the structure of the dried silicon wafer 00 is as follows. Figure 8 As shown in (A), the velvet side is not shown.

[0093] Continue to combine Figure 6 and Figure 8As shown, S0-2: The first diffusion process includes diffusion in a diffusion furnace using boron trichloride (BCl3) as the diffusion source, so that the first surface 01 and the second surface 02 simultaneously form a borosilicate glass layer 50. The borosilicate glass layer 50 includes a first borosilicate glass layer 501 and a second borosilicate glass layer 502, wherein the first surface 01 forms the first borosilicate glass layer 501, and the second surface 02 forms the second borosilicate glass layer 502. The structure of the silicon wafer 00 after forming the borosilicate glass layer 50 is as follows. Figure 8 As shown in (B), the process parameters include: the flow rate of boron trichloride is 200 sccm-350 sccm, the flow rate of nitrogen is 2000 sccm-3000 sccm, the flow rate of oxygen is 600 sccm-1000 sccm, the temperature is 860℃-960℃, and the time is 1400 s.

[0094] If the flow rate of boron trichloride is less than 200 sccm, the borosilicate glass layer 50 cannot be formed; if the flow rate is greater than 350 sccm, it is wasteful of resources. Therefore, setting the flow rate range of boron trichloride to 200-350 sccm not only avoids the problem of not being able to form the borosilicate glass layer 50, but also avoids the problem of wasted resources. Specifically, the flow rate range of boron trichloride can be 200 sccm, 240 sccm, 280 sccm, 320 sccm, or 350 sccm; if the flow rate of nitrogen... If the nitrogen flow rate is less than 2000 sccm, the source pressure is insufficient. If the nitrogen flow rate is greater than 3000 sccm, the boron trichloride gas becomes too rarefied, resulting in incomplete reaction. Therefore, setting the nitrogen flow rate range to 2000-3000 sccm not only avoids the problem of insufficient source pressure but also avoids the problem of insufficient boron trichloride gas and incomplete reaction. Specifically, the nitrogen flow rate range can be 2000 sccm, 2200 sccm, 2400 sccm, 2600 sccm, 2800 sccm, or 3000 sccm. If the oxygen flow rate is less than 600 sccm, the oxygen as a reactant gas becomes too rarefied, resulting in incomplete reaction. If the oxygen flow rate is greater than 1000 sccm, excessive borosilicate glass is easily generated. Therefore, setting the oxygen flow rate range to 600-1000 sccm not only avoids the problem of insufficient oxygen as a reactant gas and incomplete reaction but also avoids the generation of excessive borosilicate glass. Specifically, the oxygen flow rate range can be 600 sccm... The reaction temperature range is 700 sccm, 800 sccm, 900 sccm, or 1000 sccm. If the temperature is below 860℃, the reaction temperature is too low and the reaction is not complete. If the temperature is above 960℃, an excessive amount of borosilicate glass is easily generated. Therefore, setting the temperature range to 860℃-960℃ can not only avoid the problem of insufficient reaction due to low reaction temperature, but also avoid the generation of excessive borosilicate glass. Specifically, the temperature can be 860℃, 880℃, 900℃, 920℃, 940℃, or 960℃.

[0095] Continue to combine Figure 6 and Figure 8 As shown, S0-3: Laser, including irradiating a portion of the first borosilicate glass layer 501 on the first surface 01 with a laser device, causing boron atoms in a portion of the first borosilicate glass layer 501 to diffuse into the silicon wafer 00, forming a P++ heavily doped layer 41. The process parameters include: laser power of 55W, laser speed of 15000mm / s, laser frequency of 55kHz, and laser wavelength of 850nm; (Refer to...) Figure 8 (B)- Figure 8 As shown in (C), the first borosilicate glass layer 501 irradiated by the laser is region A, and a P++ heavily doped layer 41 is formed on a portion of the silicon wafer 00 corresponding to region A.

[0096] Continue to combine Figure 6 and Figure 8 As shown, S0-4: The second diffusion process includes high-temperature oxidation propulsion using a diffusion furnace with oxygen flow, which allows some boron atoms in the first borosilicate glass layer 501 to diffuse into the silicon wafer 00, forming a P+ doped layer 42. The process parameters include: oxygen flow rate range of 10000 sccm-28000 sccm, nitrogen flow rate range of 10000 sccm-15000 sccm, propulsion temperature of 1000℃, and time of 3500s.

[0097] If the oxygen flow rate is less than 10,000 sccm, the P+ doped layer 42 cannot be formed; if the oxygen flow rate is greater than 28,000 sccm, it is wasteful of resources. Therefore, setting the oxygen flow rate range to 10,000 sccm-28,000 sccm not only avoids the problem of not being able to form the P+ doped layer 42, but also avoids the problem of wasted resources. Specifically, the oxygen flow rate range can be 10,000 sccm, 15,000 sccm, 10,000 sccm, 250,000 sccm, or 28,000 sccm; if the nitrogen flow rate is less than 10,000 sccm... If the nitrogen flow rate is greater than 15000 sccm, the resulting pn junction will be too shallow. If the nitrogen flow rate is greater than 15000 sccm, the resulting pn junction will be too deep, affecting the power generation quality. Therefore, setting the nitrogen flow rate range to 10000 sccm-15000 sccm can not only avoid the problem of the resulting pn junction being too shallow, but also avoid the problem of the resulting pn junction being too deep and affecting the power generation quality. Specifically, the nitrogen flow rate range can be 10000 sccm, 11000 sccm, 12000 sccm, 13000 sccm, 14000 sccm, or 15000 sccm.

[0098] Reference Figure 8 (B)- Figure 8 As shown in (D), the first borosilicate glass layer 501 that is not irradiated by the laser is region B. A portion of the silicon wafer 00 corresponding to region B forms a P+ doped layer 42. The P+ doped layer 42 and the P++ heavily doped layer 41 constitute the entire doped layer 40. Along the illumination direction X, the depth of the P+ doped layer 42 is less than the depth of the P++ heavily doped layer 41. Unlike the P+ doped layer 42, the P++ heavily doped layer 41 is used to correspond to the position of the subsequent printed gate lines, ensuring that the electrode formed during sintering can form a good ohmic contact with the entire doped layer 40, thus ensuring the photoelectric conversion efficiency of the photovoltaic cell.

[0099] Combination Figure 6 , Figure 8 and Figure 9 As shown, S0-5: Etching, including the following steps:

[0100] S0-5-1: Etching the first surface 01 and the second surface 02 to remove the first borosilicate glass layer 501 on the first surface 01 and the second borosilicate glass layer 502 on the second surface 02: The method is to etch the first surface 01 and the second surface 02 in a chain etching machine. The process parameters include: a hydrogen fluoride solution with a volume concentration of 10% and a conveyor belt speed range of 3.5m / min-4.5m / min.

[0101] If the conveyor belt speed is less than 3.5 m / min, it wastes time; if the conveyor belt speed is greater than 4.5 m / min, it cannot guarantee that the first borosilicate glass layer 501 and the second borosilicate glass layer 502 will be completely removed. Therefore, setting the conveyor belt speed range to 3.5 m / min-4.5 m / min not only avoids the problem of wasting time, but also avoids the problem of not being able to completely remove the first borosilicate glass layer 501 and the second borosilicate glass layer 502. Specifically, the conveyor belt speed can be 3.5 m / min, 3.7 m / min, 3.9 m / min, 4.1 m / min, 4.3 m / min or 4.5 m / min.

[0102] S0-5-2: Polish the corroded second surface 02 to remove the fuzzy surface on the second surface 02: The method is to polish the second surface 02 in a tank-type equipment. The process parameters include: a potassium hydroxide solution with a volume concentration of 3.5%-4.5%, an additive with a volume of 4L-6L, a temperature of 65℃, an immersion time range of 150s-200s, and a volume ratio of potassium hydroxide solution to additive of 94:1.

[0103] Specifically, if the volume concentration of the potassium hydroxide solution is less than 3.5%, the textured surface cannot be completely removed; if the volume concentration is greater than 4.5%, it will damage the silicon wafer. Therefore, setting the volume concentration of the potassium hydroxide solution within the range of 3.5%-4.5% not only avoids the problem of incomplete texture removal but also avoids damage to the silicon wafer. Specifically, the volume concentration of the potassium hydroxide solution can be 3.5%, 3.7%, 3.9%, 4.1%, 4.3%, or 4.5%. If the volume of the additive is less than 4L, it cannot promote the etching of the textured surface by the potassium hydroxide solution; if the volume of the additive is greater than 6L, it reduces the etching ability of the potassium hydroxide solution on the textured surface. Therefore, setting the volume of the additive within the range of 4L-6L not only avoids the problem of insufficient promotion of the etching effect of the potassium hydroxide solution on the textured surface but also avoids reducing the etching ability of the potassium hydroxide solution on the textured surface. The issue of corrosion resistance; specifically, the volume of the additive can be 4L, 4.5L, 5L, 5.5L, or 6L; if the time is less than 150s, the textured surface cannot be completely removed; if the time is greater than 200s, the silicon wafer 00 will be damaged. Therefore, setting the time range to 150s-200s not only avoids the problem of not being able to completely remove the textured surface, but also avoids the problem of damaging the silicon wafer 00; specifically, the time can be 150s, 165s, 180s, 195s, or 200s; if the volume ratio of potassium hydroxide solution to additive is less than 94:1, it is easy to cause additive residue contamination; if the volume ratio of potassium hydroxide solution to additive is greater than 94:1, the first surface 01 cannot be protected. Therefore, setting the volume ratio of potassium hydroxide solution to additive to 94:1 not only avoids the problem of additive residue contamination, but also avoids the problem of not being able to protect the first surface 01.

[0104] It should be noted that the above descriptions are as follows: Figure 8 The method for preparing a silicon wafer 00 with amorphous silicon layers 10 on both sides in the embodiment shown includes the equipment, reactants and their dosage parameters. In other embodiments, the equipment, reactants and their dosage parameters can be adjusted according to the actual situation, and are not limited here.

[0105] Figure 10 This is a flowchart of the growth protective layer provided by the present invention. In an optional embodiment, the growth protective layer includes the following steps:

[0106] S0-6-1: A tunnel oxide layer 30 is grown on the second side 02 of the etched silicon wafer 00.

[0107] Specifically, in combination Figure 8 and Figure 10 As shown, the tunneling oxide layer 30 is grown using a high-temperature oxidation method, and the structure of the silicon wafer 00 after forming the tunneling oxide layer 30 is as follows. Figure 8As shown in (F), the tunneling oxide layer 30 can be a silicon dioxide layer, and the thickness of the tunneling oxide layer 30 ranges from 1 nm to 2 nm. If the thickness of the tunneling oxide layer 30 is less than 1 nm, the tunneling oxide layer 30 is too thin, which affects the passivation effect of the photovoltaic cell. If the thickness of the tunneling oxide layer 30 is greater than 2 nm, the tunneling oxide layer 30 is too thick, which affects the tunneling effect of the charge carriers. Therefore, setting the thickness range of the tunneling oxide layer 30 to 1 nm to 2 nm can not only avoid affecting the passivation effect of the photovoltaic cell, but also avoid affecting the tunneling effect of the charge carriers. Specifically, the thickness of the tunneling oxide layer 30 can be 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, or 2 nm.

[0108] S0-6-2: After growing the tunnel oxide layer 30, amorphous silicon layers 10 are grown on both the first side 01 and the second side 02 of the silicon wafer 00, resulting in a silicon wafer 00 with amorphous silicon layers 10 on both sides.

[0109] Specifically, in combination Figure 8 and Figure 10 As shown, an amorphous silicon layer 10 is deposited on both the first surface 01 and the second surface 02 using a thermal decomposition method. The amorphous silicon layer 10 includes a first amorphous silicon layer 101 and a second amorphous silicon layer 102. Specifically, the first amorphous silicon layer 101 is deposited on the first surface 01, and the second amorphous silicon layer 102 is deposited on the second surface. The structure of the silicon wafer 00 after double-sided growth of the amorphous silicon layers 10 is as follows. Figure 8 (G) or as Figure 2 As shown in (a), the thickness of the amorphous silicon layer 10 ranges from 30 nm to 150 nm.

[0110] If the thickness of the amorphous silicon layer 10 is less than 30nm, it will lead to greater difficulty in subsequent doping and metallization matching. If the thickness of the amorphous silicon layer 10 is greater than 150nm, the light absorption of the amorphous silicon layer 10 will be severe, affecting the photoelectric conversion efficiency of the photovoltaic cell. Therefore, setting the thickness range of the amorphous silicon layer 10 to 30nm-150nm can not only avoid the problems of greater difficulty in subsequent doping and metallization matching, but also avoid the problem of severe light absorption of the amorphous silicon layer 10 affecting the photoelectric conversion efficiency of the photovoltaic cell. Specifically, the thickness of the amorphous silicon layer 10 can be 30nm, 60nm, 90nm, 120nm or 150nm.

[0111] Figure 11 This is a flowchart of the process of processing a silicon wafer with a polycrystalline silicon layer provided by the present invention; Figure 12 yes Figure 11 The flowchart for obtaining a photovoltaic cell is shown. In an optional embodiment, the process of processing a silicon wafer 00 having a polycrystalline silicon layer 11 includes the following steps: passivation, coating, screen printing, and sintering.

[0112] Specifically, in combination Figure 11 and Figure 12 As shown, S5: passivation, including the deposition of an aluminum oxide layer 60 on the first surface 01 using thermal atomic layer deposition (ALD). The structure of the passivated silicon wafer 00 is as follows. Figure 12 As shown in (e), its process parameters include: temperature of 260℃ and deposition thickness of 4nm; the function of the alumina layer 60 includes: fixing negative charge, eliminating parasitic capacitance effect and improving passivation effect.

[0113] Combination Figure 11 and Figure 12 As shown, S6: Coating, including forming at least one antireflection layer 70 on both the first surface 01 and the second surface 02 using plasma chemical vapor deposition (PECVD). The antireflection layer 70 includes a first antireflection layer 701 and a second antireflection layer 702, wherein at least one first antireflection layer 701 is formed on the first surface 01 and at least one second antireflection layer 702 is formed on the second surface 02. The structure of the silicon wafer 00 after coating is as follows. Figure 12 As shown in (f), the process parameters include: ammonia to silicon tetrahydrogen 4:1-10:1 volume ratio, temperature range of 480℃-550℃, and pressure of 210Pa.

[0114] If the volume ratio of ammonia to silicon tetrahydrode is less than 4:1, the resulting antireflective layer 70 has an excessively high refractive index, which is detrimental to passivation. If the volume ratio is greater than 10:1, the resulting antireflective layer 70 has an excessively low refractive index. Therefore, setting the volume ratio of ammonia to silicon tetrahydrode to 4:1-10:1 can avoid both the problem of an excessively high refractive index in the resulting antireflective layer 70, which is detrimental to passivation, and the problem of an excessively low refractive index. Specifically, the volume ratio of ammonia to silicon tetrahydrode can be 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1. If the temperature is less than 480℃... The antireflective layer 70 has low density and refractive index. If the temperature exceeds 550℃, the antireflective layer 70 is prone to cracking. Therefore, setting the temperature range to 480℃-550℃ not only avoids the problems of low density and refractive index of the antireflective layer 70, but also avoids the problem of cracking. Specifically, the temperature can be 480℃, 495℃, 510℃, 525℃, 540℃, or 550℃. The functions of the antireflective layer 70 include: reducing light reflection, increasing light absorption, passivating the surface and bulk of the silicon wafer 00, improving the short-circuit current and open-circuit voltage of the photovoltaic cell, and improving the conversion efficiency of the photovoltaic cell.

[0115] Combination Figure 11 and Figure 12As shown, S7: screen printing, including printing metal paste on the first surface 01 and the second surface 02 respectively using a screen printing machine to obtain grid lines. The grid lines include main grids and fine grids. The main grids are used to collect current and provide sufficient tension, and the fine grids are used to collect the current generated by the photovoltaic cells. The printing sequence of the first surface 01 and the second surface 02 is to print the fine grid lines first and then print the main grids. Along the illumination direction X, the orthographic projection of the grid lines on the silicon wafer 00 overlaps at least partially with the orthographic projection of the P++ heavily doped layer 41 on the silicon wafer 00.

[0116] The first side 01 can be printed with silver-aluminum paste, and the second side 02 can be printed with silver paste. The materials of the paste that can be selected include, but are not limited to, these. The purpose of screen printing is to prepare electrodes. After the metal paste is sintered, it forms a front electrode (also known as the upper electrode or front electrode) and a back electrode (also known as the lower electrode or bottom electrode) on the surface of the battery. The current of the photovoltaic cell is collected and transported through these electrodes.

[0117] Combination Figure 11 and Figure 12 As shown, S8: Sintering, which includes feeding the silicon wafer 00 into a sintering furnace for sintering, so that the gate lines penetrate multiple film layers to form an electrode 80. The electrode 80 includes a first electrode 801 and a second electrode 802, wherein the first electrode 801 is formed on the first surface 01 and the second electrode 802 is formed on the second surface 02. The structure of the sintered silicon wafer 00 is as follows. Figure 12 As shown in (g), its process parameters include a temperature range of 750-880℃;

[0118] If the temperature is below 750℃, the series resistance of the sintered photovoltaic cells is likely to increase. If the temperature is above 800℃, the parallel resistance of the sintered photovoltaic cells is likely to decrease. Therefore, setting the temperature range to 750℃-800℃ can not only avoid the problem of increased series resistance of the sintered photovoltaic cells, but also avoid the problem of decreased parallel resistance. Specifically, the temperature can be 750℃, 785℃, 810℃, 845℃, or 880℃.

[0119] The purposes of sintering include: forming good ohmic contact between the grid lines and the photovoltaic cell structure, and forming a back surface field on the photovoltaic cell surface.

[0120] It should be noted that the above descriptions are as follows: Figure 12 The steps in the embodiment shown for processing the silicon wafer 00 with the polycrystalline silicon layer 11 include the equipment used, the reactants and their quantities, etc. In other embodiments, the equipment used, the reactants and their quantities, etc., can be adjusted adaptively according to the actual situation, and are not limited here.

[0121] In one alternative embodiment, growing a tunneling oxide layer 30 on the second side 02 of the etched silicon wafer 00 includes growing the tunneling oxide layer 30 by an oxidation method, wherein the oxygen flow rate is in the range of 30000 sccm-38000 sccm and the temperature range is 580°C-620°C.

[0122] Specifically, refer to Figure 8 As shown, the process parameters include: oxygen flow rate range of 30000sccm-38000sccm, and temperature range of 580℃-620℃.

[0123] If the oxygen flow rate is less than 30,000 sccm, a tunneling oxide layer 30 cannot be formed. If the oxygen flow rate is greater than 38,000 sccm, the formed tunneling oxide layer 30 will be too thick, affecting the tunneling effect of the charge carriers. Therefore, setting the oxygen flow rate range to 30,000 sccm-38,000 sccm not only allows for the normal formation of the tunneling oxide layer 30 but also avoids the problem of an excessively thick tunneling oxide layer 30 affecting the tunneling effect of the charge carriers. Specifically, the oxygen flow rate can be 30,000 sccm or 32,000 sccm. The temperature range is 580℃-620℃. If the temperature is below 580℃, the reaction rate is too slow and time is wasted. If the temperature is above 620℃, the growth rate of the tunneling oxide layer 30 is too fast and difficult to control. Therefore, setting the temperature range to 580℃-620℃ can not only avoid the problem of slow reaction rate and wasted time, but also avoid the problem of excessively fast growth rate of the tunneling oxide layer 30 and difficulty in control. Specifically, the temperature can be 580℃, 590℃, 600℃, 610℃ or 620℃.

[0124] In one optional embodiment, growing an amorphous silicon layer 10 on both the first side 01 and the second side 02 of the silicon wafer 00 after growing the tunnel oxide layer 30 includes growing the amorphous silicon layer 10 by decomposition, wherein the flow rate of silicon tetrahydrogen 10 is in the range of 1300 sccm-1700 sccm and the temperature is in the range of 590°C-610°C.

[0125] Specifically, refer to Figure 8 As shown, the process parameters include: a flow rate range of 1300 sccm-1700 sccm for silicon tetrahydrogenate and a temperature range of 590℃-610℃.

[0126] If the flow rate of silicon tetrahydrogen hydride is less than 1300 sccm, a suitable amorphous silicon layer 10 cannot be formed; if the flow rate is greater than 1700 sccm, it will be wasteful of resources. Therefore, setting the flow rate of silicon tetrahydrogen hydride in the range of 1300 sccm-1700 sccm not only avoids the problem of not being able to form a suitable amorphous silicon layer 10, but also avoids the problem of wasted resources. Specifically, the flow rate of silicon tetrahydrogen hydride can be 1300 sccm, 1400 sccm, 1500 sccm, 1600 sccm, or 1700 sccm. The temperature range is 590℃-610℃. If the temperature is below 590℃, the reaction rate is too slow and time is wasted. If the temperature is above 610℃, the growth rate of the amorphous silicon layer 10 is too fast and difficult to control. Therefore, setting the temperature range to 590℃-610℃ can not only avoid the problem of slow reaction rate and wasted time, but also avoid the problem of excessively fast growth rate of the amorphous silicon layer 10 and difficulty in control. Specifically, the temperature can be 590℃, 595℃, 600℃, 605℃ or 610℃.

[0127] Figure 13 This is a schematic diagram of the structure of the photovoltaic cell provided by the present invention. This embodiment also provides a photovoltaic cell 100, comprising a photovoltaic cell prepared by any of the photovoltaic cell preparation methods described above.

[0128] Specifically, in combination Figure 1 and Figure 13 As shown, the photovoltaic cell 100 prepared by the above-mentioned photovoltaic cell passivation method has the following structure: the photovoltaic cell 100 includes a first region 110 and a second region 120 arranged alternately along the second direction Y, which is perpendicular to the illumination direction X. Based on a silicon wafer 00, the front first region 110 includes, from the inside out, a P+ doped layer 42, an aluminum oxide layer 60, and a first antireflection layer 701. The back first region 110 includes, from the inside out, a tunneling oxide layer 30, a polycrystalline silicon layer 11, and a second antireflection layer 702. The front second region 120 includes, from the inside out, a P++ heavily doped layer 41 and a first electrode 801. The back second region 120 includes, from the inside out, a tunneling oxide layer 30, a second polycrystalline silicon layer 112, and a second electrode 802. The photovoltaic cell 100 provided in this embodiment can be a TOPCon cell. Photovoltaic cells prepared using any of the above-mentioned photovoltaic cell preparation methods exhibit better phosphorus atom doping uniformity in the polycrystalline silicon layer, resulting in significantly improved photoelectric conversion efficiency and yield.

[0129] As can be seen from the above embodiments, the photovoltaic cell and its preparation method provided by the present invention achieve at least the following beneficial effects:

[0130] The present invention provides a photovoltaic cell and a method for preparing the same. The method includes the following steps: providing a silicon wafer with amorphous silicon layers on both sides, the two sides including a first side and a second side disposed opposite to each other; simultaneously growing a barrier layer on the first side and the second side of the silicon wafer to obtain a silicon wafer with a barrier layer; subjecting the silicon wafer with the barrier layer to diffusion treatment, transforming the amorphous silicon layer of the silicon wafer with the barrier layer into a polycrystalline silicon layer, to obtain a silicon wafer with a polycrystalline silicon layer; processing the silicon wafer with the polycrystalline silicon layer to remove the barrier layer and the polycrystalline silicon layer on the first side, and removing the barrier layer on the second side to obtain a photovoltaic cell. By adopting the above scheme, the diffusion rate of phosphorus atoms is kept consistent through the barrier layer, improving the doping uniformity of phosphorus atoms in the polycrystalline silicon layer. At the same time, the photovoltaic cell prepared by this method has significantly improved photoelectric conversion efficiency and yield.

[0131] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that these examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A method for preparing a photovoltaic cell, characterized in that, Includes the following steps: A silicon wafer with amorphous silicon layers on both sides is provided, wherein the two sides include a first side and a second side disposed opposite to each other; A barrier layer is grown simultaneously on the first and second sides of the silicon wafer to obtain a silicon wafer with a barrier layer, including growing the barrier layer by diffusion method, wherein the oxygen flow rate is in the range of 10000 sccm-30000 sccm and the temperature range is 600℃-700℃. The silicon wafer forming the barrier layer is subjected to a diffusion process, and the amorphous silicon layer of the silicon wafer forming the barrier layer is transformed into a polycrystalline silicon layer, thereby obtaining a silicon wafer with a polycrystalline silicon layer. The silicon wafer with the polycrystalline silicon layer is processed by removing the barrier layer and polycrystalline silicon layer on the first side and removing the barrier layer on the second side to obtain a photovoltaic cell.

2. The photovoltaic cell preparation method according to claim 1, characterized in that, In the diffusion treatment of the silicon wafer forming the barrier layer, the diffusion source is phosphorus oxychloride.

3. The photovoltaic cell preparation method according to claim 1, characterized in that, The process of processing the silicon wafer having a polycrystalline silicon layer includes the following steps: The barrier layer on the first surface is removed using an acidic liquid; The polycrystalline silicon layer on the first surface is removed using an alkaline liquid; The barrier layer on the second side is removed using an acidic liquid.

4. The photovoltaic cell preparation method according to claim 1, characterized in that, The method for preparing the silicon wafer with amorphous silicon layers on both sides includes texturing, first diffusion, laser, second diffusion, etching, and growth of a protective layer.

5. The photovoltaic cell preparation method according to claim 4, characterized in that, The growth protective layer includes the following steps: A tunneling oxide layer is grown on the second side of the etched silicon wafer; After growing the tunnel oxide layer, amorphous silicon layers are grown on both the first and second sides of the silicon wafer to obtain a silicon wafer with amorphous silicon layers on both sides.

6. The photovoltaic cell preparation method according to claim 1, characterized in that, The process of processing the silicon wafer with the polycrystalline silicon layer includes the following steps: passivation, coating, screen printing, and sintering.

7. The photovoltaic cell preparation method according to claim 5, characterized in that, The growth of a tunneling oxide layer on the second side of the etched silicon wafer includes growing the tunneling oxide layer using an oxidation method, wherein the oxygen flow rate is in the range of 30000 sccm-38000 sccm and the temperature range is 580℃-620℃.

8. The photovoltaic cell preparation method according to claim 5, characterized in that, The growth of amorphous silicon layers on both the first and second sides of the silicon wafer after the growth of the tunneling oxide layer includes growing the amorphous silicon layer using a decomposition method, wherein the flow rate of silicon tetrahydrogen hydride is in the range of 1300 sccm-1700 sccm and the temperature range is 590℃-610℃.

9. A photovoltaic cell, characterized in that, The photovoltaic cell includes those prepared by the photovoltaic cell preparation method according to any one of claims 1-8.

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