Gate-all-around nanosheet devices with high hole mobility channels and methods of fabrication
By using a graphene sacrificial layer in gate-around stacked nanosheet devices, the hole mobility was improved, solving the problem of low hole mobility in traditional gate-around stacked SiNS CMOS devices and achieving performance enhancement of P-type devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2023-10-26
- Publication Date
- 2026-06-26
Smart Images
Figure CN117594447B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor devices, and in particular to a gate-around stacked nanosheet device with a high hole mobility channel and its fabrication method. Background Technology
[0002] As integrated circuit feature sizes continue to shrink, traditional triple-gate or dual-gate FinFETs are limited below 3nm. The gate-on-a-ring (GAA-FET), which is compatible with the mainstream high-k metal gate FinFET process, will be the next key structure for achieving size miniaturization. Its channel is mainly a stacked nanosheet structure.
[0003] In the traditional fabrication process of GAA-FET devices, alternating stacked layers of SiGe and Si are often epitaxially stacked. Si is the final nanosheet channel (NS channel). SiGe, as a sacrificial layer, can introduce channel stress. Since the lattice constant of SiGe is larger than that of Si, SiGe will apply tensile stress to the Si NS channel along the channel and perpendicular to the channel on the (100) plane. Such stress conditions will increase the electron mobility in the channel. However, one of the challenges faced by gate-around stacked Si NS CMOS devices is the low hole mobility in the (100) crystal orientation of the NS surface, which causes the performance of P-type devices to degrade.
[0004] Therefore, this invention is proposed. Summary of the Invention
[0005] The main objective of this invention is to provide a gate-surrounded stacked nanosheet device with a high hole mobility channel and its fabrication method, which improves hole mobility and can overcome the performance degradation problem of P-tubes.
[0006] To achieve the above objectives, the present invention provides the following technical solutions.
[0007] A first aspect of the present invention provides a method for fabricating a gate-surrounded stacked nanosheet device with a high hole mobility channel, comprising:
[0008] Provide substrate;
[0009] A superlattice stack of alternating silicon and graphene layers is formed on the surface of the substrate;
[0010] Etching a portion of the thickness of the superlattice stack and the substrate forms fins;
[0011] A first dielectric layer is formed on the substrate as a shallow trench isolation layer between the fins;
[0012] A false grid is formed on the fin, and a first sidewall is formed on the sidewall of the false grid;
[0013] The superlattice stack in the etched fins releases grooves to be formed for source and drain;
[0014] A second sidewall is formed on the sidewall of the superlattice stack in the fin;
[0015] Source and drain are formed in the epitaxial semiconductor material outside the groove;
[0016] Remove spurious barriers;
[0017] The graphene layer in the superlattice stack is etched away to release the nanosheet channels, and the stack formed by the nanosheets constitutes multiple conductive channels.
[0018] A surrounding gate is formed, which surrounds the stack formed by the nanosheet.
[0019] This invention uses graphene instead of the traditional germanium-silicon sacrificial layer. Since the lattice constant of graphene (0.246nm) is smaller than that of Si (0.543nm), it will generate compressive stress on Si on the (100) surface along the channel and perpendicular to the channel, thereby improving the hole mobility. When it is applied to P-tube devices, it can overcome the problem of P-tube performance degradation.
[0020] Furthermore, the graphene layer is formed by carbon molecular beam epitaxy.
[0021] The thickness of graphene layers can be controlled by adjusting the process conditions of carbon molecular beam epitaxy (CMBE), resulting in a single-layer graphene layer with a certain thickness.
[0022] Furthermore, when the superlattice stack in the etched fins releases the grooves to be formed for the source / drain, plasma etching is employed. Plasma etching has excellent isotropic etching effects on both Si and graphene, and is also effective on SiO2 and SiN. x Both have extremely high selectivity, so when using this method to release the source drain groove, it is easy to obtain a groove with a regular shape.
[0023] Furthermore, the plasma etching method employs at least one of O2 plasma and Ar plasma.
[0024] Furthermore, the first sidewall and the second sidewall are made of silicon nitride.
[0025] Furthermore, the method for etching away the graphene layer in the superlattice stack includes: removing the graphene layer using N-methylpyrrolidone.
[0026] N-methylpyrrolidone (NMP), a common organic solvent in semiconductor processes, is effective against Si and SiN₂. x SiO2 and other compounds have extremely high selectivity.
[0027] Furthermore, the gate-surrounded stacked nanosheet device is a P-type device. The low hole mobility is a significant problem when using traditional processes to fabricate P-type devices; therefore, the method of this invention is more suitable for fabricating P-type devices.
[0028] Furthermore, the graphene layer in the superlattice stack is located close to the substrate.
[0029] Furthermore, the superlattice stack comprises three graphene layers.
[0030] A second aspect of the present invention provides a gate-surrounded stacked nanosheet device with a high hole mobility channel, which is prepared by the preparation method of the first aspect.
[0031] In summary, compared with the prior art, the present invention achieves the following technical effects:
[0032] (1) Graphene (C 60 The lattice constant (0.246nm) is smaller than that of Si (0.543nm), which will generate compressive stress on Si on the (100) surface along the channel and perpendicular to the channel, thereby improving the hole mobility of the P-tube and overcoming the problem of P-tube performance degradation.
[0033] (2) O2 and Ar plasma etching methods have excellent isotropic etching effects on both Si and graphene, and also on SiO2 and SiN. x Both have an extremely high selection ratio.
[0034] (3) NMP, for Si, SiN x Materials such as SiO2 have extremely high selectivity, making them more suitable for etching graphene layers and releasing nanochannels. Attached Figure Description
[0035] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.
[0036] Figure 1 A flowchart illustrating the fabrication method of the gate-around stacked nanosheet device provided by the present invention;
[0037] Figure 2 This is a schematic diagram of the superlattice stack in the fabrication of a gate-enclosed stacked nanosheet device according to one embodiment of the present invention.
[0038] Figure label:
[0039] 1-Substrate, 2-Superlattice stacked layer, 21-Graphene layer, 22-Silicon layer. Detailed Implementation
[0040] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0041] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0042] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0043] To address the technical challenge of reducing the mobility of P-tubes in P-type devices with stacked nanosheets around the gate, this invention provides a fabrication method. This method differs from existing technologies in that it uses a different sacrificial layer material in the fins, selecting graphene as the sacrificial layer. Consequently, the etching method for the sacrificial material differs. Other steps in the device fabrication process can be referenced from typical procedures, such as… Figure 1 As shown, the specific steps include:
[0044] First, a substrate is provided, and the shallow surface layer of the substrate is doped. The substrate can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon, silicon carbide, germanium, silicon germanium, gallium arsenide, or germanium-on-insulator, with the corresponding top semiconductor material being silicon, germanium, silicon germanium, or gallium arsenide. The substrate can also be a stacked structure of multilayer semiconductor materials.
[0045] Then, a superlattice stack 2 for forming fins is grown, such as... Figure 2As shown, on substrate 1, silicon layer 22 and graphene layer 21 are alternately stacked. Graphene layer 21 serves as a sacrificial layer, and silicon layer 22 serves as the final nanosheet channel. Both are grown epitaxially; for graphene, carbon molecular beam epitaxy can be used. The thickness of the graphene layer can be controlled by adjusting the process conditions during epitaxy to obtain a single-layer graphene layer of a certain thickness. In this step, either the silicon layer or the graphene layer can be epitaxially grown first; the diagram illustrates graphene layer epitaxy first. The alternation period is arbitrary; for example, the diagram shows a period of 3, which includes three layers of silicon and three layers of graphene. In this step, because graphene (C... 60 The lattice constant (0.246nm) is less than that of Si (0.543nm), which will generate compressive stress on Si on the (100) surface along the channel and perpendicular to the channel. Therefore, when the device is P-type, the hole mobility of the P-type transistor can be improved, and the problem of P-type transistor performance degradation can be overcome.
[0046] Next, a portion of the thickness of the superlattice stack and the substrate is etched to form fins. During etching, functional layers such as hard masks and barrier layers can be used, and a patterning transfer process can be employed to obtain the predetermined pattern. Specifically, a layer of photoresist can be coated on the surface of the superlattice stack. Then, a mask is placed on top of the photoresist. After removing a portion of the photoresist through exposure and development, a photolithographic window is obtained. Finally, the portions of the sacrificial preparation layers and the channel preparation layers not covered by the photoresist on the substrate are etched through the photolithographic window to obtain the fins.
[0047] A dielectric layer is then formed on the substrate to serve as shallow trench isolation (STI). The material for STI is preferably a doped or undoped low-temperature oxide.
[0048] Next, a dummy gate is formed on the fin. The dummy gate material can be polysilicon or polysilicon. Those skilled in the art can reasonably select the material for forming the above-mentioned dummy gate preparation layer based on existing technology, which will not be elaborated here.
[0049] Next, a first sidewall is formed on the sidewalls of the dummy gate. This first sidewall, located on both sides of the dummy gate and spanning the fins, protects the sacrificial layer from lateral etching during subsequent processes. There are various methods and structures for forming the first sidewall; specific process steps and structures will not be described in detail here. The first sidewall can be a material such as silicon nitride, which has a high etch selectivity with the superlattice stacked layer. Deposition methods include, but are not limited to, PECVD and ALCVD.
[0050] Then, the source / drain layers are etched, specifically the superlattice stack in the fins, to release the grooves for forming the source / drain. This etching step can be performed using plasma etching. Plasma etching has excellent isotropic etching effects on both Si and graphene, and is also effective on SiO2 and SiN. xBoth have extremely high selectivity, therefore, when using this method to release the source-drain groove, it is easy to obtain a groove with a regular shape. The plasma source can be at least one of O2 plasma and Ar plasma.
[0051] A second sidewall is formed on the sidewalls of the superlattice stack in the fin. This step typically involves first etching the graphene in the superlattice stack to form inner sidewall grooves, and then depositing a low-k dielectric material to fill the inner sidewall grooves, forming the second sidewall. The second sidewall can be a material such as silicon nitride, which has a high etch selectivity to the superlattice stack. Deposition methods include, but are not limited to, PECVD and ALCVD.
[0052] Next, source and drain sources are formed by epitaxially growing semiconductor material in the groove. The doping type is determined in this step based on the transistor type. The semiconductor material can be silicon, germanium-silicon, etc., and this invention is not limited to this. This step typically involves first epitaxially growing the semiconductor material, then doping, and finally annealing.
[0053] Then, the dummy gate is removed. To remove the dummy gate, a dielectric material is typically deposited first for planarization to protect the source and drain, and then CMP, etching, and other techniques are used to remove it.
[0054] Next, the graphene layer in the superlattice stack is etched away to release the nanosheet channels. The stack formed by the nanosheets constitutes multiple conductive channels. In this step of graphene removal, to obtain a regular shape, NMP organic solvent is preferably used to dissolve the graphene to achieve the removal purpose.
[0055] Next, a surround gate is formed, which surrounds the stack formed by the nanosheet. This step is typically performed by multi-layer deposition, which may include an HK layer (high-k dielectric layer), an n-type functional metal layer, and a metal gate layer.
[0056] Finally, an insulating dielectric material is deposited to cover the functional circuit structure. Then, necessary electrode leads and interconnection processes such as etching contact holes, plugs inside the contact holes, metallization interconnects, and solder pads are performed. This invention will not elaborate on these processes.
[0057] The above methods are applicable to N-type or P-type devices, and can take advantage of the high hole mobility for P-type devices.
[0058] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A method for fabricating a gate-surrounded stacked nanosheet device with a high hole mobility channel, characterized in that, include: Provide substrate; A superlattice stack of alternating silicon and graphene layers is formed on the surface of the substrate; Etching a portion of the thickness of the superlattice stack and the substrate forms fins; A first dielectric layer is formed on the substrate as a shallow trench isolation layer between the fins; A false grid is formed on the fin, and a first sidewall is formed on the sidewall of the false grid; The superlattice stack in the etched fins releases grooves to be formed for source and drain; A second sidewall is formed on the sidewall of the superlattice stack in the fin; Source and drain are formed in the epitaxial semiconductor material outside the groove; Remove spurious barriers; The graphene layer in the superlattice stack is etched away to release the nanosheet channels, and the stack formed by the nanosheets constitutes multiple conductive channels. A surrounding gate is formed, which surrounds the stack formed by the nanosheet.
2. The preparation method according to claim 1, characterized in that, The graphene layer is formed by carbon molecular beam epitaxy.
3. The preparation method according to claim 1 or 2, characterized in that, When the superlattice stack in the etched fin releases the grooves to be formed for the source and drain, plasma etching is used.
4. The preparation method according to claim 3, characterized in that, The plasma etching method employs at least one of O2 plasma and Ar plasma.
5. The preparation method according to claim 1, characterized in that, The first sidewall and the second sidewall are made of silicon nitride.
6. The preparation method according to claim 1, characterized in that, The method for etching away the graphene layer in the superlattice stack includes: removing the graphene layer using N-methylpyrrolidone.
7. The preparation method according to any one of claims 1, 2, or 5-6, characterized in that, The grid-surrounded stacked nanosheet device is a P-type device.
8. The preparation method according to claim 1, characterized in that, The graphene layer in the superlattice stack is close to the substrate.
9. The preparation method according to claim 1 or 8, characterized in that, The superlattice stack comprises three graphene layers.
10. A gate-surrounded stacked nanosheet device with a high hole mobility channel, characterized in that, It is prepared by the preparation method described in any one of claims 1-9.