Display panel and display device
By designing the substrate, metal layer, metal oxide semiconductor layer and transparent conductive layer in the display panel, and connecting transparent electrodes through vias, the problem that the display panel in VR/AR display devices cannot take into account high resolution and product yield, achieving both high resolution and high product yield.
Patent Information
- Application Number
- CN202311513168.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-10
- Publication Date
- 2025-05-02
- Estimated Expiration
- 2043-11-10
AI Technical Summary
The display panels in existing VR/AR display devices cannot take into account both high resolution and product yield, especially when increasing pixel density units (PPI), the wiring space is cramped and the relevant safety distance cannot be guaranteed, resulting in a decrease in product yield.
A display panel is designed, including a substrate, a first metal layer, a metal oxide semiconductor layer, a first transparent conductive layer, and a second transparent conductive layer. The first electrode conductor part in the transparent active layer is electrically connected to the first transparent electrode and the second transparent electrode through the via hole, and the transparent electrode is re-divided by forming two insulated transparent conductive layers to ensure safety and stability.
While ensuring high resolution, the product yield of the display panel is improved, the safety problems caused by too small data lines are avoided, and the stability and opening ratio of the display panel are enhanced.
Smart Images

Figure CN117594608B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art
[0002] With the development of display technology, consumer electronic products that rely on the display function of display panels, such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, desktop computers, virtual reality (VR) display devices, augmented reality (AR) display devices, etc., are emerging in an endless stream. The rise of the concept of "metaverse" has also made VR / AR display devices widely concerned by consumers, and has broad market application prospects.
[0003] VR / AR display devices are near-eye display devices, which have high requirements for the resolution of the display panels. Under the existing pixel design architecture, the pixel density unit (Full name: Pixels Per Inch, PPI) of the display panels in VR / AR display devices can only reach a level between 1000-1500, which still cannot meet user needs. If the PPI is further improved, the wiring (Full name: layout) space will be cramped and the relevant safety distance cannot be guaranteed, which reduces the product yield of the display panel.
[0004] Therefore, how to improve the product yield of display panels while ensuring high pixel resolution is a problem that technical personnel in this field need to solve urgently. Summary of the invention
[0005] The present application provides a display panel and a display device, which can effectively solve the problem that the display panels in existing VR / AR display devices cannot achieve both high resolution and product yield.
[0006] In a first aspect, the present application provides a display panel, the display panel having a display area, the display panel in the display area comprising: a substrate; a first metal layer, arranged on one side of the substrate, the first metal layer comprising a plurality of data lines arranged in sequence and spaced in a first direction; a metal oxide semiconductor layer, arranged between the substrate and the first metal layer, the metal oxide semiconductor layer comprising a plurality of transparent active layers arranged in an array, the transparent active layer comprising a first electrode conductor portion, the orthographic projection of the first electrode conductor portion on the substrate being located between two adjacent data lines; a first transparent conductive layer, arranged on a side of the first metal layer away from the metal oxide semiconductor layer, the first transparent conductive layer comprising a plurality of first transparent electrodes; a second transparent conductive layer, arranged on a side of the first transparent conductive layer away from the first metal layer and insulated from the first transparent conductive layer, the second transparent conductive layer comprising a plurality of second transparent electrodes; wherein, in two adjacent transparent active layers in the first direction, the first electrode conductor portion in one of the transparent active layers is electrically connected to one of the first transparent electrodes by way of a via connection, and the first electrode conductor portion in the other of the transparent active layers is electrically connected to one of the second transparent electrodes by way of a via connection.
[0007] Optionally, the first transparent conductive layer and the second transparent conductive layer are made of the same material, have the same shape, and have the same thickness.
[0008] Optionally, the display panel also includes a pixel electrode layer, the pixel electrode layer includes a plurality of first pixel electrodes and a plurality of second pixel electrodes, wherein the first pixel electrode is electrically connected to the first transparent electrode through a third via hole, and the first transparent electrode is electrically connected to the first electrode conductor portion through the first via hole; the second pixel electrode is electrically connected to the second transparent electrode through a fourth via hole, and the second transparent electrode is electrically connected to the first electrode conductor portion through the second via hole; in a direction perpendicular to the substrate, the sum of the depths of the first via hole and the third via hole is equal to the sum of the depths of the second via hole and the fourth via hole, and the material of the pixel electrode layer is the same as that of the first transparent conductive layer and the second transparent conductive layer.
[0009] Optionally, the display panel also includes: a first insulating layer, arranged on a side of the first metal layer facing away from the substrate, and the first transparent conductive layer is arranged on a surface of the first insulating layer on a side facing away from the substrate; a second insulating layer, arranged between the first transparent conductive layer and the second transparent conductive layer; wherein the first transparent conductive layer is insulated from the second transparent conductive layer by the second insulating layer, and the first insulating layer and the second insulating layer are made of the same material.
[0010] Optionally, the thickness of the second insulating layer is greater than the thickness of the first insulating layer.
[0011] Optionally, in the first transparent electrode and the second transparent electrode adjacent to each other in the first direction, the orthographic projection of the edge of the first transparent electrode close to the second transparent electrode on the substrate overlaps with the orthographic projection of the data line on the substrate, and the orthographic projection of the edge of the second transparent electrode close to the first transparent electrode on the substrate overlaps with the orthographic projection of the data line on the substrate.
[0012] Optionally, in the first transparent electrode and the second transparent electrode adjacent to each other in the first direction, an orthographic projection of an edge of the first transparent electrode close to the second transparent electrode on the substrate is adjacent to or overlaps with an edge of the second transparent electrode close to the first transparent electrode.
[0013] Optionally, the display area includes a plurality of pixel areas arranged in an array, and the display panel of the display area includes a plurality of thin film transistors arranged in an array, each of the pixel areas corresponds to one of the thin film transistors, wherein the plurality of thin film transistors include a plurality of first thin film transistors and a plurality of second thin film transistors, the first thin film transistors and the second thin film transistors are alternately arranged in the first direction, each of the first thin film transistors includes one of the transparent active layers and one of the first transparent electrodes, and each of the second thin film transistors includes one of the transparent active layers and one of the second transparent electrodes.
[0014] Optionally, the display panel of the display area also includes: a first gate layer, which is arranged on one side of the substrate, the metal oxide semiconductor layer is arranged on a side of the first gate layer away from the substrate, and the first gate layer includes a plurality of first gate lines arranged in sequence and spaced apart in a second direction; a second gate layer, which is arranged on a side of the metal oxide semiconductor layer away from the substrate, the first metal layer is arranged on a side of the second gate layer away from the substrate, and the second gate layer includes a plurality of second gate lines arranged in sequence and spaced apart in the second direction; wherein the thin film transistor also includes a first gate, a second gate and a second electrode, the first gate line includes the first gate, the second gate line includes the second gate, and the data line includes the second electrode.
[0015] In a second aspect, the present application provides a display device, comprising a shell and a display panel as described above, wherein the shell has an accommodating space, and the display panel is arranged in the accommodating space, wherein the display panel has a display area, and the display panel in the display area includes a plurality of data lines arranged in sequence and spaced in a first direction, and the display area is divided into a plurality of pixel columns by the plurality of data lines, and each pixel column includes a plurality of pixel areas; wherein the plurality of pixel columns include a plurality of odd pixel columns and a plurality of even pixel columns, and the first electrode conductor portion in each of the pixel areas of the odd pixel columns is electrically connected to the first transparent electrode, and the first electrode conductor portion in each of the pixel areas of the even pixel columns is electrically connected to the second transparent electrode.
[0016] The present application provides a display panel and a display device, wherein the display panel has a display area, wherein the display panel in the display area comprises: a substrate; a first metal layer, arranged on one side of the substrate, wherein the first metal layer comprises a plurality of data lines arranged in sequence and spaced apart in a first direction; a metal oxide semiconductor layer, arranged between the substrate and the first metal layer, wherein the metal oxide semiconductor layer comprises a plurality of transparent active layers arranged in an array, wherein the transparent active layer comprises a first electrode conductor portion, wherein the orthographic projection of the first electrode conductor portion on the substrate is located between two adjacent data lines; a first transparent conductive layer, arranged on a side of the first metal layer away from the metal oxide semiconductor layer, wherein the first The transparent conductive layer includes a plurality of first transparent electrodes; a second transparent conductive layer is arranged on a side of the first transparent conductive layer away from the first metal layer and is insulated from the first transparent conductive layer, and the second transparent conductive layer includes a plurality of second transparent electrodes; wherein, in two adjacent transparent active layers in the first direction, a first electrode conductor portion in one of the transparent active layers is electrically connected to one of the first transparent electrodes by way of a via connection, and a first electrode conductor portion in another of the transparent active layers is electrically connected to one of the second transparent electrodes by way of a via connection. The display panel and the display device provided by the present application can improve the product yield while ensuring high resolution. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0018] Figure 1 A schematic diagram of partitioning of a display area of a display panel provided in an embodiment of the present application;
[0019] Figure 2 A cross-sectional schematic diagram of a display panel of a display area provided in an embodiment of the present application;
[0020] Figure 3 A schematic plan view of multiple film layers in a display area provided in an embodiment of the present application;
[0021] Figure 4 A schematic plan view of an active layer of a display area provided in an embodiment of the present application;
[0022] Figure 5 This is a plan view of a first transparent conductive layer and a second transparent conductive layer provided in an embodiment of the present application.
[0023] Description of reference numerals:
[0024] Substrate 10; functional layer 11; first gate insulating layer 12; first gate layer 13; first gate line 131; first gate electrode 132; second gate insulating layer 14; metal oxide semiconductor layer 15; transparent active layer 150; first electrode conductor 151; channel 152; second electrode conductor 153; third gate insulating layer 16; second gate layer 17; second gate line 171; second gate electrode 172; interlayer dielectric layer 18; first metal layer 19; data line 191; second electrode 192; first insulating layer 20; first transparent conductive layer 21; first transparent electrode 211; second insulating layer 22; second transparent conductive layer 23; second transparent electrode 231; planar layer 24; pixel electrode layer 25; first pixel electrode 251; second pixel electrode 252; passivation layer 26; common electrode layer 27; first direction X; second direction Y; first via hole H1; second via hole H2; third via hole H3; fourth via hole H4; thin film transistor TFT; first thin film transistor TFT1; second thin film transistor TFT2; display area AA; pixel column PXL; odd pixel column PXL1; even pixel column PXL2; pixel area PX; DETAILED DESCRIPTION
[0025] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words such as "upper" and "lower" used generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.
[0026] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed in itself. In addition, the present application provides various specific examples of processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials. The following is described in detail respectively, and it should be noted that the description order of the following embodiments is not used as a limitation to the preferred order of the embodiments.
[0027] Figure 1 A schematic diagram of partitioning of a display area of a display panel provided in an embodiment of the present application; Figure 2 A cross-sectional schematic diagram of a display panel of a display area provided in an embodiment of the present application; Figure 3 A schematic plan view of multiple film layers in a display area provided in an embodiment of the present application; Figure 4 A schematic plan view of an active layer of a display area provided in an embodiment of the present application; Figure 5 A schematic plan view of a first transparent conductive layer and a second transparent conductive layer provided in an embodiment of the present application. Figure 1-Figure 5 As shown, in the first aspect, an embodiment of the present application provides a display panel, which can be used in a VR / AR display device with high-resolution display requirements, and the type of the display panel can be a liquid crystal display panel.
[0028] Specifically, the display panel has a display area AA, and the display panel of the display area AA includes: a substrate 10; a first metal layer 19, which is arranged on one side of the substrate 10, and the first metal layer 19 includes a plurality of data lines 191 arranged in sequence and spaced in a first direction X; a metal oxide semiconductor layer 15, which is arranged between the substrate 10 and the first metal layer 19, and the metal oxide semiconductor layer 15 includes a plurality of transparent active layers 150 arranged in an array, and the transparent active layer 150 includes a first electrode conductor part 151, and the orthographic projection of the first electrode conductor part 151 on the substrate 10 is located between two adjacent data lines 191; a first transparent conductive layer 21, which is arranged on the back of the first metal layer 19 The first transparent conductive layer 21 includes a plurality of first transparent electrodes 211 on a side away from the metal oxide semiconductor layer 15; the second transparent conductive layer 23 is arranged on a side of the first transparent conductive layer 21 away from the first metal layer 19, and the second transparent conductive layer 23 includes a plurality of second transparent electrodes 231; wherein, in two adjacent transparent active layers 150 in the first direction X, the first electrode conductor portion 151 in one of the transparent active layers 150 is electrically connected to one of the first transparent electrodes 211 by means of a via connection, and the first electrode conductor portion 151 in the other transparent active layer 150 is electrically connected to one of the second transparent electrodes 231 by means of a via connection.
[0029] In the display panel provided in the present application, the display area AA is the area where the display panel performs the display function, and the display area AA includes a plurality of pixel columns PXL arranged in sequence along the row direction (i.e., the first direction X), each pixel column PXL includes a plurality of pixel areas PX, and the pixel area PX is the actual light-transmitting area in the display area AA. Therefore, the number and distribution density of the pixel areas PX in the display area AA are directly related to the aperture ratio and resolution of the display panel. The more the number of pixel columns PXL, the greater the number and distribution density of the pixel areas PX, and the greater the resolution of the display panel. Since the VR / AR type liquid crystal display panel has a high requirement for resolution, accordingly, it is necessary to increase the number of pixel columns PXL as much as possible, and the pixel column PXL corresponds to the area between two adjacent data lines 191.
[0030] At the same time, when the number of pixel columns PXL increases and the resolution of the display panel increases, in order to ensure the display effect of the pixel panel, the aperture ratio of the display panel also needs to be ensured. In the display panel provided by the present application, the metal oxide semiconductor layer 15 has light transmittance, so the metal oxide semiconductor layer 15 with light transmittance can be used to form a transparent active layer 150, and the first electrode conductor part 151 in the transparent active layer 150 is arranged between two adjacent data lines 191, so that the area where the first electrode conductor part 151 is located can be used as the pixel area PX in the display panel, thereby improving the space utilization and aperture ratio of the display area AA, thereby increasing the number of pixel areas PX that can be arranged in the limited display area AA, thereby improving the resolution of the display panel. Exemplarily, the display panel is a liquid crystal display panel. When the first electrode conductor portion 151 is located between two adjacent data lines 191, since the first electrode conductor portion 151 is light-transmissive, the first electrode conductor portion 151 will not block the outgoing light of the backlight source in the liquid crystal display panel, thereby ensuring that the area where the first electrode conductor portion 151 is located meets the prerequisite of being used as the pixel area PX.
[0031] The transparent active layer 150 is a part of the metal oxide thin film transistor of the display area AA. As a driving element of the display panel, the metal oxide thin film transistor needs to provide a driving signal to the pixel electrode of the pixel area PX. In order to ensure the normal transmission of the driving signal, the metal oxide thin film transistor also needs to include a transparent electrode (functionally serving as a source or a drain) electrically connecting the first electrode conductor part 151 and the pixel electrode. As a lapped structure, the transparent electrode needs to be electrically connected to the first electrode conductor part 151 through a via connection. Therefore, inevitably, the first electrode conductor part 151 and the first electrode will overlap in a direction perpendicular to the substrate 10 to facilitate the setting of the via. As mentioned above, the area where the first electrode conductor part 151 is located has a demand to be used as the pixel area PX. Therefore, in order to ensure the light transmittance of the area where the first electrode conductor part 151 is located, the present application uses a transparent conductive layer with light transmittance to form the transparent electrode.
[0032] However, the researchers unexpectedly discovered that since the transparent electrode is electrically connected to the first electrode conductor part 151 by way of via connection, in order to ensure the stability of the via connection, it is necessary to ensure the coverage of the transparent electrode on the via, which makes the maximum width of the transparent electrode in the area corresponding to the via and the first electrode conductor part 151 in the first direction X (i.e., the arrangement direction of the data line 191) should be greater than the maximum width of the via in the first direction X, thereby making the maximum width of the first electrode in the area corresponding to the via and the first electrode conductor part 151 in the first direction X larger. In the related art, in the first direction X, each transparent electrode is arranged in the same layer and arranged repeatedly in sequence, therefore, this structure will result in a smaller spacing distance between two adjacent transparent electrodes in the first direction X, which is prone to safety problems, greatly reducing the stability and yield of the display panel.
[0033] The display panel provided in the present application forms two insulating transparent conductive layers, and re-divides the transparent electrodes in the related art into a first transparent electrode 211 located in the first transparent conductive layer 21 and a second transparent electrode 231 located in the second transparent conductive layer 23, so that when the spacing distance between the adjacent first transparent electrodes 211 and the second transparent electrodes 231 in the first direction X is small, the safety between the first transparent electrodes 211 and the second transparent electrodes 231 can still be guaranteed, thereby improving the stability and yield of the display panel.
[0034] Specifically, in two adjacent transparent active layers 150 in the first direction X, the first electrode conductor portion 151 in one of the transparent active layers 150 is electrically connected to one of the first transparent electrodes 211 by way of via connection, and the first electrode conductor portion 151 in the other transparent active layer 150 is electrically connected to one of the second transparent electrodes 231 by way of via connection. Although, in order to ensure the stability of the via connection, the width of the portion of the first transparent electrode 211 corresponding to the first electrode conductor portion 151 in the first direction X is larger, and the width of the portion of the second transparent electrode 231 corresponding to the second electrode conductor portion 153 in the first direction X is larger, the first transparent electrode 211 and the second transparent electrode 231 still have a problem of a small spacing distance in the first direction X, but because the first transparent conductive layer 21 where the first transparent electrode 211 is located and the second transparent conductive layer 23 where the second transparent electrode 231 is located are arranged in different layers and are electrically insulated, the safety between the first transparent electrode 211 and the second transparent electrode 231 can be guaranteed, thereby improving the stability and yield of the display panel.
[0035] In some embodiments of the present application, the first transparent conductive layer 21 and the second transparent conductive layer 23 are made of the same material, have the same shape, and have the same thickness.
[0036] In the display panel provided by the present application, the second transparent conductive layer 23 is a key film layer for improving the product yield of the display panel while ensuring high pixel resolution, but the second transparent conductive layer 23 is a newly added film layer, which may inevitably lead to an increase in process steps and an increase in cost. The present application sets the materials of the first transparent conductive layer 21 and the second transparent conductive layer 23 to be the same, so that the second transparent conductive layer 23 can be formed by using the existing film-forming equipment for forming the first transparent conductive layer 21, thereby reducing the production and manufacturing costs as much as possible; secondly, the shapes of the first transparent conductive layer 21 and the second transparent conductive layer 23 refer to the shapes of the positive projections of the first transparent conductive layer 21 and the second transparent conductive layer 23 on the substrate 10, and the shapes thereof correspond to the shape of the mask. The present application sets the shapes of the first transparent conductive layer 21 and the second transparent conductive layer 23 to be the same, so that the existing mask for forming the first transparent conductive layer 21 can be used to form the first transparent conductive layer 21. The second transparent conductive layer 23 is formed by a mask plate, so there is no need to form a separate mask plate for the second transparent electrode 231, thereby reducing the production cost as much as possible; thirdly, the thickness of the first transparent conductive layer 21 and the second transparent conductive layer 23 refers to the thickness of the first transparent conductive layer 21 and the second transparent conductive layer 23 in the direction perpendicular to the substrate 10, and the thickness corresponds to the film forming time. The present application sets the thickness of the first transparent conductive layer 21 and the second transparent conductive layer 23 to be the same, so that the second transparent conductive layer 23 can be formed by utilizing the existing film forming parameters for forming the first transparent conductive layer 21, thereby eliminating the need to set parameters separately for the second transparent electrode 231, thereby improving the process efficiency.
[0037] In some embodiments of the present application, the display panel also includes a pixel electrode layer 25, the pixel electrode layer 25 includes a plurality of first pixel electrodes 251 and a plurality of second pixel electrodes 252, wherein the first pixel electrode 251 is electrically connected to the first transparent electrode 211 through a third via hole H3, and the first transparent electrode 211 is electrically connected to the first electrode conductor portion 151 through a first via hole H1; the second pixel electrode 252 is electrically connected to the second transparent electrode 231 through a fourth via hole H4, and the second transparent electrode 231 is electrically connected to the first electrode conductor portion 151 through a second via hole H2; in a direction perpendicular to the substrate 10, the sum of the depths of the first via hole H1 and the third via hole H3 is equal to the sum of the depths of the second via hole H2 and the fourth via hole H4, and the material of the pixel electrode layer 25 is the same as that of the first transparent conductive layer 21 and the second transparent conductive layer 23.
[0038] In the display panel provided in the present application, since the first transparent electrode 211 is electrically connected to the first pixel electrode 251 by way of a via connection, the second transparent electrode 231 is electrically connected to the second pixel electrode 252 by way of a via connection, and the first pixel electrode 251 and the second pixel electrode 252 both belong to the pixel electrode layer 25 (that is, the first pixel electrode 251 and the second pixel electrode 252 are arranged in the same layer), the sum of the depths of the first via hole H1 and the third via hole H3 in the direction perpendicular to the substrate 10 can be equal to the sum of the depths of the second via hole H2 and the fourth via hole H4, so that the transmission distances of the driving signals of the first pixel electrode 251 and the second pixel electrode 252 in the direction perpendicular to the substrate 10 are kept consistent, thereby improving the signal transmission consistency of the driving signals of the first pixel electrode 251 and the second pixel electrode 252, and improving the display effect of the display panel. Furthermore, since the material of the pixel electrode layer 25 is the same as that of the first transparent conductive layer 21 and the second transparent conductive layer 23, the resistance of the driving signal of the first pixel electrode 251 during the process of being transmitted from the first electrode conductor portion 151 to the first pixel electrode 251 is further made equal to the resistance of the driving signal of the second pixel electrode 252 during the process of being transmitted from the first electrode conductor portion 151 to the second pixel electrode 252, thereby further improving the signal transmission consistency of the driving signal of the first pixel electrode 251 and the driving signal of the second pixel electrode 252, and further improving the display effect of the display panel.
[0039] In some embodiments of the present application, the display panel also includes: a first insulating layer 20, which is arranged on the side of the first metal layer 19 away from the substrate 10, and the first transparent conductive layer 21 is arranged on the surface of the first insulating layer 20 away from the substrate 10; a second insulating layer 22, which is arranged between the first transparent conductive layer 21 and the second transparent conductive layer 23; wherein the first transparent conductive layer 21 is insulated from the second transparent conductive layer 23 by the second insulating layer 22, and the first insulating layer 20 and the second insulating layer 22 are made of the same material.
[0040] In the display panel provided by the present application, the first transparent conductive layer 21 is insulated from the second transparent conductive layer 23 by the second insulating layer 22, that is, the second insulating layer 22 is a necessary additional film layer that can electrically insulate the first transparent conductive layer 21 and the second transparent conductive layer 23. Accordingly, the second insulating layer 22 will increase the film layers of the display panel and increase the cost. The first insulating layer 20 is the bearing film layer of the first transparent conductive layer 21. The present application sets the material of the first insulating layer 20 and the second insulating layer 22 to be the same, so that the second insulating layer 22 can be formed by using the existing film forming equipment used to form the first insulating layer 20, thereby reducing the production cost as much as possible.
[0041] In some embodiments of the present application, the thickness of the second insulating layer 22 is greater than the thickness of the first insulating layer 20 .
[0042] In the display panel provided in the present application, the second insulating layer 22 is an essential film layer that can electrically insulate the first transparent conductive layer 21 and the second transparent conductive layer 23. The insulation of the second insulating layer 22 directly affects the insulation effect of the first transparent electrode 211 and the second transparent electrode 231, thereby affecting the stability and safety performance of the display panel. The present application makes the thickness of the second insulating layer 22 greater than the thickness of the first insulating layer 20, thereby further improving the insulation effect of the first transparent electrode 211 and the second transparent electrode 231, improving the stability and safety performance of the display panel, and providing a structural basis for the first transparent electrode 211 to completely cover the first via hole H1 and the second transparent electrode 231 to completely cover the second via hole H2.
[0043] In some embodiments of the present application, in the first transparent electrode 211 and the second transparent electrode 231 adjacent to each other in the first direction X, the orthographic projection of the edge of the first transparent electrode 211 close to the second transparent electrode 231 on the substrate 10 overlaps with the orthographic projection of the data line 191 on the substrate 10; the orthographic projection of the edge of the second transparent electrode 231 close to the first transparent electrode 211 on the substrate 10 overlaps with the orthographic projection of the data line 191 on the substrate 10.
[0044] In the display panel provided in the present application, since, in the first transparent electrode 211 and the second transparent electrode 231 adjacent to each other in the first direction X, the orthographic projection of the edge of the first transparent electrode 211 close to the second transparent electrode 231 on the substrate 10 overlaps with the orthographic projection of the data line 191 on the substrate 10, and the orthographic projection of the edge of the second transparent electrode 231 close to the first transparent electrode 211 on the substrate 10 overlaps with the orthographic projection of the data line 191 on the substrate 10, the maximum widths of the first transparent electrode 211 and the second transparent electrode 231 in the first direction X are further increased, the coverage of the first transparent electrode 211 on the first via hole H1 is improved, the coverage of the second transparent electrode 231 on the second via hole H2 is improved, and the connection stability of the first transparent electrode 211, the second transparent electrode 231 and the first electrode conductor portion 151 is improved.
[0045] In some embodiments of the present application, in the first transparent electrode 211 and the second transparent electrode 231 adjacent to each other in the first direction X, the orthographic projection of the edge of the first transparent electrode 211 close to the second transparent electrode 231 on the substrate 10 is adjacent to or overlaps with the edge of the second transparent electrode 231 close to the first transparent electrode 211.
[0046] In the display panel provided in the present application, since, in the first transparent electrode 211 and the second transparent electrode 231 adjacent to each other in the first direction X, the orthographic projection of the edge of the first transparent electrode 211 close to the second transparent electrode 231 on the substrate 10 is adjacent to or overlaps with the edge of the second transparent electrode 231 close to the first transparent electrode 211, that is, the first transparent electrode 211 and the second transparent electrode 231 are not restricted by the boundaries of their edges, so that the maximum widths of the first transparent electrode 211 and the second transparent electrode 231 in the first direction X can be further increased, and the coverage of the first transparent electrode 211 to the first via hole H1 is further improved, and the coverage of the second transparent electrode 231 to the second via hole H2 is improved, thereby improving the connection stability of the first transparent electrode 211, the second transparent electrode 231 and the first electrode conductor portion 151.
[0047] In some embodiments of the present application, the display area AA includes a plurality of pixel areas PX arranged in an array, and the display panel of the display area AA includes a plurality of thin film transistors TFT arranged in an array, each of the pixel areas PX corresponds to one of the thin film transistors TFT, wherein the plurality of thin film transistors TFT include a plurality of first thin film transistors TFT1 and a plurality of second thin film transistors TFT2, the first thin film transistors TFT1 and the second thin film transistors TFT2 are alternately arranged in the first direction X, each of the first thin film transistors TFT1 includes one of the transparent active layers 150 and one of the first transparent electrodes 211, and each of the second thin film transistors TFT2 includes one of the transparent active layers 150 and one of the second transparent electrodes 231.
[0048] The display panel provided in the present application can be used in VR / AR display devices, and therefore has a higher aperture ratio requirement. Each pixel area PX of the present application corresponds to one thin film transistor TFT, that is, the pixel electrode in each pixel area PX is driven by only one thin film transistor TFT, so as to reduce the number of thin film transistors TFT as much as possible and improve the aperture ratio of the display panel. In addition, the first transparent electrode 211 is located in the first transparent conductive layer 21, and the second transparent electrode 231 is located in the second transparent conductive layer 23. Therefore, in the first thin film transistor TFT1 and the second thin film transistor TFT2 adjacent to each other in the first direction X, the adjacent first transparent electrode 211 and the second transparent electrode 231 will not cause safety problems due to the small spacing distance in the first direction X, thereby improving the device stability of the first thin film transistor TFT1 and the second thin film transistor TFT2, thereby improving the safety of the display panel.
[0049] In some embodiments of the present application, the display panel of the display area AA also includes: a first gate layer 13, which is arranged on one side of the substrate 10, the metal oxide semiconductor layer 15 is arranged on the side of the first gate layer 13 away from the substrate 10, and the first gate layer 13 includes a plurality of first gate lines 131 arranged in sequence and spaced apart in the second direction Y; a second gate layer 17, which is arranged on the side of the metal oxide semiconductor layer 15 away from the substrate 10, the first metal layer 19 is arranged on the side of the second gate layer 17 away from the substrate 10, and the second gate layer 17 includes a plurality of second gate lines 171 arranged in sequence and spaced apart in the second direction Y; wherein the thin film transistor TFT also includes a first gate 132, a second gate 172 and a second electrode 192, the first gate line 131 includes the first gate 132, the second gate line 171 includes the second gate 172, and the data line 191 includes the second electrode 192.
[0050] In the display panel provided by the present application, since the transparent active layer 150 of the thin film transistor TFT is located in the metal oxide semiconductor layer 15, that is, the type of the thin film transistor TFT is a metal oxide thin film transistor, the thin film transistor TFT has a problem of low mobility. The present application can effectively improve the device performance of the thin film transistor TFT by forming the thin film transistor TFT into a double-gate structure including the first gate 132 and the second gate 172. In addition, since the first gate line 131 includes the first gate 132, the second gate line 171 includes the second gate 172, and the data line 191 includes the second electrode 192, the first gate 132, the second gate 172 and the second electrode 192 are respectively part of the first gate line 131, the second gate line 171 and the data line 191, thereby avoiding the problem of affecting the aperture ratio of the display panel due to the opacity of the first gate 132, the second gate 172 and the second electrode 192.
[0051] In some embodiments of the present application, the first transparent electrode 211 in the first thin-film transistor TFT1 is one of the source and the drain, and the second electrode 192 in the first thin-film transistor TFT1 is the other of the source and the drain; the second transparent electrode 231 in the second thin-film transistor TFT2 is one of the source and the drain, and the second electrode 192 in the second thin-film transistor TFT2 is the other of the source and the drain.
[0052] In some embodiments of the present application, the transparent active layer 150 also includes a channel 152 and a second electrode conductor portion 153, the first electrode conductor portion 151 and the second electrode conductor portion 153 are respectively located on both sides of the channel 152, and the second electrode conductor portion 153 is electrically connected to the second electrode through a via connection.
[0053] In some embodiments of the present application, the display panel further includes a functional layer 11, a first gate insulating layer 12, a second gate insulating layer 14, a third gate insulating layer 16, an interlayer dielectric layer 18, a planar layer 24, a passivation layer 26 and a common electrode layer 27. The functional layer 11 is arranged on one side of the substrate 10, the first gate insulating layer 12 is arranged on the side of the functional layer 11 away from the substrate 10, the first gate layer 13 is arranged on the side of the first gate insulating layer 12 away from the substrate 10, the second gate insulating layer 14 is arranged on the side of the first gate layer 13 away from the substrate 10, the metal oxide semiconductor layer 15 is arranged on the side of the second gate insulating layer 14 away from the substrate 10, the third gate insulating layer 16 is arranged on the side of the metal oxide semiconductor layer 15 away from the substrate 10, the second gate layer 17 is arranged on the side of the third gate insulating layer 16 away from the substrate 10, the interlayer dielectric layer 18 is arranged on the side of the second gate layer 17 away from the substrate 10, and the first metal layer 19 is arranged on the layer The interlayer dielectric layer 18 is disposed on a side away from the substrate 10, the first insulating layer 20 is disposed on a side away from the substrate 10 of the first metal layer 19, the first transparent conductive layer 21 is disposed on a side away from the substrate 10 of the first insulating layer 20, the second insulating layer 22 is disposed on a side away from the substrate 10 of the first transparent conductive layer 21, the second transparent conductive layer 23 is disposed on a side away from the substrate 10 of the second insulating layer 22, the planarizing layer 24 is disposed on a side away from the substrate 10 of the second transparent conductive layer 23, the pixel electrode layer 25 is disposed on a side away from the substrate 10 of the planarizing layer 24, the passivation layer 26 is disposed on a side away from the pixel electrode layer 25, and the common electrode layer 27 is disposed on a side away from the passivation layer 26. Among them, the first via hole H1 penetrates the first insulating layer 20, the interlayer dielectric layer 18 and the third gate insulating layer 16, the second via hole H2 penetrates the second insulating layer 22, the first insulating layer 20, the interlayer dielectric layer 18 and the third gate insulating layer 16, the third via hole H3 penetrates the planar layer 24 and the second insulating layer 22, and the fourth via hole H4 penetrates the planar layer 24.
[0054] In a second aspect, an embodiment of the present application provides a display device, comprising a shell and a display panel as described in any one of the above items, wherein the shell has an accommodating space, and the display panel is arranged in the accommodating space, wherein the display panel has a display area AA, and the display panel of the display area AA includes a plurality of data lines 191 arranged in sequence and at intervals in a first direction X, and the display area AA is divided into a plurality of pixel columns PXL by the plurality of data lines 191, and each pixel column PXL includes a plurality of pixel areas PX; wherein the plurality of pixel columns PXL include a plurality of odd pixel columns PXL1 and a plurality of even pixel columns PXL2, and the first electrode conductor portion 151 in each of the pixel areas PX of the odd pixel columns PXL1 is electrically connected to the first transparent electrode 211, and the first electrode conductor portion 151 in each of the pixel areas PX of the even pixel columns PXL2 is electrically connected to the second transparent electrode 231.
[0055] In the display device provided in the present application, a first transparent electrode 211 is correspondingly arranged in each of the pixel areas PX of the odd pixel column PXL1, that is, in each of the pixel areas PX of the odd pixel column PXL1, the transparent electrodes electrically connected to the first electrode conductor part 151 through vias are all located in the first transparent conductive layer 21; a second transparent electrode 231 is correspondingly arranged in each of the pixel areas PX of the even pixel column PXL2, that is, in each of the pixel areas PX of the even pixel column PXL2, the transparent electrodes electrically connected to the first electrode conductor part 151 through vias are all located in the second transparent conductive layer 23 insulated from the first transparent conductive layer 21, thereby improving the product yield problem caused by the small spacing between two adjacent columns of transparent electrodes in the adjacent odd pixel column PXL1 and even pixel column PXL2 in the first direction X (i.e., the row direction), so that the resolution of the display panel in the display device is improved while maintaining a high safety.
[0056] In summary, the present application provides a display panel and a display device, wherein the display panel has a display area, and the display panel in the display area comprises: a substrate; a first metal layer, arranged on one side of the substrate, the first metal layer comprising a plurality of data lines arranged in sequence and spaced apart in a first direction; a metal oxide semiconductor layer, arranged between the substrate and the first metal layer, the metal oxide semiconductor layer comprising a plurality of transparent active layers arranged in an array, the transparent active layer comprising a first electrode conductor portion, the orthographic projection of the first electrode conductor portion on the substrate being located between two adjacent data lines; a first transparent conductive layer, arranged on a side of the first metal layer away from the metal oxide semiconductor layer, the The first transparent conductive layer includes a plurality of first transparent electrodes; the second transparent conductive layer is arranged on a side of the first transparent conductive layer away from the first metal layer and is insulated from the first transparent conductive layer, and the second transparent conductive layer includes a plurality of second transparent electrodes; wherein, in two adjacent transparent active layers in the first direction, the first electrode conductor portion in one of the transparent active layers is electrically connected to one of the first transparent electrodes by means of a via connection, and the first electrode conductor portion in the other transparent active layer is electrically connected to one of the second transparent electrodes by means of a via connection. The display panel and the display device provided by the present application can improve the product yield while ensuring high resolution.
[0057] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.
Claims
1. A display panel, characterized in that: The display panel has a display area, and the display panel in the display area includes: substrate; A first metal layer is arranged on one side of the substrate, the first metal layer comprising a plurality of data lines arranged in sequence and spaced apart in a first direction; a metal oxide semiconductor layer, disposed between the substrate and the first metal layer, the metal oxide semiconductor layer comprising a plurality of transparent active layers arranged in an array, the transparent active layer comprising a first electrode conductor portion, an orthographic projection of the first electrode conductor portion on the substrate being located between two adjacent data lines; A first transparent conductive layer, disposed on a side of the first metal layer away from the metal oxide semiconductor layer, the first transparent conductive layer comprising a plurality of first transparent electrodes; a second transparent conductive layer, disposed on a side of the first transparent conductive layer away from the first metal layer and insulated from the first transparent conductive layer, the second transparent conductive layer comprising a plurality of second transparent electrodes; Among them, in the two adjacent transparent active layers in the first direction, the first electrode conductor portion in one of the transparent active layers is electrically connected to one of the first transparent electrodes by way of a via connection, and the first electrode conductor portion in the other transparent active layer is electrically connected to one of the second transparent electrodes by way of a via connection; in the first transparent electrode and the second transparent electrode adjacent to each other in the first direction, the orthographic projection of the edge of the first transparent electrode close to the second transparent electrode on the substrate is adjacent to or overlaps with the edge of the second transparent electrode close to the first transparent electrode.
2. The display panel according to claim 1, characterized in that: The first transparent conductive layer and the second transparent conductive layer are made of the same material, have the same shape, and have the same thickness.
3. The display panel according to claim 2, characterized in that: The display panel further includes a pixel electrode layer, and the pixel electrode layer includes a plurality of first pixel electrodes and a plurality of second pixel electrodes, wherein: The first pixel electrode is electrically connected to the first transparent electrode through the third via hole, and the first transparent electrode is electrically connected to the first electrode conductor through the first via hole; The second pixel electrode is electrically connected to the second transparent electrode through a fourth via hole, and the second transparent electrode is electrically connected to the first electrode conductor through a second via hole; In a direction perpendicular to the substrate, the sum of the depths of the first via hole and the third via hole is equal to the sum of the depths of the second via hole and the fourth via hole, and the material of the pixel electrode layer is the same as that of the first transparent conductive layer and the second transparent conductive layer.
4. The display panel according to claim 1, characterized in that: The display panel further includes: A first insulating layer is disposed on a side of the first metal layer facing away from the substrate, and the first transparent conductive layer is disposed on a surface of the first insulating layer facing away from the substrate; a second insulating layer, disposed between the first transparent conductive layer and the second transparent conductive layer; The first transparent conductive layer is insulated from the second transparent conductive layer by the second insulating layer, and the first insulating layer and the second insulating layer are made of the same material.
5. The display panel according to claim 4, characterized in that: The thickness of the second insulating layer is greater than that of the first insulating layer.
6. The display panel according to claim 5, characterized in that: In the first transparent electrode and the second transparent electrode adjacent to each other in the first direction, the orthographic projection of the edge of the first transparent electrode close to the second transparent electrode on the substrate overlaps with the orthographic projection of the data line on the substrate, and the orthographic projection of the edge of the second transparent electrode close to the first transparent electrode on the substrate overlaps with the orthographic projection of the data line on the substrate.
7. The display panel according to claim 1, characterized in that: The display area includes a plurality of pixel areas arranged in an array, and the display panel of the display area includes a plurality of thin film transistors arranged in an array, each of the pixel areas corresponds to one of the thin film transistors, wherein: The plurality of thin film transistors include a plurality of first thin film transistors and a plurality of second thin film transistors, the first thin film transistors and the second thin film transistors are alternately arranged in the first direction, each of the first thin film transistors includes a transparent active layer and a first transparent electrode, and each of the second thin film transistors includes a transparent active layer and a second transparent electrode.
8. The display panel according to claim 7, characterized in that: The display panel of the display area further includes: A first gate layer is arranged on one side of the substrate, the metal oxide semiconductor layer is arranged on a side of the first gate layer away from the substrate, and the first gate layer includes a plurality of first gate lines arranged in sequence and spaced apart in a second direction; A second gate layer is arranged on a side of the metal oxide semiconductor layer away from the substrate, the first metal layer is arranged on a side of the second gate layer away from the substrate, and the second gate layer includes a plurality of second gate lines arranged in sequence and spaced apart in the second direction; The thin film transistor further includes a first gate, a second gate and a second electrode, the first gate line includes the first gate, the second gate line includes the second gate, and the data line includes the second electrode.
9. A display device, characterized in that: The display device comprises a housing and a display panel according to any one of claims 1 to 8, wherein the housing has an accommodation space, the display panel is arranged in the accommodation space, wherein the display panel has a display area, the display panel in the display area comprises a plurality of data lines sequentially arranged in a first direction and spaced apart from each other, the display area is divided into a plurality of pixel columns by the plurality of data lines, and each pixel column comprises a plurality of pixel areas; Among them, the multiple pixel columns include multiple odd pixel columns and multiple even pixel columns, the first electrode conductor portion in each pixel area of the odd pixel columns is electrically connected to the first transparent electrode, and the first electrode conductor portion in each pixel area of the even pixel columns is electrically connected to the second transparent electrode.
Citation Information
Patent Citations
Display panel and display terminal
CN115032842A
Cited By
Display panel and display device
US12690269B2