Display panel and display device

Abstract

The present application provides a display panel and a display device, wherein the display panel in a display area comprises: a substrate; a first metal layer, comprising a plurality of data lines arranged in sequence and at intervals in a first direction; a metal oxide semiconductor layer, arranged between the substrate and the first metal layer, comprising a plurality of transparent active layers, wherein the transparent active layers comprise a first electrode conductor portion, wherein an orthographic projection of the first electrode conductor portion on the substrate is located between two adjacent data lines; a transparent conductive layer, arranged on a side of the first metal layer away from the metal oxide semiconductor layer, wherein the transparent conductive layer comprises a plurality of first electrodes, wherein the first electrodes are electrically connected to the first electrode conductor portion by way of via connection; in any two adjacent transparent active layers in the first direction, the two first electrode conductor portions are staggered, and the display panel provided by the present application improves product yield while ensuring high resolution by staggering the two first electrode conductor portions.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, consumer electronic products that rely on the display function of display panels, such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, desktop computers, virtual reality (VR) display devices, augmented reality (AR) display devices, etc., are emerging in an endless stream. The rise of the concept of "metaverse" has also made VR / AR display devices widely concerned by consumers, and has broad market application prospects.

[0003] VR / AR display devices are near-eye display devices, which have high requirements for the resolution of the display panels. Under the existing pixel design architecture, the pixel density unit (Full name: Pixels Per Inch, PPI) of the display panels in VR / AR display devices can only reach a level between 1000-1500, which still cannot meet user needs. If the PPI is further improved, the wiring (Full name: layout) space will be cramped and the relevant safety distance cannot be guaranteed, which reduces the product yield of the display panel.

[0004] Therefore, how to improve the product yield of display panels while ensuring high pixel resolution is a problem that technical personnel in this field need to solve urgently. Summary of the invention

[0005] The present application provides a display panel and a display device, which can effectively solve the problem that the display panels in existing VR / AR display devices cannot achieve both high resolution and product yield.

[0006] In a first aspect, the present application provides a display panel, the display panel having a display area, the display panel in the display area comprising: a substrate; a first metal layer, arranged on one side of the substrate, the first metal layer comprising a plurality of data lines arranged in sequence and spaced apart in a first direction; a metal oxide semiconductor layer, arranged between the substrate and the first metal layer, the metal oxide semiconductor layer comprising a plurality of transparent active layers, the transparent active layers comprising a first electrode conductor portion, the orthographic projection of the first electrode conductor portion on the substrate being located between two adjacent data lines; a transparent conductive layer, arranged on a side of the first metal layer away from the metal oxide semiconductor layer, the transparent conductive layer comprising a plurality of first electrodes, the first electrodes being electrically connected to the first electrode conductor portion by way of via connection; wherein, in any two adjacent transparent active layers in the first direction, the two first electrode conductor portions are staggered.

[0007] Optionally, the display panel of the display area also includes: a second metal layer, arranged between the metal oxide semiconductor layer and the first metal layer, the second metal layer includes a plurality of gate lines arranged in sequence and spaced apart in a second direction, and the first direction intersects with the second direction; wherein, in any two adjacent transparent active layers in the first direction, one of the first electrode conductor portions is arranged on one side of the gate line, and the other first electrode conductor portion is arranged on the other side of the gate line.

[0008] Optionally, a distance between an end of the first electrode conductor away from the gate line and the gate line is a first distance, and a distance between two adjacent gate lines is a second distance, wherein the first distance is less than half of the second distance.

[0009] Optionally, the transparent active layer also includes a channel and a second electrode conductor portion, and the first electrode conductor portion and the second electrode conductor portion are arranged on both sides of the channel, wherein the orthographic projection of the channel on the substrate overlaps with the orthographic projection of the gate line on the substrate, and the orthographic projection of the second electrode conductor portion on the substrate overlaps with at least part of the orthographic projection of the data line on the substrate, and the second electrode conductor portion is electrically connected to the data line by way of a via connection.

[0010] Optionally, the second electrode conductor portion in the transparent active layer is electrically connected to the data line through a second electrode connection hole, wherein the second electrode conductor portion in each transparent active layer is spaced apart from the second electrode conductor portions in other transparent active layers, and the second electrode conductor portions correspond to the second electrode connection holes one by one.

[0011] Optionally, the second electrode conductor portion in the transparent active layer is electrically connected to the data line through a second electrode connection hole, wherein the second electrode conductor portion in at least one of the transparent active layers is continuously arranged with the second electrode conductor portion in another transparent active layer, and the two continuously arranged second electrode conductor portions correspond to one second electrode connection hole.

[0012] Optionally, two transparent active layers corresponding to two consecutively arranged second electrode conductor parts are an integrated structure, and the two transparent active layers are axially symmetrically arranged.

[0013] Optionally, the first electrode is electrically connected to the first electrode conductor portion through a first electrode connection hole, wherein the first electrode includes a first part and a second part, the first part covers at least part of the channel, the second part covers the first electrode connection hole, and the maximum width of the second part in the first direction is greater than the maximum width of the first part in the first direction.

[0014] Optionally, the display panel of the display area includes a plurality of metal oxide thin film transistors, and the metal oxide thin film transistors include: the transparent active layer, a first gate, the first electrode and the second electrode, the second electrode is electrically connected to the second electrode conductor portion through a via connection, wherein the second electrode is part of the data line, and the first gate is part of the gate line.

[0015] In a second aspect, the present application provides a display device, comprising a housing and a display panel as described above, wherein the housing has a containing space, and the display panel is disposed in the containing space.

[0016] The present application provides a display panel, which has a display area, wherein the display panel in the display area comprises: a substrate; a first metal layer, which is arranged on one side of the substrate, wherein the first metal layer comprises a plurality of data lines which are arranged in sequence and spaced apart in a first direction; a metal oxide semiconductor layer, which is arranged between the substrate and the first metal layer, wherein the metal oxide semiconductor layer comprises a plurality of transparent active layers, wherein the transparent active layers comprise a first electrode conductor portion, wherein the orthographic projection of the first electrode conductor portion on the substrate is located between two adjacent data lines; a transparent conductive layer, which is arranged on a side of the first metal layer away from the metal oxide semiconductor layer, wherein the transparent conductive layer comprises a plurality of first electrodes, wherein the first electrodes are electrically connected to the first electrode conductor portion by way of via connection; wherein, in any two adjacent transparent active layers in the first direction, the two first electrode conductor portions are staggered, and the display panel provided by the present application can improve the product yield while ensuring high resolution by staggering the two first electrode conductor portions. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 This is a plan view of multiple film layers in a display panel in a display area provided in Embodiment 1 of the present application.

[0019] Figure 2 The embodiment of the present application provides Figure 1 Schematic diagram of the cross section unfolded along the AA` line.

[0020] Figure 3 This is a plan view of the first metal layer in the display area provided in the first embodiment of the present application.

[0021] Figure 4 This is a schematic plan view of the metal oxide layer in the display area provided in Example 1 of the present application.

[0022] Figure 5 This is a plan view of the transparent conductive layer in the display area provided in the first embodiment of the present application.

[0023] Figure 6 This is a schematic plan view of the second metal layer in the display area provided in the first embodiment of the present application.

[0024] Figure 7This is a plan view of multiple film layers in a display panel in a display area provided in Embodiment 2 of the present application.

[0025] Figure 8 This is a plan view of the metal oxide layer in the display area provided in the second embodiment of the present application.

[0026] Description of reference numerals:

[0027] display area AA; substrate 10; first metal layer 20; data line 21; second electrode 211; metal oxide semiconductor layer 30; transparent active layer 31; first electrode conductor portion 311; channel 312; second electrode conductor portion 313; transparent conductive layer 40; first electrode 41; first portion 411; second portion 412; second metal layer 50; gate line 51; first gate electrode 511; third metal layer 60; second gate electrode 61; functional layer 70; first gate insulating layer 80; second gate insulating layer 90; third gate insulating layer 100; first interlayer dielectric layer 110; second interlayer dielectric layer 120; first electrode connection hole H1; second electrode connection hole H2; metal oxide thin film transistor JTFT; first direction X; second direction Y; first distance d1; second distance d2; DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words such as "upper" and "lower" used generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0029] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed in itself. In addition, the present application provides various specific examples of processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials. The following is described in detail respectively, and it should be noted that the description order of the following embodiments is not used as a limitation to the preferred order of the embodiments.

[0030] Figure 1 A schematic plan view of multiple film layers in a display panel in a display area provided in Embodiment 1 of the present application; Figure 2 The embodiment of the present application provides Figure 1 Schematic diagram of the cross section unfolded along the AA` line; Figure 3 A schematic plan view of a first metal layer in a display area provided in Embodiment 1 of the present application; Figure 4 A schematic plan view of a metal oxide layer in a display area provided in Example 1 of the present application; Figure 5 This is a schematic plan view of the transparent conductive layer of the display area provided in the first embodiment of the present application. Figure 1-Figure 5 As shown, in the first aspect, Embodiment 1 of the present application provides a display panel, which can be used in a VR display device with high-resolution display requirements, and the type of the display panel can be a liquid crystal display panel.

[0031] Specifically, the display panel has a display area AA, and the display panel of the display area AA includes: a substrate 10; a first metal layer 20, which is arranged on one side of the substrate 10, and the first metal layer 20 includes a plurality of data lines 21 arranged in sequence and spaced apart in a first direction X; a metal oxide semiconductor layer 30, which is arranged between the substrate 10 and the first metal layer 20, and the metal oxide semiconductor layer 30 includes a plurality of transparent active layers 31, and the transparent active layer 31 includes a first electrode conductor portion 311, and the orthographic projection of the first electrode conductor portion 311 on the substrate 10 is located between two adjacent data lines 21; a transparent conductive layer 40, which is arranged on a side of the first metal layer 20 away from the metal oxide semiconductor layer 30, and the transparent conductive layer 40 includes a plurality of first electrodes 41, and the first electrodes 41 are electrically connected to the first electrode conductor portion 311 by via connection; wherein, in any two adjacent transparent active layers 31 in the first direction X, the two first electrode conductor portions 311 are staggered.

[0032] In the display panel provided by the present application, the metal oxide semiconductor layer 30 is light-transmissive, so the transparent active layer 31 can be formed by using the light-transmissive metal oxide semiconductor layer 30, and the first electrode conductor part 311 in the transparent active layer 31 is arranged between two adjacent data lines 21, so that the area where the first electrode conductor part 311 is located can be used as a pixel area in the display panel, thereby improving the space utilization and aperture ratio of the display area AA, thereby increasing the number of pixel areas that can be arranged in the limited display area AA, and further improving the resolution of the display panel. Exemplarily, the display panel is a liquid crystal display panel, and when the first electrode conductor part 311 is located between two adjacent data lines 21, since the first electrode conductor part 311 is light-transmissive, the first electrode conductor part 311 will not block the outgoing light of the backlight source in the liquid crystal display panel, thereby making the area where the first electrode conductor part 311 is located meet the prerequisite of being used as a pixel area.

[0033] The transparent active layer 31 is a part of the metal oxide thin film transistor JTFT of the display area AA. As a driving element of the display panel, the metal oxide thin film transistor JTFT needs to provide a driving signal to the pixel electrode of the pixel area. In order to ensure the normal transmission of the driving signal, the metal oxide thin film transistor JTFT also needs to include a first electrode 41 electrically connecting the first electrode conductor part 311 and the pixel electrode. The first electrode 41, as a lapped structure, needs to be electrically connected to the first electrode conductor part 311 through a via connection. Therefore, inevitably, the first electrode conductor part 311 and the first electrode 41 will overlap in the direction perpendicular to the substrate 10 to facilitate the setting of the via. As mentioned above, the area where the first electrode conductor part 311 is located has a demand to be used as a pixel area. Therefore, in order to ensure the light transmittance of the area where the first electrode conductor part 311 is located, the present application uses a transparent conductive layer 40 with light transmittance to form the first electrode 41.

[0034] However, the researchers unexpectedly discovered that since the first electrode 41 is electrically connected to the first electrode conductor part 311 by way of via connection, in order to ensure the stability of the via connection, it is necessary to ensure the coverage of the first electrode 41 on the via, which makes the maximum width of the first electrode 41 in the area corresponding to the via and the first electrode conductor part 311 in the first direction X (i.e., the arrangement direction of the data line 21) should be greater than the maximum width of the via in the first direction X, thereby making the maximum width of the first electrode 41 in the area corresponding to the via and the first electrode conductor part 311 larger in the first direction X. In the related art, in the first direction X, each of the first electrodes 41 is repeatedly arranged in sequence, so this structure will result in a smaller spacing distance between two adjacent first electrodes 41 in the first direction X, which is prone to safety problems and greatly reduces the stability and yield of the display panel. The present application staggers the two first electrode conductor portions 311 in any two adjacent transparent active layers 31 in the first direction X, so that the via holes respectively corresponding to the two first electrode conductor portions 311 in the two adjacent transparent active layers 31 in the first direction X are staggered, and the parts of the first electrode 41 respectively corresponding to the two first electrode conductor portions 311 in the two adjacent transparent active layers 31 in the first direction X are staggered, thereby avoiding the safety problem caused by the small spacing distance between the parts covering the via holes in the two adjacent first electrodes 41 in the first direction X, so that the display panel can achieve high resolution while improving the stability and yield of the display panel.

[0035] In some embodiments of the present application, the display panel of the display area AA also includes: a second metal layer 50, arranged between the metal oxide semiconductor layer 30 and the first metal layer 20, the second metal layer 50 includes a plurality of gate lines 51 arranged in sequence and spaced apart in a second direction Y, and the first direction X intersects with the second direction Y; wherein, in any two adjacent transparent active layers 31 in the first direction X, one of the first electrode conductor portions 311 is arranged on one side of the gate line 51, and the other first electrode conductor portion 311 is arranged on the other side of the gate line 51.

[0036] In the display panel provided by the present application, a plurality of gate lines 51 sequentially arranged at intervals in the second direction Y and a plurality of data lines 21 sequentially arranged at intervals in the first direction X are arranged crosswise, so that two adjacent data lines 21 and two adjacent gate lines 51 define a pixel area, thereby forming a plurality of pixel areas arranged in an array. That is, the gate line 51 located in the second metal layer 50 can separate two adjacent pixel areas in the second direction Y. In the present application, in any two adjacent transparent active layers 31 in the first direction X, one of the first electrode conductor parts 311 is arranged on one side of the gate line 51, and the other first electrode conductor part 311 is arranged on the other side of the gate line 51, so that when designing the layout of the display panel, the gate line 51 can be used as a reference to accurately locate one of the first electrode conductor parts 311 and the other first electrode conductor part 311, thereby ensuring the quality of the staggered arrangement of the two first electrode conductor parts 311, and making the subsequent production position of the via hole corresponding to the first electrode conductor part 311 more accurate, and further improving the production yield.

[0037] In some embodiments of the present application, the distance between one end of the first electrode conductor portion 311 away from the gate line 51 and the gate line 51 is a first distance d1, and the distance between two adjacent gate lines 51 is a second distance d2, wherein the first distance d1 is less than half of the second distance d2.

[0038] The display panel provided by the present application realizes staggered arrangement by respectively arranging two first electrode conductor parts 311 on both sides of the gate line 51. However, correspondingly, two first electrode conductor parts 311 are respectively arranged on both sides of one data line 21 in the area between two adjacent gate lines 51. In order to avoid the problem of too small spacing between two first electrodes 41 respectively electrically connected to the two first electrode conductor parts 311 arranged on both sides of the data line 21 in the area between two adjacent gate lines 51, the present application controls the distance between one end of the first electrode conductor part 311 away from the gate line 51 and the gate line 51. That is, the present application makes the distance between one end of the first electrode conductor part 311 away from the gate line 51 and the gate line 51 less than half of the distance between two adjacent gate lines 51, thereby effectively avoiding the problem of too small spacing between two first electrodes 41 respectively electrically connected to the two first electrode conductor parts 311 arranged on both sides of the data line 21 in the area between two adjacent gate lines 51, thereby improving the safety and yield of the display panel. Optionally, the width of the data line 21 is the first width, and the difference between the second distance d2 and the two first distances d1 is greater than or equal to the first width, so as to further improve the safety and yield of the display panel.

[0039] In some embodiments of the present application, the transparent active layer 31 also includes a channel 312 and a second electrode conductor portion 313, and the first electrode conductor portion 311 and the second electrode conductor portion 313 are arranged on both sides of the channel 312, wherein the orthographic projection of the channel 312 on the substrate 10 overlaps with the orthographic projection of the gate line 51 on the substrate 10, and the orthographic projection of the second electrode conductor portion 313 on the substrate 10 overlaps with at least part of the orthographic projection of the data line 21 on the substrate 10, and the second electrode conductor portion 313 is electrically connected to the data line 21 by way of a via connection.

[0040] In the display panel provided by the present application, the performance of the channel 312 of the transparent active layer 31 directly affects the device performance of the metal oxide thin film transistor JTFT, and light will deteriorate the performance of the channel 312. The present application overlaps the orthographic projection of the channel 312 on the substrate 10 with the orthographic projection of the gate line 51 on the substrate 10. On the one hand, the channel 312 can be located in the area covered by the gate line 51 in the display area AA, that is, the channel 312 is located in the area outside the pixel area in the display area AA, thereby avoiding the channel 312 occupying the space of the pixel area and improving the space utilization rate of the display area AA; on the other hand, the opacity of the gate line 51 can be used to block the external ambient light and ensure the performance of the channel 312. In addition, in order to ensure that the driving signal in the data line 21 can be smoothly transmitted to the metal oxide thin film transistor JTFT, it is necessary to electrically connect the second electrode conductor portion 313 to the data line 21. The present application makes the orthographic projection of the second electrode conductor portion 313 on the substrate 10 overlap with at least part of the orthographic projection of the data line 21 on the substrate 10, thereby ensuring that the second electrode conductor portion 313 can be electrically connected to the data line 21 through a via connection.

[0041] In some embodiments of the present application, the second electrode conductor portion 313 in the transparent active layer 31 is electrically connected to the data line 21 through the second electrode connection hole H2, wherein the second electrode conductor portion 313 in each transparent active layer 31 is spaced apart from the second electrode conductor portions 313 in other transparent active layers 31, and the second electrode conductor portions 313 correspond one-to-one to the second electrode connection holes H2.

[0042] In the display panel provided in the present application, since the second electrode conductor portion 313 in each of the transparent active layers 31 is spaced apart from the second electrode conductor portions 313 in other transparent active layers 31, and the second electrode conductor portions 313 correspond one-to-one to the second electrode connection holes H2, each of the second electrode conductor portions 313 is independently arranged. Therefore, each of the transparent active layers 31 can be arranged in the same shape, thereby reducing the difficulty of the layout design of the transparent active layer 31 and simplifying the preparation process.

[0043] In some embodiments of the present application, the first electrode 41 is electrically connected to the first electrode conductor portion 311 through the first electrode connection hole H1, wherein the first electrode 41 includes a first portion 411 and a second portion 412, the first portion 411 covers at least a portion of the channel 312, the second portion 412 covers the first electrode connection hole H1, and the maximum width of the second portion 412 in the first direction X is greater than the maximum width of the first portion 411 in the first direction X.

[0044] In the display panel provided by the present application, the first electrode 41 is electrically connected to the first electrode conductor part 311 through the first electrode connection hole H1, and the second part 412 of the first electrode 41 covers the first electrode connection hole H1. Therefore, the first electrode 41 needs to have a larger width to ensure the stability of the via connection. Accordingly, when a plurality of the second parts 412 are repeatedly arranged in the first direction X, the second parts 412 are more likely to have a safety problem of too small spacing. Since the second part 412 of the first electrode 41 covers the first electrode connection hole H1, that is, the first electrode 41 is arranged correspondingly to the first electrode conductor part 311. The present application improves the safety problem between the second parts 412 with a larger width by staggering the two first electrode conductor parts 311 in any two adjacent transparent active layers 31 in the first direction X.

[0045] In addition, the first portion 411 of the first electrode 41 is used to be electrically connected to the pixel electrode. Due to design requirements, the first portion 411 needs to cover at least part of the channel 312, but this also makes it possible for the two first portions 411 of two adjacent first electrodes 41 in the first direction X to be misaligned. Therefore, the present application sets the maximum width of the first portion 411 to be smaller than the maximum width of the second portion 412 to ensure the safety between the adjacent first electrodes 41 in the first direction X.

[0046] In some embodiments of the present application, the display panel of the display area AA includes a plurality of metal oxide thin film transistors JTFT, and the metal oxide thin film transistor JTFT includes: the transparent active layer 31, the first gate 511, the first electrode 41 and the second electrode 211, the second electrode 211 is electrically connected to the second electrode conductor portion 313 by way of a via connection, wherein the second electrode 211 is a part of the data line 21, and the first gate 511 is a part of the gate line 51.

[0047] In the display panel provided by the present application, the first electrode 41 is one of the source and the drain, the second electrode 211 is the other of the source and the drain, the transparent active layer 31, the first gate electrode 511, the first electrode 41 and the second electrode 211 are the indispensable parts of the metal oxide thin film transistor JTFT, and the present application greatly improves the aperture ratio of the display panel by adopting the transparent active layer 31 and the first electrode 41 with light transmittance. Furthermore, the present application can avoid the problem of complicated layout design caused by the separate preparation of the first gate electrode 511 and the second electrode 211 by using the second electrode 211 as a part of the data line 21 and the first gate electrode 511 as a part of the gate line 51, and in addition, it can also reduce the layout design area of ​​the first gate electrode 511 and the second electrode 211 as much as possible, thereby reducing the area of ​​the opaque parts in the metal oxide thin film transistor JTFT, and further improving the aperture ratio of the display panel.

[0048] In some embodiments of the present application, the pixel electrode in the display panel is arranged on a side of the transparent conductive layer 40 away from the substrate 10 , and the pixel electrode may be one layer or more layers.

[0049] In some embodiments of the present application, the display panel further includes a third metal layer 60, and the third metal layer 60 is disposed on the side of the metal oxide semiconductor layer 30 facing the substrate 10. The metal oxide thin film transistor JTFT includes a second gate 61, and the second gate 61 is located in the third metal layer 60. The orthographic projection of the second gate 61 on the substrate 10 overlaps with the orthographic projection of the channel 312 in the transparent active layer 31 on the substrate 10 to shield the channel 312 and avoid the problem of device performance deterioration caused by the outgoing light of the backlight source irradiating the channel 312. Optionally, the third metal layer 60 includes a bottom gate line, and the second gate 61 is a part of the bottom gate line.

[0050] In some embodiments of the present application, the display panel further includes a functional layer 70, a first gate insulating layer 80, a second gate insulating layer 90, a third gate insulating layer 100, a first interlayer dielectric layer 110, and a second interlayer dielectric layer 120, wherein the functional layer 70 is arranged on one side of the substrate 10, and the functional layer 70 can be at least one of a buffer layer and a barrier layer; the first gate insulating layer 80 is arranged on the side of the functional layer 70 away from the substrate 10; the third metal layer 60 is arranged on the side of the first gate insulating layer 80 away from the functional layer 70; the second gate insulating layer 90 is arranged on the side of the third metal layer 60 away from the first gate insulating layer 80; the metal oxide semiconductor layer 30 is arranged on the second gate insulating layer 90 away from the functional layer 70 The third metal layer 60 is disposed on one side of the third metal layer 60; the third gate insulating layer 100 is disposed on a side of the metal oxide semiconductor layer 30 away from the second gate insulating layer 90; the second metal layer 50 is disposed on a side of the third gate insulating layer 100 away from the metal oxide semiconductor layer 30; the first interlayer dielectric layer 110 is disposed on a side of the second metal layer 50 away from the third gate insulating layer 100; the first metal layer 20 is disposed on a side of the first interlayer dielectric layer 110 away from the second metal layer 50; the second interlayer dielectric layer 120 is disposed on a side of the first metal layer 20 away from the first interlayer dielectric layer 110; the transparent conductive layer 40 is disposed on a side of the second interlayer dielectric layer 120 away from the first metal layer 20.

[0051] In a second aspect, a first embodiment of the present application provides a display device, comprising a housing and a display panel as described above, wherein the housing has a containing space, and the display panel is disposed in the containing space.

[0052] Embodiment 2

[0053] Figure 7 A schematic plan view of multiple film layers in a display panel in a display area provided in Embodiment 2 of the present application; Figure 8 This is a schematic plan view of the metal oxide layer in the display area provided in the second embodiment of the present application. Figure 2 , Figure 7 and Figure 8As shown, in the first aspect, the second embodiment of the present application provides a display panel, the display panel has a display area AA, and the display panel of the display area AA includes: a substrate 10; a first metal layer 20, arranged on one side of the substrate 10, the first metal layer 20 includes a plurality of data lines 21 arranged in sequence and spaced apart in a first direction X; a metal oxide semiconductor layer 30, arranged between the substrate 10 and the first metal layer 20, the metal oxide semiconductor layer 30 includes a plurality of transparent active layers 31, the transparent active layer 31 includes a first electrode conductor portion 311, the orthographic projection of the first electrode conductor portion 311 on the substrate 10 is located between two adjacent data lines 21; a transparent conductive layer 40, arranged on a side of the first metal layer 20 away from the metal oxide semiconductor layer 30, the transparent conductive layer 40 includes a plurality of first electrodes 41, the first electrodes 41 are electrically connected to the first electrode conductor portion 311 by via connection; wherein, in any two adjacent transparent active layers 31 in the first direction X, the two first electrode conductor portions 311 are staggered.

[0054] It should be noted that the structure of the display panel provided in the second embodiment of the present application is similar to the structure of the display panel provided in the first embodiment of the present application, and the same parts will not be described in detail in the second embodiment of the present application.

[0055] In some embodiments of the present application, the second electrode conductor portion 313 in the transparent active layer 31 is electrically connected to the data line 21 through the second electrode connection hole H2, wherein the second electrode conductor portion 313 in at least one of the transparent active layers 31 is continuously arranged with the second electrode conductor portion 313 in another of the transparent active layers 31, and the two continuously arranged second electrode conductor portions 313 correspond to one second electrode connection hole H2.

[0056] In the display panel provided in the present application, since the second electrode conductor portion 313 in at least one of the transparent active layers 31 is continuously arranged with the second electrode conductor portion 313 in another of the transparent active layers 31, the two continuously arranged second electrode conductor portions 313 can correspond to one second electrode connection hole H2, that is, the two continuously arranged second electrode conductor portions 313 can be electrically connected to the data line 21 through one second electrode connection hole H2 at the same time, thereby reducing the number of the second connection holes, simplifying the preparation process of the display panel, reducing the production cost, and further improving the product yield.

[0057] In some embodiments of the present application, the two transparent active layers 31 corresponding to the two second electrode conductor portions 313 arranged continuously are an integrated structure, and the two transparent active layers 31 are arranged axially symmetrically.

[0058] In the display panel provided by the present application, since the two transparent active layers 31 corresponding to the two second electrode conductor parts 313 disposed continuously are of an integrated structure, the number of independent patterns in the metal oxide semiconductor layer 30 can be reduced, and the difficulty of forming the second electrode conductor parts 313 by the conductorization process can be reduced. In addition, since the two transparent active layers 31 are disposed axially symmetrically, the difficulty of layout design can be further reduced, and the production and preparation process can be simplified. Optionally, the two transparent active layers 31 corresponding to the two second electrode conductor parts 313 disposed continuously are disposed sequentially in the second direction Y.

[0059] In some embodiments of the present application, the two first electrodes 41 corresponding to the two transparent active layers 31 are arranged axially symmetrically.

[0060] In a second aspect, a first embodiment of the present application provides a display device, comprising a housing and a display panel as described above, wherein the housing has a containing space, and the display panel is disposed in the containing space.

[0061] In summary, the present application provides a display panel, the display panel having a display area, the display panel in the display area comprising: a substrate; a first metal layer, arranged on one side of the substrate, the first metal layer comprising a plurality of data lines arranged in sequence and spaced apart in a first direction; a metal oxide semiconductor layer, arranged between the substrate and the first metal layer, the metal oxide semiconductor layer comprising a plurality of transparent active layers, the transparent active layers comprising a first electrode conductor portion, the orthographic projection of the first electrode conductor portion on the substrate being located between two adjacent data lines; a transparent conductive layer, arranged on a side of the first metal layer away from the metal oxide semiconductor layer, the transparent conductive layer comprising a plurality of first electrodes, the first electrodes being electrically connected to the first electrode conductor portion by way of via connection; wherein, in any two adjacent transparent active layers in the first direction, the two first electrode conductor portions are staggered, and the display panel provided by the present application enables the display panel to improve product yield while ensuring high resolution by staggering the two first electrode conductor portions.

[0062] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: The display panel has a display area, and the display panel in the display area includes: substrate; A first metal layer is arranged on one side of the substrate, the first metal layer comprising a plurality of data lines arranged in sequence and spaced apart in a first direction; a metal oxide semiconductor layer, disposed between the substrate and the first metal layer, the metal oxide semiconductor layer comprising a plurality of transparent active layers, the transparent active layers comprising a first electrode conductor portion, an orthographic projection of the first electrode conductor portion on the substrate being located between two adjacent data lines; a transparent conductive layer, disposed on a side of the first metal layer away from the metal oxide semiconductor layer, the transparent conductive layer comprising a plurality of first electrodes, the first electrodes being electrically connected to the first electrode conductor portion by via connection; A second metal layer is disposed between the metal oxide semiconductor layer and the first metal layer, the second metal layer includes a plurality of gate lines sequentially spaced apart in a second direction, the first direction intersecting the second direction; Among them, in any two adjacent transparent active layers in the first direction, one of the first electrode conductor parts is arranged on one side of the gate line, and the other first electrode conductor part is arranged on the other side of the gate line.

2. The display panel according to claim 1, characterized in that: The distance between one end of the first electrode conductor away from the gate line and the gate line is a first distance, and the distance between two adjacent gate lines is a second distance, wherein the first distance is less than half of the second distance.

3. The display panel according to claim 1, characterized in that: The transparent active layer further includes a channel and a second electrode conductor portion, wherein the first electrode conductor portion and the second electrode conductor portion are arranged on both sides of the channel. The orthographic projection of the channel on the substrate overlaps with the orthographic projection of the gate line on the substrate, the orthographic projection of the second electrode conductor on the substrate overlaps with at least part of the orthographic projection of the data line on the substrate, and the second electrode conductor is electrically connected to the data line by via connection.

4. The display panel according to claim 3, characterized in that: The second electrode conductor portion in the transparent active layer is electrically connected to the data line through the second electrode connection hole. The second electrode conductor part in each of the transparent active layers is spaced apart from the second electrode conductor parts in other transparent active layers, and the second electrode conductor parts correspond to the second electrode connection holes one by one.

5. The display panel according to claim 3, characterized in that: The second electrode conductor portion in the transparent active layer is electrically connected to the data line through the second electrode connection hole. The second electrode conductor portion in at least one of the transparent active layers is continuously arranged with the second electrode conductor portion in another of the transparent active layers, and two continuously arranged second electrode conductor portions correspond to one second electrode connecting hole.

6. The display panel according to claim 5, characterized in that: The two transparent active layers corresponding to the two second electrode conductor parts arranged continuously are an integrated structure, and the two transparent active layers are arranged axially symmetrically.

7. The display panel according to claim 3, characterized in that: The first electrode is electrically connected to the first electrode conductor portion through the first electrode connection hole. The first electrode includes a first portion and a second portion, the first portion covers at least a portion of the channel, the second portion covers the first electrode connection hole, and the maximum width of the second portion in the first direction is greater than the maximum width of the first portion in the first direction.

8. The display panel according to claim 1, characterized in that: The display panel of the display area includes a plurality of metal oxide thin film transistors, and the metal oxide thin film transistors include: the transparent active layer, a first gate, the first electrode and the second electrode, the second electrode is electrically connected to the second electrode conductor portion by a via connection, wherein the second electrode is a part of the data line, and the first gate is a part of the gate line.

9. A display device, characterized in that: The display device comprises a housing and a display panel as claimed in any one of claims 1 to 8, wherein the housing has an accommodating space, and the display panel is arranged in the accommodating space.

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