An interface-free wurtzite ferroelectric nitride memory and a method of fabricating the same

Abstract

The application discloses a no-interface wurtzite ferroelectric nitride memory, which comprises a nitride semiconductor substrate and a wurtzite ferroelectric dielectric layer in contact; the wurtzite ferroelectric dielectric layer is directly grown on the nitride semiconductor substrate by using a good lattice matching between the wurtzite ferroelectric material and the nitride substrate material, through an in-situ sputtering process, an atomic layer deposition process or an epitaxial growth process; and finally, the no-interface wurtzite ferroelectric nitride memory between the wurtzite ferroelectric material and the nitride semiconductor substrate is realized, so as to solve a series of problems such as additional power consumption and reliability degradation caused by the existing non-ideal interface layer of the ferroelectric memory. The no-interface wurtzite ferroelectric nitride memory provided by the application has low power consumption, high reliability, high switching ratio and high memory window, and can be applied to the development of high-computing-power, high-energy-efficiency, low-power-consumption and high-reliability storage and computing devices and chip technologies.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic device technology, and specifically relates to an interface-free wurtzite ferroelectric nitride memory and its preparation method. Background Technology

[0002] Current computing systems based on the von Neumann architecture suffer from significant energy loss and latency due to data transmission between discrete storage and computation modules. This makes them unable to meet the ever-increasing demands for sensing, storing, and processing massive amounts of complex data, posing unprecedented challenges to the microelectronics and integrated circuit industries: high computing power, low latency, low power consumption, and high reliability. Ferroelectric memories, with their advantages of fast erasure and write speeds, strong retention characteristics, and CMOS process compatibility, are an indispensable type of modern memory device. Currently, mainstream ferroelectric memories typically use semiconductors such as Si and Ge as substrates, and ferroelectric materials in oxide systems such as HZO (zirconia-doped hafnium oxide) and HAO (aluminum-doped hafnium oxide) as the dielectric layer. Therefore, during the growth of oxide ferroelectric materials, the Si or Ge substrate inevitably oxidizes, resulting in a non-ideal interface between the ferroelectric dielectric layer and the substrate. This non-ideal interface leads to a series of problems:

[0003] (1) Non-ideal interfaces lead to additional power consumption. Due to the presence of non-ideal interfaces, a portion of the applied operating voltage will fall across the interface, reducing the voltage drop across the ferroelectric layer. This prevents the ferroelectric polarization charge from fully reversing, thus reducing the device's storage window. To enable the device to operate in its optimal state, i.e., with full reversal of the ferroelectric polarization charge, an additional operating voltage must be applied to offset the voltage drop across the non-ideal interface. This not only leads to additional power consumption but also contradicts the decreasing trend of device operating voltage in Moore's Law. Furthermore, the uniformity and quality of non-ideal interfaces are generally poor, resulting in larger leakage currents and additional static power consumption, which is detrimental to the device's application in low-power applications.

[0004] (2) Non-ideal interfaces lead to device reliability degradation. Eraser / write lifetime is one of the key parameters for measuring the reliability of memory devices. Eraser / write lifetime refers to the maximum number of erase and write cycles that a memory can withstand while ensuring that data can be stored normally. The thickness of a non-ideal interface is usually around 1 nm. The electric field inside the interface layer is extremely high when the device is operating. Therefore, the interface layer is very prone to breakdown during repeated erase and write voltage applications, which can lead to the failure of the entire device and seriously affect the reliability of the memory.

[0005] In addition, the residual polarization charge P of ferroelectric materials r The size of the magnetometer largely determines the on / off ratio and storage window of the ferroelectric memory. Traditional oxide ferroelectric materials have a residual polarization charge of only 20 μC / cm². 2Around 150 μC / cm², while wurtzite-structured ferroelectric nitride materials, such as scandium-doped aluminum nitride, can have a residual polarization charge as high as 150 μC / cm². 2 Therefore, although oxide-based ferroelectric materials have been widely used in ferroelectric memory devices, ferroelectric memories based on oxide-based ferroelectric materials still face severe challenges in terms of low power consumption, reliability, on / off ratio, and memory window. Summary of the Invention

[0006] To overcome the shortcomings of the prior art, the present invention aims to provide an interface-free wurtzite ferroelectric nitride memory and its preparation method. By utilizing the good lattice matching between the wurtzite ferroelectric material and the nitride substrate material, the wurtzite ferroelectric material is directly grown on the nitride semiconductor substrate through in-situ sputtering, atomic layer deposition, or epitaxial growth processes, ultimately realizing an interface-free wurtzite ferroelectric nitride memory between the ferroelectric material and the nitride semiconductor substrate.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] A wurtzite ferroelectric nitride memory without interface includes a substrate and a dielectric layer. The substrate is a nitride semiconductor substrate, and the dielectric layer is a wurtzite ferroelectric dielectric layer. The wurtzite ferroelectric dielectric layer and the nitride semiconductor substrate are lattice-matched so that there is no non-ideal interface layer between them.

[0009] In one embodiment, the wurtzite ferroelectric dielectric layer is aluminum nitride doped with a certain element X, denoted as AlXN. This material has a wurtzite structure and exhibits ferroelectric properties.

[0010] In one embodiment, element X is scandium, boron, or yttrium, and the doping amount is 5% to 40% of the total AlXN by molar amount.

[0011] In one embodiment, the nitride semiconductor substrate is any one of AlN, BN, GaN, and InN.

[0012] In one embodiment, the interfaceless wurtzite ferroelectric nitride memory is a ferroelectric field-effect transistor. The device structure includes, from bottom to top, a nitride semiconductor substrate, a wurtzite ferroelectric dielectric layer, a gate electrode, and a source region and a drain region disposed on the nitride semiconductor substrate. The source region is provided with a source electrode, and the drain region is provided with a drain electrode.

[0013] or,

[0014] The interfaceless wurtzite ferroelectric nitride memory is a ferroelectric capacitor type memory. The device structure includes a bottom electrode, a nitride semiconductor substrate, a wurtzite ferroelectric dielectric layer, and a top electrode arranged sequentially from bottom to top.

[0015] In one embodiment, the gate electrode, source electrode, drain electrode, top electrode, and bottom electrode are made of any one of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

[0016] The present invention also provides a method for fabricating the interface-free wurtzite ferroelectric nitride memory. In a vacuum environment, a wurtzite ferroelectric layer is grown on a nitride semiconductor substrate. The wurtzite ferroelectric layer and the nitride semiconductor substrate are lattice-matched so that there is no non-ideal interface layer between them. Electrodes are fabricated on the wurtzite ferroelectric layer and the nitride semiconductor substrate to form a memory structure.

[0017] In one embodiment, the surface of the nitride semiconductor substrate is first subjected to organic cleaning and inorganic cleaning respectively to remove surface organic matter and naturally grown oxides; then a wurtzite ferroelectric layer is grown on the nitride semiconductor substrate.

[0018] In one embodiment, a wurtzite ferroelectric layer is grown on a nitride semiconductor substrate under an N2 and argon atmosphere, using one of the following processes;

[0019] Process 1, in-situ sputtering process, the steps are as follows:

[0020] The reaction chamber is evacuated until the vacuum pressure in the reaction chamber reaches below 1e-5 Torr. First, an AlN thin film is grown on the nitride semiconductor substrate as a seed layer, and then AlXN is sputtered to grow.

[0021] Process 2, epitaxial growth process, the steps are as follows:

[0022] AlXN is heteroepitaxially grown on a nitride semiconductor substrate. Al atoms and X atoms provided by Al source and X source react with nitrogen atoms provided by nitrogen gas. By adjusting the temperature of Al source and X source and the flow rate of nitrogen gas, the growth rate of AlXN layer and the doping concentration of X are controlled, thereby precisely controlling the composition of AlXN. The epitaxial temperature is 1000-1300℃.

[0023] Specifically, the present invention can employ one of the following methods to fabricate electrodes on a wurtzite ferroelectric layer and a nitride semiconductor substrate to form a memory structure;

[0024] Method 1:

[0025] Metals are deposited on a wurtzite ferroelectric layer using magnetron sputtering or deposition processes.

[0026] Using photolithography, the source region, gate region, and drain region are selected on the deposited metal;

[0027] Using an etching process, the metal and wurtzite ferroelectric layer of the source and drain regions on both sides of the gate region are etched away, while the wurtzite ferroelectric layer above the gate region is retained, and the gate electrode is formed on the wurtzite ferroelectric layer.

[0028] Ion implantation is used to dope the source and drain regions on a nitride semiconductor substrate to form doped source and drain regions.

[0029] By using magnetron sputtering or deposition processes, metal is deposited above the source region to form the source electrode, and metal is deposited above the drain region to form the drain electrode, thus obtaining an interface-free wurtzite ferroelectric nitride field-effect transistor.

[0030] Method 2:

[0031] An electrode material is grown on top of a wurtzite ferroelectric layer using sputtering or deposition processes.

[0032] Using photolithography and etching processes, excess metal and wurtzite ferroelectric layer around the perimeter are etched away, leaving the wurtzite ferroelectric layer in the middle, and a top electrode is formed on the wurtzite ferroelectric layer.

[0033] By using sputtering or deposition processes, an electrode material is grown under a nitride semiconductor substrate to form a bottom electrode, resulting in an interface-free wurtzite ferroelectric nitride capacitor memory.

[0034] In one embodiment, the ion implantation process has an energy range of 20-180 keV and a dose range of 1e14 to 2e15 cm⁻¹. -3 The sputtering process involves first evacuating the reaction chamber until the vacuum pressure in the reaction chamber reaches 0.02 Torr, and then sputtering to form the gate electrode, source electrode, drain electrode, top electrode, or bottom electrode under conditions of sputtering power of 350W and argon pressure of 5 millitor.

[0035] Compared with the prior art, the beneficial effects of the present invention are:

[0036] The beneficial effects of this invention are as follows: This invention provides a wurtzite ferroelectric nitride memory structure design and its fabrication method without an interface. By utilizing in-situ sputtering, atomic layer deposition, or epitaxial growth processes, a wurtzite ferroelectric dielectric layer is directly grown on a nitride substrate, thereby obtaining good lattice matching between the AlXN ferroelectric material and the nitride substrate material. This achieves a wurtzite ferroelectric nitride memory device without an interface between the AlXN ferroelectric material and the nitride substrate, thus solving a series of problems such as additional power consumption and reliability degradation caused by non-ideal interfaces in existing ferroelectric memories based on oxide system ferroelectric materials.

[0037] In addition, this invention selects AlXN with a wurtzite structure as the ferroelectric material, and utilizes the extremely high residual polarization charge of AlXN to solve the problems of small on / off ratio and memory window of traditional ferroelectric memory devices based on oxide system ferroelectric materials, which is conducive to the development of in-memory computing technology with high computing power, high energy efficiency, low power consumption and high reliability.

[0038] This invention provides a design and fabrication method for an interface-free wurtzite ferroelectric nitride memory structure with low power consumption, high reliability, high on / off ratio, and high memory window. It can be used in memory computing devices and chip technologies with high computing power, high energy efficiency, low power consumption, and high reliability. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the core structure of the interface-free wurtzite ferroelectric nitride memory of the present invention.

[0040] Figure 2 This is a schematic diagram of the structure of the interfaceless wurtzite ferroelectric nitride ferroelectric field-effect transistor device of the present invention.

[0041] Figure 3 This is a schematic diagram of the interface-free wurtzite ferroelectric nitride capacitor memory structure of the present invention.

[0042] Figure 4 This is a schematic diagram of the fabrication process of the interface-free wurtzite ferroelectric nitride ferroelectric field-effect transistor of the present invention.

[0043] Figure 5 This is a schematic diagram of the fabrication process of the interfaceless wurtzite ferroelectric nitride capacitive memory of the present invention.

[0044] Among them, 1. wurtzite ferroelectric layer, 2. nitride semiconductor substrate, 3. gate electrode, 4. bottom electrode, 5. source electrode, 6. drain electrode, 7. source region, 8. drain region, and 9. top electrode. Detailed Implementation

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0046] Those skilled in the art should understand that, in the disclosure of this invention, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0047] It is understood that the term "a" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple, and the term "a" should not be understood as a limitation on the number.

[0048] like Figure 1 As shown, Figure 1 This is a schematic diagram of the core structure of the interface-free wurtzite ferroelectric nitride memory. The core structure of the interface-free wurtzite ferroelectric nitride memory includes a wurtzite ferroelectric dielectric layer 1 and a nitride semiconductor substrate 2 in contact. That is, the nitride semiconductor substrate 2 and the wurtzite ferroelectric dielectric layer 1 replace the conventional substrate and dielectric layer, respectively. The wurtzite ferroelectric dielectric layer 1 and the nitride semiconductor substrate 2 have lattice matching and good contact; there is no non-ideal interface between them, which is the meaning of "interface-free" in this invention.

[0049] In an embodiment of the present invention, the wurtzite ferroelectric dielectric layer 1 is aluminum nitride doped with a certain element X, denoted as AlXN. This material has a wurtzite structure and exhibits ferroelectricity, and can be prepared on a nitride semiconductor substrate 2 by in-situ sputtering, atomic layer deposition, or epitaxial growth. For example, any one of AlScN with a scandium content between 5% and 40%, AlBN with a boron content between 5% and 40%, or AlYN with a yttrium content between 5% and 40% can be used.

[0050] In embodiments of the present invention, the nitride semiconductor substrate 2 is any one of AlN, BN, GaN and InN.

[0051] In this invention, an in-situ sputtering process or an epitaxial growth process can be used to grow a wurtzite ferroelectric layer 1 on a nitride semiconductor substrate 2 in a vacuum environment. Electrodes are then fabricated on the wurtzite ferroelectric layer 1 and the nitride semiconductor substrate 2 to form a memory structure.

[0052] In this invention, it is necessary to ensure that the surface of the nitride semiconductor substrate 2 is clean. Therefore, before the reaction, the surface of the nitride semiconductor substrate 2 can be organically cleaned and inorganically cleaned respectively. The purpose of organic cleaning is to remove organic matter on the surface, and the purpose of inorganic cleaning is to remove naturally grown oxides on the surface. Then, the wurtzite ferroelectric layer 1 is grown on the nitride semiconductor substrate 2. The chemical used can be a solution of HF:H2O = 1:20.

[0053] The process conditions of this invention are N2 and argon atmosphere, and one of the following processes can be used:

[0054] The in-situ sputtering process consists of the following steps:

[0055] The reaction chamber was evacuated until the vacuum pressure in the reaction chamber reached below 1e-5 Torr. First, an AlN thin film was grown on the nitride semiconductor substrate 2 as a seed layer. Then, AlXN was sputtered under the conditions of magnetron sputtering power of 15W, argon pressure of 5 mTorr, nitrogen flow rate of 100 sccm, argon flow rate of 20 sccm, and chamber temperature of 200℃.

[0056] In this process, a seed layer is grown on a clean substrate surface before AlScN is grown, which ensures that there is no non-ideal interface layer. Compared with oxides, nitride substrates have the inherent advantage of good lattice matching with wurtzite ferroelectric materials.

[0057] The epitaxial growth process consists of the following steps:

[0058] AlXN is heteroepitaxially grown on a nitride semiconductor substrate 2. Al atoms and X atoms provided by Al source and X source react with nitrogen atoms provided by nitrogen gas. By adjusting the temperature of Al source and X source and the flow rate of nitrogen gas, the growth rate of AlXN layer and the doping concentration of X are controlled, thereby precisely controlling the composition of AlXN. The epitaxial temperature is 1000-1300℃.

[0059] In this invention, to ensure good lattice matching between the wurtzite ferroelectric dielectric and the nitride semiconductor substrate, the cavity of the equipment (e.g., magnetron sputtering or molecular beam epitaxy equipment) must be highly clean, and the wurtzite ferroelectric dielectric layer 1 and the nitride semiconductor substrate 2 are grown in situ.

[0060] In one embodiment of the present invention, an interface-free wurtzite ferroelectric nitride ferroelectric field-effect transistor is provided, such as... Figure 2 As shown, the interfaceless wurtzite ferroelectric nitride ferroelectric field-effect transistor includes a nitride semiconductor substrate 2, a wurtzite ferroelectric dielectric layer 1, a gate electrode 3 arranged sequentially from bottom to top, and a source region 7 and a drain region 8 disposed on the nitride semiconductor substrate 2. The source region 7 is provided with a source electrode 5, and the drain region 8 is provided with a drain electrode 6.

[0061] Based on the aforementioned preparation of wurtzite ferroelectric layer 1 and nitride semiconductor substrate 2:

[0062] 11. Deposit metal on wurtzite ferroelectric layer 1 using magnetron sputtering or deposition processes;

[0063] 12. Using photolithography, select the source region, gate region, and drain region on the deposited metal;

[0064] 13. Using an etching process, the metal and wurtzite ferroelectric layer 1 of the source and drain regions on both sides of the gate region are etched away, while the wurtzite ferroelectric layer 1 above the gate region is retained, and the gate electrode 3 is formed on the wurtzite ferroelectric layer 1.

[0065] 14. Using ion implantation technology, the source and drain regions on the nitride semiconductor substrate 2 are ion implanted and doped to form doped source region 7 and drain region 8.

[0066] 15. Using magnetron sputtering or deposition processes, deposit metal above the source region 7 to form the source electrode 5, and deposit metal above the drain region 8 to form the drain electrode 6, to obtain an interface-free wurtzite ferroelectric nitride field-effect transistor.

[0067] In another embodiment of the present invention, an interface-free wurtzite ferroelectric nitride capacitor memory is provided, such as... Figure 3 As shown, the interfaceless wurtzite ferroelectric nitride capacitor memory includes a bottom electrode 4, a nitride semiconductor substrate 2, a wurtzite ferroelectric dielectric layer 1, and a top electrode 9 arranged sequentially from bottom to top.

[0068] Based on the aforementioned preparation of wurtzite ferroelectric layer 1 and nitride semiconductor substrate 2:

[0069] 21. Using sputtering or deposition processes, grow an electrode material layer on top of the wurtzite ferroelectric layer 1;

[0070] 22. Using photolithography and etching processes, the excess metal and wurtzite ferroelectric layer 1 around the periphery are etched away, leaving the wurtzite ferroelectric layer 1 in the middle, and a top electrode 9 is formed on the wurtzite ferroelectric layer 1.

[0071] 23. Using sputtering or deposition processes, an electrode material is grown under the nitride semiconductor substrate 2 to form the bottom electrode 4, thus obtaining an interface-free wurtzite ferroelectric nitride capacitor memory.

[0072] In embodiments of the present invention, the gate electrode 3, source electrode 5, drain electrode 6, top electrode 9, and bottom electrode 4 are all made of metallic materials. Specifically, the materials of the gate electrode 3, source electrode 5, drain electrode 6, top electrode 9, and bottom electrode 4 can be any one of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

[0073] The ion implantation process described in this invention preferably has an energy range of 20-180 keV and a dose range of 1e14 to 2e15 cm⁻¹. -3 The sputtering process described in this invention first uses a molecular pump or a cold pump to evacuate the reaction chamber until the vacuum pressure in the reaction chamber reaches 0.02 Torr. Then, sputtering is performed under the conditions of sputtering power of 350W and argon pressure of 5 millitor to form the gate electrode 3, source electrode 5, drain electrode 6, top electrode 9 or bottom electrode 4.

[0074] This invention utilizes in-situ sputtering, atomic layer deposition, or epitaxial growth processes to directly grow a wurtzite ferroelectric layer on a nitride substrate, thereby achieving excellent lattice matching between the AlXN ferroelectric material and the nitride substrate material. This enables a wurtzite ferroelectric memory device without an interface between the AlXN ferroelectric material and the nitride substrate, solving a series of problems such as additional power consumption and reliability degradation caused by non-ideal interfaces in existing oxide-based ferroelectric memory devices. Furthermore, this invention selects wurtzite-structured AlXN as the ferroelectric material, leveraging AlXN's extremely high residual polarization charge to address the issues of small on / off ratio and memory window in traditional oxide-based ferroelectric memory devices. This is beneficial for the development of high-performance, high-energy-efficiency, low-power, and high-reliability in-memory computing technologies. This invention simultaneously provides a low-power, high-reliability, high-on / off ratio, and large-memory-window interface-free wurtzite ferroelectric nitride memory structure design and its fabrication method, which can be used in high-performance, high-energy-efficiency, low-power, and high-reliability in-memory computing devices and chip technologies.

[0075] To make the above features and advantages more apparent and understandable, specific implementation examples are provided below, along with detailed explanations in conjunction with the accompanying drawings.

[0076] Example 1

[0077] One embodiment of the present invention is an interfaceless wurtzite ferroelectric nitride memory, specifically an interfaceless Al... 0.7 Sc 0.3 The fabrication process of N / GaN ferroelectric field-effect transistor devices is as follows: Figure 4 This includes the following steps:

[0078] Step 1: Select a substrate.

[0079] N-type GaN was chosen as the nitride semiconductor substrate 2, such as Figure 4 (a).

[0080] Step 2: Growth of Al 0.7 Sc 0.3 N-ferroelectric materials.

[0081] A 50 nm thick Al layer was epitaxially grown on a GaN substrate using in-situ molecular beam epitaxy. 0.7 Sc 0.3 N-ferroelectric materials, such as Figure 4 (b)

[0082] Step 3: Growing metallic materials.

[0083] Using reactive sputtering, a molecular pump and a cold pump are used to evacuate the reaction chamber until the vacuum pressure reaches 8E-6 Torr. Then, under conditions of 350W power and 5mTorr Ar pressure, a platinum (Pt) target is used to uniformly sputter the sample surface, depositing a 50nm thick layer of Pt metal material. Figure 4 (c)

[0084] Step 4: Select the source region, gate region, and drain region to form Al 0.7 Sc 0.3 N-ferroelectric layer and gate electrode.

[0085] Using a 365nm I-line photolithography process, the source, gate, and drain regions were marked on a Pt metal substrate. The gate region was located in the center of the sample, while the source and drain regions were located on either side of the gate region. Using an ion beam etching process, argon ions were accelerated by an anolyte field to physically bombard the sample surface. Under the masking effect of photoresist, the source and drain regions on either side of the gate region were etched onto the surface of the nitride semiconductor substrate 2. Excess portions around the gate, source, and drain regions were etched onto the surface of the nitride semiconductor substrate 2, forming Al2. 0.7 Sc 0.3 N-ferroelectric layer 4 and gate electrode 3, such as Figure 4 (d)

[0086] Step 5: Form the doped source and drain regions.

[0087] An energy of 20 keV and a dose of 1.3e14 cm⁻¹ were injected into the source and drain regions. -3 The Mg element was added, and the implanted sample was placed in an MOCVD device and annealed for 5 min under a nitrogen atmosphere, atmospheric pressure, and 1230℃. This activated the source and drain regions by ion implantation, forming p-type doped source regions 7 and 8. Figure 4 (e).

[0088] Step 6: Form the source electrode and drain electrode.

[0089] Using electron beam deposition at room temperature, solid Ni was deposited as the source to form source electrode 5 and drain electrode 6 on top of source region 7 and drain region 8, respectively, thus achieving interface-free Al. 0.7 Sc 0.3 Fabrication of N / GaN ferroelectric field-effect transistor devices, such as Figure 4 (f).

[0090] Example 2

[0091] One embodiment of the present invention is an interfaceless wurtzite ferroelectric nitride memory, specifically an interfaceless Al... 0.8 B 0.2 The fabrication process of N / AlN ferroelectric capacitor memory is as follows: Figure 5 This includes the following steps:

[0092] Step 1: Select a substrate, such as... Figure 5 (a).

[0093] AlN was chosen as the nitride semiconductor substrate.

[0094] Step 2: Growth of Al 0.8 B 0.2 N-ferroelectric materials, such as Figure 5 (b)

[0095] A 30 nm thick Al layer was grown on the surface of an AlN substrate using in-situ sputtering and atomic layer deposition processes. 0.8 B 0.2 N-ferroelectric materials.

[0096] Step 3: Growing metallic materials, such as Figure 5 (c)

[0097] Using magnetron sputtering, a 50 nm thick W layer was grown on a gate dielectric layer at room temperature with solid W as the sputtering target under nitrogen and argon atmospheres and a pressure of 1.2e-7 Pa.

[0098] Step 4: Formation of Al 0.8 B 0.2 N-ferroelectric layer and top electrode, such as Figure 5 (d)

[0099] Using a dry etching process, the excess portion around the top electrode is etched to the substrate surface to form Al. 0.8 B 0.2 N-ferroelectric layer 11 and top electrode 9.

[0100] Step 5: Form the bottom electrode, such as Figure 5 (e).

[0101] Using the same process as described in step three, an electrode material is grown beneath the AlN semiconductor substrate to form the bottom electrode 4, thus completing the interface-free Al... 0.8 B 0.2 Fabrication of N / AlN ferroelectric capacitor memory.

[0102] Example 3

[0103] One embodiment of the present invention is an interfaceless wurtzite ferroelectric nitride memory, specifically an interfaceless Al... 0.75 Y 0.25 The fabrication process of N / BN ferroelectric field-effect transistor devices is as follows: Figure 4 This includes the following steps:

[0104] Step A: Select a substrate, such as Figure 4 (a).

[0105] N-type BN was selected as the nitride semiconductor substrate.

[0106] Step B: Growth of Al 0.75 Y 0.25 N-ferroelectric materials, such as Figure 4 (b)

[0107] A 20 nm thick Al layer was grown on a BN substrate using in-situ molecular beam epitaxy. 0.75 Y 0.25 N-ferroelectric materials.

[0108] Step C: Growing metallic materials, such as Figure 4 (c)

[0109] Using magnetron sputtering, a 50 nm thick TiN layer was grown on the upper surface of a sample at room temperature with solid TiN as the sputtering target under nitrogen and argon atmospheres and a pressure of 1.2e-7 Pa.

[0110] Step D: Select the source region, gate region, and drain region to form Al. 0.75 Y 0.25 N-ferroelectric dielectric layer and gate electrode, such as Figure 4 (d)

[0111] Using a 365nm I-line photolithography process, the source, gate, and drain regions were marked on a TiN metal substrate. The gate region was located in the center of the sample, while the source and drain regions were located on either side of the gate region. Using a dry etching process, under the masking effect of photoresist, the source and drain regions on either side of the gate region were etched onto the surface of the nitride semiconductor substrate 2. Excess portions around the gate, source, and drain regions were etched onto the surface of the nitride semiconductor substrate 2, forming Al0. 0.75 Y 0.25 N-ferroelectric layer 4 and gate electrode 3.

[0112] Step E: Form doped source and drain regions, such as Figure 4 (e).

[0113] An energy of 50 keV and a dose of 1.3e14 cm⁻¹ were injected into the source and drain regions. -3 The Mg element was injected, and the implanted sample was placed in an annealing furnace and annealed for 5 minutes under a nitrogen atmosphere, normal pressure, and 1230℃, thereby realizing the ion implantation activation of the source and drain regions and forming p-type doped source regions 7 and 8.

[0114] Step F: Form the source and drain electrodes, such as Figure 4 (f).

[0115] Using magnetron sputtering, at room temperature, with solid Pt as the sputtering target, and under nitrogen and argon atmospheres and a pressure of 1.2e-7 Pa, a 50 nm thick Pt layer was deposited above the source region 7 and drain region 8 to form the source electrode 5 and drain electrode 6, completing the interface-free Al deposition process. 0.75 Y 0.25 Fabrication of N / BN ferroelectric field-effect transistor devices.

[0116] In summary, this invention utilizes the excellent lattice matching between wurtzite ferroelectric material and nitride substrate material to directly grow a wurtzite ferroelectric dielectric layer on a nitride semiconductor substrate through in-situ sputtering, atomic layer deposition, or epitaxial growth processes. This ultimately achieves a wurtzite ferroelectric nitride memory without an interface layer between the wurtzite ferroelectric material and the nitride semiconductor substrate, thus solving a series of problems in existing ferroelectric memories caused by the presence of non-ideal interface layers, such as additional power consumption and reliability degradation. The low-power, high-reliability, high on / off ratio, and high memory window interface-free wurtzite ferroelectric nitride memory provided by this invention can be applied to the development of high-performance, high-energy-efficiency, low-power, and high-reliability in-memory computing devices and chip technologies.

[0117] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Anyone can modify or make equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the claims.

Claims

1. A wurtzite ferroelectric nitride memory without interface, comprising a substrate and a dielectric layer, characterized in that, The substrate is a nitride semiconductor substrate (2), the dielectric layer is a wurtzite ferroelectric dielectric layer (1), the wurtzite ferroelectric dielectric layer (1) and the nitride semiconductor substrate (2) are lattice matched so that there is no non-ideal interface layer between them, the wurtzite ferroelectric dielectric layer (1) is aluminum nitride doped with a certain element X, denoted as AlXN, the AlXN material has a wurtzite structure and ferroelectricity, the element X is scandium, boron or yttrium, the nitride semiconductor substrate (2) is any one of AlN, BN, GaN and InN; wherein the surface of the nitride semiconductor substrate (2) is first organically cleaned and inorganically cleaned to remove organic matter and naturally grown oxides on the surface; then, the wurtzite ferroelectric dielectric layer (1) is grown on the nitride semiconductor substrate (2) in a vacuum environment.

2. The interfaceless wurtzite ferroelectric nitride memory according to claim 1, characterized in that, In terms of molar amount, the doping amount of element X is 5% to 40% of the total AlXN.

3. The interfaceless wurtzite ferroelectric nitride memory according to claim 1 or 2, characterized in that, The interfaceless wurtzite ferroelectric nitride memory is a ferroelectric field-effect transistor. The device structure includes a nitride semiconductor substrate (2), a wurtzite ferroelectric dielectric layer (1), a gate electrode (3) arranged from bottom to top, and a source region (7) and a drain region (8) disposed on the nitride semiconductor substrate (2). The source region (7) is provided with a source electrode (5), and the drain region (8) is provided with a drain electrode (6). or, The interfaceless wurtzite ferroelectric nitride memory is a ferroelectric capacitor type memory. The device structure includes a bottom electrode (4), a nitride semiconductor substrate (2), a wurtzite ferroelectric dielectric layer (1), and a top electrode (9) arranged sequentially from bottom to top.

4. The interfaceless wurtzite ferroelectric nitride memory according to claim 3, characterized in that, The gate electrode (3), source electrode (5), drain electrode (6), top electrode (9), and bottom electrode (4) are made of any one of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

5. The method for preparing the interfaceless wurtzite ferroelectric nitride memory according to claim 1, characterized in that, First, the surface of the nitride semiconductor substrate (2) is cleaned organically and inorganically to remove organic matter and naturally grown oxides. Then, in a vacuum environment, a wurtzite ferroelectric layer (1) is grown on the nitride semiconductor substrate (2). The wurtzite ferroelectric layer (1) and the nitride semiconductor substrate (2) are lattice matched so that there is no non-ideal interface layer between them. Electrodes are processed on the wurtzite ferroelectric layer (1) and the nitride semiconductor substrate (2) to form a memory structure.

6. The method for preparing the interfaceless wurtzite ferroelectric nitride memory according to claim 5, characterized in that, A wurtzite ferroelectric layer (1) is grown on a nitride semiconductor substrate (2) under an N2 and argon atmosphere, using one of the following processes; Process 1, in-situ sputtering, the steps are as follows: The reaction chamber is evacuated until the vacuum pressure in the reaction chamber reaches below 1e-5 Torr. First, an AlN thin film is grown on the nitride semiconductor substrate (2) as a seed layer, and then AlXN is sputtered to grow. Process 2, epitaxial growth, the steps are as follows: AlXN is heteroepitaxially grown on a nitride semiconductor substrate (2). Al atoms and X atoms provided by Al source and X source react with nitrogen atoms provided by nitrogen gas. By adjusting the temperature of Al source and X source and the flow rate of nitrogen gas, the growth rate of AlXN layer and the doping concentration of X are controlled, thereby precisely controlling the composition of AlXN. The epitaxial temperature is 1000-1300℃.

7. The method for preparing the interfaceless wurtzite ferroelectric nitride memory according to claim 6, characterized in that, Electrodes are fabricated on a wurtzite ferroelectric layer (1) and a nitride semiconductor substrate (2) using one of the following methods to form a memory structure; Method 1: (11) Deposit metal on the wurtzite ferroelectric layer (1) using magnetron sputtering or deposition process; (12) Using photolithography, the source region, gate region and drain region are selected on the deposited metal; (13) Using an etching process, the metal and wurtzite ferroelectric layer (1) of the source region and drain region on both sides of the gate region are etched away, while the wurtzite ferroelectric layer (1) above the gate region is retained, and a gate electrode (3) is formed on the wurtzite ferroelectric layer (1). (14) Using ion implantation process, the source region and drain region on the nitride semiconductor substrate (2) are ion implanted and doped to form doped source region (7) and drain region (8). (15) Using magnetron sputtering or deposition process, metal is deposited above the source region (7) to form the source electrode (5), and metal is deposited above the drain region (8) to form the drain electrode (6), thus obtaining an interface-free wurtzite ferroelectric nitride field-effect transistor. Method 2: (21) An electrode material is grown on top of the wurtzite ferroelectric layer (1) using a sputtering or deposition process; (22) Using photolithography and etching processes, the excess metal and wurtzite ferroelectric layer (1) around the periphery are etched away, leaving the wurtzite ferroelectric layer (1) in the middle, and a top electrode (9) is formed on the wurtzite ferroelectric layer (1). (23) Using sputtering or deposition processes, an electrode material is grown under the nitride semiconductor substrate (2) to form a bottom electrode (4), thus obtaining an interface-free wurtzite ferroelectric nitride capacitor memory.

8. The method for preparing the interfaceless wurtzite ferroelectric nitride memory according to claim 7, characterized in that, The ion implantation process has an energy range of 20-180 keV and a dose range of 1e14~2e15 cm⁻¹. -3 The sputtering process first evacuates the reaction chamber until the vacuum pressure in the reaction chamber reaches 0.02 Torr, and then sputters to form a gate electrode (3), source electrode (5), drain electrode (6), top electrode (9) or bottom electrode (4) under the conditions of sputtering power of 350W and argon pressure of 5 millitor.

Images