Integrated circuit (IC) and method of operating the same

Abstract

An integrated circuit (IC) employs a subsystem shared cache memory to facilitate expansion of a low power island (LPI) memory. An LPI subsystem and a primary subsystem access a memory subsystem on a first access interface in a first power mode, and the LPI subsystem accesses the memory subsystem through a second access interface in a low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access data stored in an external memory or a version of data stored in a shared memory circuit. In the low power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to the LPI memory interface of the memory subsystem to access the shared memory circuit to expand the LPI memory.

Description

[0001] Priority application

[0002] This application claims priority to U.S. patent application serial number 17 / 390,274, filed on July 30, 2021, entitled “INTEGRATED CIRCUITS (IC) EMPLOYING SUBSYSTEM SHARED CACHE MEMORY FOR FACILITATING EXTENSION OF LOW-POWER ISLAND (LPI) MEMORY AND RELATED METHODS,” which is incorporated herein by reference in its entirety. Background Art

[0003] I. Technical field

[0004] The field of the present disclosure relates generally to integrated circuits (ICs) that include multiple subsystems that function during normal operation of the IC and a low power island (LPI) subsystem that also operates in a low power mode.

[0005] II. Background Technology

[0006] An integrated circuit (IC) including multiple subsystems (including peripherals and communication interfaces) for instruction and data processing may be referred to as a system on chip (SoC). SoCs may be used to replace multiple chips in electronic devices to perform multiple functions and user applications. The subsystems in the SoC may execute applications or threads of applications that require instructions and data, or may read and write stored information in other ways. The SoC may be coupled to an external memory. The memory subsystem manages the storage of data and instructions in the external memory and in the SoC. In this regard, the SoC also includes a cache memory in which copies or versions of instructions and data are stored to reduce access latency compared to accessing external memory. Each of the subsystems may have its own dedicated cache, and the memory subsystem may also access a cache memory shared between the subsystems. The shared cache memory is used as a higher level cache than the dedicated cache in each subsystem. In some cases, the shared cache may be the highest level cache in the SoC, referred to as the last level cache of the memory subsystem.

[0007] When the subsystems of the electronic device are inactive, the SoC may enter a low power mode. For example, in low power mode, the supply voltage to the subsystem may be decoupled or turned off to save power. Some circuits must remain active to perform functions that are expected to continue, and detect stimuli that can wake up the electronic device to return to normal operation from low power mode. The circuits that remain active in low power mode may be coupled to a secondary power supply, and such circuits may be referred to as low power island (LPI) subsystems, in which all other circuits (e.g., all circuits around the LPI) are powered off. The LPI subsystem may include processing circuits that execute instructions and generate data, which require access to memory. The amount of memory available for the LPI subsystem to store instructions and data affects the capability level of the LPI subsystem, but increasing the amount of memory in the SoC to be used in the LPI subsystem increases the area and cost of the IC. Therefore, the amount of memory in the LPI subsystem may be limited, which limits the functionality of the SoC in low power mode. Summary of the invention

[0008] Aspects disclosed herein include an integrated circuit (IC) that facilitates expansion of a low power island (LPI) memory using a subsystem shared cache memory. Related methods are also disclosed. The IC includes a plurality of main subsystems operating in a first power mode, and an LPI subsystem operating in the first power mode and a second power mode (e.g., a low power mode). The LPI subsystem and the main subsystems access a shared memory circuit in a memory subsystem through a subsystem memory interface in the first power mode. The main subsystems and the LPI subsystem can send a subsystem memory access request to the memory subsystem on the subsystem memory interface to access instructions and data that can be stored in an external memory and can be cached in the shared memory circuit. The subsystem memory interface includes a tag random access memory (RAM) to identify a cache line in the shared memory circuit that is dynamically assigned to a memory address in a subsystem memory access request.

[0009] The LPI subsystem accesses instructions and data in a first LPI memory image in the first power mode. The first LPI memory image is a memory area that includes instructions and data for all processes executed by the LPI subsystem in the first power mode. The LPI subsystem accesses a second LPI memory image in the second power mode. The second LPI memory image is a subset of the first LPI memory image because the LPI subsystem executes fewer processes in the second power mode. Therefore, the second LPI memory image requires less memory in the second power mode. In various exemplary aspects, memory addresses in the second LPI memory image are directly mapped to cache lines in the shared memory circuit, which can store the entire second LPI memory image in the second power mode. Directly mapping these addresses eliminates the need for the tag RAM and associated hardware to operate in the second power mode. The LPI subsystem can access these cache lines in the shared memory circuit in the second power mode by sending LPI memory access requests to the LPI memory interface. Since the second LPI memory image is a subset of the first LPI memory image, the second LPI memory image is also accessible by the LPI subsystem in the first power mode. In the first power mode, the subsystem memory interface also maps memory addresses in the second LPI memory image directly to associated cache lines in the shared memory circuit. In this regard, the addresses of instructions and data in the second LPI memory image need to remain constant in the first power mode and the second power mode. Therefore, the second LPI memory image is stored in a static memory address range in the external memory, which means that the instructions and data of the second LPI memory image are fixed and will not be relocated by the memory controller.

[0010] In various exemplary aspects disclosed herein, an IC configured to operate in one of a first power mode and a second power mode is disclosed. The IC includes an LPI subsystem circuit and a memory subsystem. The memory subsystem includes a shared memory circuit and a subsystem memory interface, the subsystem memory interface being configured to: in response to the IC operating in the first power mode, receive a first subsystem memory access request from the LPI subsystem circuit, and access the shared memory circuit in response to the first subsystem memory access request. The memory subsystem also includes an LPI memory interface, the LPI memory interface being configured to: in response to the IC operating in the second power mode, receive an LPI memory access request from the LPI subsystem circuit, and access the shared memory circuit in response to the LPI memory access request.

[0011] In another exemplary aspect, a method of operating an IC in one of a first power mode and a second power mode is disclosed. The method includes: in response to the IC operating in the first power mode, receiving a first subsystem memory access request from an LPI subsystem circuit in a subsystem memory interface in a memory subsystem; and in response to the first subsystem memory access request, accessing a shared memory circuit by the subsystem memory interface. The method also includes: in response to the IC operating in the second power mode, receiving an LPI memory access request from the LPI memory interface in the LPI memory interface in the memory subsystem; and in response to the LPI memory access request, accessing the shared memory circuit by the LPI memory interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram of a conventional integrated circuit (IC) including a memory subsystem that receives memory access requests for data stored in an external memory from a plurality of subsystems and a low power island (LPI) subsystem in a first power mode and is powered off in a second power mode;

[0013] Figure 2 is an illustration of a cache memory circuit in an IC partitioned into cache lines assigned to one or more subsystems and accessed by a tagged random access memory (RAM) in the first power mode;

[0014] Figure 3 is an exemplary IC including an LPI subsystem configured to access a shared memory circuit through a subsystem memory interface in a memory subsystem in a first power mode and to access the shared memory circuit through an LPI memory interface in a second power mode;

[0015] Figure 4 is a diagram showing a memory map of an external memory of a low power image statically mapped to a contiguous address range including memory used in low power mode Figure 3 Instructions and data for the LPI subsystem in;

[0016] Figure 5 is a diagram of a shared memory circuit including dynamically allocated cache lines and cache lines that map directly to memory addresses in LPI memory access requests;

[0017] Figure 6 yes Figure 3a flow chart of a method in an IC of claim 1, the IC comprising an LPI subsystem configured to access a shared memory circuit as a last level cache on a subsystem memory interface to a memory subsystem in a first power mode and to access the shared memory circuit as an LPI subsystem memory on an LPI memory interface in a second power mode;

[0018] Figure 7 is a block diagram of an exemplary wireless communication device including a radio frequency (RF) module, the RF module including a system on chip (SoC) in an IC, in which an LPI subsystem circuit is configured to access a shared memory circuit by a subsystem memory interface of a memory subsystem in a first power mode and to access the shared memory circuit by an LPI memory interface in a low power mode, such as Figure 3 as shown; and

[0019] Figure 8 is a block diagram of an exemplary IC package including an exemplary IC die, the exemplary IC die including a SoC in an IC in which an Figure 3 As shown and in accordance with any of the aspects disclosed herein, the LPI subsystem circuit is configured to access the shared memory circuit by the subsystem memory interface of the memory subsystem in a first power mode and to access the shared memory circuit by the LPI memory interface in a low power mode. DETAILED DESCRIPTION

[0020] Referring now to the drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0021] Aspects disclosed herein include an integrated circuit (IC) that facilitates expansion of a low power island (LPI) memory using a subsystem shared cache memory. Related methods are also disclosed. The IC includes a plurality of main subsystems operating in a first power mode, and an LPI subsystem operating in the first power mode and a second power mode (e.g., a low power mode). The LPI subsystem and the main subsystems access a shared memory circuit in a memory subsystem through a subsystem memory interface in the first power mode. The main subsystems and the LPI subsystem can send a subsystem memory access request to the memory subsystem on the subsystem memory interface to access instructions and data that can be stored in an external memory and can be cached in the shared memory circuit. The subsystem memory interface includes a tag random access memory (RAM) to identify a cache line in the shared memory circuit that is dynamically assigned to a memory address in a subsystem memory access request.

[0022] The LPI subsystem accesses instructions and data in a first LPI memory image in the first power mode. The first LPI memory image is a memory area that includes instructions and data for all processes executed by the LPI subsystem in the first power mode. The LPI subsystem accesses a second LPI memory image in the second power mode. The second LPI memory image is a subset of the first LPI memory image because the LPI subsystem executes fewer processes in the second power mode. Therefore, the second LPI memory image requires less memory in the second power mode. In various exemplary aspects, memory addresses in the second LPI memory image are directly mapped to cache lines in the shared memory circuit, which can store the entire second LPI memory image in the second power mode. Directly mapping these addresses eliminates the need for the tag RAM and associated hardware to operate in the second power mode. The LPI subsystem can access these cache lines in the shared memory circuit in the second power mode by sending LPI memory access requests to the LPI memory interface. Since the second LPI memory image is a subset of the first LPI memory image, the second LPI memory image is also accessible to the LPI subsystem in the first power mode. In the first power mode, the subsystem memory interface also maps memory addresses in the second LPI memory image directly to associated cache lines in the shared memory circuit. In this regard, the addresses of instructions and data in the second LPI memory image need to remain constant in the first power mode and the second power mode. Therefore, the second LPI memory image is stored in a static memory address range in the external memory, which means that the instructions and data of the second LPI memory image are fixed and will not be relocated by the memory controller.

[0023] An IC that includes all or many components of a system is called a system on chip (SoC). SoCs are used in handheld and mobile electronic devices to reduce the number of devices required in a package, thereby reducing the package size. Although the size of the transistors within the IC can become smaller with each generation, the number of transistors in the IC tends to increase. In addition, the size of the software image including instructions and data for the SoC subsystems also continues to increase to provide improved functionality and performance. Therefore, the capacity of the cache used by the processor and processing circuits in the SoC continues to increase. As the cache size in the SoC increases, the power consumption rate in the SoC also increases. Power consumption affects battery life and generates heat. A technique for reducing power consumption is to implement a low power mode that can be triggered in the device when there is no activity in the main subsystems of the SoC for a threshold period of time. The low power mode reduces the power consumption in areas of the IC that are not required before the system wakes up from the low power mode.

[0024] Figure 1 1 is a block diagram of a conventional IC 100 including a memory subsystem 102 that receives subsystem memory access requests 104 to access data in an external memory 106 that may be coupled to the IC 100. The subsystem memory access requests 104 are received from a plurality of primary subsystems 108(A)-108(E) and from an LPI subsystem 110. In this context, subsystem memory access requests include read operations and write operations that result in the transfer of "data" between the memory subsystem 102 and one of the primary subsystems 108(A)-108(E) or the LPI subsystem 110 ("subsystems 108(A)-108(E) and 110"). In this context, "data" includes instructions, application data, user data, and any other information that may be stored in or for the primary subsystems 108(A)-108(E) and the LPI subsystem 110 of the IC 100. Memory subsystem 102 also includes memory circuit 112, which may include, for example, a plurality of memory banks (not shown). Memory circuit 112 is a last (i.e., highest) level cache in memory subsystem 102 for storing data on IC 100 to reduce data access (i.e., read or write) time for subsystems 108 (A)-108 (E) and 110.

[0025] Examples of the main subsystems 108(A)-108(E) may include a central processing unit (CPU), a graphics processing unit (GPU), multimedia, peripheral interfaces and devices, a modem, etc. The main subsystems 108(A)-108(E) may execute applications based on instructions stored in the external memory 106. The subsystem memory access request 104 from the main subsystems 108(A)-108(E) and the LPI subsystem 110 includes a memory address of data stored in the external memory 106. In the memory subsystem 102, the subsystem memory access request 104 is received in a subsystem memory interface 116 coupled to each of the main subsystems 108(A)-108(E) and to the LPI subsystem 110. The subsystem memory interface 116 accesses the memory circuit 112 in response to the subsystem memory access request 104. If the data being accessed by the subsystem memory access request 104 is not found in the memory circuit, the memory controller 114 accesses the data in the external memory 106. Subsystem memory interface 116 includes tag RAM 120 that dynamically allocates cache lines in memory circuit 112 to store versions of data from memory addresses in external memory 106. Tag RAM may be accessed in response to each subsystem memory access request 104 received in memory subsystem 102.

[0026] As described above, the LPI subsystem 110 is also coupled to the subsystem memory interface 116. The LPI subsystem 110 supports an "always on" feature that is intended to function even when the primary subsystems 108(A)-108(E) are inactive in a low power mode. For example, the always on functions supported by the LPI subsystem 110 include clocks, timers, sensors, and audio receivers. Under normal operating conditions where all of the primary subsystems 108(A)-108(E) and the memory subsystem 102 are coupled to the supply voltage source 122, the LPI subsystem 110 also accesses data in the external memory 106 by sending memory access requests to the subsystem memory interface 116. The LPI subsystem 110 includes a processor 124 and other hardware that provides the always on feature. The processor 124 can execute instructions 126 stored in a first LPI memory image in the external memory 106. The instructions 126 can also be copied to an LPI cache 128 external to the processor 124 for fast access. The processor 124 may include an internal level 1 (L1) cache (not shown), and the LPI cache 128 may be a level 2 (L2) cache (not shown). Instructions and other data of the first LPI memory image may be stored in a tightly coupled memory (TCM) 130 in the LPI subsystem 110, which is accessible by the processor 124 on the LPI interconnect bus 132 during the low power mode. Versions of data for the LPI subsystem 110 may also be stored in a memory circuit 112 in the memory subsystem 102 in the first power mode. It should be understood that in this context, a "version" of data such as user data or instructions may be an identical copy of the data stored in the external memory 106, or may be modified after being read from the external memory 106. The access time to the memory circuit 112 may be greater than the access time to the LPI cache 128 or TCM 130, but the memory circuit 112 may have a larger capacity than the LPI cache 128 and TCM 130, and have a shorter access time than the external memory 106.

[0027] In contrast to normal operating conditions, the IC 100 may be placed into a "low power mode" by a user or by the SoC power manager 134, e.g., after detecting that all of the major subsystems 108(A)-108(E) have been inactive for a period of time. In the low power mode, the supply voltage source 122 may be decoupled from the major subsystems 108(A)-108(E) and the memory subsystem 102, while the LPI subsystem 110 may remain coupled to the LPI voltage source 136. The LPI voltage source 136 may provide the same voltage as the supply voltage source 122 or a different voltage that reduces power consumption in the LPI subsystem 110. With the supply voltage source 122 decoupled from the subsystem memory interface 116, the LPI subsystem 110 is isolated from the rest of the IC 100 and from the external memory 106. Thus, in the low power mode, the processor 124 is limited to a second LPI memory image that is a subset of the first LPI memory image and includes only instructions and other data that may be used in the low power mode. As a result, LPI subsystem 110 has reduced functionality, which may be due to reduced memory capacity in the low power mode.

[0028] Figure 2 is corresponding to Figure 1 1 is an illustration of a cache memory 200 of a memory circuit 112 in which the cache memory has been partitioned into sub-caches 202(A)-202(C) for use in a normal operating mode. For example, each of the sub-caches 202(A)-202(C) may be dedicated to one or more of the primary subsystems 108(A)-108(E) and the LPI subsystem 110, and the sub-caches 202(A)-202(C) may be identified by a sub-cache identifier (SCID). The SCID may be included in a subsystem memory access request. The cache memory 200 may be an N-way set associative cache having N=eight (8) ways 204 and eight (8) sets 206, as shown. Figure 2 As shown in the example in . The sub-caches 202(A)-202(C) may be arranged in cache lines 208 according to ways 204 and / or sets 206. Alternatively, for example, each of the sub-caches 202(A)-202(C) may be limited to a maximum number of cache lines 208 based on priority, without a predetermined location, such as Figure 2 As shown. Figure 1 In the context of IC 100 in FIG. 1 , cache memory 200 may be accessed under the control of subsystem memory interface 116 . Figure 1Tag RAM 120 in can be used to allocate and track cache lines 208 in cache memory 200 for each of sub-caches 202(A)-202(C) based on the SCID. In some examples, the SCID can be part of the memory address provided in subsystem memory access request 104.

[0029] Figure 3 3 is a block diagram of an exemplary IC 300 including an LPI subsystem circuit 302 configured to access a shared memory circuit 304 on a subsystem memory interface 306 of a memory subsystem 308 in a first power mode and to access the shared memory circuit 304 on an LPI memory interface 310 of the memory subsystem 308 in a second power mode. The different ways in which the LPI subsystem circuit 302 accesses the shared memory circuit 304 are explained in the context of the following detailed description of the IC 300.

[0030] IC 300 includes a plurality of major subsystem circuits 312(A)-312(E), which are referred to herein as "major" because they support the functions and applications of IC 300 in a normal operating mode. For example, major subsystems 312(A)-312(E) may include a CPU 314 configured to execute one or more instruction threads for an application executed in an electronic device (not shown). For example, major subsystems 312(A)-312(E) may include a GPU 316 configured to perform graphics processing for video features of a user application. Other examples of major subsystems 312(A)-312(E) may include a peripheral subsystem 318, which includes interfaces and devices such as gaming, audio, video, and input / output features or a modem.

[0031] Each of the main subsystems 312(A)-312(E) can execute software instructions that process various forms of data, including application data, databases, and user data. As described above, for simplicity, instructions may also be referred to as data in this article. In this example, the data of the main subsystems 312(A)-312(E) can be stored in an external memory 320 coupled to the IC 300 through a memory controller 322. The main subsystems 312(A)-312(E) access the external memory 320 by sending a subsystem memory access request 324 to the subsystem memory interface 306. The subsystem memory interface 306 is configured to receive the subsystem memory access request 324 from the main subsystems 312(A)-312(E) in the first power mode. The instructions executed in the corresponding main subsystems 312(A)-312(E) can each access a memory range in the external memory 320. Thus, the subsystem memory access request 324 includes the memory addresses of instructions and other data to be read from and / or written to the external memory 320 . The memory controller 322 accesses the external memory 320 based on the memory addresses in the subsystem memory access request 324 .

[0032] A request by one of the primary subsystems 312(A)-312(E) to access external memory 320 may result in a long delay or latency between sending a subsystem memory access request 324 and receiving a response, which may result in idle processing cycles in the CPU 314 or GPU 316, for example, which may result in significant delays and poor performance in user applications. Because many instructions and data are frequently reused by the processing device, the primary subsystems 312(A)-312(E) may each include their own internal cache memory (not shown) in which versions of data read from external memory 320 may be kept locally for fast access. In some examples, the primary subsystems 312(A)-312(E) may include multiple levels of cache (e.g., L1, L2, L3, etc.). In addition, the memory subsystem 308 also includes a shared memory circuit 304, thereby providing another level of cache storage. The subsystem memory interface 306 may access the shared memory circuit 304 in response to the subsystem memory access request 324. The shared memory circuit 304 may be a last level cache (LLC) or a top level cache in the IC 300. The shared memory circuit 304 may be partitioned for use by multiple subsystems, such as Figure 2 As shown in the cache memory 200.

[0033] The LPI subsystem circuit 302 may provide functions such as receiving voice commands, sensing light levels, detecting motion, and responding to other forms of stimuli. These functions are expected to run in parallel with the main subsystems 312(A)-312(E). Therefore, the subsystem memory interface 306 is also configured to receive a subsystem memory access request 324 from the LPI subsystem circuit 302 in the first power mode.

[0034] The main subsystems 312(A)-312(E) are coupled to the first supply voltage source 326 in the first power mode. In mobile devices and other battery-powered devices, saving power can extend battery life. In this regard, periods of inactivity in the main subsystems 312(A)-312(E) can be detected by the IC power manager circuit 328 or in some other manner. Thus, after a period of inactivity, the IC 300 can enter a second power mode (e.g., a low power mode) in which the main subsystems 312(A)-312(E) can be decoupled from the first supply voltage source 326 to reduce power consumption. The IC 300 can also be placed in the second power mode by a user of an electronic device that includes the IC 300. However, it is contemplated that the LPI subsystem circuit 302 continues to function even when the main subsystems 312(A)-312(E) are inactive. In the first power mode, the LPI subsystem circuit 302 is coupled to the first supply voltage source 326. In the second power mode, the LPI subsystem circuit 302 may be decoupled from the first supply voltage source 326 and coupled to the second supply voltage source 330. In the second power mode, the main subsystems 312(A)-312(E) are not coupled to the second supply voltage source. The second power mode is also referred to as a low power mode because the rate of power consumption in the second power mode can be significantly reduced by decoupling inactive circuits from both the supply voltage sources 326 and 330. As further described below, a first group of circuits of the IC 300 are powered and function in response to the IC 300 operating in the first power mode, and a second group of circuits are powered and function in response to the IC 300 operating in the second power mode. For example, the following may refer to the phrases "in the first power mode" and "in the second power mode" to describe the difference in the operation of the LPI subsystem circuit 302.

[0035] The second supply voltage source 330 may provide a voltage that is the same as or different (e.g., lower) than the voltage provided by the first supply voltage source. The second supply voltage source 330 may be configured to be coupled to a different circuit than the first supply voltage source 326. In an alternative example, rather than decoupling the LPI subsystem circuit 302 from the first supply voltage source 326 and coupling to the second supply voltage source 330, the LPI subsystem 302 may continue to be coupled to the first supply voltage source 326 when the primary subsystems 312(A)-312(E) are decoupled from the first supply voltage source 326 in the second power mode.

[0036] Although decoupling the primary subsystems 312(A)-312(E) from the first supply voltage source 326 significantly reduces power consumption, additional steps may be taken to further save power in the second power mode, including shutting down access to the external memory 320. The external memory 320 may be, for example, a dynamic RAM (DRAM), which may be a double data rate (DDR) RAM. To save power, the DRAM may be placed in a self-refresh mode, in which low-power circuits are used to refresh the memory cells as needed to maintain the stored data. These circuits may be external to the IC 300. Since the primary subsystems 312(A)-312(E) are inactive and the external memory 320 is in the self-refresh mode, in the second power mode, the subsystem memory interface 306 in the memory subsystem 308 is decoupled from the first supply voltage source 326. In the second power mode, the subsystem memory interface 306 is not coupled to the second supply voltage source 330.

[0037] The LPI subsystem circuit 302 may include a processor 332 that executes a set of instructions that determine the functional level of the LPI subsystem circuit 302. In a first power mode, the LPI subsystem circuit 302 accesses a first LPI memory image that may have increased capabilities and performance due to access to a larger memory space available in the external memory 320. The first LPI memory image includes instructions and data for providing the capabilities of the LPI subsystem in the first power mode. The LPI subsystem circuit 302 includes an LPI cache circuit 334, which may be a level 2 (L2) cache for low latency temporary storage external to the processor 332. The LPI subsystem may also include a TCM 336 that can be accessed from the processor 332 via an LPI interconnect bus 338. The TCM 336 may provide local storage within the LPI subsystem circuit 302. In either power mode, first data of the LPI subsystem circuit 302 may be stored in the TCM 336, and a version of the first data may be stored in the LPI cache circuit 334.

[0038] In the first power mode, the LPI subsystem circuit 302 generates a subsystem memory access request 324 on a first LPI interface 340 coupled to the subsystem memory interface 306. In the second power mode, the LPI subsystem circuit 302 operates without accessing the external memory 320. Therefore, the processor 332 can access a second LPI memory image that includes a smaller set of instructions and data (i.e., a smaller image) than the first LPI memory image. The second LPI memory image includes instructions and data for providing the capabilities of the LPI subsystem in the second power mode. The second LPI memory image may be a subset of the first LPI memory image. Therefore, in the first power mode, the second LPI memory image may also be accessed via a subsystem memory access request 324 to the subsystem memory interface 306. In some examples, the size of the second LPI memory image may be limited by the memory capacity of the TCM 336. The size of the TCM 336 may be increased, but because the increase in the size of the TCM will provide increased functionality that is only used in the second power mode (low power mode), the increase in the size of the IC 300 for this purpose may be unacceptable.

[0039] In an exemplary aspect, the LPI subsystem circuit 302 accesses the shared memory circuit 304 in the second power mode to increase the memory capacity in which the larger second LPI memory image can be stored. Thus, the shared memory circuit 304 is coupled to the first supply voltage source 326 in the first power mode and is also coupled to the second supply voltage source 330 in the second power mode. In this regard, the functionality of the LPI subsystem circuit 302 can be increased without increasing the size of the TCM 336, which would increase the area of ​​the IC 300.

[0040] In another aspect, the subsystem memory interface 306 includes a tag RAM 344 ​​to access the shared memory circuit 304 in response to the subsystem memory access request 324. In one example, access to the shared memory circuit 304 may result in data being stored in a cache line 208 (e.g., Figure 2208). The tag RAM 344 ​​may determine an unused cache line 208 or a cache line 208 that may be evicted, and dynamically map the memory address of the data to be stored to the cache line 208. Alternatively, the tag RAM 344 ​​may determine that the cache line 208 has been previously dynamically mapped to the memory address and write the data to be stored into the cache line 208. In another example, access to the shared memory circuit 304 may include reading data from the cache line 208. In this example, the tag RAM 344 ​​may be accessed to dynamically map the memory address to be read to one of the cache lines 208 and read the contents of the cache line 208. In this context, the phrase "dynamic mapping" refers to determining which of several possible cache lines is the destination of the memory access instruction. For example, dynamic mapping may correspond to selecting among the ways in a set of caches corresponding to a given memory address. Dynamic mapping is different from direct mapping, at least because direct mapping refers to a one-to-one relationship between a memory address and a cache line in the shared memory circuit 304.

[0041] In contrast, the LPI memory interface 310 is configured to receive an LPI memory access request 346 from the LPI subsystem circuit 302 in the second power mode and access the shared memory circuit 304 in response to the LPI memory access request 346. Only one cache line 208 is directly mapped to the memory address. Therefore, no dynamic mapping is performed in the LPI memory interface 310. The LPI memory interface 310 provides access to the shared memory circuit 304 in the second power mode without the tag RAM 344, which reduces power consumption compared to the combinational circuit of the subsystem memory interface 306. The LPI memory interface 310 is coupled to the second supply voltage source 330 in the second power mode and is decoupled from the second supply voltage source 330 in the first power mode. The LPI memory interface 310 is not coupled to the first supply voltage source 326.

[0042] In another exemplary aspect, the second LPI memory image for the LPI subsystem circuit 302 is stored in a static (ie, fixed) and contiguous memory address range in the external memory 320 (see Figure 4 Memory addresses within the second LPI memory image are directly mapped to cache lines 208 in the shared memory circuit 304 (in Figure 2340 ). In the first power mode, memory addresses within the second LPI memory image may be directly addressed by the LPI subsystem circuit 302 in a subsystem memory access request 324 sent to the subsystem memory interface 306 via the first LPI interface 340. In the second power mode, memory addresses within the second LPI memory image may also be directly addressed by the LPI subsystem circuit 302 in an LPI memory access request 346 sent to the LPI memory interface 310. The subsystem memory interface 306 is configured to access the shared memory circuit 304 on the first memory interface 348 based on the memory address in the subsystem memory access request 324 in the first power mode. The memory address on the first memory interface 348 is a cache line address of a cache line 208 in the shared memory circuit 304, which is directly mapped to the memory address in the subsystem memory access request 324 to the second LPI memory image. Memory addresses outside the second LPI memory image are not directly mapped. In response to a memory address outside the second LPI memory image in subsystem memory access request 324 , tag RAM 344 ​​identifies a cache line of shared memory circuitry 304 that can be dynamically assigned to the memory address and provides a cache line address of the cache line on first memory interface 348 .

[0043] In contrast, the LPI memory interface 310 is configured to access the shared memory circuit 304 on the second memory interface 350 based on the direct memory address in the LPI memory access request 346. The LPI subsystem circuit 302 accesses the shared memory circuit 304 like a scratch pad. Prior to entering the low power mode, instructions and data of the second LPI memory image may be read from the external memory 320 and stored in the shared memory circuit 304. Since the LPI memory interface 310 may be used in the second power mode to access only memory addresses in the second LPI memory image, a cache line address directly mapped to the cache line 208 of the second LPI memory image is provided to the shared memory circuit 304 on the second memory interface 350. At this point, the tag RAM 344 ​​is not required, and the shared memory circuit 304 may be accessed with reduced power consumption. In the second power mode, access to the shared memory circuit 304 provides the LPI subsystem circuit 302 with more memory space than the storage capacity of the TCM 336 without increasing the size of the IC 300. In one example, the TCM 336 may be omitted because the entire second LPI memory image may be stored in the shared memory circuit 304 .

[0044] In the second power mode, the LPI subsystem circuit 302 generates an LPI memory access request 346 on a second LPI interface 352 coupled to the LPI memory interface 310. If a TCM 336 is present, the shared memory circuit 304 may be an extension of the memory space available in the TCM 336. In the second power mode, a version of the data stored in the shared memory circuit 304 may be stored in the LPI cache circuit 334 of the LPI subsystem circuit 302 for faster access by the processor 332.

[0045] Subsystem memory interface 306 and LPI memory interface 310 may not be directly coupled to shared memory circuit 304. Figure 3 , the memory subsystem 308 also includes a switch circuit 354 configured to couple the subsystem memory interface 306 to the first memory interface 348 in the first power mode and to couple the LPI memory interface 310 to the second memory interface 350 in the second power mode. The switch circuit 354 may be a multiplexer circuit that is coupled to the first supply voltage source 326 in the first power mode and to the second supply voltage source 330 in the second power mode. The IC power manager circuit 328 may couple and decouple the first supply voltage source 326 and the second supply voltage source 330 to and from respective circuits in the IC 300 in response to the first power mode and the second power mode.

[0046] Figure 4 yes Figure 3 4, which shows a static and continuous second LPI memory image 402 including instructions and other data for the LPI subsystem circuit 302 in the second power mode. The second LPI memory image 402 corresponds to Figure 3 The memory address range of the "scratch pad" memory provided by the LPI subsystem circuit 302 in the shared memory circuit 304 in the second LPI memory image 402 is directly mapped to the cache line 208 in the shared memory circuit 304 (see Figure 2). In other aspects, the cache lines 208 mapped to the second LPI memory image may function as normal cache lines for storing versions (e.g., exact copies or updated versions) of data stored in the external memory 320. For example, there may be a dirty / modified indicator associated with each cache line 208 that may indicate whether the contents of the cache line should be written to the external memory 320. Instructions and data for the first LPI memory image outside of the second LPI memory image 402 may be located in any available portion 404 in the memory map 400. Similarly, instructions and data for the primary subsystems 312(A)-312(E) may be located in available portions 404 of the memory map 400 outside of the second LPI memory image.

[0047] Figure 5 is with Figure 3 FIG. 5 is a diagram of a memory circuit 500 corresponding to the shared memory circuit 304 in FIG. Figure 5 3 shows a method of direct address mapping used in LPI memory access request 346 for accessing cache line 502 in memory circuit 500, as shown in FIG. Figure 3 Each cache line 502 may correspond to an addressable memory space. For example, the memory circuit 500 may be organized into rows 504 and columns 506. For example, the rows 504 and columns 506 may correspond to sets and ways, respectively. A first address portion 508 of a direct memory address 510 may be decoded to identify the column 506, and a second address portion 512 of the direct memory address 510 may be decoded to identify the row 504. In this manner, the cache lines 502 may be decoded in relation to the address space. Figure 3 The direct memory address 510 received in the LPI memory access request 346 or the subsystem memory access request 324 identifies the corresponding cache line 502. Therefore, in low power mode, cache control circuitry including tag RAM is not required to access the memory circuit 500, which improves power savings.

[0048] Figure 6 yes Figure 36 is a flow chart of a method in an IC 300 in FIG. 6. The method 600 includes, in response to the IC 300 operating in a first power mode (block 602), receiving, in a subsystem memory interface 306 in a memory subsystem 308, a first subsystem memory access request 324 from an LPI subsystem circuit 302 (block 604). The method also includes, in response to the IC 300 operating in a first power mode (block 604), accessing, by the subsystem memory interface 306, a shared memory circuit 304 in response to the first subsystem memory access request 324 (block 606). The method also includes, in response to the IC 300 operating in a second power mode (block 608), receiving, in an LPI memory interface 310, an LPI memory access request 346 from an LPI subsystem circuit 302 (block 610). The method includes accessing, by the LPI memory interface 310, a shared memory circuit 304 in response to the LPI memory access request 346 (block 612).

[0049] Figure 7 An exemplary wireless communication device 700 is shown including radio frequency (RF) components formed of one or more ICs 702, wherein any of the ICs 702 may include a SoC in the IC in which, for example, Figure 3 As shown in and according to any of the aspects disclosed herein, the LPI subsystem circuit is configured to access the shared memory circuit by the subsystem memory interface of the memory subsystem in the first power mode and access the shared memory circuit by the LPI memory interface in the low power mode. As an example, the wireless communication device 700 may include or be provided in any of the above-mentioned devices. Figure 7 As shown, the wireless communication device 700 includes a transceiver 704 and a data processor 706. The data processor 706 may include a memory to store data and program codes. The transceiver 704 includes a transmitter 708 and a receiver 710 that support two-way communication. In general, the wireless communication device 700 may include any number of transmitters 708 and / or receivers 710 for any number of communication systems and frequency bands. All or part of the transceiver 704 may be implemented on one or more analog ICs, RFICs, mixed signal ICs, etc.

[0050] The transmitter 708 or the receiver 710 may be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is converted between RF and baseband in multiple stages, such as from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in one stage. Superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements. Figure 7 In the wireless communication device 700 in FIG. 1 , the transmitter 708 and the receiver 710 are implemented using a direct conversion architecture.

[0051] In the transmit path, the data processor 706 processes data to be transmitted and provides I and Q analog output signals to the transmitter 708. In the exemplary wireless communication device 700, the data processor 706 includes digital-to-analog converters (DACs) 712(1), 712(2) to convert digital signals generated by the data processor 706 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0052] Within the transmitter 708, low pass filters 714(1), 714(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 716(1), 716(2) amplify the signals from the low pass filters 714(1), 714(2), respectively, and provide I and Q baseband signals. An up converter 718 upconverts the I and Q baseband signals with I and Q TX LO signals from a transmit (TX) local oscillator (LO) signal generator 722 via mixers 720(1), 720(2) to provide upconverted signals 724. A filter 726 filters the upconverted signals 724 to remove undesired signals caused by the upconversion and noise in the receive band. A power amplifier (PA) 728 amplifies the upconverted signals 724 from the filter 726 to obtain a desired output power level and provide a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 730 and transmitted via an antenna 732 .

[0053] In the receive path, antenna 732 receives signals transmitted by a base station and provides a received RF signal that is routed through a duplexer or switch 730 and provided to a low noise amplifier (LNA) 734. The duplexer or switch 730 is designed to operate with a specific receive (RX) and TX duplexer frequency separation so that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 734 and filtered by filter 736 to obtain the desired RF input signal. Down-conversion mixers 738 (1), 738 (2) mix the output of filter 736 with I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 740 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 742 (1), 742 (2) and further filtered by low pass filters 744 (1), 744 (2) to obtain I and Q analog input signals provided to data processor 706. In this example, the data processor 706 includes analog-to-digital converters (ADCs) 746 ( 1 ), 746 ( 2 ) for converting analog input signals into digital signals to be further processed by the data processor 706 .

[0054] exist Figure 7In the wireless communication device 700 of FIG. 7 , the TX LO signal generator 722 generates I and Q TX LO signals for up-conversion, and the RX LO signal generator 740 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 748 receives timing information from the data processor 706 and generates a control signal for adjusting the frequency and / or phase of the TX LO signal from the TX LO signal generator 722. Similarly, the RX PLL circuit 750 receives timing information from the data processor 706 and generates a control signal for adjusting the frequency and / or phase of the RX LO signal from the RX LO signal generator 740.

[0055] Each includes an IC (wherein, Figure 3 The wireless communication device 700 of a system on chip (SoC) in which the LPI subsystem circuit is configured to access the shared memory circuit by the subsystem memory interface of the memory subsystem in a first power mode and access the shared memory circuit by the LPI memory interface in a low power mode) as shown and according to any of the aspects disclosed herein may be provided in or integrated into any processor-based device. Non-limiting examples include: set-top box, entertainment unit, navigation device, communication device, fixed location data unit, mobile location data unit, global positioning system (GPS) device, mobile phone, cellular phone, smart phone, Session Initiation Protocol (SIP) phone, tablet device, tablet phone, server, computer, portable computer, mobile computing device, wearable computing device (e.g., smart watch, health or fitness tracker, glasses, etc.), desktop computer, personal digital assistant (PDA), monitor, computer monitor, television, tuner, radio, satellite radio, music player, digital music player, portable music player, digital video player, video player, digital video disc (DVD) player, portable digital video player, automobile, vehicle component, avionics system, drone, and multirotor aircraft.

[0056] At this point, Figure 8 An example of a processor-based system 800 is shown that includes an IC that includes a SoC in an IC in which, for example, Figure 3As shown and in accordance with any aspect disclosed herein, the LPI subsystem circuit is configured to access the shared memory circuit by the subsystem memory interface of the memory subsystem in a first power mode and to access the shared memory circuit by the LPI memory interface in a low power mode. In this example, the processor-based system 800 includes one or more CPUs 802, which may also be referred to as CPUs or processor cores, each of which includes one or more processors 804. The CPU 802 may have a cache memory 806 coupled to the processor 804 for quickly accessing temporarily stored data. As an example, the processor 804 may include a system on chip (SoC) in an IC in which, for example, Figure 3 As shown and in accordance with any aspect disclosed herein, the LPI subsystem circuit is configured to access the shared memory circuit by the subsystem memory interface of the memory subsystem in a first power mode and to access the shared memory circuit by the LPI memory interface in a low power mode. The CPU 802 is coupled to the system bus 808 and may interactively couple the master devices and slave devices included in the processor-based system 800. As is well known, the CPU 802 communicates with these other devices by exchanging address, control, and data information on the system bus 808. For example, the CPU 802 may communicate a bus transaction request to a memory controller 810, which is an example of a slave device. Although in Figure 8 Although not shown, multiple system buses 808 may be provided, each of which may form a different structure.

[0057] Other master devices and slave devices may be connected to the system bus 808. Figure 8 As shown, as an example, these devices may include a memory system 812 including a memory controller 810 and one or more memory arrays 814, one or more input devices 816, one or more output devices 818, one or more network interface devices 820, and one or more display controllers 822. Each of the memory system 812, the one or more input devices 816, the one or more output devices 818, the one or more network interface devices 820, and the one or more display controllers 822 may include a system on a chip (SoC) in an IC in which, for example, Figure 3As shown and in accordance with any of the aspects disclosed herein, the LPI subsystem circuit is configured to access the shared memory circuit by the subsystem memory interface of the memory subsystem in the first power mode, and to access the shared memory circuit by the LPI memory interface in the low power mode. The input device 816 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device 818 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The network interface device 820 may be any device configured to allow data exchange to and from the network 824. The network 824 may be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH TM Networks and the Internet. The network interface device 820 may be configured to support any type of communication protocol desired.

[0058] The CPU 802 may also be configured to access a display controller 822 via the system bus 808 to control information sent to one or more displays 826. The display controller 822 sends information to be displayed to the display 826 via one or more video processors 828, which processes the information to be displayed into a format suitable for the display 826. The display 826 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc. The display controller 822, the display 826, and / or the video processor 828 may include a system on a chip (SoC) in an IC, in which, for example, Figure 3 As shown and in accordance with any of the aspects disclosed herein, the LPI subsystem circuit is configured to access the shared memory circuit by the subsystem memory interface of the memory subsystem in a first power mode and to access the shared memory circuit by the LPI memory interface in a low power mode.

[0059] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits and algorithms described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or a combination of the two. As an example, the master device and slave device described herein can be used in any circuit, hardware component, IC or IC chip. The memory disclosed herein can be a memory of any type and size, and can be configured to store any type of information desired. In order to clearly illustrate this interchangeability, the functions of various exemplary components, blocks, modules, circuits and steps are generally described above. How such functionality is implemented depends on specific applications, design choices, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functions in different ways for each specific application, but such implementation decisions should not be interpreted as causing deviations from the scope of the present disclosure.

[0060] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or executed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in cooperation with a DSP core, or any other such configuration).

[0061] The various aspects disclosed herein may be implemented in hardware and instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from and write information to the storage medium. In an alternative, the storage medium may be integrated with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0062] It is also noted that the operational steps described in any exemplary aspect of this article are described in order to provide examples and discussions. The described operations can be performed in many different orders except for the order shown. In addition, the operations described in a single operational step can actually be performed in multiple different steps. In addition, one or more operational steps discussed in the exemplary aspects can be combined. It will be understood that, as will be apparent to those skilled in the art, many different modifications can be made to the operational steps shown in the flow chart. It will be equally understood by those skilled in the art that a variety of different technologies and techniques can be used to represent information and signals. For example, the data, instructions, commands, information, signals, bits, symbols and chips mentioned throughout the description above can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles or any combination thereof.

[0063] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the universal principles defined herein may be applied to other variations. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but to be consistent with the widest scope consistent with the principles and novel features disclosed herein.

[0064] Implementation examples are described in the following numbered clauses:

[0065] 1. An integrated circuit (IC) configured to operate in one of a first power mode and a second power mode, the IC comprising:

[0066] Low power island (LPI) subsystem circuitry; and

[0067] A memory subsystem, the memory subsystem comprising:

[0068] shared memory circuit;

[0069] a subsystem memory interface configured to: in response to the IC operating in the first power mode;

[0070] receiving a first subsystem memory access request from the LPI subsystem circuit; and

[0071] accessing the shared memory circuit in response to the first subsystem memory access request; and

[0072] an LPI memory interface configured to: in response to the IC operating in the second power mode;

[0073] receiving an LPI memory access request from the LPI subsystem circuit;

[0074] as well as

[0075] The shared memory circuit is accessed in response to the LPI memory access request.

[0076] 2. The IC of clause 1, further comprising a plurality of major subsystem circuits, wherein:

[0077] The subsystem memory interface is further configured to respond to the IC in the

[0078] Operation in the first power mode:

[0079] receiving a second subsystem memory access request from one of the plurality of primary subsystem circuits; and

[0080] The shared memory circuit is accessed in response to the second subsystem memory access request.

[0081] 3. An IC according to clause 1 or clause 2, wherein:

[0082] The LPI subsystem circuit is configured to couple to a first supply voltage source in response to the IC operating in the first power mode, and to couple to a first supply voltage source in response to the IC operating in the first power mode.

[0083] operating in a second power mode and coupled to a second supply voltage source;

[0084] The shared memory circuit is configured as follows:

[0085] coupled to the first supply voltage source in response to the IC operating in the first power mode; and

[0086] coupled to the second supply voltage source in response to the IC operating in the second power mode; and

[0087] The subsystem memory interface and the plurality of major subsystems are each further

[0088] The configuration is:

[0089] coupled to the first supply voltage source in response to the IC operating in the first power mode; and

[0090] decoupling from the first supply voltage source in response to the IC operating in the second power mode; and

[0091] The LPI memory interface is further configured as:

[0092] coupled to the second supply voltage source in response to the IC operating in the second power mode; and

[0093] The IC is decoupled from the second supply voltage source in response to the IC operating in the first power mode.

[0094] 4. An IC according to clause 2 or clause 3, wherein:

[0095] The IC is further configured to be coupled to an external memory;

[0096] In response to the IC operating in the first power mode, the subsystem stores

[0097] The device interface is further configured as:

[0098] directly mapping a memory address in the first subsystem memory access request to a first cache line address in the shared memory circuit;

[0099] dynamically mapping a memory address in the second subsystem memory access request to a second cache line address in the shared memory circuit; and

[0100] accessing the shared memory circuit over a first memory interface; and

[0101] In response to the IC operating in the second power mode, the LPI memory

[0102] The interface is further configured as:

[0103] mapping a memory address in the LPI memory access request directly to a third cache line in the shared memory circuit; and

[0104] The shared memory circuit is accessed over a second memory interface.

[0105] 5. The IC of clause 4, wherein the subsystem memory interface comprises a tagged random access memory (RAM), the subsystem memory interface being further configured to: in response to the IC operating in the first power mode:

[0106] accessing the tag RAM to dynamically map the memory address in the second subsystem memory access request to the second cache line address; and providing one of the first cache line address and the second cache line address on the first memory interface.

[0107] 6. The IC of clause 4 or clause 5, wherein in response to the IC operating in the second power mode, the LPI memory interface is further configured to provide a third cache line address on the second memory interface.

[0108] 7. An IC as described in any of clauses 4 to 6, the memory subsystem further comprising a switch configured to:

[0109] In response to the IC operating in the first power mode:

[0110] coupled to the first supply voltage source; and

[0111] coupling the subsystem memory interface to the first memory interface of the shared memory circuit; and

[0112] In response to the IC operating in the second power mode:

[0113] coupled to the second supply voltage source; and

[0114] The LPI memory interface is coupled to the second memory interface of the shared memory circuit.

[0115] 8. An IC as described in any of clauses 4 to 7, wherein the LPI subsystem circuit includes an LPI processor, the LPI processor being configured to:

[0116] generating the first subsystem memory access request to access data stored in the external memory in response to the IC operating in the first power mode; and

[0117] In response to the IC operating in the second power mode, the LPI memory access request is generated to access data stored in the shared memory circuit.

[0118] 9. An IC as described in any of clause 4 or clause 8, wherein the LPI subsystem circuit is further configured to:

[0119] generating the first subsystem memory access request on a first LPI interface coupled to the subsystem memory interface in response to the IC operating in the first power mode; and

[0120] In response to the IC operating in the second power mode, the LPI memory access request is generated on a second LPI interface coupled to the LPI memory interface.

[0121] 10. The IC of any of clause 4 or clause 9, wherein the LPI subsystem circuit further comprises:

[0122] a tightly coupled memory (TCM), the TCM configured to store first data; and

[0123] LPI cache circuit, wherein:

[0124] The shared memory circuit is configured to store second data; and

[0125] In response to the IC operating in the second power mode, the LPI cache circuit is configured to store at least one of a version of the first data and a version of the second data.

[0126] 11. An IC according to any one of clauses 2 to 10, wherein:

[0127] The plurality of subsystem circuits include at least one of a central processing unit (CPU), a graphics processing unit (GPU), a peripheral interface, and a modem;

[0128] At least one of the plurality of subsystem circuits includes an internal cache memory,

[0129] The internal cache memory is configured to store a first version of the subsystem data stored in the external memory; and

[0130] In response to the IC operating in the first power mode, the shared memory circuit is configured to store a second version of the subsystem data stored in the external memory.

[0131] 12. A method of operating an integrated circuit (IC) in one of a first power mode and a second power mode, the method comprising:

[0132] In response to the IC operating in the first power mode:

[0133] receiving, in a subsystem memory interface in a memory subsystem, a first subsystem memory access request from a low power island (LPI) subsystem circuit; and accessing, by the subsystem memory interface, a shared memory circuit in response to the first subsystem memory access request; and

[0134] In response to the IC operating in the second power mode:

[0135] receiving, in an LPI memory interface in the memory subsystem, an LPI memory access request from the LPI memory interface; and

[0136] The shared memory circuit is accessed by the LPI memory interface in response to the LPI memory access request.

[0137] 13. The method according to clause 12, further comprising:

[0138] receiving in the subsystem memory interface in the memory subsystem a second subsystem memory access request from one of a plurality of primary subsystem circuits; and

[0139] The shared memory circuit is accessed by the subsystem memory interface in response to the second subsystem memory access request.

[0140] 14. The method according to clause 13, further comprising:

[0141] In response to the IC operating in the first power mode:

[0142] coupling the LPI subsystem circuit, the shared memory circuit, the subsystem memory interface, and the plurality of primary subsystem circuits to a first supply voltage source; and

[0143] decoupling the LPI memory interface from a second supply voltage source; and

[0144] In response to the IC operating in the second power mode:

[0145] coupling the LPI subsystem circuit, the shared memory circuit, and the LPI memory interface to the second supply voltage source; and

[0146] The subsystem memory interface and the plurality of major subsystem circuits are decoupled from the first supply voltage source.

[0147] 15. The method according to clause 13 or clause 14, further comprising:

[0148] dynamically mapping a memory address in the second subsystem memory access request to a first cache line address in the shared memory circuit;

[0149] accessing, by the subsystem memory interface on a first memory interface, the first cache line in the shared memory circuit;

[0150] directly mapping a memory address in the first subsystem memory request to a second cache line address in the shared memory circuit; and

[0151] The second cache line address on a second memory interface is accessed by the LPI memory interface.

[0152] 16. The method of clause 15, further comprising: in response to the IC operating in the first power mode:

[0153] receiving, in the subsystem memory interface in the memory subsystem, a third subsystem memory access request from the LPI subsystem circuit; and

[0154] A cache line in the shared memory circuit is accessed on the first memory interface by the subsystem memory interface, the cache line comprising a cache line address that directly maps to the memory address in the third subsystem memory access request.

[0155] 17. The method according to clause 16, wherein the dynamic mapping further comprises:

[0156] determining a cache line address of the first cache line corresponding to the memory address in the shared memory circuit by accessing a tag random access memory (RAM); and

[0157] The cache line address of the first cache line is provided on the first memory interface.

[0158] 18. The method of clauses 15 to 17, further comprising providing, by the LPI memory interface, a cache line address of the second cache line to the second memory interface in response to the IC operating in the second power mode.

[0159] 19. The method according to any one of clauses 15 to 18, further comprising:

[0160] responsive to the IC operating in the first power mode, coupling the first memory interface to the shared memory circuit via a switch; and

[0161] In response to the IC operating in the second power mode, coupling the second memory interface to the shared memory circuit through the switch.

[0162] 20. The method according to any one of clauses 12 to 19, further comprising:

[0163] generating, by an LPI processor in the LPI subsystem circuit, the first subsystem memory access request in response to the IC operating in the first power mode; and

[0164] The LPI memory access request is generated by the LPI processor in the LPI subsystem circuit in response to the IC operating in the second power mode.

[0165] 21. The method according to any one of clauses 12 to 20, further comprising:

[0166] generating the first subsystem memory access request on a first LPI memory interface coupled to the subsystem memory interface in response to the IC operating in the first power mode; and

[0167] In response to the IC operating in the second power mode, the LPI memory access request is generated on a second LPI memory interface coupled to the LPI memory interface.

[0168] 22. The method of any one of clauses 12 to 21, further comprising: in response to the IC operating in the second power mode:

[0169] storing first LPI data of the LPI subsystem circuit in a tightly coupled memory (TCM);

[0170] storing second LPI data in the shared memory circuit; and

[0171] At least one of a version of the first LPI data and a version of the second LPI data is stored in an LPI cache circuit.

[0172] 23. A method according to any one of clauses 13 to 22, wherein:

[0173] storing a first version of the subsystem data stored in the external memory in a cache memory of one of the plurality of primary subsystem circuits; and

[0174] In response to the IC operating in the first power mode, a second version of the subsystem data is stored in the shared memory circuit.

Claims

1. An integrated circuit (IC) configured to operate in two power modes, the IC comprising: Low power island (LPI) subsystem circuit; and A memory subsystem, the memory subsystem comprising: shared memory circuit; a subsystem memory interface configured to: in response to the IC operating in a first power mode; receiving a first subsystem memory access request from the LPI subsystem circuit; and accessing the shared memory circuit in response to the first subsystem memory access request; and an LPI memory interface configured to: in response to the IC operating in a second power mode; receiving an LPI memory access request from the LPI subsystem circuit; and accessing the shared memory circuit in response to the LPI memory access request, The IC also includes several major subsystem circuits, including: The subsystem memory interface is further configured to: in response to the IC operating in the first power mode: receiving a second subsystem memory access request from one of the plurality of primary subsystem circuits; and accessing the shared memory circuit in response to the second subsystem memory access request, in: The IC is further configured to be coupled to an external memory; In response to the IC operating in the first power mode, the subsystem memory interface is further configured to: directly mapping a memory address in the first subsystem memory access request to a first cache line address in the shared memory circuit; dynamically mapping a memory address in the second subsystem memory access request to a second cache line address in the shared memory circuit; and accessing the shared memory circuit over a first memory interface; and In response to the IC operating in the second power mode, the LPI memory interface is further configured to: mapping a memory address in the LPI memory access request directly to a third cache line in the shared memory circuit; and The shared memory circuit is accessed over a second memory interface.

2. The IC of claim 1, wherein: the LPI subsystem circuit being configured to couple to a first supply voltage source in response to the IC operating in the first power mode, and to couple to a second supply voltage source in response to the IC operating in the second power mode; The shared memory circuit is configured as follows: coupling to the first supply voltage source in response to the IC operating in the first power mode; as well as coupled to the second supply voltage source in response to the IC operating in the second power mode; and The subsystem memory interface and the plurality of major subsystems are each further configured to: coupled to the first supply voltage source in response to the IC operating in the first power mode; and decoupling from the first supply voltage source in response to the IC operating in the second power mode; and The LPI memory interface is further configured as: coupled to the second supply voltage source in response to the IC operating in the second power mode; and The IC is decoupled from the second supply voltage source in response to the IC operating in the first power mode.

3. The IC of claim 1 , wherein the subsystem memory interface comprises a tagged random access memory (RAM), the subsystem memory interface being further configured to: in response to the IC operating in the first power mode: accessing the tag RAM to dynamically map the memory address in the second subsystem memory access request to the second cache line address; and One of the first cache line address and the second cache line address is provided on the first memory interface.

4. The IC of claim 3, wherein in response to the IC operating in the second power mode, the LPI memory interface is further configured to provide a third cache line address on the second memory interface.

5. The IC of claim 4, the memory subsystem further comprising a switch, the switch being configured to: In response to the IC operating in the first power mode: coupled to a first supply voltage source; and coupling the subsystem memory interface to the first memory interface of the shared memory circuit; as well as In response to the IC operating in the second power mode: coupled to a second supply voltage source; as well as The LPI memory interface is coupled to the second memory interface of the shared memory circuit.

6. The IC of claim 1 , wherein the LPI subsystem circuit comprises an LPI processor, the LPI processor being configured to: generating the first subsystem memory access request to access data stored in the external memory in response to the IC operating in the first power mode; and In response to the IC operating in the second power mode, the LPI memory access request is generated to access data stored in the shared memory circuit.

7. The IC of claim 6, wherein the LPI subsystem circuit is further configured to: generating the first subsystem memory access request on a first LPI interface coupled to the subsystem memory interface in response to the IC operating in the first power mode; and In response to the IC operating in the second power mode, the LPI memory access request is generated on a second LPI interface coupled to the LPI memory interface.

8. The IC of claim 7, wherein the LPI subsystem circuit further comprises: a tightly coupled memory (TCM), the TCM being configured to store first data; and LPI cache circuit, wherein: The shared memory circuit is configured to store second data; and In response to the IC operating in the second power mode, the LPI cache circuit is configured to store at least one of a version of the first data and a version of the second data.

9. The IC of claim 1, wherein: The plurality of subsystem circuits include at least one of a central processing unit (CPU), a graphics processing unit (GPU), a peripheral interface, and a modem; At least one of the plurality of subsystem circuits includes an internal cache memory configured to store a first version of subsystem data stored in the external memory; and In response to the IC operating in the first power mode, the shared memory circuit is configured to store a second version of the subsystem data stored in the external memory.

10. A method of operating an integrated circuit (IC) in two power modes, the method comprising: In response to the IC operating in the first power mode: receiving, in a subsystem memory interface in the memory subsystem, a first subsystem memory access request from a low power island (LPI) subsystem circuit; as well as accessing, by the subsystem memory interface, a shared memory circuit in response to the first subsystem memory access request; as well as In response to the IC operating in the second power mode: receiving, in an LPI memory interface in the memory subsystem, an LPI memory access request from the LPI memory interface; as well as accessing the shared memory circuit by the LPI memory interface in response to the LPI memory access request, The method further comprises: receiving in the subsystem memory interface in the memory subsystem a second subsystem memory access request from one of a plurality of primary subsystem circuits; and accessing the shared memory circuit by the subsystem memory interface in response to the second subsystem memory access request, The method further comprises: dynamically mapping a memory address in the second subsystem memory access request to a first cache line address in the shared memory circuit; accessing, by the subsystem memory interface on a first memory interface, the first cache line in the shared memory circuit; directly mapping a memory address in the first subsystem memory request to a second cache line address in the shared memory circuit; and The second cache line address on a second memory interface is accessed by the LPI memory interface.

11. The method according to claim 10, further comprising: In response to the IC operating in the first power mode: coupling the LPI subsystem circuit, the shared memory circuit, the subsystem memory interface, and the plurality of main subsystem circuits to a first supply voltage source; as well as decoupling the LPI memory interface from a second supply voltage source; as well as In response to the IC operating in the second power mode: coupling the LPI subsystem circuit, the shared memory circuit, and the LPI memory interface to the second supply voltage source; as well as The subsystem memory interface and the plurality of major subsystem circuits are decoupled from the first supply voltage source.

12. The method according to claim 10, further comprising: In response to the IC operating in the first power mode: receiving, in the subsystem memory interface in the memory subsystem, a third subsystem memory access request from the LPI subsystem circuit; as well as A cache line in the shared memory circuit is accessed on the first memory interface by the subsystem memory interface, the cache line comprising a cache line address that directly maps to the memory address in the third subsystem memory access request.

13. The method of claim 12, dynamically mapping the memory address in the second subsystem memory access request to the first cache line address in the shared memory circuit further comprising: determining a cache line address of the first cache line corresponding to the memory address in the shared memory circuit by accessing a tag random access memory (RAM); as well as The cache line address of the first cache line is provided on the first memory interface.

14. The method according to claim 13, further comprising: In response to the IC operating in the second power mode, a cache line address of the second cache line is provided by the LPI memory interface to the second memory interface.

15. The method according to claim 14, further comprising: responsive to the IC operating in the first power mode, coupling the first memory interface to the shared memory circuit via a switch; as well as In response to the IC operating in the second power mode, coupling the second memory interface to the shared memory circuit through the switch.

16. The method according to claim 10, further comprising: generating, by an LPI processor in the LPI subsystem circuit, the first subsystem memory access request in response to the IC operating in the first power mode; as well as The LPI memory access request is generated by the LPI processor in the LPI subsystem circuit in response to the IC operating in the second power mode.

17. The method according to claim 16, further comprising: generating the first subsystem memory access request on a first LPI memory interface coupled to the subsystem memory interface in response to the IC operating in the first power mode; as well as In response to the IC operating in the second power mode, the LPI memory access request is generated on a second LPI memory interface coupled to the LPI memory interface.

18. The method according to claim 17, further comprising: In response to the IC operating in the second power mode: storing first LPI data of the LPI subsystem circuit in a tightly coupled memory (TCM); storing second LPI data in the shared memory circuit; as well as At least one of a version of the first LPI data and a version of the second LPI data is stored in an LPI cache circuit.

19. The method of claim 18, wherein: storing a first version of subsystem data stored in external memory in a cache memory of one of the plurality of primary subsystem circuits; as well as In response to the IC operating in the first power mode, a second version of the subsystem data is stored in the shared memory circuit.

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