Power supply circuit and chip

Abstract

The present disclosure provides a power supply circuit and a chip using the same. The power supply circuit comprises a reference voltage generating circuit configured to generate a positive temperature coefficient substrate reference voltage; a voltage generating circuit configured to raise a substrate voltage according to an enable signal; and an enable signal generating circuit connected to the reference voltage generating circuit and the voltage generating circuit, configured to output the enable signal to the voltage generating circuit when the substrate reference voltage is greater than a product of the substrate voltage and a preset coefficient. The embodiment of the present disclosure can raise the substrate voltage of a transistor when the temperature rises, thereby reducing the power consumption of the chip.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more specifically, to a power supply circuit and a chip using the power supply circuit. Background Technology

[0002] With technological advancements, the demand for low-power integrated circuits is increasing. Related technologies typically optimize power consumption during signal transmission and processing. However, during standby or sleep modes, there is almost no signal transmission or processing, thus further reductions in power consumption are possible.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a power supply circuit and a chip using the power supply circuit, for at least a certain extent further reducing the power consumption of integrated circuits.

[0005] According to a first aspect of this disclosure, a power supply circuit is provided, comprising:

[0006] A reference voltage generation circuit is used to generate a substrate reference voltage with a positive temperature coefficient.

[0007] A voltage generation circuit is used to increase the substrate voltage according to an enable signal;

[0008] An enable signal generation circuit, connected to the reference voltage generation circuit and the voltage generation circuit, is used to output the enable signal to the voltage generation circuit when the substrate reference voltage is greater than the product of the substrate voltage and a preset coefficient.

[0009] In one exemplary embodiment of this disclosure, the voltage generation circuit includes:

[0010] An oscillation module has an input terminal for receiving the enable signal and an output terminal for outputting an oscillation signal. The oscillation module is used to generate the oscillation signal according to the enable signal.

[0011] The charge pump module has its input terminal connected to the oscillation module and its output terminal used to output the substrate voltage. The charge pump module is used to raise the substrate voltage according to the oscillation signal.

[0012] In one exemplary embodiment of this disclosure, the charge pump module includes:

[0013] A first capacitor, the first end of which is coupled to the output terminal of the oscillation module;

[0014] The positive terminal of the first diode is connected to the power supply voltage, and the negative terminal is connected to the second terminal of the first capacitor.

[0015] The second diode has its positive terminal connected to the second terminal of the first capacitor, and its negative terminal used to output the substrate voltage.

[0016] In one exemplary embodiment of this disclosure, the charge pump module further includes a driving circuit connected between the output terminal of the oscillation module and the first terminal of the first capacitor, the driving circuit being used to increase the amplitude of the oscillation signal.

[0017] In one exemplary embodiment of this disclosure, the charge pump module further includes a second capacitor, a first terminal of which is connected to the negative terminal of the second diode, and a second terminal of which is grounded. The second capacitor is used to maintain the output voltage of the charge pump module.

[0018] In one exemplary embodiment of this disclosure, the enable signal generation circuit includes:

[0019] A comparator, wherein the inverting input of the comparator is used to receive the substrate reference voltage;

[0020] An inverter, the input of which is connected to the output of the comparator, and the output of which is connected to the voltage generation circuit, for outputting the enable signal;

[0021] The first voltage divider resistor unit has a first end connected to the output end of the charge pump module for receiving the substrate voltage, and a second end connected to the non-inverting input end of the comparator.

[0022] The second voltage divider resistor unit has its first end connected to the non-inverting input of the comparator and its second end grounded.

[0023] Wherein, the resistance ratio of the first voltage divider resistor unit and the second voltage divider resistor unit is K-1, where K is the preset coefficient.

[0024] In one exemplary embodiment of this disclosure, the resistance value of the first voltage divider resistor unit is adjustable.

[0025] In one exemplary embodiment of this disclosure, the first voltage divider resistor includes a plurality of resistor sub-units connected in series, each resistor sub-unit including one or more sub-resistors, each resistor sub-unit being connected in parallel with a resistance adjustment switch, and the control terminal of each resistance adjustment switch being used to receive a control signal.

[0026] In one exemplary embodiment of this disclosure, the resistance value of each of the sub-resistors is equal.

[0027] In one exemplary embodiment of this disclosure, the reference voltage generating circuit includes:

[0028] A constant current generation module is used to generate a first current with a positive temperature coefficient and a second current with a negative temperature coefficient, and to generate a constant current based on the first current and the second current.

[0029] A substrate reference voltage generation module includes a transistor, the substrate reference voltage generation module being coupled to the constant current generation module and used to generate the substrate reference voltage with a positive temperature coefficient based on the constant current and transistor characteristics.

[0030] In one exemplary embodiment of this disclosure, the constant current generation module includes:

[0031] A positive temperature coefficient current generating unit is used to generate the first current;

[0032] A negative temperature coefficient current generating unit is connected to the positive temperature coefficient current generating unit and is used to generate the second current.

[0033] In one exemplary embodiment of this disclosure, the positive temperature coefficient current generating unit includes:

[0034] First amplifier;

[0035] The first feedback transistor has its source connected to the power supply voltage, its gate connected to the output terminal of the first amplifier, and its drain connected to the first node.

[0036] The first bridge arm includes a first resistor connected in series and a plurality of first PN junction units connected in parallel. The first end of the first resistor is connected to the first node, and the second end is connected to the inverting input terminal of the first amplifier. The positive terminal of the first PN junction unit is connected to the inverting input terminal of the first amplifier, and the negative terminal is grounded.

[0037] The second bridge arm includes a second resistor, a third resistor, and multiple second PN junction units connected in series. The first end of the second resistor is connected to the first node, and the second end is connected to the non-inverting input terminal of the first amplifier. The first end of the third resistor is connected to the non-inverting input terminal of the first amplifier, and the second end is connected to the positive terminal of the second PN junction unit. The negative terminal of the second PN junction unit is grounded.

[0038] The first output transistor has its source connected to the power supply voltage, its gate connected to the output terminal of the first amplifier, and its drain used to output the first current.

[0039] In one exemplary embodiment of this disclosure, the resistance values ​​of the first resistor and the second resistor are equal.

[0040] In one exemplary embodiment of this disclosure, the number of the second PN junction units is N, where N = (M + 2). 2 -M 2 The number of the first PN junction units is M 2 There are 1, where M is an integer greater than or equal to 1.

[0041] In one exemplary embodiment of this disclosure, the negative temperature coefficient current generating unit includes:

[0042] A second amplifier, the inverting input of which is connected to the inverting input of the first amplifier;

[0043] The second feedback transistor has its source connected to the power supply voltage, its gate connected to the output terminal of the second amplifier, and its drain connected to the non-inverting input terminal of the second amplifier.

[0044] The fourth resistor has one end connected to the non-inverting input of the second amplifier and the other end grounded.

[0045] The second output transistor has its source connected to the power supply voltage, its gate connected to the output terminal of the second amplifier, and its drain used to output the second current.

[0046] In an exemplary embodiment of this disclosure, both the third resistor and the fourth resistor are adjustable resistors. The resistance values ​​of the third resistor and the fourth resistor satisfy the condition that the derivative of (kT / q)*lnZ / R3+(kT / q*lnZ+VBE2) / R4 with respect to temperature T is zero, where R3 is the resistance value of the third resistor, R4 is the resistance value of the fourth resistor, K is the Boltzmann constant, q is the electron charge, T is the operating temperature of the power supply circuit, VBE2 is the voltage difference across the second PN junction unit, and Z is the ratio of the number of the second PN junction units to the number of the first PN junction units.

[0047] In one exemplary embodiment of this disclosure, the substrate reference voltage generation module includes:

[0048] A first N-type transistor, wherein the drain and gate of the first N-type transistor are connected to a second node, the second node is connected to the drain of the first output transistor and the drain of the second output transistor, and the source of the first N-type transistor is grounded;

[0049] The second N-type transistor has its gate connected to the drain of the first output transistor and the drain of the second output transistor, and its source grounded and connected to the third node.

[0050] A first P-type transistor, the source of which is connected to a power supply voltage, and the gate and drain of which are both connected to the third node, the third node being used to output the substrate reference voltage.

[0051] According to a second aspect of this disclosure, a chip is provided, including a power supply circuit as described in any of the preceding claims.

[0052] This embodiment of the present disclosure provides a substrate reference voltage with a positive temperature coefficient and an enable signal output module that outputs an enable signal based on the increase of the substrate reference voltage. When the temperature rises and the transistor leakage current increases, the enable signal controls the voltage output module to automatically increase the substrate voltage of the transistor, thereby reducing the transistor leakage current and thus reducing the power consumption of the integrated circuit. When this power supply circuit is used to provide the substrate voltage of a P-type transistor, it can automatically decrease the substrate voltage of the P-type transistor in the integrated circuit when the temperature rises, thereby reducing the leakage current of the P-type transistor and reducing the overall power consumption of the integrated circuit.

[0053] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0054] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0055] Figure 1 This is a schematic diagram of the power supply circuit 100 in an exemplary embodiment of this disclosure.

[0056] Figure 2 This is a schematic diagram of voltage generation circuit 2 in one embodiment of the present disclosure.

[0057] Figure 3 This is a schematic diagram of voltage generation circuit 2 in another embodiment of this disclosure.

[0058] Figure 4 This is a schematic diagram of the enable signal generation circuit 3 in one embodiment of this disclosure.

[0059] Figure 5A and Figure 5B These are schematic diagrams of the adjustable resistor unit in the embodiments of this disclosure.

[0060] Figure 6 This is a schematic diagram of a reference voltage generation circuit 1 in one embodiment of this disclosure.

[0061] Figure 7 This is a schematic diagram of a constant current generation module 11 in one embodiment of this disclosure.

[0062] Figure 8 This is a schematic diagram of a substrate reference voltage generation module 12 in one embodiment of the present disclosure. Detailed Implementation

[0063] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0064] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0065] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0066] Figure 1 This is a schematic diagram of a power supply circuit in an exemplary embodiment of this disclosure.

[0067] refer to Figure 1 The power supply circuit 100 may include:

[0068] Reference voltage generation circuit 1 is used to generate a substrate reference voltage Vref with a positive temperature coefficient.

[0069] Voltage generation circuit 2 is used to raise the substrate voltage VBP according to the enable signal EN;

[0070] The enable signal generation circuit 3 is connected to the reference voltage generation circuit 1 and the voltage generation circuit 2, and is used to output an enable signal EN to the voltage generation circuit 2 when the substrate reference voltage Vref is greater than the product of the substrate voltage VBP and a preset coefficient.

[0071] This embodiment of the present disclosure provides a substrate reference voltage with a positive temperature coefficient and an enable signal output module that outputs an enable signal based on the increase of the substrate reference voltage. When the temperature rises, the voltage output module can automatically increase the substrate voltage by controlling the enable signal. When this power supply circuit is used to provide the substrate voltage of the P-type transistor, the substrate voltage of the P-type transistor in the integrated circuit can be automatically increased when the temperature rises, thereby reducing the leakage current of the P-type transistor and reducing the overall power consumption of the integrated circuit.

[0072] Figure 2 This is a schematic diagram of a voltage generation circuit in one embodiment of the present disclosure.

[0073] refer to Figure 2 In one embodiment, the voltage generation circuit 2 may include:

[0074] The oscillation module 21 has an input terminal for receiving the enable signal EN and an output terminal for outputting the oscillation signal OSC. The oscillation module 21 is used to generate the oscillation signal OSC based on the enable signal EN.

[0075] The charge pump module 22 has its input terminal connected to the oscillation module 21 and its output terminal used to output the substrate voltage VBP. The charge pump module 22 is used to raise the substrate voltage VBP according to the oscillation signal OSC.

[0076] The oscillation module 21 can be implemented using a controlled ring oscillator, which may include an odd number of input / output ring-connected components with signal inversion function, such as inverters or NAND gates. The oscillation module 21 outputs an oscillation signal OSC when it receives an enable signal EN, and can stop outputting the oscillation signal OSC when it does not receive an enable signal EN.

[0077] Under the control of the oscillation module 21, the charge pump module 22 can maintain the substrate reference voltage Vref equal to the product of the substrate voltage VBP and a preset coefficient. When the temperature rises, the substrate reference voltage Vref rises, or the substrate voltage VBP falls, causing the substrate reference voltage Vref to be greater than the product of the substrate voltage VBP and the preset coefficient, the oscillation module 21 receives the enable signal EN and outputs the oscillation signal OSC. When the charge pump module 22 receives the oscillation signal OSC, it can start the charge pump function to increase the output voltage, that is, raise the substrate voltage VBP, so that the substrate reference voltage Vref equals the product of the substrate voltage VBP and the preset coefficient.

[0078] exist Figure 2In the illustrated embodiment, the charge pump module 22 includes:

[0079] The first capacitor C1, the first end of the first capacitor C1 is coupled to the output end of the oscillation module 21;

[0080] The positive terminal of the first diode D1 is connected to the power supply voltage VCC, and the negative terminal is connected to the second terminal of the first capacitor C1.

[0081] The positive terminal of the second diode D2 is connected to the second terminal of the first capacitor C1, and the negative terminal is used to output the substrate voltage VBP.

[0082] The charge pump module 22 can draw positive charge from the power supply voltage terminal VCC to the negative terminal of the second diode D2 according to the oscillation signal OSC, thereby raising the potential of the negative terminal of the second diode D2 and generating the substrate voltage VBP.

[0083] When the oscillation module 21 stops outputting the oscillation signal OSC, the output voltage of the charge pump module 22, i.e., the negative voltage of the second diode D2, no longer increases.

[0084] Figure 3 This is a schematic diagram of a voltage generation circuit in another embodiment of this disclosure.

[0085] refer to Figure 3 In another embodiment, in order to adjust the output voltage rise of the charge pump module 22, the charge pump module 22 further includes a drive circuit DR connected between the output terminal of the oscillation module 21 and the first terminal of the first capacitor C1. The drive circuit DR can be used to increase the amplitude of the oscillation signal OSC.

[0086] In addition, the charge pump module 22 may also include a second capacitor C2. The first terminal of the second capacitor C2 is connected to the negative terminal of the second diode D2, and the second terminal of the second capacitor C2 is grounded. The second capacitor C2 is used to maintain the output voltage of the charge pump module 22. The second voltage C2 can be used as a filter voltage to further smooth the output voltage of the charge pump module 22, and maintain the negative terminal voltage of the second diode D2 as a nearly stable DC voltage during the output of the oscillation signal OSC.

[0087] Figure 4 This is a schematic diagram of an enable signal generation circuit in one embodiment of the present disclosure.

[0088] refer to Figure 4 In one embodiment, the enable signal generation circuit 3 may include:

[0089] The inverting input of comparator COMP is used to receive the substrate reference voltage Vref;

[0090] Inverter OP, the input of inverter OP is connected to the output of comparator COMP, and the output of inverter is connected to voltage generation circuit 2 to output enable signal EN;

[0091] The first voltage divider resistor unit RZ1 has its first end connected to the output of the voltage generation circuit 2 to receive the substrate voltage VBP, and its second end connected to the non-inverting input of the comparator COMP.

[0092] The second voltage divider resistor unit RZ2 has its first end connected to the non-inverting input of the comparator COMP, and its second end grounded.

[0093] The resistance ratio of the first voltage divider resistor unit RZ1 to the second voltage divider resistor unit RZ2 is K-1, where K is a preset coefficient.

[0094] exist Figure 4 In the embodiment shown, if the resistance of the second voltage divider resistor unit RZ2 is R, then the resistance of the first voltage divider resistor unit RZ1 is (K-1)R.

[0095] Analysis shows that the voltage at the non-inverting input of comparator COMP is equal to VBP / K. When the substrate reference voltage Vref is less than VBP / K, comparator COMP outputs a high level, inverter OP outputs a low level, and the enable signal EN is low. When the enable signal EN is set to high, voltage generation circuit 2 does not raise the substrate voltage VBP. When the substrate reference voltage Vref gradually increases to greater than VBP / K, comparator COMP flips to output a low level, inverter OP outputs a high level, the enable signal EN is high, and voltage generation circuit 2 begins to raise the substrate voltage VBP.

[0096] Therefore, when a substrate reference voltage Vref with a positive temperature coefficient is applied to control the substrate voltage of an N-type transistor, the substrate reference voltage Vref rises as the temperature increases and the transistor leakage current increases. When the substrate reference voltage Vref rises to a value greater than VBP / K, the enable signal generation circuit 3 outputs a valid enable signal EN, controlling the voltage generation circuit 2 to start raising the substrate voltage VBN, thereby automatically reducing the transistor leakage current and the impact of temperature rise on transistor power consumption.

[0097] In one embodiment, the resistance value of the first voltage divider resistor unit RZ1 is adjustable. The first voltage divider resistor unit RZ1 can be adjusted via... Figure 5A or Figure 5B The adjustable resistor unit shown is used to achieve this.

[0098] Figure 5A and Figure 5B This is a schematic diagram of the adjustable resistor unit in an embodiment of this disclosure.

[0099] An adjustable resistor unit may include multiple resistor sub-units connected in series. Each resistor sub-unit includes one or more sub-resistors, and each resistor sub-unit is connected in parallel with a resistance adjustment switch. The control terminal of each resistance adjustment switch is used to receive control signals. The resistance value of each sub-resistor can be set to be equal. In this case, the adjustable resistor unit can... Figure 5A The resistor string shown is used to achieve this.

[0100] refer to Figure 5A The resistor string 501 includes multiple sub-resistors R01, R02, R03, R04, R05, and R06 connected in series, and controllable resistance adjustment switches Con1, Con2, and Con3 connected to the first or second terminals of the sub-resistors. The first and second terminals of resistance adjustment switch Con1 are respectively connected to the two ends of sub-resistor R01; the first and second terminals of resistance adjustment switch Con2 are respectively connected to the second terminal of sub-resistor R01 / the first terminal of sub-resistor R02 and the second terminal of sub-resistor R03 / the first terminal of sub-resistor R04; the first and second terminals of resistance adjustment switch Con3 are respectively connected to the second terminal of sub-resistor R03 / the first terminal of sub-resistor R04 and the second terminal of sub-resistor R06. Thus, sub-resistor R01 constitutes a resistor sub-unit, sub-circuits R02 and R03 constitute a resistor sub-unit, and sub-resistors R04, R05, and R06 constitute a resistor sub-unit.

[0101] The control terminals of the resistor-regulating switching transistors Con1, Con2, and Con3 all receive control signals. These control signals may come from a processor or a one-time programmable controller, and this disclosure does not specifically limit them.

[0102] exist Figure 5A In the illustrated embodiment, the resistance adjustment switch is implemented using an N-type transistor, with the gate of the N-type transistor serving as the control terminal. In other embodiments of this disclosure, the resistance adjustment switch may be implemented using other components, and this disclosure does not impose any special limitations on this.

[0103] Assuming that the resistance values ​​of sub-resistors R01, R02, R03, R04, R05, and R06 are all R0, then the resistance values ​​of resistor series 501 and the on / off states of resistor adjustment switches Con1, Con2, and Con3 are shown in Table 1:

[0104]

[0105] Table 1

[0106] The resistance values ​​in the above table vary depending on the number of resistors connected across the resistor-adjusting switching transistors Con1, Con2, and Con3. Those skilled in the art can determine the appropriate values ​​based on these values. Figure 5AThe principle shown allows for the adjustment of the number and resistance value of sub-resistors, the number of switching elements, and the connection relationship between the switching elements and sub-resistors, thereby achieving various resistance value settings.

[0107] Alternatively, an adjustable resistor unit can be implemented using another type of resistor string.

[0108] refer to Figure 5B The resistor string 502 includes multiple sub-resistors R01, R02, R03, and R04 connected in series. The first end of sub-resistor R01 serves as the first end of the resistor string 502. The first ends of sub-resistors R02, R03, and R04 are respectively connected to the second ends of sub-resistors R01, R02, and R03. The second ends of sub-resistors R01, R02, and R03 are respectively connected to the second ends of resistance adjustment switches Con1, Con2, and Con3.

[0109] The first and second terminals of the resistance regulating switch Con1 are respectively connected to the two ends of the sub-resistor R01; the first and second terminals of the resistance regulating switch Con2 are respectively connected to the first terminal of the resistor string 502 and the second terminal of the sub-resistor R02; the first and second terminals of the resistance regulating switch Con3 are respectively connected to the first terminal of the resistor string 502 and the second terminal of the sub-resistor R03.

[0110] Assuming that the resistance values ​​of sub-resistors R01, R02, R03, and R04 are all R, the resistance values ​​of resistor series 502 and the on / off states of resistor adjustment switches Con1, Con2, and Con3 are shown in Table 2:

[0111]

[0112] Table 2

[0113] As shown in Table 2, in Figure 5B In the illustrated embodiment, at most one switching element is controlled to be turned on to adjust the resistance value of resistor series 502. Although in Figure 5B In the illustrated embodiment, the second terminals of the two resistance-adjusting switches are separated by only one sub-resistor. However, in other embodiments of this disclosure, the second terminals of the two resistance-adjusting switches may be separated by a different number of sub-resistors, or sub-resistors of different resistance values, or sub-resistors of different numbers and resistance values. It should be noted that for the resistance-adjusting switch with the maximum number of sub-resistors across its two ends, its second terminal needs to be connected to a sub-resistor to prevent the resistance of the resistor series 502 from being zero.

[0114] Figure 6 This is a schematic diagram of a reference voltage generation circuit in one embodiment of the present disclosure.

[0115] refer to Figure 6 In one embodiment, the reference voltage generation circuit 1 includes:

[0116] The constant current generation module 11 is used to generate a first current I1 with a positive temperature coefficient and a second current I2 with a negative temperature coefficient, and to generate a constant current I based on the first current I1 and the second current I2.

[0117] The substrate reference voltage generation module 12 includes a transistor. The substrate reference voltage generation module 12 is coupled to the constant current generation module 11 and is used to generate a substrate reference voltage Vref with a positive temperature coefficient based on the constant current I and the characteristics of the transistor.

[0118] Figure 6 In the illustrated embodiment, the substrate reference voltage Vref generated is related to the temperature characteristics of the transistor.

[0119] The threshold voltage of a transistor is temperature-dependent. The threshold voltage of an N-type transistor decreases with increasing temperature, while the absolute value of the threshold voltage of a P-type transistor decreases with increasing temperature. Since the threshold voltage of a P-type transistor is negative, it decreases with increasing temperature. Therefore, when a constant current I is input to the transistor in the substrate reference voltage generation module 12, the threshold voltage Vth of the transistor changes with temperature. Consequently, the voltage output through the transistor is independent of the current and depends only on the temperature.

[0120] Figure 7 This is a schematic diagram of a constant current generation module 11 in one embodiment of this disclosure.

[0121] refer to Figure 7 In one embodiment, the constant current generation module 11 may include:

[0122] Positive temperature coefficient current generating unit 111 is used to generate the first current I1;

[0123] The negative temperature coefficient current generating unit 112 is connected to the positive temperature coefficient current generating unit 111 and is used to generate a second current I2.

[0124] The first current I1 and the second current I2 together form a constant current I.

[0125] The substrate reference voltage generation module 12 is used to output a substrate reference voltage Vref with a positive temperature coefficient based on a constant current I. The substrate reference voltage Vref with a positive temperature coefficient is, for example, a voltage output based on the temperature characteristics of a P-type transistor.

[0126] exist Figure 7 In the illustrated embodiment, the positive temperature coefficient current generating unit 11 may include:

[0127] First amplifier AMP1;

[0128] The first feedback transistor MB1 has its source connected to the power supply voltage VCC, its gate connected to the output terminal of the first amplifier AMP1, and its drain connected to the first node N1.

[0129] The first bridge arm B1 includes a first resistor R1 connected in series and multiple first PN junction units J1 connected in parallel. The first end of the first resistor R1 is connected to the first node N1, and the second end is connected to the inverting input terminal of the first amplifier AMP1 and the positive terminal of the first PN junction unit J1. The negative terminal of the first PN junction unit J1 is grounded.

[0130] The second bridge arm B2 includes a second resistor R2, a third resistor R3, and a second PN junction unit J2 connected in series. The first end of the second resistor R2 is connected to the first node N1, and the second end is connected to the non-inverting input terminal of the first amplifier AMP1. The first end of the third resistor R3 is connected to the non-inverting input terminal of the first amplifier AMP1, and the second end is connected to the positive terminal of the second PN junction unit J2. The negative terminal of the second PN junction unit J2 is grounded.

[0131] The first output transistor MO1 has its source connected to the power supply voltage VCC, its gate connected to the output terminal of the first amplifier AMP1, and its drain used to output the first current I1.

[0132] Both the first feedback transistor MB1 and the first output transistor MO1 can be P-type transistors.

[0133] There can be multiple second PN junction units J2. These multiple second PN junction units J2 are connected in parallel, with the positive terminal of each second PN junction unit connected to the second terminal of the third resistor R3, and the negative terminal grounded. In one embodiment, the number of second PN junction units can be N = (M + 2). 2 -M 2 There are M units in the first PN junction. 2 There are 1, where M is an integer greater than or equal to 1. This arrangement allows the second PN junction unit J2 to surround the first PN junction unit J1 during manufacturing, forming a (M+2)*(M+2) PN junction unit array.

[0134] For example, when M=1, N=3, the number of the first PN junction unit J1 is 1, and the number of the second PN junction unit J2 is 3*3-1=8. The first PN junction unit J1 and the second PN junction unit J2 are arranged in a 3*3 array.

[0135] When M=2, N=4, the number of the first PN junction unit J1 is 4, and the number of the second PN junction unit J2 is 4*4-4=12. The first PN junction unit J1 and the second PN junction unit J2 are arranged in a 4*4 array.

[0136] When M=3, N=5, the number of first PN junction units J1 is 9, and the number of second PN junction units J2 is 5*5-9=16. The first PN junction units J1 and the second PN junction units J2 are arranged in a 5*5 array. And so on.

[0137] exist Figure 7 In the embodiment shown, for the sake of simplifying the analysis, we assume M=1, N=3, the number of the first PN junction unit J1 is 1, and the number of the second PN junction unit J2 is 8.

[0138] exist Figure 7 In the illustrated embodiment, the first resistor R1 and the second resistor R2 are the same. Due to the virtual short characteristic of the amplifier, the voltage difference between the first node N1 and the inverting input terminal of the first amplifier AMP1 is equal to the voltage difference between the first node N1 and the non-inverting input terminal of the first amplifier AMP1, and the first resistor R1 between the first node N1 and the inverting input terminal of the first amplifier AMP1 and the second resistor R2 between the first node N1 and the non-inverting input terminal of the first amplifier AMP1 are equal. Therefore, the current on the first bridge arm B1 and the second bridge arm B2 is the same.

[0139] Continuing the deduction, the voltage difference between the first node N1 and the inverting input terminal of the first amplifier AMP1 is equal to the voltage difference between the first node N1 and the non-inverting input terminal of the first amplifier AMP1, and the voltage difference between the first node N1 and the inverting input terminal of the first amplifier AMP1 is equal to the PN junction voltage V of the first PN junction unit J1. BE1 Then the voltage across the first terminal of the third resistor R1 is Let the positive voltage at the second terminal of the third resistor R3, i.e., the second PN junction unit J2, be... According to the VI characteristic expression of the PN junction, we have:

[0140] (1)

[0141] in, It is the current in the PN junction unit. It is the reverse saturation current of the PN junction unit (temperature-dependent, and constant at a given temperature), V T It is thermal voltage, with V T =kT / q, where K is the Boltzmann constant and q is the electron charge, and k = 1.38 × 10⁻⁶. - 23 J / K (joules / Kelvin), q = 1.6 × 10 -19 C (coulomb); T is absolute temperature, the unit is Kelvin. V T Also known as the temperature voltage equivalent, it refers to the potential difference that occurs between two points in a closed circuit due to a temperature difference. When T = 300K (room temperature), V T=kT / q≈0.026V. n is the emission coefficient, which is related to the size and material of the PN junction and the current passing through it, and is between 1 and 2.

[0142] Since the currents on the first bridge arm B1 and the second bridge arm B2 are equal, the currents on the eight parallel second PN junction units J2 are equal to the currents on the first PN junction unit J1. Let the current on each second PN junction unit J2 be... Then the current on the first PN junction unit J1 is 8. .

[0143] When the number of the first PN junction unit J1 and the second PN junction unit J2 are other values, let the current of each second PN junction unit J2 be... Then the current on the first PN junction unit J1 is Z. Z represents the ratio of the number of second PN junction units J2 to the number of first PN junction units J1.

[0144] When V BE Much greater than V T When n=1, the 1 in the parentheses of formula (1) can be ignored, and we have:

[0145] (2)

[0146] thereby,

[0147] (3)

[0148] Similarly, we obtain V BE2 The formula:

[0149] (4)

[0150] Based on the same assumptions and derivations, we obtain:

[0151] (5)

[0152] Therefore, the voltage V across the third resistor R3 BE1 -V BE2 have:

[0153] (6)

[0154] Therefore, the current I on the second bridge arm B2 112 have:

[0155] (7)

[0156] Where R3 is the resistance value of the third resistor R3. Since N is fixed, and Proportional, VT The current I on the second bridge arm B2 is proportional to the temperature T. 112 It is proportional to temperature T and has a positive temperature coefficient.

[0157] In the above formulas, when the number of the first PN junction unit J1 and the second PN junction unit J2 is other values, the number 8 in formulas (2) to (7) can be replaced by the ratio Z of the number of the second PN junction unit J2 and the first PN junction unit J1.

[0158] Since the currents on the first bridge arm B1 and the second bridge arm B2 are the same, the current in the first feedback transistor MB1 is equal to twice the current in the second bridge arm B2, which is 2V. T lnN / R3.

[0159] The first feedback transistor MB1 and the first output transistor MO1 form a current mirror. In one embodiment, the channel width-to-length ratio of the first feedback transistor MB1 and the first output transistor MO1 is 2:1. Therefore, the first current I1 output from the drain of the first output transistor MO1 is equal to half the current on the first feedback transistor MB1, and equal to the current I on the second bridge arm B2. 112 .

[0160] It can be seen that the drain current I1 of the first output transistor MO1 is negatively correlated with the resistance value of the third resistor R3. Therefore, the third resistor R3 can be set as an adjustable resistor to adjust the value of the first current I1.

[0161] exist Figure 7 In the illustrated embodiment, the first PN junction unit J1 and the second PN junction unit J2 are implemented using a self-biased transistor, which is an N-type transistor, and both its gate and source are grounded. In other embodiments of this disclosure, the first PN junction unit J1 and the second PN junction unit J2 can be implemented in various ways, or they can be implemented directly using diodes; this disclosure does not impose any special limitations on this.

[0162] Continue to refer to Figure 7 In the embodiment shown, the negative temperature coefficient current generating unit 12 may include:

[0163] The second amplifier AMP2 has its inverting input connected to the inverting input of the first amplifier AMP1.

[0164] The second feedback transistor MB2 has its source connected to the power supply voltage VCC, its gate connected to the output terminal of the second amplifier AMP2, and its drain connected to the non-inverting input terminal of the second amplifier AMP2.

[0165] The fourth resistor R4 is connected at one end to the non-inverting input of the second amplifier AMP2, and at the other end to ground;

[0166] The second output transistor MO2 has its source connected to the power supply voltage VCC, its gate connected to the output terminal of the second amplifier AMP2, and its drain used to output the second current I2.

[0167] Analysis shows that the second output transistor MO2 and the second feedback transistor MB2 form a current mirror. The voltages at the non-inverting and inverting input terminals of the second amplifier AMP2 are equal, and the voltage across the fourth resistor R4 is equal to the junction voltage V of the first PN junction unit J1. BE1 Then the current on the second feedback transistor MB2 is equal to Assuming the channel width-to-length ratio of the second feedback transistor MB2 and the second output transistor MO2 is 1:1, the second current I2 output from the drain of the second output transistor MO2 is:

[0168] (8)

[0169] According to formula (6):

[0170] (9)

[0171] Therefore, we have:

[0172] (10)

[0173] The voltage drop across a PN junction when current flows through it is related to the forward current and temperature; the larger the current, the larger the voltage drop, and the higher the temperature, the smaller the voltage drop. This means a PN junction has a negative temperature coefficient voltage. Therefore, V BE2 If I is a negative temperature coefficient voltage, then I2 is a negative temperature coefficient current.

[0174] And since the final output constant current I = I1 + I2, the formula for the constant current I is:

[0175] (11)

[0176] Where I1 is the positive temperature coefficient current and I2 is the negative temperature coefficient current. and All of these are values ​​related to temperature T. Adjust the resistance values ​​of the third resistor R3 and the fourth resistor R4. When the derivative of formula (11) with respect to temperature T is zero, the constant current I is the zero temperature coefficient current.

[0177] In one exemplary embodiment of this disclosure, both the third resistor R3 and the fourth resistor R4 are adjustable resistors, and both can be adjusted by... Figure 5A or Figure 5B The implementation shown is illustrated and will not be described in detail here.

[0178] Figure 8This is a schematic diagram of a substrate reference voltage generation module in one embodiment of the present disclosure.

[0179] refer to Figure 8 In one embodiment, the substrate reference voltage generation module 12 may include:

[0180] The first N-type transistor MN1 has its drain and gate connected to the second node N2. The second node N2 is connected to the drain of the first output transistor MO1 and the drain of the second output transistor MO2. The source of the first N-type transistor MN1 is grounded.

[0181] The gate of the second N-type transistor MN2 is connected to the drain of the first output transistor MO1 and the drain of the second output transistor MO2. The source of the second N-type transistor MN2 is grounded and connected to the third node N3.

[0182] The first P-type transistor MP1 has its source connected to the power supply voltage VCC, and its gate and drain are both connected to the third node N3. The third node N3 is used to output the substrate reference voltage Vref.

[0183] pass Figure 8 In the embodiment shown, the substrate reference voltage generation module 12 can output a substrate reference voltage Vref with a positive temperature coefficient.

[0184] As described above, the threshold voltage (Vth) of the first N-type transistor MN1 decreases with increasing temperature. The current flowing through the first N-type transistor MN1 is a constant current I, which is proportional to the difference between the gate-source voltage (Vgs) and the threshold voltage (Vth). Therefore, when the constant current I remains constant, the source voltage remains constant, and the threshold voltage (Vth) decreases, the gate voltage (Vn) of the first N-type transistor MN1 decreases. Thus, Vn is a negative temperature coefficient voltage, meaning that the higher the temperature, the smaller Vn becomes.

[0185] The second N-type transistor MN2 and the first N-type transistor MN1 form a current mirror, and the drain current of the second N-type transistor MN2 is proportional to the drain current of the first N-type transistor MN1. Therefore, the drain current of the first P-type transistor MP1 is also a constant current with zero temperature coefficient. In this embodiment, for the sake of simplifying the analysis, the channel width-to-length ratio of the second N-type transistor MN2 and the first N-type transistor MN1 is set to be the same, so the drain current of the first P-type transistor MP1 is equal to the constant current I on the first N-type transistor MN1.

[0186] The substrate reference voltage Vref with a positive temperature coefficient is only affected by the constant current I and the characteristics of the first P-type transistor MP1. Since the constant current I is independent of temperature, the substrate reference voltage Vref with a positive temperature coefficient is only related to the characteristics of the first P-type transistor MP1.

[0187] The threshold voltage of a P-type transistor increases with increasing temperature. The current I on the first P-type transistor MP1 is a constant current, which is proportional to the difference between the gate-source voltage (Vgs, which is negative when on) and the threshold voltage (Vth, which is negative) of the first P-type transistor MP1. Therefore, when the threshold voltage of the first P-type transistor MP1 increases with increasing temperature, the difference between the gate-source voltage (Vgs) and the threshold voltage (Vth) of the first P-type transistor MP1 remains unchanged, and the gate-source voltage (Vgs) of the first P-type transistor MP1 will increase. At this time, the source voltage of the first P-type transistor MP1 remains unchanged, but the gate voltage of the first P-type transistor MP1 will increase, that is, the substrate reference voltage Vref increases with increasing temperature.

[0188] Therefore, the substrate reference voltage generation module 12 can automatically output a substrate reference voltage Vref with a positive temperature coefficient when the temperature changes.

[0189] According to a second aspect of this disclosure, a chip is provided, including a power supply circuit as described in any of the above embodiments.

[0190] In one embodiment of this disclosure, a switching circuit can be used to switch the power supply circuit that provides substrate voltage to the transistors according to the chip's operating mode. For example, when the chip is working normally, the power supply circuit that provides substrate voltage to the transistors is controlled to be the power supply voltage VCC. When the chip enters Deep Sleep Mode (DSM), the power supply circuit of any of the above embodiments is switched to provide substrate voltage VBP to the chip.

[0191] In this embodiment, the temperature is, for example, the chip's operating temperature (ambient temperature). Assuming that in a high-temperature environment, the chip uses a fixed power supply voltage VCC as the substrate voltage of the P-type transistor during normal operation, the substrate voltage VCC is constant regardless of temperature. Therefore, the power consumption caused by leakage current is negligible compared to the chip's overall power consumption. However, when the chip enters DSM mode, the power consumption caused by leakage current is significantly higher. Therefore, the power supply circuit 100 of this embodiment can be controlled by a switching circuit to switch the substrate voltage of the P-type transistor to a substrate voltage VBP with a positive temperature coefficient. The substrate voltage VBP will either rise with the ambient temperature or remain constant, thereby reducing the leakage current increased by the temperature and thus reducing the chip's power consumption in DSM mode.

[0192] In the embodiments of this disclosure, the power supply circuit providing substrate voltage to the chip can be switched in various ways. For example, it can be achieved by controlling the enable of the driver DR with a DSM signal, or by making a control switch between the oscillation module 21 and the charge pump module 22, or by directly using the DSM signal to control the enable of the reference voltage generation circuit 1, or by making a selection circuit at the substrate end to select the substrate voltage source, etc. There are many ways to achieve substrate voltage switching, and this disclosure does not impose any special limitations on them.

[0193] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0194] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.

Claims

1. A power supply circuit, characterized by comprising: The application relates to a reference voltage generation circuit, which comprises: a reference voltage generation circuit for generating a positive temperature coefficient substrate reference voltage; a voltage generation circuit for lifting a substrate voltage according to an enable signal; an enable signal generation circuit connected with the reference voltage generation circuit and the voltage generation circuit, for outputting the enable signal to the voltage generation circuit when the substrate reference voltage is greater than the product of the substrate voltage and a preset coefficient; the voltage generation circuit comprises: an oscillation module, an input end of which is used for receiving the enable signal, and an output end of which is used for outputting an oscillation signal, the oscillation module being used for generating the oscillation signal according to the enable signal; a charge pump module, an input end of which is connected with the oscillation module, and an output end of which is used for outputting the substrate voltage, the charge pump module being used for lifting the substrate voltage according to the oscillation signal; the enable signal generation circuit comprises: a comparator, an inverting input end of the comparator being used for receiving the substrate reference voltage; an inverter, an input end of the inverter being connected with the output end of the comparator, and an output end of the inverter being connected with the voltage generation circuit and being used for outputting the enable signal; a first voltage division resistor unit, a first end of the first voltage division resistor unit being connected with the output end of the charge pump module and being used for receiving the substrate voltage, and a second end of the first voltage division resistor unit being connected with the non-inverting input end of the comparator; a second voltage division resistor unit, a first end of the second voltage division resistor unit being connected with the non-inverting input end of the comparator, and a second end of the second voltage division resistor unit being grounded; wherein the resistance ratio of the first voltage division resistor unit and the second voltage division resistor unit is K-1, and K is the preset coefficient.

2. The power supply circuit of claim 1, wherein, the charge pump module comprises: a first capacitor, a first end of the first capacitor being coupled with the output end of the oscillation module; a first diode, a positive electrode of the first diode being connected with a power supply voltage, and a negative electrode of the first diode being connected with a second end of the first capacitor; a second diode, a positive electrode of the second diode being connected with the second end of the first capacitor, and a negative electrode of the second diode being used for outputting the substrate voltage.

3. The power supply circuit of claim 2, wherein, the charge pump module further comprises a driving circuit connected between the output end of the oscillation module and the first end of the first capacitor, the driving circuit being used for increasing the amplitude of the oscillation signal.

4. The power supply circuit of claim 2, wherein, the charge pump module further comprises a second capacitor, a first end of the second capacitor being connected with the negative electrode of the second diode, and a second end of the second capacitor being grounded, the second capacitor being used for maintaining the output voltage of the charge pump module.

5. The power supply circuit of claim 1, wherein, the resistance of the first voltage division resistor unit is adjustable.

6. The power supply circuit of claim 5, wherein, the first voltage division resistor comprises a plurality of resistor subunits connected in series, each resistor subunit comprises one or more subresistors, each resistor subunit is connected in parallel with a resistor adjusting switch tube, and the control end of each resistor adjusting switch tube is used for receiving a control signal.

7. The power supply circuit of claim 6, wherein, the resistance of each subresistor is equal.

8. The power supply circuit of claim 1, wherein, the reference voltage generation circuit comprises: a constant current generation module for generating a first current with a positive temperature coefficient and a second current with a negative temperature coefficient, and generating a constant current according to the first current and the second current; a substrate reference voltage generation module comprising a transistor, the substrate reference voltage generation module being coupled with the constant current generation module and being used for generating the substrate reference voltage with a positive temperature coefficient according to the constant current and transistor characteristics.

9. The power supply circuit of claim 8, wherein, the constant current generation module comprises: A positive temperature coefficient current generating unit for generating the first current; A negative temperature coefficient current generating unit connected to the positive temperature coefficient current generating unit for generating the second current.

10. The power supply circuit of claim 9, wherein, The positive temperature coefficient current generating unit comprises: A first amplifier; A first feedback transistor, a source of the first feedback transistor connected to a power supply voltage, a gate connected to an output of the first amplifier, and a drain connected to a first node; A first bridge arm, the first bridge arm comprising a first resistor and a plurality of first PN junction units connected in parallel in series, a first end of the first resistor connected to the first node, and a second end connected to an inverting input of the first amplifier, positive poles of the first PN junction units connected to the inverting input of the first amplifier, and negative poles grounded; A second bridge arm, the second bridge arm comprising a second resistor, a third resistor, and a plurality of second PN junction units connected in parallel in series, a first end of the second resistor connected to the first node, and a second end connected to a non-inverting input of the first amplifier, a first end of the third resistor connected to the non-inverting input of the first amplifier, and a second end connected to positive poles of the second PN junction units, and negative poles grounded; A first output transistor, a source connected to the power supply voltage, a gate connected to the output of the first amplifier, and a drain for outputting the first current.

11. The power supply circuit of claim 10, wherein, The first resistor and the second resistor have equal resistance values.

12. The power supply circuit of claim 11, wherein, The number of the second PN junction units is N, N=(M+2) 2 -M 2 The number of the first PN junction units is M 2 , wherein M is an integer greater than or equal to 1.

13. The power supply circuit of claim 10, wherein, The negative temperature coefficient current generating unit comprises: A second amplifier, an inverting input of the second amplifier connected to the inverting input of the first amplifier; A second feedback transistor, a source of the second feedback transistor connected to the power supply voltage, a gate connected to an output of the second amplifier, and a drain connected to a non-inverting input of the second amplifier; A fourth resistor, one end connected to the non-inverting input of the second amplifier, and the other end grounded; A second output transistor, a source connected to the power supply voltage, a gate connected to the output of the second amplifier, and a drain for outputting the second current.

14. The power supply circuit of claim 13, wherein, The third resistor and the fourth resistor are adjustable resistors, and resistance values of the third resistor and the fourth resistor satisfy that a derivative of (kT / q)*lnZ / R3+(kT / q*lnZ+VBE2) / R4 with respect to temperature T is zero, where R3 is the resistance value of the third resistor, R4 is the resistance value of the fourth resistor, K is the Boltzmann constant, q is the electronic charge, T is the working temperature of the power supply circuit, VBE2 is a voltage difference across the second PN junction unit, and Z is a quantity ratio of the second PN junction unit to the first PN junction unit.

15. The power supply circuit of claim 13, wherein, The substrate reference voltage generating module comprises: A first N-type transistor, a drain and a gate of the first N-type transistor connected to a second node, the second node connected to a drain of the first output transistor and a drain of the second output transistor, and a source grounded; A second N-type transistor, a gate of the second N-type transistor connected to the drain of the first output transistor and the drain of the second output transistor, a source grounded, and a source connected to a third node; a first P-type transistor having a source connected to a power supply voltage, a gate and a drain both connected to the third node for outputting the substrate reference voltage.

16. A chip, characterized by A power supply circuit comprising the power supply circuit as claimed in any one of claims 1 to 15.

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