Interface control method, device, system and computer device

Abstract

An embodiment of the present application provides an interface control method, device, system, and computer device. The interface control method includes: configuring a corresponding physical line for each device line of a port, where the port includes at least two device lines; the number of the physical lines is at least two; obtaining mapping information between the device line and the physical line, and determining inversion information between the device line and the physical line according to the mapping information; determining the physical line through which a clock signal passes according to the inversion information, and making the physical line through which the clock signal passes unable to be turned off; detecting whether the physical line transmits data, and turning off the physical line that does not pass data. In this way, when turning off the physical line that does not transmit data, the physical line through which the clock signal passes will not be erroneously turned off, so as to reduce the power consumption of the interface on the premise of ensuring the stability of the read clock, and further reduce the power consumption of the processor.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of computer technologies, and in particular, to an interface control method, apparatus, system, and computer device. Background Art

[0002] A port of a high-speed serial interface in the prior art has multiple lanes, but some lanes are in an idle or unused state in this port. At this time, these idle lanes need to be closed to save power consumption, and at the same time, it is necessary to avoid closing the physical lanes of the clock signal passing through the interface, because the physical lanes of the clock signal passing through provide a working clock for the port. Therefore, how to save the power consumption of the high-speed serial interface has become a problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0003] In view of this, embodiments of the present application provide an interface control method, apparatus, system, and computer device to save the power consumption of a high-speed serial interface.

[0004] To achieve the above object, embodiments of the present invention provide the following technical solutions:

[0005] Embodiments of the present application provide an interface control method, including:

[0006] Configuring a physical lane corresponding to each device lane of the port, where the port includes at least two device lanes; the number of physical lanes is at least two;

[0007] Obtaining mapping information between the device lane and the physical lane, and determining inversion information between the device lane and the physical lane according to the mapping information;

[0008] Determining the physical lane through which the clock signal passes according to the inversion information, so that the physical lane through which the clock signal passes cannot be closed;

[0009] Detecting whether the physical lane transmits data, and closing the physical lanes that do not pass data.

[0010] Optionally, the at least two device lanes have device lane numbers from low to high;

[0011] The at least two physical lanes have physical lane numbers from low to high;

[0012] The mapping information includes the actual correspondence between the device lane number of the device lane and the physical lane number of the physical lane and the inversion information.

[0013] Optionally, the inversion information includes: forced inversion information, indicating that there is a forced inversion between the device lane and the physical lane when the forced inversion information exists;

[0014] The forced inversion includes: the physical line numbers of the physical lines corresponding from high to low and the device line numbers of the device lines corresponding from low to high.

[0015] Optionally, the step of determining the physical line through which the clock signal passes according to the inversion information and making the physical line through which the clock signal passes unable to be closed includes:

[0016] Detecting whether there is forced inversion information;

[0017] If there is forced inversion information, making the physical line with the highest physical line number the physical line through which the clock signal passes;

[0018] If there is no such forced inversion information, making the physical line with the lowest physical line number the physical line through which the clock signal passes.

[0019] Optionally, the step of detecting whether the physical line transmits data and closing the physical line that does not pass data includes:

[0020] Detecting whether the physical line transmits data and sending a closing signal to the physical line that does not pass data.

[0021] Optionally, the inversion information further includes: training inversion information, which indicates that there is a training inversion between the device line and the physical line when there is the training inversion information;

[0022] The training inversion includes: the device line numbers of the device lines corresponding from high to low and the physical line numbers of the physical lines corresponding from low to high.

[0023] Optionally, before the step of detecting whether there is forced inversion information, it further includes:

[0024] Detecting whether there is training inversion information;

[0025] If there is the training inversion information, masking the closing signal of the physical line corresponding to the device line with the largest device line number.

[0026] The embodiment of the present application further provides an interface control device, including:

[0027] A port configuration module, configured to configure corresponding physical lines for the device lines of the port, where the port includes at least two device lines; the number of the physical lines is at least two;

[0028] A mapping information acquisition module, configured to acquire the mapping information between the device line and the physical line, and determine the inversion information between the device line and the physical line according to the mapping information;

[0029] A clock line determination module, which determines a physical line for a clock signal according to the inversion information, and makes the physical line for the clock signal unable to be turned off;

[0030] A line closing module, which is used to detect whether data is transmitted on the physical line and close the physical lines that do not pass data.

[0031] Optionally, the at least two device lines have device line numbers from low to high;

[0032] The at least two physical lines have physical line numbers from low to high;

[0033] The mapping information includes the actual correspondence between the device line numbers of the device lines and the physical line numbers of the physical lines and the inversion information.

[0034] Optionally, the inversion information includes: forced inversion information, which indicates that there is a forced inversion between the device line and the physical line when the forced inversion information exists;

[0035] The forced inversion includes: the correspondence of the physical line numbers of the physical lines from high to low and the device line numbers of the device lines from low to high.

[0036] Optionally, the line determination module, which determines a physical line for a clock signal according to the inversion information and makes the physical line for the clock signal unable to be turned off, includes:

[0037] A forced inversion information detection module, which is used to detect whether forced inversion information exists;

[0038] A first line setting module, which, if forced inversion information exists, makes the physical line with the highest physical line number the physical line for the clock signal;

[0039] A second line setting module, which, if the forced inversion information does not exist, makes the physical line with the lowest physical line number the physical line for the clock signal.

[0040] Optionally, the line closing module, which is used to detect whether data is transmitted on the physical line and close the physical lines that do not pass data, includes:

[0041] A closing signal sending module, which is used to detect whether data is transmitted on the physical line and send a closing signal to the physical lines that do not pass data.

[0042] Optionally, the inversion information further includes: training inversion information, which indicates that there is a training inversion between the device line and the physical line when the training inversion information exists;

[0043] The training inversion includes: the correspondence of the device line numbers of the device lines from high to low and the physical line numbers of the physical lines from low to high.

[0044] Optionally, the line determination module is configured to determine the physical line through which the clock signal passes according to the inversion information, so that the physical line through which the clock signal passes cannot be turned off, and further includes:

[0045] A training inversion information detection module, configured to detect whether there is training inversion information;

[0046] A shutdown signal shielding module, configured to shield the shutdown signal of the physical line corresponding to the device line with the largest device line number if there is the training inversion information.

[0047] An embodiment of the present application further provides an interface system, including the interface control device described above, and further including:

[0048] A line mapping module, configured to store the correspondence between the device lines and the physical lines;

[0049] At least one first-in first-out buffer, configured to buffer the data transmitted from the device line to the physical line;

[0050] A register module, configured to configure forced inversion for the port.

[0051] An embodiment of the present application further provides a system including the interface system described above.

[0052] The interface control method provided by the embodiment of the present application includes: configuring a physical line corresponding to each device line of a port, where the port includes at least two device lines; the number of physical lines is at least two; obtaining mapping information between the device line and the physical line, and determining inversion information between the device line and the physical line according to the mapping information; determining the physical line through which the clock signal passes according to the inversion information, so that the physical line through which the clock signal passes cannot be turned off; detecting whether the physical line transmits data, and turning off the physical lines that do not pass data.

[0053] That is, after configuring a physical line corresponding to each device line of a port, first determine the physical line through which the clock signal passes according to the inversion information obtained from the mapping information, and then turn off other physical lines that do not pass data. It can be seen that by determining the physical line through which the clock signal passes according to the inversion information obtained from the mapping information and making the physical line through which the clock signal passes unable to be turned off, when turning off the physical lines that do not transmit data subsequently, the physical line through which the clock signal passes will not be wrongly turned off, so as to ensure the stability of the read clock, reduce the power consumption of the interface, and further reduce the power consumption of the processor. Description of the Drawings

[0054] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on the provided drawings.

[0055] Figure 1 It is a schematic structural diagram of an interface system;

[0056] Figure 2 It is a schematic flowchart of the interface control method provided by the embodiment of the present application;

[0057] Figure 3 It is a schematic diagram corresponding to the serial number of the physical line provided by the embodiment of the present application;

[0058] Figure 4 It is a schematic diagram corresponding to the line with forced inversion provided by the embodiment of the present application;

[0059] Figure 5 It is a schematic diagram corresponding to the line with training inversion provided by the embodiment of the present application;

[0060] Figure 6 It is a schematic diagram corresponding to the line with both forced inversion and training inversion provided by the embodiment of the present application;

[0061] Figure 7 It is another schematic flowchart of the interface control method provided by the embodiment of the present application;

[0062] Figure 8 It is a schematic structural diagram of the interface control device provided by the embodiment of the present application;

[0063] Figure 9 It is another schematic structural diagram of the interface control device provided by the embodiment of the present application;

[0064] Figure 10 It is a schematic structural diagram of an interface system including the interface control device provided by the embodiment of the present application. Detailed implementation manners

[0065] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0066] With the growth of big data, the demand for the bandwidth and the number of ports of high-speed serial interfaces is also increasing. Therefore, it is necessary to integrate multiple high-speed serial interfaces in a single chip to meet the bandwidth requirements and the interconnection between multiple devices.

[0067] The high-speed serial interfaces of multiple ports in a processor chip generally share the PHY (Physical) of the high-speed serial interfaces in the chip. A certain number of PHYs of high-speed serial interfaces are integrated inside the chip, and multiple ports are flexibly allocated PHYs. Each PHY includes multiple lanes, and these lanes located in the PHY are also called physical lanes. A high-speed serial interface is composed of 1 to multiple physical lanes. Further, the physical lanes are allocated to the ports according to the type of the ports. For example, when the port is an x8 port, the port will be allocated 8 physical lanes. The types of the ports include x2, x4, or x8, etc. The ports are used to connect the chip to external devices of the chip. The devices include multiple device lanes. After the device lanes are connected to the ports, data can be transmitted through the ports and connected to the physical lanes. Taking a chip with 16 physical lanes set in the PHY as an example, as Figure 1 shown in a certain chip, the PHY3 integrated on the main board 1 has 16 physical lanes, which are allocated to 4 ports, and each port occupies 8, 4, 2, and 2 physical lanes respectively. Although a port has multiple physical lanes, some physical lanes will be idle or unused in this port. At this time, it is necessary to turn off these idle physical lanes to save power consumption. Therefore, it is necessary to make the corresponding physical lanes of the ports reasonably enter or exit the low-power state according to the actual working state of the ports. At the same time, among the above multiple physical lanes, there are also physical lanes that pass through clock signals. The physical lanes that pass through clock signals will provide working clocks for the ports. Therefore, it is necessary to avoid turning off the physical lanes that pass through clock signals in the interface.

[0068] Please continue to refer to Figure 1 , as Figure 1As shown, the multi-port controller 2 of the high-speed serial interface may include 4 logical interfaces, namely the first port 10 to the fourth port 13. These ports can all be connected to devices outside the chip. The devices outside the chip are all provided with device lines, so that the device lines are connected to the physical lines through the ports. A total of 16 device lines can be connected to the 4 ports, namely the first device line 100 to the sixteenth device line 115. The 4 ports share 16 physical lines, namely the first physical line 200 to the sixteenth physical line 215, through the line mapping module 40. In a combination mode as shown in the figure, the first port 10 is connected to the first device line 100 - the eighth device line 107 and uses the first physical line 200 - the eighth physical line 207. The second port 11 is connected to the ninth device line 108 - the twelfth device line 111 and uses the ninth physical line 208 - the twelfth physical line 211. The third port 12 is connected to the thirteenth device line 112 - the fourteenth device line 113 and uses the thirteenth physical line 212 - the fourteenth physical line 213. The fourth port 13 is connected to the fifteenth device line 114 - the sixteenth device line 115 and uses the fifteenth physical line 214 - the sixteenth physical line 215.

[0069] It should be noted that a first-in-first-out (FIFO) buffer is also provided between the above ports and physical lines. The FIFO buffer is a kind of buffer that stores the data to be transmitted. It is a buffer with the characteristic of first-in-first-out for data storage, which can prevent data loss during transmission and storage operations, avoid frequent bus operations, reduce the burden on the processor, and improve the data transmission speed. Since the clock signals on the port side and the physical line side may be different, clock signals need to be provided to the FIFO buffer on both sides respectively. Among them, the multi-port controller 2 on the port side provides a write-side clock to the FIFO buffer, and each port provides the data to be sent. Each physical line corresponds to a FIFO buffer, and the physical line provides a read clock to the FIFO buffer. The multiple FIFO buffers belonging to the same port can be regarded as a whole, so that the FIFO buffers belonging to the same port use the same read clock and write clock, which can align the data between multiple physical lines belonging to the same port and avoid misaligned transmission; it can also eliminate the deviation between the write clock and the read clock.

[0070] That is, the above ports and physical lines allocate physical lines to each port according to the mapping logic between the ports and physical lines in the line mapping module 40. After determining the usage of physical lines by each port, the physical lines belonging to one port and the corresponding first-in-first-out (FIFO) buffer form a link. The FIFO buffers within a link use the same write clock and read clock. The write clock comes from the multi-port controller where the port is located, and the read clock comes from the physical line that transmits the clock signal.

[0071] Furthermore, it is necessary to select one physical line from the lines belonging to the same port as the physical line for transmitting the clock signal. Since the read clocks of the FIFO buffers of all the lines belonging to one port are provided by the same physical line for transmitting the clock signal, it is necessary to ensure that the physical line for transmitting the clock signal cannot be turned off.

[0072] Specifically, as Figure 1 shown, the first port 10 is an x8 port, and its eighth physical line 207 is the physical line for transmitting the clock signal, providing the read clock to the first FIFO buffer 30 belonging to the first port 10. The motherboard 1 has an x8 slot, which can connect devices with x8, x4, x2, and x1 interfaces. The second port 11 is an x4 port, and the ninth physical line is the physical line for transmitting the clock signal, providing the read clock to the second FIFO buffer 31 belonging to the second port 11. The motherboard 1 has an x4 slot, which can connect devices with x4, x2, and x1 interfaces. The third port 12 is an x2 port, and the thirteenth physical line 12 is the physical line for transmitting the clock signal, providing the read clock to the third FIFO buffer 32 belonging to the third port 12. The motherboard 1 has an x2 slot, which can connect devices with x2 and x1 interfaces. The fourth port 13 is an x2 port, and the fifteenth physical line 14 is the physical line for transmitting the clock signal, providing the read clock to the fourth FIFO buffer 33 belonging to the fourth port 13. The motherboard 1 has an x2 slot, which can connect devices with x2 and x1 interfaces.

[0073] Based on this, the embodiments of the present application consider turning off other unused physical lines when determining the physical line for transmitting the clock signal of a port to save the power consumption of the chip.

[0074] Based on the above idea, the embodiments of the present application provide an interface control method. As an optional implementation, Figure 2 FIG. shows a schematic flowchart of the interface control method provided by the embodiments of the present application. As Figure 2 shown, the interface control method provided by the embodiments of the present application includes:

[0075] Step S1: Configure corresponding physical lines for the device lines of the port, where the port includes at least two device lines; the number of physical lines is at least two.

[0076] It should be noted that a device using a high-speed serial interface is connected to the port, and at least two device lines are used to transmit data within the device. Furthermore, in order to facilitate the correspondence and connection between the port and the physical line for data communication, in an alternative implementation, the step S1 further includes: performing link training before the port communicates with the physical line. Thus, after the port is connected to the device, the device lines used by the device on the port are correspondingly connected to the physical lines within the PHY to which the port belongs. The link training is completed by hardware logic without the participation of the software system. In this way, the configuration information on the PHY side, the configuration information on the port side, and the connection state between the device line and the physical line can be initialized, and the mapping relationship between the device line and the physical line within the PHY can be determined.

[0077] Further, for the convenience of managing device lines and physical lines, in an alternative implementation, the at least two device lines have device line numbers increasing from low to high. The device line numbers start from 0 and increase accordingly, such as Lane0, Lane1, Lane2, Lane3. The device line number of the device line with a higher priority is smaller, and the device line number of the device line with a lower priority is larger. That is, when the number of device lines used by the device decreases, the device line with a larger device line number is preferentially turned off. In an alternative implementation, the at least two physical lines have physical line numbers (physical Lane numbers) increasing from low to high. The physical line numbers start from 0 and increase accordingly, such as Lane0, Lane1, Lane2, Lane3. It should be noted that in an alternative implementation, the device line numbers of the at least two device lines from low to high correspond to the physical line numbers of the at least two physical lines from low to high. Further, due to the need for link training, in an alternative implementation, the physical line number is the number determined for the physical line before link training. After link training, the physical line will also determine a logical line number (logical Lane number). In an alternative implementation, the physical line corresponding to the device line needs to be assigned a logical line number, and the logical line number is equal to the physical line number of the physical line itself. For example, when the physical line with a physical line number of Lane0 needs to correspond to a device line, the logical line number of the physical line with a physical line number of Lane0 is Lane0; for example, when the physical line with a physical line number of Lane1 does not need to correspond to a device line, the physical line with a physical line number of Lane1 has no logical line number. When mapping between the physical line and the device line, the device line number of the device line is equal to the logical line number of the physical line. In addition, since when the number of device lines used by the device decreases, the device line with a larger device line number is preferentially turned off, it can be seen that when the number of device lines used by the device decreases, the physical line with a larger logical line number is preferentially turned off. Therefore, the mapping relationship between the device line and the physical line can be determined only by the physical line number and the logical line number of the physical line.

[0078] Step S2: Obtain the mapping information between the device line and the physical line, and determine the inversion information between the device line and the physical line according to the mapping information.

[0079] It should be noted that in an optional implementation, the mapping information includes the above-mentioned link training result information, and the mapping method and specific corresponding relationship between the physical line and the device line. Usually, the mapping method between the physical line and the device line is that the device line number of the device line is equal to the logical line number of the physical line, that is, the device line and the physical line are correspondingly connected in sequence according to the magnitude order of the device line number and the logical line number. For example Figure 3 As shown, when there is no inversion, taking the insertion device as x4 as an example, within the processor 4, the logical line number of the physical line with the physical line number Lane0 is also Lane0, so that the physical line with the physical line number Lane0 corresponds to and is connected to the device line with the device line number Lane0. The logical line number of the physical line with the physical line number Lane1 is also Lane1, so that the physical line with the physical line number Lane1 corresponds to and is connected to the device line with the device line number Lane1, and so on. However, the physical lines with the physical line numbers Lane4, Lane5, Lane6, and Lane7 have no logical line numbers because they are not correspondingly connected to the device lines. However, due to the need for circuit routing and / or layout convenience within the substrate of the processor 4, and the circuit design during the soldering of the motherboard where the processor 4 is located, there may be an inversion in the mapping method between the physical line and the device line. Therefore, in an optional implementation, the mapping information further includes the inversion information between the physical line and the device line; the mapping information includes the actual corresponding relationship between the device line number of the device line and the physical line number of the physical line and the inversion information.

[0080] Specifically, the inversion includes training inversion and forced inversion. Therefore, in an optional implementation, the inversion information includes: forced inversion information, which indicates that there is a forced inversion between the device line and the physical line when there is the forced training inversion information; the forced inversion includes: the correspondence of the physical line numbers of the physical lines from high to low and the device line numbers of the device lines from low to high.

[0081] It should be noted that the routing of the port slots on the motherboard where the processor 4 is located is reversed, or the port slots connecting the ports and the devices are soldered in reverse, that is, the physical line with the physical line number Lane7 is connected to the starting pin of the slot. At the same time, due to the slot design, the device line with the device number Lane0 is fixedly connected to the starting pin of the slot, that is, at this time, the physical line with the physical line number Lane7 is correspondingly connected to the device line with the device number Lane0. However, the mapping information in the processor still records that the physical line with the physical line number Lane7 is correspondingly connected to the device line with the device line number Lane7. At this time, to offset the error between the actual corresponding relationship and the corresponding relationship recorded in the mapping information caused by the routing reversal or reverse soldering, a forced reversal needs to be set. Specifically, in an optional implementation, the physical line order is reversed through register configuration and then connected to the port. That is, through register configuration, the physical line numbers sorted from low to high before register configuration become the reversed line numbers sorted from high to low. For example, the physical line number of the physical line with Lane0 is reversed to the reversed line number of Lane7, and the physical line number of the physical line with Lane1 is reversed to the reversed line number of Lane6, and so on. Then, the logical line numbers correspond to the reversed line numbers sorted from low to high. After the logical line numbers correspond to the device line numbers, the device line numbers correspond to the reversed line numbers sorted from low to high, so as to realize the correspondence between the device line numbers sorted from low to high and the reversed line numbers sorted from high to low. In addition, since the routing reversal or reverse soldering can be determined during the motherboard production, in an optional implementation, a register is configured in the processor to force a reversal between the physical line and the device line. And the forced reversal information can be obtained through the register.

[0082] Specifically, the forced reversal is as Figure 4 shown. Taking the inserted device as x8 as an example, the forced reversal between the physical line and the device line is configured by register 5. Therefore, in the processor 4, the logical line number of the physical line with the physical line number Lane0 is Lane7, that is, the physical line with the physical line number Lane0 corresponds to and is connected to the device line with the device number Lane7, and the logical line number of the physical line with the physical line number Lane1 is Lane6, and so on.

[0083] Furthermore, in an optional implementation, the reversal information further includes: training reversal information, which indicates that there is a training reversal between the device line and the physical line when there is the training reversal information; the training reversal includes: the device line numbers of the device lines correspond to the physical line numbers of the physical lines from high to low.

[0084] It should be noted that due to the need to optimize the transmission efficiency of the physical line, there will be a training inversion between the physical line and the device line, that is, the physical line with a lower physical line number corresponds to the device line with a higher device line number. In an alternative implementation, the training inversion occurs during link training, that is, the order of the logical line numbers is inverted. Specifically, after the device lines are corresponded to the physical lines in ascending order of the device line numbers and the physical lines are corresponded to the logical lines in ascending order of the logical line numbers during link training, the corresponding relationship between the physical line number and the higher logical line number is inverted, so that the logical line number of the physical line with a lower physical line number is higher, thereby making the device line with a lower device line number correspond to the physical line with a higher logical line number. At the same time, since whether the training inversion occurs is determined during the link training process, the training inversion can be regarded as a link training result, which can be simply determined from the link training result information after the link training is completed.

[0085] Specifically, the training inversion is as Figure 5 shown. Taking the inserted device as x4 as an example, there is a training inversion between the physical line and the device line. Therefore, in the processor 4, the logical line number of the physical line with the physical line number of Lane0 is Lane3, that is, the physical line with the physical line number of Lane0 corresponds to and is connected to the device line with the device line number of Lane3, and the logical line number of the physical line with the physical line number of Lane1 is Lane2, and so on. The physical lines with the physical line numbers of Lane4, Lane5, Lane6, and Lane7 have no logical line numbers because they do not correspond to and are not connected to the device lines.

[0086] Furthermore, in an alternative implementation, there is both the training inversion and the forced inversion configured by the register 5 in the processor. Specifically, as Figure 6 shown. Taking the inserted device as x4 as an example, there are both the training inversion and the forced inversion between the physical line and the device line. Therefore, in the processor 4, after the physical line with the physical line number of Lane7 is inverted twice, the corresponding logical line number is Lane0, that is, the physical line with the physical line number of Lane7 corresponds to and is connected to the device line with the device line number of Lane0, and the logical line number of the physical line with the physical line number of Lane6 is Lane1 after being inverted twice, and so on. The physical lines with the physical line numbers of Lane0, Lane1, Lane2, and Lane3 have no logical line numbers because they do not correspond to and are not connected to the device lines. Please continue to refer to Figure 2 , the interface control method provided by the embodiment of the present application further includes step S3: determining the physical lines passing through the clock signal according to the inversion information, so that the physical lines passing through the clock signal cannot be turned off.

[0087] In this way, after the physical line passing through the clock signal cannot be turned off, when the physical line is subsequently turned off, the physical line passing through the clock signal is prevented from being turned off, ensuring that the physical line passing through the clock signal stably sends a read clock to the first-in first-out buffer.

[0088] Step S4: Detect whether the physical line transmits data, and turn off the physical lines that do not pass data.

[0089] Specifically, within the processor, the physical line can be turned off by making the port controller send a turnoff signal to the physical line. Therefore, in an alternative implementation, the detection in step S4 includes step S41: Detect whether the physical line transmits data, and send a turnoff signal to the physical lines that do not pass data.

[0090] Specifically, in an alternative implementation, a device detection structure for device detection determines whether the physical line transmits data. It should be noted that during the use of the device, due to reasons such as the signal quality, bandwidth requirements, and power consumption management of the physical line, in an alternative implementation, the port needs to re-perform link training. After re-performing link training, the number of physical lines will increase or decrease compared to before. Therefore, in an alternative implementation, device detection also needs to be performed again after re-link training, the device detection result is updated, and a turnoff signal is sent again to the physical lines that do not pass data according to the updated device detection result.

[0091] In this way, by determining the physical line passing through the clock signal according to the inversion information obtained from the mapping information and making the physical line passing through the clock signal unable to be turned off, when the physical lines that do not transmit data are subsequently turned off, the physical line passing through the clock signal will not be erroneously turned off, thereby reducing the power consumption of the interface on the premise of ensuring the stability of the read clock, and further reducing the power consumption of the processor.

[0092] Furthermore, since the inversion information includes training inversion information and forced inversion information, it is necessary to determine the physical line passing through the clock signal according to whether a forced inversion occurs, and further control the turnoff signal according to whether a training inversion occurs so that the physical line passing through the clock signal cannot be turned off. In an alternative implementation, as Figure 7 shown, step S3 includes: step S31: Detect whether there is forced inversion information. If there is forced inversion information, then execute step S311: Make the physical line with the highest physical line number be the physical line passing through the clock signal. Please continue to refer to Figure 4 , since only forced inversion information exists, the physical line with the highest physical line number is set as the physical line passing through the clock signal, that is, even ifFigure 4 The physical line with the physical line number Lane7 in the middle is the physical line that passes the clock signal. It should be noted that the physical line number mentioned in step S311 refers to the physical line number before the register configuration mentioned above, and does not include the inverted line number obtained by inverting the physical line number after the register configuration mentioned above.

[0093] If there is no such forced inversion information, then step S312 is executed: make the physical line with the lowest physical line number be the physical line that passes the clock signal. Please continue to refer to Figure 3 , such as Figure 3 shown, since there is no inversion, the physical line with the lowest physical line number is set as the physical line that passes the clock signal, that is, Figure 3 the physical line with the physical line number Lane0 in the middle is the physical line that passes the clock signal.

[0094] Furthermore, after determining the physical line that passes the clock, from Figure 3 and Figure 4 it can be found that when there is only forced inversion and no inversion, the logical line number of the physical line that passes the clock is the lowest logical line number, that is, the device line connected by the physical line that passes the clock is the device line with the lowest device line number, and the device line with the lowest device line number has the highest usage priority, so it will be closed last. Similarly, the physical line that passes the clock is also closed last. Therefore, only when the device on the port is disconnected, the physical line that passes the clock will be closed. Therefore, it is equivalent to ensuring that the physical line that passes the clock cannot be closed.

[0095] Furthermore, as Figure 5 and Figure 6 shown, Figure 5 there is no forced inversion in the processor 4 in the middle, and there is only training inversion. Therefore, the physical line with the physical line number Lane0 is the physical line that passes the clock; as Figure 6 shown, taking the inserted device as x4 as an example, there is both the training inversion and the forced inversion configured by the register 5 in the processor 4. At this time, still only according to whether there is forced inversion, it is determined that the physical line with the physical line number Lane7 is the physical line that passes the clock. Further from Figure 5 and Figure 6 it can be found that Figure 5 and Figure 6 the logical line number of the physical line that passes the clock in the middle is the highest logical line number, that is, the device line corresponding to and connected by the physical line that passes the clock is the device line with the highest device line number. Therefore, when sending a close signal to the physical line that has not passed data again according to the updated device detection result, the physical line that passes the clock is at risk of being closed.

[0096] Further, to ensure that the physical line of the clock cannot be turned off, before step S31, step S32 is further included: detecting whether there is training inversion information. If there is no such training inversion information, no other operations are required. If there is such training inversion information, step S321 is executed: masking the shutdown signal of the physical line corresponding to the device line with the largest device line number. It should be noted that when there is training inversion, the device line corresponding to and connected to the physical line of the clock is the device line with the highest device line number, that is, the physical line corresponding to the device line with the highest device line number is the physical line of the clock. Therefore, as long as the shutdown signal of the physical line corresponding to the device line with the largest device number is masked, it can be ensured that the physical line of the clock cannot receive the shutdown signal, and further ensured that the physical line of the clock cannot be turned off.

[0097] It should be noted that when the trace of the port on the motherboard where the processor is located is inverted or the slot connecting the port and the device is reversely soldered, in an optional implementation, instead of configuring forced inversion, the physical line with the physical line number of Lane0 can be normally made to correspond to and connect to the device line with the device number of Lane0. At this time, through the software in the processor, the physical line of the clock can be selected when the chip is started. Then execute step S32 and step S321.

[0098] This application also provides an interface control device, as Figure 8 shown, including:

[0099] A port configuration module 300, configured to configure one-to-one corresponding physical lines for the device lines of the port. Wherein the port includes at least two device lines. The number of the physical lines is at least two.

[0100] A mapping information acquisition module 400, configured to acquire the mapping information between the device line and the physical line, and determine the inversion information between the device line and the physical line according to the mapping information.

[0101] A clock line determination module 500, configured to determine the physical line passing through the clock signal according to the inversion information, and make the physical line passing through the clock signal unable to be turned off.

[0102] A line shutdown module 600, configured to detect whether the physical line transmits data, and shut down the physical line that does not pass data.

[0103] Further, in an optional implementation, as Figure 8The at least two device lines shown have device line numbers from low to high; the at least two physical lines have physical line numbers from low to high; the device line numbers of the at least two device lines from low to high correspond to the physical line numbers of the at least two physical lines from low to high.

[0104] Further, in an alternative implementation, the inversion information includes: forced inversion information, which indicates that there is a forced inversion between the device line and the physical line when there is such forced inversion information; the forced inversion includes: the physical line numbers of the physical lines corresponding from high to low with the device line numbers of the device lines from low to high.

[0105] Further, in an alternative implementation, as Figure 9 shown, the clock line determination module 400 includes:

[0106] A forced inversion information detection module 700, configured to detect whether there is forced inversion information;

[0107] A first line setting module 710, configured to, if there is forced inversion information, make the physical line with the highest physical line number the physical line passing the clock signal;

[0108] A second line setting module 720, configured to, if there is no such forced inversion information, make the physical line with the lowest physical line number the physical line passing the clock signal.

[0109] Further, in an alternative implementation, as Figure 8 shown, the line shutdown module 600 includes: a shutdown signal sending module 610, configured to detect whether the physical line transmits data and send a shutdown signal to the physical line that does not pass data.

[0110] Further, in an alternative implementation, as Figure 8 shown, the inversion information further includes: training inversion information, which indicates that there is a training inversion between the device line and the physical line when there is such training inversion information; the training inversion includes: the device line numbers of the device lines corresponding from high to low with the physical line numbers of the physical lines from low to high.

[0111] Further, in an alternative implementation, as Figure 9 shown, the clock line determination module 400 further includes:

[0112] A training inversion information detection module 800, configured to detect whether there is training inversion information.

[0113] The closing signal shielding module 810 is configured to shield the closing signal of the physical line corresponding to the device line with the largest device number if there is the training inversion information.

[0114] In this way, by determining the physical line passing through the clock signal according to the inversion information obtained from the mapping information and preventing the physical line passing through the clock signal from being closed, when the physical lines that do not transmit data are closed subsequently, the physical line passing through the clock signal will not be wrongly closed, so as to reduce the power consumption of the interface on the premise of ensuring the stability of the read clock, and further reduce the power consumption of the processor.

[0115] Furthermore, an embodiment of the present application further provides an interface system, which includes the interface control device as described above, and further includes a line mapping module for storing the correspondence between the device line and the physical line; at least one first-in first-out buffer for buffering the data transmitted from the device line to the physical line; and an inversion configuration module disposed in the port for implementing the inversion. It should be noted that different interface systems can be provided with different numbers of physical lines and first-in first-out buffers according to requirements. For example Figure 10As shown, taking an interface system with 16 physical lines as an example, the main board 1 includes a multi-port controller 2, PHY 3, a first port 10 to a fourth port 13 connecting to devices with device lines set, a line mapping module 40 for storing the correspondence between the device lines and the physical lines, a first first-in-first-out buffer 30 to a fourth first-in-first-out buffer 33 for caching data transmitted from the device lines to the physical lines, and a first physical line 200 to a sixteenth physical line 215. Specifically, in an optional implementation, the inversion configuration module includes: a forced inversion module for implementing forced inversion within the port according to the inversion information; a logical inversion module for implementing logical inversion within the port according to the inversion information; a register module for configuring inversion information for the forced inversion module; a training inversion module for configuring inversion information for the logical inversion module. It also includes a training control module 310 for performing link training between the port and the physical lines. The training control module 310 can send training inversion information to the training inversion module 330 according to the result of the link training. When the training inversion module 330 receives the training inversion information, the first port 10 to the fourth port 13 can achieve training inversion through the training inversion module 330. In addition, in an optional implementation, it further includes a register module 320 for storing forced inversion information and configuring forced inversion for the port according to the forced inversion information. Specifically, when the traces on the main board 1 are inverted or the slots are reversely soldered, the forced inversion information is stored in the register module 320. When the register module 320 stores the forced inversion information, the forced inversion module 340 within the first port 10 to the fourth port 13 is configured to enable the first port 10 to the fourth port 13 to achieve forced inversion through the forced inversion module 340. Further, data is sent out by the sending module 150 within the first port 10 to the fourth port 13, passes through the training inversion module 330 and the forced inversion module 340, then passes through the line mapping module 40, and enters the PHY 3; while the data coming from the PHY 3, after passing through the line mapping module 40, then passes through the forced inversion module 340 and the training inversion module 330, and is received by the receiving module 360 within the first port 10 to the fourth port 13.Further, it further includes an interface control device 900 provided in an embodiment of the present application. The above port configuration module 300, mapping information acquisition module 400, clock line determination module 500, and line closing module 600 are all provided in the interface control device 900. After the interface control device 900 configures a corresponding physical line for each device line of the port, the register module 320 and the line mapping module 40 acquire mapping information, and then determine the physical line passing through the clock signal according to the mapping information. It should control the corresponding physical line to send a clock signal to its corresponding first-in-first-out buffer. Finally, it detects whether the physical line transmits data and closes the physical line that does not pass data. It should be noted that in an optional implementation, the above training inversion information detection module 800 and the shutdown signal shielding module 710 may also be provided in the training inversion module 330.

[0116] An embodiment of the present application further provides a computer device, including the above interface system.

[0117] It should be noted that in the above optional implementation, the number of physical lines in the PHY in the chip, the number and type of ports on the chip, and the number of device lines in the device, etc., need to be selected according to the actual needs of the chip. The interface control method, device, system, and computer device provided in the embodiments of the present application are not limited.

[0118] Although the embodiments of the present application are disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. An interface control method, characterized in that, Including: Configuring corresponding physical lines for the device lines of the port, where the port includes at least two device lines; The number of the physical lines is at least two; Obtaining mapping information between the device lines and the physical lines, and determining reverse information between the device lines and the physical lines according to the mapping information; The reverse information is used to map the reverse between the device lines and the physical lines; Determining the physical lines passing the clock signal according to the reverse information, and making the physical lines passing the clock signal unable to be turned off; Detecting whether the physical lines transmit data, and turning off the physical lines that do not pass data.

2. An interface control method according to claim 1, wherein The at least two device lines have device line numbers from low to high; The at least two physical lines have physical line numbers from low to high; The mapping information includes the actual corresponding relationship between the device line numbers of the device lines and the physical line numbers of the physical lines and the reverse information.

3. The interface control method according to claim 2, wherein The reverse information includes: forced reverse information, indicating that there is a forced reverse between the device lines and the physical lines when the forced reverse information exists; The forced reverse includes: the correspondence of the physical line numbers of the physical lines from high to low with the device line numbers of the device lines from low to high.

4. The interface control method according to claim 3, wherein The step of determining the physical lines passing the clock signal according to the reverse information, and making the physical lines passing the clock signal unable to be turned off includes: Detecting whether there is forced reverse information; If there is forced reverse information, making the physical line with the highest physical line number be the physical line passing the clock signal; If there is no such forced reverse information, making the physical line with the lowest physical line number be the physical line passing the clock signal.

5. The interface control method according to claim 4, wherein The step of detecting whether the physical lines transmit data and turning off the physical lines that do not pass data includes: Detecting whether the physical lines transmit data, and sending a turn-off signal to the physical lines that do not pass data.

6. The interface control method according to claim 5, wherein The reverse information further includes: training reverse information, indicating that there is a training reverse between the device lines and the physical lines when the training reverse information exists; The training reverse includes: the correspondence of the device line numbers of the device lines from high to low with the physical line numbers of the physical lines from low to high.

7. The interface control method according to claim 6, wherein Before the step of detecting whether there is forced reverse information, it further includes: Detecting whether there is training reverse information; If there is the training reverse information, shielding the turn-off signal of the physical line corresponding to the device line with the largest device line number.

8. An interface control device, characterized in that, Including: A port configuration module, configured to configure corresponding physical lines for the device lines of the port, where the port includes at least two device lines; The number of the physical lines is at least two; A mapping information acquisition module, configured to obtain mapping information between the device lines and the physical lines, and determine reverse information between the device lines and the physical lines according to the mapping information; The reverse information is used to map the reverse between the device lines and the physical lines; A clock line determination module, configured to determine the physical lines passing the clock signal according to the reverse information, and making the physical lines passing the clock signal unable to be turned off; A line closing module, configured to detect whether data is being transmitted on the physical line and close the physical line that fails to pass the data.

9. An interface control device according to claim 8, wherein the at least two device lines have device line numbers that increase from low to high; the at least two physical lines have physical line numbers that increase from low to high; the mapping information includes the actual correspondence between the device line numbers of the device lines and the physical line numbers of the physical lines, as well as inversion information.

10. An interface control device according to claim 9, characterized in that, The inversion information includes: forced inversion information, which indicates that there is a forced inversion between the device line and the physical line when the forced inversion information exists; The forced inversion includes: the correspondence where the physical line number of the physical line decreases from high to low and the device line number of the device line increases from low to high.

11. The interface control device according to claim 10, characterized in that The clock line determination module, configured to determine the physical line through which the clock signal passes according to the inversion information, so that the physical line through which the clock signal passes cannot be closed, includes: A forced inversion information detection module, configured to detect whether forced inversion information exists; A first line setting module, configured to, if forced inversion information exists, set the physical line with the highest physical line number as the physical line through which the clock signal passes; A second line setting module, configured to, if the forced inversion information does not exist, set the physical line with the lowest physical line number as the physical line through which the clock signal passes.

12. An interface control device according to claim 11, characterized in that, The line closing module, configured to detect whether data is being transmitted on the physical line and close the physical line that fails to pass the data, includes: A closing signal sending module, configured to detect whether data is being transmitted on the physical line and send a closing signal to the physical line that fails to pass the data.

13. An interface control device according to claim 12, characterized in that, The inversion information further includes: training inversion information, which indicates that there is a training inversion between the device line and the physical line when the training inversion information exists; The training inversion includes: the correspondence where the device line number of the device line decreases from high to low and the physical line number of the physical line increases from low to high.

14. An interface control device according to claim 13, characterized in that, The line determination module, configured to determine the physical line through which the clock signal passes according to the inversion information, so that the physical line through which the clock signal passes cannot be closed, further includes: A training inversion information detection module, configured to detect whether training inversion information exists; A closing signal shielding module, configured to, if the training inversion information exists, shield the closing signal of the physical line corresponding to the device line with the largest device line number.

15. An interface system, comprising the interface control device according to any one of claims 8-14, characterized in that, Further includes: A line mapping module, configured to store the correspondence between the device line and the physical line; At least one first-in, first-out buffer, configured to buffer the data transmitted from the device line to the physical line; An inversion configuration module, disposed within the port, configured to implement the inversion.

16. An interface system according to claim 15, characterized in that, The inversion configuration module includes: A forced inversion module, configured to implement forced inversion within the port according to the inversion information; A logical inversion module, configured to implement logical inversion within the port according to the inversion information; A register module, configured to configure inversion information for the forced inversion module; A training inversion module, configured to configure inversion information for the logical inversion module.

17. A computer device, characterized in that, Includes an interface system according to any one of claims 15 - 16.

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