Test device and test method thereof

Abstract

The present application provides a test apparatus and a test method thereof, the test method comprising: generating an error correction code according to base data; dividing the base data into a plurality of base data sections; generating a plurality of candidate test data according to the base data, wherein each of the candidate test data has a plurality of test data sections, and each of the test data sections corresponds to each of the base data sections; and performing a plurality of test schemes. Each of the test schemes comprises: generating a plurality of write test data according to the plurality of candidate test data, and continuously writing the plurality of write test data and the error correction code into a device under test; reading a plurality of mode register values and a plurality of readout data of the device under test from the device under test; and generating a test result according to the plurality of mode register values and the readout data.

Description

Technical Field

[0001] The present invention generally relates to a testing apparatus and a testing method thereof, and more specifically, to a testing method for testing the link error correction code (ECC) functionality. Background Technology

[0002] With the increasing number of new branded applications in the era of 5G and AI that have critical response time and low power consumption requirements, low-power, high-speed devices are essential for these applications, such as Low Power Double Data Rate 5 (LPDDR5) memory devices. These devices offer data rates up to 6400 Mbps. However, various noise interferences can compromise the transmission and reception links between the controller and the LPDDR5 memory device. Therefore, LPDDR5 memory devices define error checking and correction (ECC) functions for link error checking and correction (ECC) for data exchange between the controller and the memory device to provide robust communication. Summary of the Invention

[0003] The present invention provides a testing apparatus and a testing method thereof, and the testing method is applied to the link error checking and correction (ECC) function testing of low power dual data rate 5 (LPDDR5) memory or other memory devices.

[0004] The testing method includes: generating error correction codes based on basic data; dividing the basic data into multiple basic data segments; generating multiple candidate test data based on the basic data, wherein each candidate test data has multiple test data segments, and each test data segment corresponds to each of the basic data segments; and executing multiple test schemes. Each test scheme includes: generating multiple write test data based on the multiple candidate test data, and continuously writing the multiple write test data and error correction codes into the device under test; reading multiple mode register values ​​and multiple read data from the device under test; and generating test results based on the multiple mode register values ​​and read data.

[0005] The test setup is configured to test the Link Error Correction Code (ECC) functionality. The test setup includes a controller. The controller is coupled to the device under test (DUT) and configured to: generate error correction codes based on basic data; divide the basic data into multiple basic data segments; generate multiple candidate test data based on the basic data, each of the candidate test data having multiple test data segments, and each of the test data segments corresponding to each of the basic data segments; and execute multiple test schemes. The controller executes each of the multiple test schemes by: generating multiple write test data based on the multiple candidate test data, and sequentially writing the multiple write test data and error correction codes into the DUT; reading multiple mode register values ​​and multiple read data from the DUT; and generating test results based on the multiple mode register values ​​and read data.

[0006] In summary, the test apparatus generates multiple candidate test data segments with multiple test data sections. The test apparatus also sets each test data segment to have 0, one, or two error bits based on the corresponding base data segment. During each of the various test schemes, multiple write test data segments can be generated, and the test apparatus writes the write test data and error correction codes into the device under test. Test results regarding the link ECC functionality can be obtained by reading multiple mode register values ​​and multiple read data segments from the device under test.

[0007] To make the foregoing more understandable, several embodiments of the accompanying drawings are described in detail below. Attached Figure Description

[0008] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and form a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the implementation methods, serve to explain the principles of the present disclosure.

[0009] Figure 1 A flowchart illustrating a test method according to an embodiment of the present disclosure is provided.

[0010] Figure 2 Showing according to this disclosure Figure 1 A flowchart of each of the various test schemes in the embodiments;

[0011] Figure 3 A schematic diagram illustrating multiple candidate test data according to embodiments of the present disclosure is shown.

[0012] Figure 4 A flowchart illustrating a test scheme according to another embodiment of this disclosure is shown;

[0013] Figure 5 Showing according to this disclosure Figure 4A schematic diagram of the mode register reading state list of an embodiment;

[0014] Figure 6 A test apparatus according to an embodiment of the present disclosure is shown.

[0015] Explanation of icon numbers

[0016] 600: Test apparatus;

[0017] 601: Device under test;

[0018] 611: Controller;

[0019] 612: Storage device;

[0020] S110, S120, S130, S140, S210, S220, S230: Steps. Detailed Implementation

[0021] Reference will now be made in detail to the presently preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and embodiments to refer to the same or similar parts.

[0022] Please refer to Figure 1 This diagram illustrates a flowchart of a test method according to an embodiment of the present disclosure. The test method is configured to test the link ECC functionality of a device under test (DUT). The DUT may be a low-power dual data rate 5 (LPDDR5) memory or any other type of memory device. In step S110, an error correction code (ECC) is generated based on basic data. In this embodiment, the ECC can be generated by encoding the basic data using an ECC encoder based on an ECC algorithm with one error bit correction capability. In step S120, the basic data may be divided into multiple basic data segments. In this embodiment, the basic data may be divided into four data segments. For a DUT that is a dynamic random access memory (DRAM), the four data segments include first basic data information, second basic data information, first basic data mask inversion information, and second basic data mask inversion information. In some embodiments, the first basic data information may have 8 bits, the second basic data information may also have 8 bits, the first basic data mask inversion information may have 8 bits, and the second basic data mask inversion information may also have 8 bits.

[0023] In step S130, multiple candidate test data can be generated based on the basic data. In this embodiment, each of the candidate test data has multiple test data segments, and each of the test data segments corresponds to each of the basic data segments. Specifically, each of the multiple test data segments can be a valid test data segment, a single bit error segment, or a double bit error data segment. If the first test data segment is the same as the first basic data segment, then the first test data segment is taken as an instance where the first test data segment corresponds to the first basic data segment. If the first test data segment is a valid data segment, then the first test data segment is the same as the first basic data segment; if the first test data segment is a single bit error data segment, then compared with the first basic data segment, the first test data segment has a single bit error; if the first test data segment is a double bit error data segment, then compared with the first basic data segment, the first test data segment has a double bit error.

[0024] Please refer to Figure 3 The diagram illustrates a plurality of candidate test data according to an embodiment of the present disclosure. In this embodiment, 19 candidate test data may be generated, and each of the first test data segments may be marked as “V” if each of the first test data segments is a valid data segment; each of the first test data segments may be marked as “IS” if each of the first test data segments is a single-bit error data segment (invalid); and each of the first test data segments may be marked as “DBE” if each of the first test data segments is a double-bit error data segment (invalid).

[0025] For example, in the first candidate test data, all test data segments are valid data segments, and the first test data segment DQ[7:0] of the first candidate test data can be in hexadecimal form as 5A, A5, 69, 96, F0, 0F, AA, 55, FF, 00, 33, CC, 7E, E7, 8F and 70; the second test data segment DQ[15:8] of the first candidate test data can be in hexadecimal form as 5A, A5, 69, 96, F0, 0F, AA, 55, FF, 00, 33, CC, 7E, E7, 8F and 70; the third test data segment DM0 of the first candidate test data can be in binary form as 1011010000111010; and the fourth test data segment DM1 of the first candidate test data can be in binary form as 1011010000111010. In the first candidate test data, the first byte of the first test data segment DQ[7:0] is complementary to the second byte of the first test data segment DQ[7:0]; the third byte of the first test data segment DQ[7:0] is complementary to the fourth byte of the first test data segment DQ[7:0]; the fifth byte of the first test data segment DQ[7:0] is complementary to the sixth byte of the first test data segment DQ[7:0]; and the seventh byte of the first test data segment DQ[7:0] is complementary to the eighth byte of the first test data segment DQ[7:0]. Furthermore, in the first candidate test data, the first byte of the second test data segment DQ[15:8] is complementary to the second byte of the second test data segment DQ[15:8]; the third byte of the second test data segment DQ[15:8] is complementary to the fourth byte of the second test data segment DQ[15:8]; the fifth byte of the second test data segment DQ[15:8] is complementary to the sixth byte of the second test data segment DQ[15:8]; and the seventh byte of the second test data segment DQ[15:8] is complementary to the eighth byte of the second test data segment DQ[15:8].

[0026] Since all test data segments of candidate test data No. 1 are valid data segments, candidate test data No. 1 is the same as the basic data.

[0027] The second candidate test data may have four test data segments labeled IS, V, V, and IS respectively. That is, the first and fourth test data segments of the second candidate test data are unit error data segments, and the second and third test data segments of the second candidate test data are valid data segments. In this embodiment, the first test data segment DQ[7:0] of the second candidate test data may be in hexadecimal form 5A, A5, 69, 96, F0, 0F, A2, 55, FF, 00, 33, CC, 7E, E7, 8F, and 70, and the fourth test data segment DM1 of the second candidate test data may be in binary form 1011010000111000.

[0028] On the other hand, candidate test data No. 3 may have four test data segments labeled IS, IS, IS, IS; candidate test data No. 4 may have four test data segments labeled ID, V, ID, V; candidate test data No. 5 may have four test data segments labeled V, ID, V, ID; candidate test data No. 6 may have four test data segments labeled ID, ID, ID, ID; candidate test data No. 7 may have four test data segments labeled V, IS, IS, V; candidate test data No. 8 may have four test data segments labeled IS, ID, IS, ID; candidate test data No. 9 may have four test data segments labeled ID, IS, ID, IS; candidate test data No. 10 may have four test data segments labeled IS, V, V, V.

[0029] In addition, candidate test data No. 11 may have four test data segments labeled V, V, IS, V; candidate test data No. 12 may have four test data segments labeled V, IS, V, V; candidate test data No. 13 may have four test data segments labeled V, V, V, IS; candidate test data No. 14 may have four test data segments labeled V, ID, V, V; candidate test data No. 15 may have four test data segments labeled V, V, V, ID; candidate test data No. 16 may have four test data segments labeled ID, V, V, V; candidate test data No. 17 may have four test data segments labeled V, V, ID, V; candidate test data No. 18 may have four test data segments labeled IS, V, IS, IS; and candidate test data No. 19 may have four test data segments labeled IS, IS, ID, IS.

[0030] The first test data segment DQ[7:0], the second test data segment DQ[15:8], the third test data segment DMI0, and the fourth test data segment DMI1 of candidate test data from No. 3 to No. 19 can be set as follows: Figure 3 The example shown is illustrated here. It should be noted that engineers can also set the contents of the first test data segment DQ[7:0], the second test data segment DQ[15:8], the third test data segment DMI0, the fourth test data segment DMI1, and the fourth test data segment DMI1 according to actual needs. Figure 3 The examples shown are merely exemplary embodiments and are not intended to limit the scope of this disclosure.

[0031] It should be noted here that engineers can set the number of candidate test data to be greater than or less than the actual needs. Figure 3 The candidate test data shown. Figure 3 The candidate test data No. 1 to No. 19 in the above are merely exemplary embodiments and are not intended to limit the scope of this disclosure.

[0032] Please refer to this again. Figure 1 Following step S130, in step S140, various test schemes can be performed on the device under test. For details, please refer to [link / reference needed]. Figure 2 This shows the following according to the present disclosure Figure 1 The flowcharts illustrate various test schemes in the embodiments. In step S210, multiple write test data are generated based on multiple candidate test data, and the multiple write test data, along with ECC, are continuously written to the device under test. Next, in step S220, multiple mode register values ​​are read from the device under test, and multiple read data are also read from the device under test. In step S230, the test result can be obtained based on the multiple mode register values ​​and the multiple read data.

[0033] For details, please refer to Figure 4 and Figure 5 ,in Figure 4 A flowchart illustrating a test scheme according to another embodiment of this disclosure is provided, and Figure 5 Showing according to this disclosure Figure 4A schematic diagram of the mode register read status list of an embodiment. In this embodiment, the device under test may have registers MR43, MR44, and MR45. Register MR43 has multiple bits OP1[7:0] to form a first mode register value indicating a double-bit error flag, a unit error rule, and the number of unit errors. Specifically, bit OP1[7] is a double-bit error flag, bit OP1[6] indicates a unit error rule, and bits OP[5:0] indicate the number of unit errors during ECC operation. In this embodiment, bit OP1[6] may be user-defined. Register MR44 has multiple bits OP2[7:0] to form a second mode register value indicating a checksum value of the most recent unit error from ECC operation. Register MR45 has multiple bits OP3[7:0] to form a third mode register value indicating a checksum value of test data information, an error byte channel, and a checksum value of data mask inversion information of the most recent unit error from ECC operation. In detail, bit OP3[7] indicates the checksum of the test data information, bit OP3[6] indicates the error byte channel, and bits OP3[5:0] indicate the checksum of the data mask inversion information of the ECC operation.

[0034] refer to Figure 4 In test scheme (1), the device under test (DUT) is powered on and initialized, and the mode register of the DUT can be read. At this time, all bits OP1[7:0], OP2[7:0], and OP3[7:0] of registers MR43, MR44, and MR45 are logic 0, and the value of register A can be obtained. In test scheme (2), three valid write test data WR1 to WR3 have been generated as candidate test data No. 1, and these three write test data are written to the DUT consecutively. At this time, registers MR43, MR44, and MR45 are read, and the value of register A can be obtained. In addition, by reading read data RD1 to RD3 from the DUT, the read data will remain as it was initially (the same as candidate test data No. 1) because no correction is performed since all write test data are valid.

[0035] In test scheme (3), three write test data WR1 to write test data WR3 have been generated as candidate test data No. 1, No. 2 and No. 1 respectively, and the three write test data are written to the device under test continuously. At this time, registers MR43, MR44 and MR45 are read, and the value of register B can be obtained. Since no double bit error occurred, bit OP1[7] of register MR43 should be logic 0. When bit OP1[6] is logic 0, bits [5:0] of register MR43 are in binary form logic 000001; and when bit OP1[6] is logic 1, bits [5:0] of register MR43 are in binary form logic 000010. Bits OP2[7:0] of register MR44 are logic 0; when bit OP1[6] is logic 0, bits [5:0] of register MR43 are logic 000001 in binary form; and when bit OP1[6] is logic 1, bits [5:0] of register MR43 are logic 000010 in binary form. Since there is a unit error in the written test data WR2, bits OP2[7:0] record the checksum value corresponding to the second first test data segment DQ[7:0] of the written test data WR2, and bits OP3[7] and OP3[5:0] record the checksum value corresponding to the second first test data inversion segment DMI0 in the written test data WR2. Furthermore, bit OP3[6] is logic 0 because, in the case of a unit error, only errors from the last byte will be stored.

[0036] Furthermore, by reading read data RD1 to RD3 from the device under test, read data RD1 to RD3 should respectively be candidate test data number 1, candidate test data number 1, and candidate test data number 1. This is because the unit error written to test data WR2 has been corrected via ECC operation. In other words, by checking the register values ​​and read data RD1 to RD3, the link ECC function via ECC operation can be tested, and the test results can be obtained.

[0037] It should be noted here that after reading the values ​​of registers MR43, MR44, and MR45, the values ​​of registers MR43, MR44, and MR45 are cleared. Therefore, if registers MR43, MR44, and MR45 are read again, the value of register A can be obtained.

[0038] In test scheme (4), four write test data WR1 to write test data WR4 have been generated as candidate test data No. 3, No. 4, No. 5 and No. 6 respectively, and the four write test data are written to the device under test continuously. At this time, registers MR43, MR44 and MR45 are read, and the value of register No. C can be obtained. Due to a double bit error, bit OP1[7] of register MR43 should be logic 1. When bit OP1[6] is logic 0, bits [5:0] of register MR43 are logic 000001 in binary form; and when bit OP1[6] is logic 1, bits [5:0] of register MR43 are logic 000100 in binary form. Because a unit error exists in the written test data WR1, bits OP2[7:0] of register MR44 record the checksum value corresponding to the third first test data segment DQ[7:0] in the written test data WR2, and bits OP3[7] and OP3[5:0] record the checksum value corresponding to the third first test data inversion segment DMI0 in the written test data WR1. Furthermore, bit OP3[6] is logic 0 because, in the event of a unit error, only errors from the last byte will be stored.

[0039] Furthermore, by reading read data RD1 to read data RD4 from the device under test, since the unit error in the written test data WR1 has been corrected by ECC operation, and the double error in the written test data WR2 to written test data WR4 has not been corrected by ECC operation, the read data RD1 to read data RD3 should be candidate test data No. 1, candidate test data No. 4, candidate test data No. 5 and candidate test data No. 6, respectively.

[0040] If registers MR43, MR44, and MR45 are read again, the value of register A can be obtained.

[0041] In test scheme (5), two write test data WR1 and write test data WR2 have been generated as candidate test data No. 3 and candidate test data No. 8, respectively, and the two write test data are continuously written into the device under test. At this time, registers MR43, MR44 and MR45 are read, and the value of register No. D can be obtained. Due to a double bit error, bit OP1[7] of register MR43 should be logic 1. When bit OP1[6] is logic 0, bits [5:0] of register MR43 are logic 000010 in binary form; and when bit OP1[6] is logic 1, bits [5:0] of register MR43 are logic 000110 in binary form. Bits OP2[7:0] of register MR44 record the checksum value corresponding to the 8th first test data segment DQ[7:0] written to test data WR2, and bits OP3[7] and OP3[5:0] record the checksum value corresponding to the 8th first test data inversion segment DMI0 written to test data WR2. In addition, bit OP3[6] is logic 0.

[0042] Furthermore, by reading readout data RD1 and readout data RD2 from the device under test, readout data RD1 and readout data RD2 should be candidate test data No. 1 and candidate test data No. 4, respectively, because the unit error of written test data WR1 and written test data WR2 has been corrected by ECC operation.

[0043] If registers MR43, MR44, and MR45 are read again, the value of register A can be obtained.

[0044] In test scheme (6), two write test data WR1 and write test data WR2 have been generated as candidate test data No. 3 and candidate test data No. 9, respectively, and the two write test data are continuously written into the device under test. At this time, registers MR43, MR44 and MR45 are read, and the value of register E can be obtained. Bit OP1[7] of register MR43 should be logic 1. When bit OP1[6] is logic 0, bits [5:0] of register MR43 are logic 000010 in binary form; and when bit OP1[6] is logic 1, bits [5:0] of register MR43 are logic 000110 in binary form. Bits OP2[7:0] of register MR44 record the checksum value corresponding to the 9th second test data segment DQ[15:8] written to test data WR2, and bits OP3[7] and OP3[5:0] record the checksum value corresponding to the 9th second test data inversion segment DMI1 written to test data WR2. In addition, bit OP3[6] is logic 1.

[0045] Furthermore, by reading readout data RD1 and readout data RD2 from the device under test, readout data RD1 and readout data RD2 should be candidate test data No. 1 and candidate test data No. 4, respectively, because the unit error of written test data WR1 and written test data WR2 has been corrected by ECC operation.

[0046] If registers MR43, MR44, and MR45 are read again, the value of register A can be obtained.

[0047] In test scheme (7), two write test data WR1 and write test data WR2 have been generated as candidate test data No. 2 and candidate test data No. 7, respectively, and the two write test data are continuously written into the device under test. At this time, registers MR43, MR44 and MR45 are read, and the value of register No. F can be obtained. Bit OP1[7] of register MR43 should be logic 0. When bit OP1[6] is logic 0, bits [5:0] of register MR43 are logic 000010 in binary form; and when bit OP1[6] is logic 1, bits [5:0] of register MR43 are logic 000110 in binary form. Bits OP2[7:0] of register MR44 record the checksum value corresponding to the 7th first test data segment DQ[7:0] written to test data WR2, and bits OP3[7] and OP3[5:0] record the checksum value corresponding to the 7th first test data inversion segment DMI0 written to test data WR2. In addition, bit OP3[6] is logic 0.

[0048] Furthermore, by reading readout data RD1 and readout data RD2 from the device under test, readout data RD1 and readout data RD2 should be candidate test data No. 1 and candidate test data No. 4, respectively, because the unit error of written test data WR1 and written test data WR2 has been corrected by ECC operation.

[0049] If registers MR43, MR44, and MR45 are read again, the value of register A can be obtained.

[0050] In test scheme (8), two write test data WR1 and write test data WR2 have been generated as candidate test data No. 2 and candidate test data No. 5, respectively, and the two write test data are continuously written into the device under test. At this time, registers MR43, MR44 and MR45 are read, and the value of register G can be obtained. Due to a double bit error, bit OP1[7] of register MR43 should be logic 1. When bit OP1[6] is logic 0, bits [5:0] of register MR43 are logic 000001 in binary form; and when bit OP1[6] is logic 1, bits [5:0] of register MR43 are logic 000010 in binary form. Bits OP2[7:0] of register MR44 record the checksum value corresponding to the second first test data segment DQ[7:0] written to test data WR1, and bits OP3[7] and OP3[5:0] record the checksum value corresponding to the second first test data inversion segment DMI0 written to test data WR1. In addition, bit OP3[6] is logic 0.

[0051] Furthermore, by reading read data RD1 and read data RD2 from the device under test, read data RD1 and read data RD2 should be candidate test data No. 1 and candidate test data No. 1, respectively, because the unit error of written test data WR1 and written test data WR2 has been corrected by ECC operation.

[0052] If registers MR43, MR44, and MR45 are read again, the value of register A can be obtained.

[0053] In test scheme (9), two write test data WR1 and write test data WR2 have been generated as candidate test data No. 3 and candidate test data No. 10, respectively, and the two write test data are continuously written into the device under test. At this time, registers MR43, MR44 and MR45 are read, and the value of register No. H can be obtained. Bit OP1[7] of register MR43 should be logic 0. When bit OP1[6] is logic 0, bits [5:0] of register MR43 are logic 000010 in binary form; and when bit OP1[6] is logic 1, bits [5:0] of register MR43 are logic 000101 in binary form. Bits OP2[7:0] of register MR44 record the checksum value corresponding to the 10th first test data segment DQ[7:0] written to test data WR2, and bits OP3[7] and OP3[5:0] record the checksum value corresponding to the 3rd first test data inversion segment DMI0 written to test data WR1. In addition, bit OP3[6] is logic 0.

[0054] Furthermore, by reading read data RD1 and read data RD2 from the device under test, read data RD1 and read data RD2 should be candidate test data No. 1 and candidate test data No. 1, respectively, because the unit error of written test data WR1 and written test data WR2 has been corrected by ECC operation.

[0055] If registers MR43, MR44, and MR45 are read again, the value of register A can be obtained.

[0056] In test scheme (10), two write test data WR1 and write test data WR2 have been generated as candidate test data No. 3 and candidate test data No. 11, respectively, and the two write test data are continuously written into the device under test. At this time, registers MR43, MR44 and MR45 are read, and the value of register No. I can be obtained. Bit OP1[7] of register MR43 should be logic 0. When bit OP1[6] is logic 0, bits [5:0] of register MR43 are logic 000010 in binary form; and when bit OP1[6] is logic 1, bits [5:0] of register MR43 are logic 000101 in binary form. Bits OP2[7:0] of register MR44 record the checksum value corresponding to the third first test data segment DQ[7:0] written to test data WR1, and bits OP3[7] and OP3[5:0] record the checksum value corresponding to the eleventh first test data inversion segment DMI0 written to test data WR2. In addition, bit OP3[6] is logic 0.

[0057] Furthermore, by reading read data RD1 and read data RD2 from the device under test, read data RD1 and read data RD2 should be candidate test data No. 1 and candidate test data No. 1, respectively, because the unit error of written test data WR1 and written test data WR2 has been corrected by ECC operation.

[0058] If registers MR43, MR44, and MR45 are read again, the value of register A can be obtained.

[0059] In test scheme (11), two write test data WR1 and write test data WR2 have been generated as candidate test data No. 3 and candidate test data No. 12, respectively, and the two write test data are continuously written into the device under test. At this time, registers MR43, MR44 and MR45 are read, and the value of register No. J can be obtained. Bit OP1[7] of register MR43 should be logic 0. When bit OP1[6] is logic 0, bits [5:0] of register MR43 are logic 000010 in binary form; and when bit OP1[6] is logic 1, bits [5:0] of register MR43 are logic 000101 in binary form. Bits OP2[7:0] of register MR44 record the checksum value corresponding to the 12th second test data segment DQ[15:8] written to test data WR2, and bits OP3[7] and OP3[5:0] record the checksum value corresponding to the 3rd first test data inversion segment DMI0 written to test data WR1. In addition, bit OP3[6] is logic 1.

[0060] Furthermore, by reading read data RD1 and read data RD2 from the device under test, read data RD1 and read data RD2 should be candidate test data No. 1 and candidate test data No. 1, respectively, because the unit error of written test data WR1 and written test data WR2 has been corrected by ECC operation.

[0061] If registers MR43, MR44, and MR45 are read again, the value of register A can be obtained.

[0062] In test scheme (12), two write test data WR1 and write test data WR2 have been generated as candidate test data No. 3 and candidate test data No. 13, respectively, and the two write test data are continuously written into the device under test. At this time, registers MR43, MR44 and MR45 are read, and the value of register No. K can be obtained. Bit OP1[7] of register MR43 should be logic 0. When bit OP1[6] is logic 0, bits [5:0] of register MR43 are logic 000010 in binary form; and when bit OP1[6] is logic 1, bits [5:0] of register MR43 are logic 000101 in binary form. Bits OP2[7:0] of register MR44 record the checksum value corresponding to the third first test data segment DQ[7:0] written to test data WR1, and bits OP3[7] and OP3[5:0] record the checksum value corresponding to the thirteenth second test data inversion segment DMI1 written to test data WR2. In addition, bit OP3[6] is logic 1.

[0063] Furthermore, by reading read data RD1 and read data RD2 from the device under test, read data RD1 and read data RD2 should be candidate test data No. 1 and candidate test data No. 1, respectively, because the unit error of written test data WR1 and written test data WR2 has been corrected by ECC operation.

[0064] If registers MR43, MR44, and MR45 are read again, the value of register A can be obtained.

[0065] In test scheme (13), two write test data WR1 and write test data WR2 have been generated as candidate test data No. 3 and candidate test data No. 14, respectively, and the two write test data are continuously written into the device under test. At this time, registers MR43, MR44 and MR45 are read, and the value of register No. L can be obtained. Bit OP1[7] of register MR43 should be logic 1. When bit OP1[6] is logic 0, bits [5:0] of register MR43 are logic 000001 in binary form; and when bit OP1[6] is logic 1, bits [5:0] of register MR43 are logic 000100 in binary form. Bits OP2[7:0] of register MR44 record the checksum value corresponding to the third first test data segment DQ[7:0] written to test data WR2, and bits OP3[7] and OP3[5:0] record the checksum value corresponding to the third first test data inversion segment DMI0 written to test data WR1. In addition, bit OP3[6] is logic 0.

[0066] Furthermore, by reading readout data RD1 and readout data RD2 from the device under test, readout data RD1 and readout data RD2 should be candidate test data No. 1 and candidate test data No. 14, respectively, because the unit error of written test data WR1 and written test data WR2 has been corrected by ECC operation.

[0067] If registers MR43, MR44, and MR45 are read again, the value of register A can be obtained.

[0068] In test scheme (14), two write test data WR1 and write test data WR2 have been generated as candidate test data No. 3 and candidate test data No. 15, respectively, and the two write test data are continuously written into the device under test. At this time, registers MR43, MR44 and MR45 are read, and the value of register No. L can be obtained. Bit OP1[7] of register MR43 should be logic 1. When bit OP1[6] is logic 0, bits [5:0] of register MR43 are logic 000001 in binary form; and when bit OP1[6] is logic 1, bits [5:0] of register MR43 are logic 000100 in binary form. Bits OP2[7:0] of register MR44 record the checksum value corresponding to the third first test data segment DQ[7:0] written to test data WR2, and bits OP3[7] and OP3[5:0] record the checksum value corresponding to the third first test data inversion segment DMI0 written to test data WR1. In addition, bit OP3[6] is logic 0.

[0069] Furthermore, by reading readout data RD1 and readout data RD2 from the device under test, readout data RD1 and readout data RD2 should be candidate test data No. 1 and candidate test data No. 15, respectively, because the unit error of written test data WR1 and written test data WR2 has been corrected by ECC operation.

[0070] If registers MR43, MR44, and MR45 are read again, the value of register A can be obtained.

[0071] In test scheme (15), two write test data WR1 and write test data WR2 have been generated as candidate test data No. 3 and candidate test data No. 16, respectively, and the two write test data are continuously written into the device under test. At this time, registers MR43, MR44 and MR45 are read, and the value of register No. L can be obtained. Bit OP1[7] of register MR43 should be logic 1. When bit OP1[6] is logic 0, bits [5:0] of register MR43 are logic 000001 in binary form; and when bit OP1[6] is logic 1, bits [5:0] of register MR43 are logic 000100 in binary form. Bits OP2[7:0] of register MR44 record the checksum value corresponding to the third first test data segment DQ[7:0] written to test data WR2, and bits OP3[7] and OP3[5:0] record the checksum value corresponding to the third first test data inversion segment DMI0 written to test data WR1. In addition, bit OP3[6] is logic 0.

[0072] Furthermore, by reading readout data RD1 and readout data RD2 from the device under test, readout data RD1 and readout data RD2 should be candidate test data No. 1 and candidate test data No. 16, respectively, because the unit error of written test data WR1 and written test data WR2 has been corrected by ECC operation.

[0073] If registers MR43, MR44, and MR45 are read again, the value of register A can be obtained.

[0074] In test scheme (16), two write test data WR1 and write test data WR2 have been generated as candidate test data No. 3 and candidate test data No. 17, respectively, and the two write test data are continuously written into the device under test. At this time, registers MR43, MR44 and MR45 are read, and the value of register No. L can be obtained. Bit OP1[7] of register MR43 should be logic 1. When bit OP1[6] is logic 0, bits [5:0] of register MR43 are logic 000001 in binary form; and when bit OP1[6] is logic 1, bits [5:0] of register MR43 are logic 000100 in binary form. Bits OP2[7:0] of register MR44 record the checksum value corresponding to the third first test data segment DQ[7:0] written to test data WR2, and bits OP3[7] and OP3[5:0] record the checksum value corresponding to the third first test data inversion segment DMI0 written to test data WR1. In addition, bit OP3[6] is logic 0.

[0075] Furthermore, by reading readout data RD1 and readout data RD2 from the device under test, readout data RD1 and readout data RD2 should be candidate test data No. 1 and candidate test data No. 17, respectively, because the unit error of written test data WR1 and written test data WR2 has been corrected by ECC operation.

[0076] If registers MR43, MR44, and MR45 are read again, the value of register A can be obtained.

[0077] In the test scheme (17), nine write test data WR1 to write test data WR9 have been generated as candidate test data No. 2, candidate test data No. 4, candidate test data No. 3, candidate test data No. 1, candidate test data No. 18, candidate test data No. 7, candidate test data No. 17 and candidate test data No. 19, respectively, and the nine write test data are continuously written into the device under test. At this time, registers MR43, MR44 and MR45 are read, and the value of register M can be obtained. Bit OP1[7] of register MR43 should be logic 1. When bit OP1[6] is logic 0, bits [5:0] of register MR43 are logic 000110 in binary form; and when bit OP1[6] is logic 1, bits [5:0] of register MR43 are logic 001111 in binary form. Bits OP2[7:0] of register MR44 record the checksum value corresponding to the 19th first test data segment DQ[7:0] written to test data WR9, and bits OP3[7] and OP3[5:0] record the checksum value corresponding to the 7th first test data inversion segment DMI0 written to test data WR7. In addition, bit OP3[6] is logic 0.

[0078] Furthermore, by reading read data RD1 to read data RD9 from the device under test, read data RD1 and read data RD2 should be candidate test data No. 1, candidate test data No. 1, candidate test data No. 4, candidate test data No. 1, candidate test data No. 1, candidate test data No. 1, candidate test data No. 1, candidate test data No. 17, and candidate test data No. 17, respectively. This is because the unit error in writing test data WR1 to writing test data WR9 has been corrected through ECC operation.

[0079] If registers MR43, MR44, and MR45 are read again, the value of register A can be obtained.

[0080] It can be seen that by applying test schemes (1) to (17) to the device under test, the link ECC function of the device under test can be tested effectively. In this way, the reliability of data transmission of the device under test can be improved.

[0081] It should be noted here that test schemes (1) to (17) are merely exemplary embodiments and are not intended to limit the scope of this disclosure. Those skilled in the art can adjust the test order of the test schemes. Those skilled in the art can also add at least one test scheme to test schemes (1) to (17) or remove at least one test scheme from test schemes (1) to (17) as needed.

[0082] Please refer to Figure 6 This diagram illustrates a test apparatus according to an embodiment of the present disclosure. The test apparatus 600 is coupled to a device under test (DUT) 601. The test apparatus 600 includes a controller 611 and a storage device 612. The DUT 601 may be a dynamic random access memory (DRAM) or any other type of memory. The controller 611 is coupled to the storage device 612. The controller 611 is configured to perform the test methods mentioned in the previous embodiments. The storage device 612 may be any type of memory and is configured to store... Figure 3 The controller 611 is a processor with computational capabilities. Alternatively, the controller 611 may be a hardware circuit designed using a hardware description language (HDL) or any digital circuit design method known to those skilled in the art, implemented via a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), or an application-specific integrated circuit (ASIC).

[0083] In summary, the testing method of this invention provides multiple candidate test data, and each of the test data segments of the candidate test data can be valid data, single-bit error data, or double-bit error data. By writing multiple write data generated based on the multiple candidate test data to execute each of multiple test schemes, the test results can be obtained through the register values ​​and read data of the device under test. This method can effectively test the link ECC function to improve the reliability of data transmission of the device under test.

[0084] Those skilled in the art will appreciate that various modifications and variations can be made to the disclosed embodiments without departing from the spirit or scope of this disclosure. In view of the foregoing, it is intended that this disclosure cover modifications and variations, provided that such modifications and variations fall within the scope of the appended claims and their equivalents.

Claims

1. A testing method, comprising: Generate error correction codes based on the basic data; The basic data is divided into multiple basic data segments; Multiple candidate test data are generated based on the basic data, wherein each of the candidate test data has multiple test data segments, and each of the test data segments corresponds to each of the basic data segments; as well as Execute multiple test plans, each of which includes: Multiple write test data are generated based on the multiple candidate test data, and the multiple write test data and the error correction code are continuously written into the device under test. Read multiple mode register values ​​and multiple readout data from the device under test; and Test results are generated based on the multiple mode register values ​​and the read data. Each test data segment of each candidate test data is marked as a valid data segment, a single-error data segment, or a double-error data segment.

2. The test method according to claim 1, wherein each of the test data segments is a valid data segment, a single-bit error data segment, or a double-bit error data segment based on the error correction code.

3. The test method according to claim 1, wherein the plurality of basic data segments include first basic data information, second basic data information, first basic data mask inversion information, and second basic data mask inversion information.

4. The testing method according to claim 3, wherein the plurality of test data segments include first test data information, second test data information, first test data mask inversion information, and second test data mask inversion information.

5. The test method according to claim 1, wherein the number of written test data in each of the test schemes is 2 to 9.

6. The test method according to claim 1, wherein the first register value among the plurality of mode register values ​​indicates a two-bit error flag, a unit error rule, and the number of unit errors; the second register value among the plurality of mode register values ​​indicates a checksum value for the error correction code operation; and the third register value among the plurality of mode register values ​​indicates a checksum value for the test data information, an error byte channel, and a checksum value for the data mask inversion information of the error correction code operation.

7. The test method according to claim 1, further comprising: After the multiple mode register values ​​have been read, the multiple mode register values ​​are cleared.

8. A testing apparatus adapted for testing link error correction code functionality, the testing apparatus comprising: The controller is coupled to the device under test. The controller is configured to: Generate error correction codes based on the basic data; The basic data is divided into multiple basic data segments; Multiple candidate test data are generated based on the basic data, wherein each of the candidate test data has multiple test data segments, and each of the test data segments corresponds to each of the basic data segments; as well as Execute multiple test plans, each of which includes: Multiple write test data are generated based on the multiple candidate test data, and the multiple write test data and the error correction code are continuously written into the device under test. Read multiple mode register values ​​and multiple readout data from the device under test; and Test results are generated based on the multiple mode register values ​​and the read data. Each test data segment of each candidate test data is marked as a valid data segment, a single-error data segment, or a double-error data segment.

9. The testing apparatus according to claim 8, further comprising: A storage device, coupled to the controller, is used to store the plurality of candidate test data.

10. The testing apparatus of claim 8, wherein each of the test data segments is a valid data segment, a single-error data segment, or a double-error data segment based on the error correction code.

11. The testing apparatus according to claim 8, wherein the plurality of basic data segments include first basic data information, second basic data information, first basic data mask inversion information, and second basic data mask inversion information.

12. The testing apparatus according to claim 11, wherein the plurality of test data segments include first test data information, second test data information, first test data mask inversion information, and second test data mask inversion information.

13. The testing apparatus according to claim 8, wherein the number of written test data in each of the test schemes is 2 to 9.

14. The testing apparatus according to claim 8, wherein the first register value among the plurality of mode register values ​​indicates a two-bit error flag, a unit error rule, and the number of unit errors; the second register value among the plurality of mode register values ​​indicates a checksum value for an error correction code operation; and the third register value among the plurality of mode register values ​​indicates a checksum value for the error byte channel and the data mask inversion information of the error correction code operation.

15. The test apparatus according to claim 14, wherein the plurality of mode register values ​​are respectively recorded in a plurality of registers in the device under test.

16. The test apparatus of claim 15, wherein after the plurality of mode register values ​​have been read, the device under test clears the plurality of mode register values.

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