Chip layout method, device and readable storage medium of multi-project wafer

Abstract

The application provides a chip layout method, device and readable storage medium of a multi-project wafer. The chip layout method of the multi-project wafer comprises the following steps: acquiring relevant information, arranging chips in a maximum single exposure area, comparing different chip arrangement schemes, adjusting the chips to longitudinally fill the maximum single exposure area, adjusting the maximum single exposure area to obtain a final chip layout scheme, closely arranging the final chip layout scheme in a first quadrant of the wafer, and completing an overall layout scheme by mirror processing of the chip layout scheme in the first quadrant of the wafer. The method not only optimizes the range of the single exposure area, improves the effective layout area utilization rate, and further improves the overall yield, but also adopts a central symmetric layout, facilitates chip cutting, improves the cutting efficiency, and further reduces the cost.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a chip layout method, apparatus and readable storage medium for multi-project wafers. Background Technology

[0002] As semiconductor manufacturing processes continue to advance, reaching technology nodes of 3nm or even smaller, the cost of wafer fabrication increases dramatically. 3nm processes can cost over $100 million, and even a 1% reduction can save hundreds of thousands of dollars. Under current technological conditions, improving yield and optimizing layout are effective ways to reduce costs. Because of the high cost of wafer fabrication, multi-project wafer (MPW) fabrication is increasingly being adopted, allowing more chips with the same process design to be placed in a single fabrication run, thus reducing the cost per chip. Patent 201780073750.3 discloses a method for mixed layout of large and small devices, using small devices to fill areas where large devices cannot be fully placed, increasing wafer utilization. However, this layout method increases the complexity of wafer dicing and reduces dicing efficiency. Patents 200810114345.4 and 202010939198.5 both disclose optimization methods for single-chip layout, which are not applicable to MPW layouts. Patent 201010155820.X discloses a chip layout planning principle that prioritizes ensuring high-priority chips are not damaged during cutting. This approach can lead to lower-priority chips being neglected, resulting in a decrease in overall yield. Since MPWs contain multiple chips of varying sizes, and the ease and efficiency of subsequent chip cutting must also be considered, the chip layout becomes more complex. Summary of the Invention

[0003] The purpose of this invention is to provide a chip layout method, apparatus and readable storage medium for multi-project wafers, which efficiently utilizes wafer area, increases the yield of multi-project wafer chips and effectively reduces production costs.

[0004] To achieve the above objectives, the present invention provides the following technical solution: a chip layout method for multi-project wafers, comprising the following steps: S1, obtain the effective layout area of ​​the wafer, the maximum single exposure area, and the specific dimensions of different chips; S2, the different chips are arranged laterally along the maximum single exposure area with cleaving paths S spaced apart in both the length and width directions, resulting in a distance D between the different chips and the lateral end of the maximum single exposure area. i D of all different chips i Form a set of horizontal layout schemes P; S3, based on the horizontal layout schemes of different chips in the scheme set P, compare the D of the same chip. iSelect the same chip D i The smaller solution yields a smaller distance D. i ', the D of the different chips i 'Form a horizontal layout scheme set P', according to the aforementioned D i Arrange them from bottom to top of the largest single exposure area, in ascending order; S4, based on meeting the different chip quantity requirements, increase different chips in integer multiples of N, and adjust the multiple of each chip until the maximum single exposure area is filled vertically; S5, adjust the maximum single exposure area so that the horizontal and vertical distances of the final single exposure area are both the distances from the cut-off track of the already arranged chip ends, thus obtaining the final single exposure area and the final chip layout scheme under the final single exposure area; S6, the wafer is divided into four quadrants with the center of the wafer as the center. In the first quadrant, starting from (S / 2, S / 2), the final chip layout scheme under the final single exposure area is closely laid out along the X-axis and Y-axis. Chips that exceed the effective layout area of ​​the wafer are directly deleted, and the final chip layout in the first quadrant is completed. S7, the second quadrant layout and the final layout of the first quadrant chip are mirrored with the X-axis as the axis of symmetry to complete the final layout of the second quadrant chip. The third quadrant layout and the final layout of the second quadrant chip are mirrored with the Y-axis as the axis of symmetry. The fourth quadrant layout and the final layout of the first quadrant chip are mirrored with the Y-axis as the axis of symmetry to complete the complete layout scheme of the effective layout area of ​​the wafer.

[0005] Furthermore, the cutting groove has different ranges from different manufacturers, and the cutting groove S is the minimum value of the manufacturer's cutting groove.

[0006] Furthermore, "vertical filling" means that by adjusting the multiples of each chip, the maximum single exposure area can no longer accommodate any chip in the scheme set P', and the distance between the end of the vertical chip and the top of the maximum single exposure area is minimized.

[0007] Furthermore, adjusting the maximum single exposure area means moving the right side and top edge of the maximum single exposure area closer to the end of the arranged chips.

[0008] Furthermore, the final single exposure area is the single exposure area provided to the wafer fabrication plant for processing, and is smaller than the maximum single exposure area.

[0009] Furthermore, the complete layout scheme also includes the final single-exposure area size information.

[0010] The present invention also provides a chip layout apparatus for multi-project wafers, comprising the following modules: The acquisition module is used to acquire data on the effective layout area of ​​the wafer, the maximum single exposure area, the specific dimensions of different chips, and the dicing track, and transmit the relevant data to the layout module. The layout module is used to realize the overall chip layout. It includes a calculation submodule and a comparison submodule. The calculation submodule completes the layout scheme of various chips in the maximum single exposure area, and the comparison submodule obtains the optimal layout scheme. Then, by adjusting the range of the maximum single exposure area, the final single exposure area and the final chip layout scheme are obtained. The layout is then further carried out on the wafer to complete the complete layout, and the complete layout scheme is transmitted to the output module. The calculation submodule is used to calculate the layout scheme of different chips within the maximum single exposure area, and to obtain D. i data; The comparison submodule is used to compare different Ds. i D i The system collects data and compares different layout schemes to determine the optimal layout scheme; the output module is used to output the processing data, including the complete layout scheme and the final single exposure area.

[0011] The workflow of the multi-project wafer chip placement device is as follows: After the acquisition module acquires the data of the effective placement area of ​​the wafer, the maximum single exposure area, the specific dimensions of different chips, and the dicing track, it transmits the relevant data to the placement module; after receiving the relevant data, the placement module completes the placement scheme of various chips within the maximum single exposure area through the calculation submodule, and obtains the optimal placement scheme through the comparison submodule. Then, by adjusting the range of the maximum single exposure area, the final single exposure area and the final chip placement scheme are obtained, and further placement is performed on the wafer to complete the complete placement. The complete placement scheme is then transmitted to the output module; after receiving the complete placement scheme, the final single exposure area, and other processing data, the output module outputs the corresponding data file according to the specified requirements.

[0012] The chip placement apparatus for the multi-project wafer includes: Memory; and A processor coupled to the memory, the memory being connected to the processor via a bus, the processor being connected to an acquisition module, a placement module, and an output module via a bus, the processor being configured to execute the chip placement method for a multi-project wafer as described above based on instructions stored in the memory device.

[0013] The present invention further provides a computer-readable storage medium for chip layout of a multi-project wafer, wherein a computer program is stored thereon, characterized in that the program, when executed by a processor, implements the steps of the chip layout method of any of the preceding claims.

[0014] The beneficial effects of this invention are as follows: The range of the single exposure area has been optimized, improving the utilization rate of the effective layout area and further increasing the overall yield; the layout of the wafer edge area has been optimized, resulting in more complete chips; The centrally symmetrical layout facilitates chip cutting, improves cutting efficiency, and further reduces costs. Attached Figure Description

[0015] Figure 1 This is a flowchart of a chip layout method for multi-project wafers according to an embodiment of the present invention.

[0016] Figure 2 This is a schematic diagram of the horizontal arrangement of a single chip in the chip layout method for multi-project wafers according to an embodiment of the present invention.

[0017] Figure 3 This is a schematic diagram of the vertical arrangement of a single chip in the chip layout method for multi-project wafers according to an embodiment of the present invention.

[0018] Figure 4 This is a schematic diagram of the basic arrangement of different chips in the chip layout method of the multi-project wafer according to an embodiment of the present invention.

[0019] Figure 5 This is a schematic diagram showing different chips arranged vertically in a multi-project wafer chip layout method according to an embodiment of the present invention.

[0020] Figure 6 This is a schematic diagram illustrating the adjustment of the maximum single exposure area in the chip layout method for multi-project wafers according to an embodiment of the present invention.

[0021] Figure 7 This is a schematic diagram of the final single-exposure area of ​​the chip layout method for multi-project wafers according to an embodiment of the present invention.

[0022] Figure 8 This is a magnified schematic diagram of the wafer center of the chip layout method for multi-project wafers according to an embodiment of the present invention.

[0023] Figure 9 This is a magnified schematic diagram of the effective boundary of the wafer in the chip layout method for multi-project wafers according to an embodiment of the present invention.

[0024] Figure 10 This is a schematic diagram of the structure of a chip layout apparatus for a multi-project wafer according to an embodiment of the invention. Implementation

[0025] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0028] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0029] Figure 1 A flowchart of a multi-project wafer chip layout method according to an embodiment of the present invention.

[0030] See Figure 1 The chip layout method for multi-project wafers described in this invention includes the following steps: S1, obtain the effective layout area of ​​the wafer, the maximum single exposure area, and the specific dimensions of different chips. In this embodiment, three chips are selected, namely chips A, B, and C, which have different dimensions. S2, the different chips are arranged laterally along the maximum single exposure area with cleaving paths S spaced apart in both the length and width directions, resulting in a distance D between the different chips and the lateral end of the maximum single exposure area. i , Figure 2 The diagram shows a chip A arranged laterally along the maximum single exposure area 100 with dicing lines S spaced apart along its length. The distance D between the chip A and the lateral end of the maximum single exposure area is obtained. A1. Figure 3 The diagram shows a chip A arranged laterally along the maximum single exposure area with dicing paths S spaced apart in the width direction. The distance D between the different chips and the lateral end of the maximum single exposure area is obtained. A2 The same operation can be used to obtain the D values ​​of chips B and C. B1 D B2 D C1 D C2 D of all chips i D A1 D A2 D B1 D B2 D C1 D C2 Form a set of horizontal layout schemes P; S3, based on the horizontal layout schemes of different chips in the scheme set P, compare the D of the same chip. i Select the same chip D i The smaller solution yields a smaller distance D. i For chip A, in comparison Figure 2 and Figure 3 D can be derived A2 <D A1 That is, the D of chip A i 'For D A2 Then compare and select chip B and chip C for D. i 'Form a horizontal layout scheme set P', according to the aforementioned D i Arrange them in ascending order from the bottom to the top of the largest single exposure area, such as... Figure 4 As shown; S4, based on meeting the different chip quantity requirements, increase the number of different chips in integer multiples of N, and adjust the multiple of each chip until the maximum single exposure area is vertically filled, such as... Figure 5 As shown, chip A is 3 times, chip B is 2 times, and chip C is 1 time. S5, such as Figure 6 As shown, the maximum single exposure area is adjusted so that the final single exposure area is both horizontally and vertically distanced from the distance of the cut track at the end of the pre-arranged chip, resulting in the following... Figure 7 The final single exposure area 200 and the final chip layout scheme under the final single exposure area are shown. The area of ​​the adjusted final single exposure area is smaller than the area of ​​the maximum single exposure area. The shaded part in the figure is the actual area reduced. This area can be used directly, which is equivalent to improving the wafer utilization rate. S6, such as Figure 8As shown, the wafer is divided into four quadrants with the center of the wafer as the center. In the first quadrant, starting from (S / 2, S / 2), the final chip layout scheme under the final single exposure area is closely laid out along the X and Y axes. Chips that exceed the effective layout area of ​​the wafer are directly deleted, and the final chip layout in the first quadrant is completed. S7, the second quadrant layout and the final layout of the first quadrant chip are mirrored with the X-axis as the axis of symmetry to complete the final layout of the second quadrant chip. The third quadrant layout and the final layout of the second quadrant chip are mirrored with the Y-axis as the axis of symmetry. The fourth quadrant layout and the final layout of the first quadrant chip are mirrored with the Y-axis as the axis of symmetry to complete the complete layout scheme of the effective layout area of ​​the wafer.

[0031] In some embodiments, the cutting groove has different ranges from different manufacturers. The cutting groove S is the minimum value of the manufacturer's cutting groove. For example, if the cutting groove range of a certain manufacturer is 50~150um, then the cutting groove S is 50um.

[0032] In some embodiments, "vertical filling" means adjusting the multiples of each chip so that the maximum single exposure area can no longer accommodate any chip in the scheme set P', and the distance between the end of the vertical chip and the top of the maximum single exposure area is minimized.

[0033] In some embodiments, adjusting the maximum single exposure area means moving the right and top edges of the maximum single exposure area closer to the end of the arranged chips.

[0034] In some embodiments, the final single exposure area is a single exposure area provided to the wafer fabrication plant for processing, which is smaller than the maximum single exposure area.

[0035] In some embodiments, the complete layout scheme may also include final single-exposure area size information.

[0036] In some embodiments, a mirror layout method is adopted, which allows the chip cutting process to be set only once during the later chip cutting process, which can be used for chip cutting in all four quadrants, thus improving cutting efficiency.

[0037] In some embodiments, such as Figure 9 As shown, through design and optimization, the arc-shaped boundary of the effective area of ​​the wafer is staggered from the chip layout gap in the final single exposure area, which preserves the complete chip to the greatest extent and effectively increases the number of complete chips.

[0038] Regarding the aforementioned chip placement method for multi-project wafers, this embodiment also mentions an apparatus for chip placement of multi-project wafers, such as... Figure 10 As shown, the device includes: The acquisition module is used to acquire data on the effective layout area of ​​the wafer, the maximum single exposure area, the specific dimensions of different chips, and the dicing track, and transmit the relevant data to the layout module. The layout module is used to realize the overall chip layout. It includes a calculation submodule and a comparison submodule. The calculation submodule completes the layout scheme of various chips in the maximum single exposure area, and the comparison submodule obtains the optimal layout scheme. Then, by adjusting the range of the maximum single exposure area, the final single exposure area and the final chip layout scheme are obtained. The layout is then further carried out on the wafer to complete the complete layout, and the complete layout scheme is transmitted to the output module.

[0039] The calculation submodule is used to calculate the layout scheme of different chips within the maximum single exposure area, and to obtain D. i data.

[0040] The comparison submodule is used to compare different Ds. i D i The data, and by comparing different layout schemes, yields the optimal layout scheme.

[0041] The output module is used to output the processing data, including the complete layout scheme and the final single exposure area.

[0042] In other embodiments, the chip placement apparatus for multi-project wafers operates as follows: the acquisition module acquires data on the effective placement area of ​​the wafer, the maximum single exposure area, the specific dimensions of different chips, and the dicing channels, and then transmits the relevant data to the placement module; after receiving the relevant data, the placement module completes the placement schemes for various chips within the maximum single exposure area through the calculation submodule, and obtains the optimal placement scheme through the comparison submodule, and then obtains the final single exposure area and the final chip placement scheme by adjusting the range of the maximum single exposure area, and further places the chips on the wafer to complete the complete placement, and transmits the complete placement scheme to the output module; after receiving the complete placement scheme, the final single exposure area, and other processing data, the output module outputs the corresponding data files according to the specified requirements.

[0043] In other embodiments, the chip placement apparatus for the multi-project wafer includes: Memory; and A processor coupled to the memory, the memory being connected to the processor via a bus, the processor being connected to an acquisition module, a placement module, and an output module via a bus, the processor being configured to execute the chip placement method for a multi-project wafer as described above based on instructions stored in the memory device.

[0044] The memory may include, for example, system memory, fixed non-volatile readable storage media, etc. System memory may store, for example, the operating system, application programs, boot loader, database, and other programs.

[0045] In some other embodiments, the present invention provides a computer-readable storage medium for chip layout of a multi-project wafer, having stored thereon a computer program, characterized in that the program, when executed by a processor, implements the steps of the chip layout method for any of the preceding claims.

[0046] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable non-transitory readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0047] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0048] These computer program instructions may also be stored in a computer memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer memory produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0049] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0050] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0051] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A chip layout method for multi-project wafers, characterized in that, The chip placement method for the multi-project wafer includes the following steps: S1, obtain the effective layout area of ​​the wafer, the maximum single exposure area, and the specific dimensions of different chips; S2, the different chips are arranged laterally along the maximum single exposure area with cleaving paths S spaced apart in both the length and width directions, thus obtaining the distance between the different chips and the lateral end of the maximum single exposure area. Di, the Di of all different chips forms a horizontal layout scheme set P; S3, based on the horizontal layout schemes of different chips in the scheme set P, compare the Di of the same chip, select the scheme with the smaller Di of the same chip, and obtain the smaller distance Di'. The Di' of the different chips form the horizontal layout scheme set P', and arrange them from the bottom to the top of the largest single exposure area in order of Di' from smallest to largest. S4, based on meeting the different chip quantity requirements, increase different chips in integer multiples of N, and adjust the multiple of each chip until the maximum single exposure area is filled vertically; S5, adjust the maximum single exposure area so that the horizontal and vertical distances of the final single exposure area are both the distances from the cut-off track of the already arranged chip ends, thus obtaining the final single exposure area and the final chip layout scheme under the final single exposure area; S6. Divide the wafer into four quadrants with the center of the wafer as the center. In the first quadrant, starting from (S / 2, S / 2), the final chip layout scheme under the final single exposure area is closely laid out along the X-axis and Y-axis. Chips that exceed the effective layout area of ​​the wafer are directly deleted, and the final chip layout in the first quadrant is completed. S7, the second quadrant layout is mirrored with respect to the final layout of the first quadrant chip, with the X-axis as the axis of symmetry, to complete the final layout of the second quadrant chip. The third quadrant layout is mirrored with respect to the final layout of the second quadrant chip, with the Y-axis as the axis of symmetry, and the fourth quadrant layout is mirrored with respect to the final layout of the first quadrant chip, with the Y-axis as the axis of symmetry, to complete the complete layout scheme of the effective layout area of ​​the wafer.

2. The chip layout method for multi-project wafers as described in claim 1, characterized in that, The cutting groove has different ranges in different chip manufacturers, and the cutting groove S is the minimum cutting groove value of the corresponding chip manufacturer.

3. The chip layout method for multi-project wafers as described in claim 1, characterized in that, The term "vertical filling" refers to adjusting the multiplier of each chip so that the maximum single exposure area can no longer accommodate any chip in the scheme set P', and the distance between the end of the vertical chip and the top of the maximum single exposure area is minimized.

4. The chip layout method for multi-project wafers as described in claim 1, characterized in that, The adjustment of the maximum single exposure area refers to moving the right side and top edge of the maximum single exposure area closer to the end of the arranged chips.

5. The chip layout method for multi-project wafers as described in claim 1, characterized in that, The final single exposure area is the single exposure area provided to the wafer fabrication plant for processing, and is smaller than the maximum single exposure area.

6. The chip layout method for multi-project wafers as described in claim 1, characterized in that, The complete layout scheme also includes the final single-exposure area size information.

7. A chip placement apparatus for multi-project wafers, characterized in that, The apparatus is used to implement the chip layout method for multi-project wafers according to any one of claims 1 to 6, and the apparatus includes the following modules: The acquisition module is used to acquire data on the effective layout area of ​​the wafer, the maximum single exposure area, the specific dimensions of different chips, and the dicing track, and transmit the relevant data to the layout module. The layout module is used to realize the overall chip layout. It includes a calculation submodule and a comparison submodule. The calculation submodule completes the layout scheme of various chips in the maximum single exposure area, and the comparison submodule obtains the optimal layout scheme. Then, by adjusting the range of the maximum single exposure area, the final single exposure area and the final chip layout scheme are obtained. The layout is then further carried out on the wafer to complete the complete layout, and the complete layout scheme is transmitted to the output module. The calculation submodule is used to calculate the layout scheme of different chips within the maximum single exposure area and obtain Di data; The comparison submodule is used to compare different Di to obtain Di' data, and to compare different layout schemes to obtain the optimal layout scheme; The output module is used to output the processing data, including the complete layout scheme and the final single exposure area.

8. The chip placement apparatus for multi-project wafers as described in claim 7, characterized in that, The workflow of the chip placement device for the multi-project wafer is as follows: after the acquisition module acquires the data of the effective placement area of ​​the wafer, the maximum single exposure area, the specific dimensions of different chips, and the dicing track, it transmits the relevant data to the placement module. After receiving relevant data, the layout module completes the layout schemes of various chips within the maximum single exposure area through the calculation submodule, and obtains the optimal layout scheme through the comparison submodule. Then, by adjusting the range of the maximum single exposure area, the final single exposure area and the final chip layout scheme are obtained. The layout is then further performed on the wafer to complete the complete layout, and the complete layout scheme is transmitted to the output module. After receiving the complete layout scheme, the final single exposure area, and other processing data, the output module outputs the corresponding data files according to the specified requirements.

9. The chip placement apparatus for multi-project wafers as described in claim 7, characterized in that, The device includes: Memory; and A processor coupled to the memory, the memory being connected to the processor via a bus, the processor being connected to an acquisition module, a placement module, and an output module via a bus, the processor being configured to execute the chip placement method for a multi-project wafer according to any one of claims 1-6 based on instructions stored in the memory device.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the program implements the steps of the chip layout method for a multi-project wafer as described in any one of claims 1-6.

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