A method for improving deep trench isolation structure

Abstract

The present invention provides a method for improving a deep trench isolation structure, which is applied to the field of semiconductor technology. Specifically, a plurality of deep trenches can be first formed on a substrate, and the substrate can be divided into a densely patterned area and a sparsely patterned area by having different numbers of deep trenches in different areas. Then, a membrane structure of a deep trench isolation structure is formed on the substrate, namely, a first hard mask layer, a second hard mask layer, and a polysilicon layer. Then, a chemical mechanical polishing process is performed on the membrane structure of the deep trench isolation structure, and the chemical mechanical polishing process is specifically divided into three grinding wheels using two types of polishing fluids. Thus, while completely removing the polysilicon layer and the second hard mask layer, the polishing time of the over-polishing step is reduced, the thickness difference of the hard mask layer between the densely patterned area and the sparsely patterned area is improved, and the occurrence of etch pits or dishing defects on the surface of the formed deep trench isolation structure is avoided.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic semiconductor technology, and in particular to a method for improving a deep trench isolation structure. Background Art

[0002] Chemical Mechanical Polish (CMP) is one of the most critical processes in semiconductor manufacturing, and can be used to prepare deep trench isolation structures in semiconductor structures.

[0003] At present, the preparation process of deep trench isolation structure is as follows: forming a deep trench in the substrate, depositing silicon oxide by chemical vapor deposition, and then using polysilicon as the deposition material. Chemical mechanical polishing (CMP) is used to remove excess polysilicon outside the deep trench, and silicon oxide is used as the polishing stop layer of CMP. After reaching the end point, over-polishing is performed for a period of time to remove the residual polysilicon.

[0004] However, due to the influence of pattern densities in different regions on the substrate on the CMP process polishing rate, deep trench isolation structures formed using existing processes are prone to etch pits or dishing pits. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for improving a deep trench isolation structure, so as to reduce the grinding time of the over-grinding step while completely removing the polysilicon layer and the second hard mask layer, improve the thickness difference of the hard mask between the pattern-dense area and the pattern-sparse area, and avoid the occurrence of etch pits or dished pit defects on the surface of the formed deep trench isolation structure.

[0006] To solve the above technical problems, the present invention provides a method for improving a deep trench isolation structure, which may include at least the following steps:

[0007] A substrate is provided, comprising a pattern-dense area and a pattern-sparse area, wherein the pattern density of the pattern-dense area is greater than that of the pattern-sparse area, and a first hard mask layer is formed on the substrate.

[0008] The substrate is etched to form a plurality of deep trenches in the substrate in the pattern-dense area and the pattern-sparse area.

[0009] A second hard mask layer and a polysilicon layer are formed, wherein the second hard mask layer is located on the first hard mask layer between adjacent deep trenches, and the polysilicon layer fills the deep trenches and extends to cover the second hard mask layer.

[0010] The second hard mask layer is used as the grinding stop layer, and the substrate placed on the second grinding disk is ground for a second time using a second grinding liquid to remove the remaining polysilicon layer on the second hard mask layer, and at the same time allow part of the polysilicon layer to remain on part of the surface of the second hard mask layer, that is, to obtain a relatively flat second hard mask layer surface. The second grinding includes an over-grinding step, and the grinding time of the over-grinding step is: 10s~20s.

[0011] Using the first hard mask layer as a grinding stop layer, the substrate placed on the third grinding wheel is ground for a third time using the first grinding slurry to remove the second hard mask layer and obtain a flat surface of the first hard mask layer, wherein the third grinding includes an over-grinding step, and the grinding time of the over-grinding step is 8 seconds to 12 seconds;

[0012] Wherein, during the grinding, the pressure of the first grinding disk is equal to the pressure of the second grinding disk, and the pressure of the second grinding disk is greater than the pressure of the third grinding disk.

[0013] In some optional examples, the material of the first hard mask layer includes silicon nitride, and the material of the second hard mask layer includes silicon oxide.

[0014] In some optional examples, the material of the first polishing liquid includes silicon dioxide.

[0015] In some optional examples, during the first grinding, the pressure of the first grinding disc is 3psi~4psi.

[0016] In some optional examples, a material of the second polishing liquid includes silicon dioxide, and a polishing selectivity ratio of the second polishing liquid to the polysilicon layer and the second hard mask layer is 50-70.

[0017] In some optional examples, during the second grinding, the pressure of the second grinding disc is 3psi~4psi.

[0018] In some optional examples, when the first polishing liquid is used to polish the substrate placed on the third polishing disk for the third time, the polishing selection ratio of the first polishing liquid to the second hard mask layer and the first hard mask layer is: 2~4.

[0019] In some optional examples, when performing the third grinding, the pressure of the third grinding disk is: 1.4psi~1.8psi.

[0020] In some optional examples, the second grinding includes a main grinding step and an over-grinding step, wherein in the main grinding step, the polysilicon layer is ground using a second grinding liquid compatible with the second hard mask layer, and the main grinding step is completed by an endpoint detection method, and the over-grinding step is used to continue grinding and removing the second hard mask layer after the main grinding step is completed, so as to remove the polysilicon layer in the pattern-dense area and the pattern-sparse area while allowing part of the polysilicon layer to remain on part of the surface of the second hard mask layer, thereby obtaining a relatively smooth second hard mask layer interface.

[0021] In some optional examples, the third grinding includes a main grinding step and an over-grinding step, wherein in the main grinding step, the second hard mask layer is ground using a first grinding liquid compatible with the first hard mask layer, and the main grinding step is completed by an endpoint detection method, and the over-grinding step is used to continue grinding and removing the first hard mask layer after the main grinding step is completed, so as to obtain a smooth first hard mask layer interface while completely removing the second hard mask layer in the pattern-dense area and the pattern-sparse area.

[0022] In some optional examples, during the process of forming the second hard mask layer, the second hard mask layer further extends to cover the inner surface of each of the deep trenches.

[0023] In some optional examples, during the process of forming the second hard mask layer, the second hard mask layer further extends to cover the sidewall of each of the deep trenches.

[0024] In some optional examples, before forming the first hard mask layer on the substrate, the preparation method further includes: forming a linear silicon oxide layer on the substrate.

[0025] Based on the same inventive concept, the present invention further provides a deep trench isolation structure, which can be specifically prepared by the above-mentioned method for improving the deep trench isolation structure, and will not be described again here.

[0026] Based on the same concept, the present invention further provides a semiconductor process, which may specifically include the method for improving the deep trench isolation structure as described above, but is not limited thereto.

[0027] Based on the same inventive concept, the present invention also provides an electronic device, which specifically includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus.

[0028] Memory, used to store computer programs.

[0029] The processor is used to implement the above-mentioned method steps for improving the deep trench isolation structure when executing the program stored in the memory.

[0030] Based on the same inventive concept, the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the computer program implements the various steps of the above-mentioned method for improving the deep trench isolation structure.

[0031] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0032] The present invention provides a method for improving a deep trench isolation structure. First, a plurality of deep trenches are formed on a substrate. By using different numbers of deep trenches in different areas, the substrate is divided into a pattern-dense area and a pattern-sparse area. Then, a film layer structure of the deep trench isolation structure is formed on the substrate, namely, a first hard mask layer, a second hard mask layer and a polysilicon layer. Then, a chemical mechanical polishing process is performed on the film layer structure of the deep trench isolation structure. Specifically, the chemical mechanical polishing process is divided into three grinding discs using two types of grinding fluids. An unexpected effect is obtained: the silicon oxide grinding fluid of the first grinding disc is used to remove the bulk polysilicon layer deposited on the substrate, and the polysilicon grinding fluid of the second grinding disc is used to partially remove the remaining polysilicon layer on the substrate. End point detection is performed and only the thinner one is used. A short over-grinding step can obtain a relatively flat second hard mask layer interface on a partial surface of which a portion of the polysilicon layer is allowed to remain. Then, the second hard mask layer on the substrate is completely removed using the silicon oxide grinding liquid of the third grinding disk, and the endpoint detection is passed again. Only using a relatively short over-grinding step can also obtain a deep trench isolation structure with no etch pits or dished pit defects on the surface, as well as a first hard mask layer interface with a flat surface on the entire substrate including the pattern-dense area and the pattern-sparse area. That is, while completely removing the polysilicon layer and the second hard mask layer, the grinding time of the over-grinding step is reduced, the thickness difference of the hard mask layer between the pattern-dense area and the pattern-sparse area is improved, and the occurrence of etch pits or dished pit defects on the surface of the formed deep trench isolation structure is avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 FIG. 1 is a flow chart of a method for improving a deep trench isolation structure provided in one embodiment of the present invention.

[0034] Figure 2 The use provided in one embodiment of the present invention Figure 1 The manufacturing method shown is a schematic structural diagram after forming a deep trench 101, a first hard mask layer 120, a second hard mask layer 130 and a polysilicon layer 140 on a substrate 100.

[0035] Figure 3 The method for improving the deep trench isolation structure provided in the embodiment of the present invention is Figure 2 Schematic diagram of the structure of the semiconductor structure after the first grinding.

[0036] Figure 4 The method for improving the deep trench isolation structure provided in the embodiment of the present invention is Figure 3 Schematic diagram of the structure of the semiconductor structure after the second grinding.

[0037] Figure 5 The method for improving the deep trench isolation structure provided in the embodiment of the present invention is Figure 4 Schematic diagram of the structure of the semiconductor structure after the third grinding.

[0038] Among them, Figures 2 to 5 middle,

[0039] substrate;

[0040] 100a-graphically dense area;

[0041] 100b graphics sparse area;

[0042] 101-deep groove;

[0043] linear silicon oxide layer;

[0044] a first hard mask layer;

[0045] 120 ′—the first hard mask layer remaining after the third grinding is performed;

[0046] a second hard mask layer;

[0047] 130 ′-the second hard mask layer remaining after the second grinding is performed;

[0048] polysilicon layer;

[0049] 140 ′-the polysilicon layer remaining after the first grinding is performed;

[0050] 150-ion implantation area. DETAILED DESCRIPTION

[0051] To make the technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although the accompanying drawings show exemplary implementation methods of the present invention, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0052] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in illustrating the purpose of the embodiments of the present invention. It will be understood that the meanings of "on...", "above..." and "above..." in the present invention should be interpreted in the broadest way, so that "on..." not only means that it is "on" something and there are no intervening features or layers (i.e., directly on something), but also includes the meaning of being "on" something and having intervening features or layers.

[0053] Furthermore, for ease of description, spatially relative terms such as "on," "over," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0054] In the embodiments of the present invention, the terms "first" and "second" are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.

[0055] According to relevant technologies, in the current process of forming a deep trench isolation structure in a substrate, multiple deep trenches are formed in the substrate, and combined with a deposition process, silicon oxide and silicon nitride are sequentially formed as hard mask layers, and then polysilicon is filled in the deep trenches. Finally, chemical mechanical polishing (CMP) is used to grind the excess polysilicon deposited on the substrate.

[0056] Specifically, in this chemical mechanical polishing process, silicon oxide located on the surface of the substrate (equivalent to the first hard mask layer in the embodiment of the present invention) is used as the CMP polishing stop layer, that is, when the endpoint detection device detects silicon oxide, the polishing is stopped. However, since the CMP process is affected by many factors such as the pattern structure in the different pattern density areas on the substrate on the polishing rate, the problem of polysilicon residue often occurs on the substrate corresponding to the sparse pattern area after the CMP process. Based on this problem, the solution of the existing technology is: after the endpoint detection device detects silicon oxide, the polishing is not stopped, but an over-polishing process with a duration of about 100 seconds is added.

[0057] However, due to the selective removal rate and selectivity of the polishing liquid used in the prior art for polysilicon and silicon oxide, the polysilicon polishing removal rate in the deep trench is fast, while the silicon oxide polishing removal rate is slow. Long-term over-polishing will cause erosion pits on the surface of the deep trench isolation structure in the pattern-dense area, and in the area with a large deep trench opening width, it is easy to cause dishing problems on its surface, which in turn leads to a larger thickness difference between the hard mask layer remaining on the corresponding substrate in the pattern-dense area and the pattern-sparse area after polishing. In the subsequent process, the different polysilicon thicknesses will cause the tungsten plug connection to fail, affecting the electrical performance of the chip.

[0058] To this end, the present invention provides a method for improving a deep trench isolation structure. The overall inventive concept is: first, the existing one-step chemical mechanical polishing (CMP) process is divided into three steps, that is, the number of CMP process steps is changed, and then the three-step CMP process uses two polishing liquids, and the polishing selectivity ratios of the two polishing liquids have a certain difference, and then multiple combinations are performed with an endpoint detection device or equipment.

[0059] Specifically, in the present invention, the low polishing selectivity of the silicon oxide polishing liquid (first polishing liquid) can be used to remove the bulk polysilicon layers deposited in different areas on the substrate at similar polishing rates. Then, the high polishing selectivity of the polysilicon polishing liquid (second polishing liquid) can be used to partially remove the remaining polysilicon layer on the substrate under the detection of the endpoint detection device or equipment, thereby obtaining a silicon nitride film interface that allows polysilicon to remain and has a relatively smooth surface. The residual polysilicon will be removed together with the silicon oxide polishing liquid with a low polishing selectivity in the subsequent third polishing step during the removal of the silicon nitride film layer, thereby achieving a deep trench isolation structure with no surface etch pits or dished pit defects, and a first hard mask layer interface with a smooth surface on the entire substrate including the densely patterned area and the sparsely patterned area, using only a relatively short over-polishing step.

[0060] The following will introduce the method for improving the deep trench isolation structure provided by the present invention.

[0061] See Figure 1 , and combined with Figures 2 to 5 , Figure 1 A schematic flow chart of a method for improving a deep trench isolation structure provided in one embodiment of the present invention, Figures 2 to 5 Schematic diagram of the structure of the deep trench isolation structure provided in an embodiment of the present invention during the preparation process.

[0062] like Figure 1 As shown, the preparation method provided by the present invention comprises at least the following steps:

[0063] In step S101 , a substrate is provided. The substrate includes a pattern-dense area and a pattern-sparse area. The pattern density of the pattern-dense area is greater than the pattern density of the pattern-sparse area. A first hard mask layer is formed on the substrate.

[0064] Step S102 , etching the substrate to form a plurality of deep trenches in the substrate in the pattern-dense area and the pattern-sparse area.

[0065] Step S103 , forming a second hard mask layer and a polysilicon layer, wherein the second hard mask layer is located on the first hard mask layer between adjacent deep trenches, and the polysilicon layer fills the deep trenches and extends to cover the second hard mask layer.

[0066] Step S104 , performing a first grinding operation on the substrate placed on the first grinding disk using a first grinding liquid to remove a portion of the polysilicon layer.

[0067] In step S105, the second hard mask layer is used as a grinding stop layer, and the substrate placed on the second grinding disk is ground for a second time using a second grinding liquid to remove the remaining polysilicon layer on the second hard mask layer, and at the same time, a portion of the polysilicon layer is allowed to remain on a portion of the surface of the second hard mask layer, thereby obtaining a relatively smooth second hard mask layer interface.

[0068] Step S106 , using the first hard mask layer as a grinding stop layer, and using the first grinding liquid to grind the substrate placed on a third grinding disk for a third time, so as to remove the second hard mask layer and obtain a smooth first hard mask layer interface.

[0069] See Figure 2 , Figure 2 The use provided in one embodiment of the present invention Figure 1 The manufacturing method shown is a schematic structural diagram after forming a deep trench 101, a first hard mask layer 120, a second hard mask layer 130 and a polysilicon layer 140 on a substrate 100.

[0070] In the above step S101, a substrate 100 can be first provided, and the substrate 100 can be divided into a pattern-dense area 100a and a pattern-sparse area 100b with different pattern densities. Then, a deposition process, such as a physical vapor deposition process, a chemical vapor deposition process, and an atomic layer deposition process, is used to form a linear silicon oxide layer 110 and a first hard mask layer 120 on the entire surface of the substrate 100. Exemplarily, the material of the first hard mask layer 120 is preferably silicon nitride.

[0071] In this embodiment, the substrate 100 may be any suitable substrate material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or double-side polished silicon wafers (DSP), or ceramic substrates such as alumina, quartz, or glass substrates. For example, in this embodiment, the substrate 100 is, for example, a silicon wafer.

[0072] Continue reading Figure 2 In the above step S102, an etching process, such as a dry etching process, a wet etching process, or a hybrid process of the two, can be used to form a plurality of deep trenches 101 in the first hard mask layer 120, the linear silicon oxide layer 110, and a portion of the substrate 100, wherein the number of deep trenches 101 formed in the substrate 100 corresponding to the pattern-dense area 100a is greater than the number of deep trenches 101 formed in the substrate 100 corresponding to the pattern-sparse area 100b, thereby making the pattern density of the pattern-dense area 100a greater than the pattern density of the pattern-sparse area 100b.

[0073] Continue reading Figure 2 In the above step S103, after forming the plurality of deep trenches 101, a deposition process, such as a chemical vapor deposition process or a physical vapor deposition process, can be used to form a second hard mask layer 130 on both side walls of each deep trench 101 formed on the substrate 100, and on the first hard mask layer 120 between two adjacent deep trenches 101. Exemplarily, the material of the second hard mask layer 130 is silicon oxide, such as silicon dioxide.

[0074] As an example, an ion implantation process may be used to implant N-type or P-type ions into the substrate 100 at the bottom of each deep trench 101 to form an ion implantation region 150 .

[0075] Furthermore, the deep trenches 101 can be filled with a deposition process, so that when each of the deep trenches 101 is filled, a polysilicon layer 140 is stacked on the substrate 100. In this case, since an ion implantation region 150 is formed in the substrate 100 at the bottom of the deep trenches 101, and the polysilicon filled in the deep trenches 101 has conductivity, in a high-voltage semiconductor device, Figure 2 The semiconductor structure shown is subsequently formed with special functions such as a metal conductive plug (not shown) for electrically connecting the polysilicon layer 120 on the polysilicon layer 120 filled with the deep trench 101 by using semiconductor process technologies such as depositing a dielectric layer, etching, and filling metal.

[0076] It is understandable that due to the diversity of applications of semiconductor structures, in other embodiments, the Figure 2 The ion implantation region 150 may not be formed at the bottom of the deep trench 101 , but a first hard mask layer 120 covering the portion of the substrate 100 may be formed. The present invention will not describe this embodiment in detail.

[0077] See Figure 3 , Figure 3 The method for improving the deep trench isolation structure provided in the embodiment of the present invention is Figure 2 The schematic diagram of the structure of the semiconductor structure after the first grinding is shown. In the above step S104, the substrate 100 formed with the first hard mask layer 120, the second hard mask layer 130 and the polysilicon layer 140 can be placed on the first grinding disk of a chemical mechanical grinding device having three grinding disks, and then the first grinding liquid is transported to the first grinding disk carrying the substrate 100 through the first grinding liquid delivery pipeline corresponding to the first grinding disk, so as to perform the first grinding of the polysilicon layer 140 deposited on the substrate 100.

[0078] As a preferred example, the material of the first polishing liquid is silicon dioxide.

[0079] In this step, since the material of the first polishing liquid used in the first polishing is silicon dioxide and the pressure of the first polishing disk is 3psi~4psi, under the action of this high pressure and silicon dioxide polishing liquid, the large polysilicon layer 140 on the substrate 100 will be completely removed, thereby obtaining the following Figure 3 As shown in the polysilicon layer 140 ′, the surface of the polysilicon layer 140 ′ may be an uneven interface.

[0080] See Figure 4 , Figure 4 The method for improving the deep trench isolation structure provided in the embodiment of the present invention is Figure 3The schematic diagram of the structure of the semiconductor structure after the second grinding is shown. In the above step S105, the substrate 100 can be transferred from the first grinding disk to the second grinding disk by using the robot arm of the chemical mechanical grinding equipment, and then the second grinding liquid is delivered to the second grinding disk carrying the substrate 100 through the second grinding liquid delivery pipeline corresponding to the second grinding disk, so as to perform a second grinding on the polysilicon layer 140 deposited on the substrate 100.

[0081] As a preferred example, the material of the second polishing liquid is silicon dioxide, and the polishing selection ratio of the second polishing liquid to the polysilicon layer and the second hard mask layer is: 50~70, that is, 50, 51, 52, 55, 60, 65, 70, etc.

[0082] Specifically, the second grinding may include a main grinding step and an over-grinding step, wherein in the main grinding step of the second grinding, a second grinding liquid (polysilicon) adapted to the second hard mask layer 130 is used to grind the polysilicon layer 140', and the main grinding step is completed by an endpoint detection method, and the over-grinding step of the second grinding is used to continue grinding and removing the second hard mask layer 130 after the main grinding step is completed, so as to partially remove the second hard mask layer 130 in the pattern-dense area 100a and the pattern-sparse area 100b, that is, to allow part of the polysilicon layer to remain on part of the surface of the second hard mask layer, that is, to obtain a relatively flat silicon oxide interface (that is, a flat second hard mask layer 130').

[0083] Among them, in the second grinding, the pressure of the second grinding disk is: 3psi~4psi, and the grinding time of the over-grinding step is: 10s~20s, that is, it can be specifically 10s, 11s, 12s, 13s, 14s, 15s, 16s, 17s, 18s, 19s, 20s and a value between any two of the above values, but is not limited to.

[0084] In this step, since the material of the second polishing liquid used in the second polishing is silicon dioxide, the pressure of the second polishing disk is relatively high, and the second polishing liquid has a relatively large polishing selectivity for the polysilicon layer 140' and the second hard mask layer 130, and the second polishing is also provided with an over-polishing step, therefore, under the action of the polysilicon polishing liquid with high pressure and high polishing selectivity, most of the polysilicon layer 140' remaining on the substrate 100 will be removed, thereby obtaining the following Figure 4 As shown, a relatively flat second hard mask layer 130 ′ remains on the entire surface of the substrate 100 .

[0085] It should be noted that, in the second grinding in the embodiment of the present invention, a preset endpoint detection device can be used to detect the interface position during the second grinding process in real time, and then the main grinding step of the second grinding is stopped after the second hard mask layer 130 is exposed. Then, an over-grinding step of 10s to 20s is performed. If the thickness of the second hard mask layer 130 is 2000 Ǻ and the grinding selectivity of the second grinding liquid is 70, an over-grinding step of 15s is performed, so that even if some residual polysilicon material remains on the surface of the second hard mask layer 130' after the second grinding, a relatively flat second hard mask layer 130' is achieved from the overall interface of the substrate 100.

[0086] It is understandable that, since the present invention allows some polysilicon to remain during the second grinding of the substrate 100, the over-grinding time of the second grinding does not need to be set too long, that is, the over-grinding time is shortened.

[0087] See Figure 5 , Figure 5 The method for improving the deep trench isolation structure provided in the embodiment of the present invention is Figure 4 The schematic structural diagram of the semiconductor structure after the third grinding is shown. In the above step S106, the substrate 100 can be transferred from the second grinding disk to the third grinding disk by using the robot arm of the chemical mechanical grinding equipment, and then the first grinding liquid is delivered to the third grinding disk carrying the substrate 100 through the third grinding liquid delivery pipeline corresponding to the third grinding disk, so as to perform a third grinding on the second hard mask layer 130 deposited on the substrate 100.

[0088] As a preferred example, in the third grinding, the grinding time of the over-grinding step is: 8s~12s, that is, it can be specifically 8s, 9s, 10s, 11s, 12s and a value between any two of the above values. The material of the grinding liquid transported by the third grinding liquid delivery pipeline can be silicon dioxide, and the grinding selection ratio of the silicon dioxide to the second hard mask layer 130 and the first hard mask layer 120 is: 2~4, that is, it can be specifically 2, 3, 4 and a decimal thereof, etc., and when performing the third grinding, the pressure of the third grinding disk can be specifically: 1.4psi~1.8psi, that is, 1.4psi, 1.5psi, 1.6psi, 1.7psi, 1.8psi, etc.

[0089] Specifically, the third grinding may include a main grinding step and an over-grinding step, wherein in the main grinding step of the third grinding, the second hard mask layer 130' is ground using a first grinding liquid compatible with the first hard mask layer 120, and the main grinding step is completed by an endpoint detection method, and the over-grinding step of the third grinding is used to continue grinding and removing the first hard mask layer 120 after the main grinding step is completed, so as to obtain a smooth first hard mask layer 120' interface while completely removing the second hard mask layer 120 in the pattern-dense area 100a and the pattern-sparse area 100b.

[0090] In this step, since the material of the first polishing liquid used in the third polishing is silicon dioxide, the pressure of the third polishing disk is relatively small, and the polishing selectivity of the third polishing liquid on the second hard mask layer 130' and the first hard mask layer 120 is relatively small, and the third polishing is also provided with an over-polishing step. Therefore, under the action of this silicon dioxide polishing liquid with low pressure and low polishing selectivity, the second hard mask layer 130' on the substrate 100 will be completely removed, thereby obtaining the following Figure 5 As shown, a relatively smooth interface of the first hard mask layer 120 ′ remains on the entire surface of the substrate 100 .

[0091] It can be understood that during the second grinding and third grinding processes as described above, if the grinding time of each over-grinding step is well controlled, the second grinding can stop just on the surface of the second hard mask layer 110, and the third grinding can stop just on the surface of the first hard mask layer 120. The present invention does not make specific limitations on this.

[0092] In addition, based on the same concept, the present invention also provides a semiconductor process, which may specifically include the method for improving the deep trench isolation structure as described above, but is not limited thereto.

[0093] In summary, the present invention provides a method for improving a deep trench isolation structure, wherein a plurality of deep trenches are first formed on a substrate, and the substrate is divided into a pattern-dense area and a pattern-sparse area by different numbers of deep trenches in different areas, and then a film layer structure of a deep trench isolation structure is formed on the substrate, namely a first hard mask layer, a second hard mask layer and a polysilicon layer, and then the film layer structure of the deep trench isolation structure is subjected to a chemical mechanical polishing process, and the chemical mechanical polishing process is specifically divided into three grinding discs using different grinding fluids, which can achieve the unexpected effect of removing a large polysilicon layer deposited on the substrate by using the silicon oxide grinding fluid of the first grinding disc, and partially removing the remaining polysilicon layer on the substrate by using the polysilicon grinding fluid of the second grinding disc, and performing endpoint detection. By using only a relatively short over-grinding step, a relatively flat second hard mask layer interface can be obtained, in which a portion of the polysilicon layer is allowed to remain on a partial surface. The second hard mask layer on the substrate is completely removed using the silicon oxide grinding liquid of the third grinding disk, and the endpoint detection is passed again. By using only a relatively short over-grinding step, a deep trench isolation structure with no etch pits or dished pit defects on the surface and a first hard mask layer interface with a flat surface on the entire substrate including the pattern-dense area and the pattern-sparse area can be obtained. That is, the purpose of completely removing the polysilicon layer and the second hard mask layer while reducing the grinding time of the over-grinding step, improving the thickness difference of the hard mask layer between the pattern-dense area and the pattern-sparse area, and avoiding the occurrence of etch pits or dished pit defects on the surface of the formed deep trench isolation structure is achieved.

[0094] Here, based on the same inventive concept as the above-mentioned method for improving the deep trench isolation structure, the present invention can also provide a trench isolation structure, which can be specifically used as follows: Figure 1 The preparation method is shown in the figure, and the present invention will not be repeated here.

[0095] In addition, an embodiment of the present invention further provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus.

[0096] Memory for storing computer programs;

[0097] The processor is used to implement a method for improving a deep trench isolation structure provided by an embodiment of the present invention when executing a program stored in a memory.

[0098] In addition, other implementations of a method for improving a deep trench isolation structure implemented by the processor executing a program stored in the memory are the same as the implementations mentioned in the aforementioned method embodiment, and will not be repeated here.

[0099] The communication bus mentioned in the control terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. This communication bus can be divided into address buses, data buses, and control buses. For ease of illustration, the figure uses only a single thick line, but this does not mean that there is only one bus or only one type of bus.

[0100] The communication interface is used for communication between the above electronic device and other devices.

[0101] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage. Alternatively, the memory may be at least one storage device located away from the processor.

[0102] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components.

[0103] In another embodiment of the present invention, a computer-readable storage medium is provided. The computer-readable storage medium stores instructions that, when executed on a computer, enable the computer to execute the method for improving the deep trench isolation structure described in any of the above embodiments.

[0104] In the above embodiments, all or part of the embodiments can be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with the embodiments of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be magnetic media (e.g., floppy disk, hard disk, tape), optical media (e.g., DVD), or semiconductor media (e.g., solid-state disk (SSD)).

[0105] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0106] Each embodiment in this specification is described in a related manner. Similar portions between the various embodiments can be referenced to each other. Each embodiment focuses on the differences between the other embodiments. In particular, the device, electronic device, and computer-readable storage medium embodiments are generally similar to the method embodiments, so their descriptions are relatively simple. For related portions, reference can be made to the descriptions of the method embodiments.

[0107] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention are included in the scope of protection of the present invention.

Claims

1. A method for improving a deep trench isolation structure, characterized in that: include: Providing a substrate, the substrate comprising a pattern-dense area and a pattern-sparse area, wherein the pattern density of the pattern-dense area is greater than the pattern density of the pattern-sparse area, and a first hard mask layer is formed on the substrate; Etching the substrate to form a plurality of deep trenches in the substrate in the pattern-dense area and the pattern-sparse area; forming a second hard mask layer and a polysilicon layer, wherein the second hard mask layer is located on the first hard mask layer between adjacent deep trenches, and the polysilicon layer fills the deep trenches and extends to cover the second hard mask layer; performing a first grinding operation on the substrate placed on the first grinding disk using a first grinding liquid to remove a portion of the polysilicon layer; The second hard mask layer is used as a grinding stop layer, and the substrate placed on the second grinding wheel is ground for a second time using a second grinding liquid to remove the remaining polysilicon layer on the second hard mask layer, while allowing a portion of the polysilicon layer to remain on a portion of the surface of the second hard mask layer, thereby obtaining a relatively flat second hard mask layer interface. The second grinding includes an over-grinding step, and the grinding time of the over-grinding step is: 10s to 20s; Using the first hard mask layer as a grinding stop layer, the substrate placed on the third grinding wheel is ground for a third time using the first grinding slurry to remove the second hard mask layer and obtain a flat first hard mask layer interface, wherein the third grinding includes an over-grinding step, and the grinding time of the over-grinding step is 8 seconds to 12 seconds; Wherein, during the grinding, the pressure of the first grinding disk is equal to the pressure of the second grinding disk, and the pressure of the second grinding disk is greater than the pressure of the third grinding disk.

2. The method for improving the deep trench isolation structure according to claim 1, wherein: The material of the first hard mask layer includes silicon nitride, and the material of the second hard mask layer includes silicon oxide.

3. The method for improving the deep trench isolation structure according to claim 2, wherein: The material of the first polishing liquid includes silicon dioxide.

4. The method for improving the deep trench isolation structure according to claim 3, wherein: During the first grinding, the pressure of the first grinding disc is 3 psi to 4 psi.

5. The method for improving the deep trench isolation structure according to claim 2, wherein: The material of the second polishing liquid includes silicon dioxide, and the polishing selectivity ratio of the second polishing liquid to the polysilicon layer and the second hard mask layer is 50-70.

6. The method for improving the deep trench isolation structure according to claim 5, wherein: During the second grinding, the pressure of the second grinding disc is 3 psi to 4 psi.

7. The method for improving the deep trench isolation structure according to claim 2, wherein: When the first polishing liquid is used to polish the substrate placed on the third polishing disk for the third time, the polishing selection ratio of the first polishing liquid to the second hard mask layer and the first hard mask layer is 2-4.

8. The method for improving the deep trench isolation structure according to claim 7, wherein: During the third grinding, the pressure of the third grinding disc is: 1.4psi~1.8psi.

9. The method for improving the deep trench isolation structure according to claim 5, wherein: The second grinding includes a main grinding step and an over-grinding step, wherein in the main grinding step, the polysilicon layer is ground using a second grinding liquid compatible with the second hard mask layer, and the main grinding step is completed by an endpoint detection method, and the over-grinding step is used to continue grinding and removing the second hard mask layer after the main grinding step is completed, so as to remove the polysilicon layer in the pattern-dense area and the pattern-sparse area while allowing part of the polysilicon layer to remain on part of the surface of the second hard mask layer, that is, to obtain a relatively flat second hard mask layer interface.

10. The method for improving the deep trench isolation structure according to claim 8, wherein: The third grinding includes a main grinding step and an over-grinding step, wherein in the main grinding step, the second hard mask layer is ground using a first grinding liquid compatible with the first hard mask layer, and the main grinding step is completed by an endpoint detection method, and the over-grinding step is used to continue grinding and removing the first hard mask layer after the main grinding step is completed, so as to obtain a flat first hard mask layer interface while completely removing the second hard mask layer in the pattern-dense area and the pattern-sparse area.

11. The method for improving a deep trench isolation structure according to claim 1, wherein: During the process of forming the second hard mask layer, the second hard mask layer further extends to cover the inner surface of each of the deep trenches.

12. The method for improving the deep trench isolation structure according to claim 1, wherein: During the process of forming the second hard mask layer, the second hard mask layer further extends to cover the sidewall of each of the deep trenches.

13. The method for improving the deep trench isolation structure according to claim 12, wherein: Before forming the first hard mask layer on the substrate, the method further includes: A linear silicon oxide layer is formed on the substrate.

14. A semiconductor process, characterized in that: The invention comprises the method for improving the deep trench isolation structure according to any one of claims 1 to 13.

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