Trench gate SiC power device and preparation method thereof

Abstract

The present invention relates to a trench gate SiC power device and a preparation method thereof. The device comprises: a SiC substrate; an active region, comprising a plurality of cells connected in parallel, wherein any cell comprises a source trench, a first gate trench unit and a second conductive type shielding unit; a gate body is filled in the first gate trench; a source body is filled in the source trench; the second conductive type shielding unit comprises a second conductive type gate shielding body at least covering the bottom of the end of the first gate trench and a second conductive type source shielding body at least covering the bottom of the source trench; the second conductive type gate shielding body and the second conductive type source shielding body are electrically connected to the source metal above the front side of the SiC substrate; the source metal is electrically connected to the source body in the source trench, and the source metal is insulated and isolated from the gate body in the first gate trench. The present invention can effectively protect the gate oxide layer and improve the reliability of the trench gate SiC power device.

Description

Technical Field

[0001] The present invention relates to a power device and a preparation method thereof, in particular to a trench gate SiC power device and a preparation method thereof. Background Art

[0002] In response to the country's call for green and environmentally friendly energy needs, the power electronics industry is vigorously developing and iterating various types of devices to seek high power handling capabilities and low energy loss.

[0003] As the third generation wide bandgap representative, silicon carbide materials have been used in the semiconductor field for some time. Its material properties determine that such devices will inevitably shine in the medium and high voltage fields and high frequency fields. Silicon carbide-based MOSFET devices have a place in the medium and high voltage market due to their advantages such as high voltage level, high switching frequency, low dynamic and static losses, and high thermal conductivity. At the same time, domestic and foreign companies are also committed to continuously reducing the key dimensions of devices to increase current density.

[0004] As trench technology has been applied to SiC power devices, the industry has discovered that the gate oxide layer at the bottom of the trench will be subjected to the ultra-high electric field strength brought by the SiC material, which is different from power devices made of silicon-based materials. The main problems include: at the very least, it will lead to long-term reliability degradation of SiC power devices, and at worst, it will cause the gate oxide layer to be unable to withstand the operating voltage and break down.

[0005] From the above description, it can be seen that for trench SiC power devices, how to effectively protect the gate oxide layer and improve the reliability of trench SiC power devices is a technical problem that urgently needs to be solved. Summary of the invention

[0006] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a trench gate SiC power device and a preparation method thereof, which can effectively protect the gate oxide layer and improve the reliability of the trench gate SiC power device.

[0007] According to the technical solution provided by the present invention, a trench gate SiC power device comprises:

[0008] The SiC substrate is of a first conductivity type;

[0009] The active area is located in the central area of ​​the SiC substrate and includes a plurality of cells connected in parallel, wherein any cell includes a source trench, a gate first trench unit and a second conductive type shielding unit;

[0010] The gate trench unit comprises gate first trenches symmetrically distributed on both sides of the source trench, the gate first trench is in a strip shape, and the source trench is located between the two ends of the gate first trench;

[0011] A gate body is filled in the first gate trench, and the gate body is insulated and isolated from the inner wall of the first gate trench;

[0012] Filling a source body in the source trench, wherein the source body is insulated and isolated from an inner wall of the source trench;

[0013] The second conductive type shielding unit comprises a second conductive type gate shield at least covering the bottom of the end of the first trench of the gate and a second conductive type source shield at least covering the bottom of the source trench;

[0014] A second conductive type gate shield body and a second conductive type source shield body are electrically connected to a source metal on the front side of the SiC substrate;

[0015] The source metal is electrically connected to the source body in the source trench, and the source metal is insulated and isolated from the gate body in the first gate trench.

[0016] The second conductive type shielding unit further includes a second conductive type shielding first connecting body and a second conductive type shielding second connecting body, wherein:

[0017] The second conductive type source shield body is in contact and connected with the corresponding second conductive type gate shield body through the second conductive type shielding first connector;

[0018] The second conductive type shielding second connector covers the outer side wall of the source trench, the lower end of the second conductive type shielding second connector is in contact with the second conductive type source shielding body, and the upper end of the second conductive type shielding second connector is in ohmic contact with the source metal.

[0019] The second conductive type source shield, the second conductive type gate shield and the second conductive type shielding first connection are prepared and formed based on the same process steps.

[0020] The gate trench unit further includes gate second trenches symmetrically distributed on both sides of the source trench, wherein:

[0021] The second gate trench is also in a strip shape, and the length direction of the second gate trench is perpendicular to the length direction of the first gate trench;

[0022] For any gate second trench, two ends of the gate second trench are respectively connected to corresponding ends of the gate first trench, and the gate second trench is connected to the gate first trench;

[0023] The end of the second gate trench is connected to the end of the first gate trench to form a trench end node, and the second conductive type gate shield at least covers the bottom of the trench end node area;

[0024] The gate body in the second gate trench is connected to the gate body in the first gate trench as a whole, the gate body in the second gate trench is insulated and isolated from the inner wall of the second gate trench by the gate oxide layer in the second gate trench, and the gate body in the first gate trench is insulated and isolated from the inner wall of the first gate trench by the gate oxide layer in the first gate trench.

[0025] In the active region, a second conductive type base region and a first conductive type source region located in the second conductive type base region are also provided, wherein:

[0026] The second conductive type base region is located above the corresponding bottoms of the first gate trench, the second gate trench and the source trench;

[0027] The first conductive type source region is distributed on both sides of the first gate trench and the second gate trench, and the first conductive type source region is in contact with the corresponding outer side walls of the first gate trench and the second gate trench;

[0028] The source metal is in ohmic contact with the first conductivity type source region and the second conductivity type base region in the active region.

[0029] The source trench and the gate first trench in the gate trench unit have the same trench depth in the active area.

[0030] A method for preparing a trench gate SiC power device, used for preparing the above-mentioned SiC power device, the preparation method comprising:

[0031] A SiC substrate having a first conductivity type is provided, and a front cell process is performed on the front surface of the SiC substrate, wherein:

[0032] When the front cell process is performed on the front side of the SiC substrate, an active area is prepared in the central area of ​​the SiC substrate, including a plurality of cells connected in parallel;

[0033] For any cell, it includes a source trench, a gate first trench unit and a second conductive type shielding unit;

[0034] The gate trench unit comprises gate first trenches symmetrically distributed on both sides of the source trench, the gate first trench is in a strip shape, and the source trench is located between the two ends of the gate first trench;

[0035] A gate body is filled in the first gate trench, and the gate body is insulated and isolated from the inner wall of the first gate trench;

[0036] Filling a source body in the source trench, wherein the source body is insulated and isolated from an inner wall of the source trench;

[0037] The second conductive type shielding unit comprises a second conductive type gate shield at least covering the bottom of the end of the first trench of the gate and a second conductive type source shield at least covering the bottom of the source trench;

[0038] A second conductive type gate shield body and a second conductive type source shield body are electrically connected to a source metal on the front side of the SiC substrate;

[0039] The source metal is electrically connected to the source body in the source trench, and the source metal is insulated and isolated from the gate body in the first gate trench.

[0040] The front cell process of the SiC substrate includes:

[0041] Performing second conductive type impurity ion implantation on the front surface of the SiC substrate to form a second conductive type shielding layer in the SiC substrate;

[0042] Performing an epitaxial process on the front side of the SiC substrate to prepare an epitaxial layer body located on the front side of the SiC substrate, wherein the epitaxial layer body covers the second conductive type shielding layer;

[0043] A second conductive type base region and a first conductive type source region located in the second conductive type base region are prepared in the epitaxial layer body, wherein the second conductive type base region traverses the active region;

[0044] Performing a trench etching process to prepare at least a source trench and first gate trenches symmetrically distributed on both sides of the source trench, wherein the first gate trench is in a strip shape, and the source trench is located between the two ends of the first gate trench, wherein the corresponding bottoms of the first gate trench and the source trench are located below the second conductive type base region, the first conductive type source region is in corresponding contact with the corresponding outer sidewalls of the first gate trench, a second conductive type shielding body is formed based on the second conductive type shielding layer, the second conductive type gate shielding body at least covers the bottom of the end of the first gate trench, and the second conductive type source shielding body at least covers the bottom of the source trench;

[0045] Filling a gate body in the above-mentioned first gate trench and a source body in the source trench, wherein the gate body is insulated and isolated from the inner wall of the first gate trench, and the source body is insulated and isolated from the inner wall of the source trench;

[0046] Preparing an insulating dielectric layer on the epitaxial layer, wherein the insulating dielectric layer covers the first trench of the gate and the corresponding notches of the source trench;

[0047] Contact holes are etched on the insulating dielectric layer, and metal deposition is performed after the contact hole etching to prepare at least source metal and gate metal, wherein the gate metal is electrically connected to the gate bodies in all the first gate grooves, the source metal is electrically connected to the source bodies in the source grooves, and the source metal is electrically connected to the second conductive type gate shield and the second conductive type source shield.

[0048] The second conductive type shielding unit further includes a second conductive type shielding first connecting body and a second conductive type shielding second connecting body, wherein:

[0049] The second conductive type source shield is in contact with and connected to the corresponding second conductive type gate shield through the second conductive type shielding first connector, and the second conductive type source shield, the second conductive type gate shield and the second conductive type shielding first connector are prepared and formed based on the same process steps;

[0050] After the source trench is prepared, second conductivity type impurity ions are implanted in the source trench to prepare a second conductivity type shielding second connector, the second conductivity type shielding second connector covers the outer side wall of the source trench, and the lower end of the second conductivity type shielding second connector contacts the second conductivity type source shielding body;

[0051] The upper end of the second conductive type shielding second connection body is in ohmic contact with the source metal.

[0052] During the trench etching, second gate trenches symmetrically distributed on both sides of the source trench are also prepared, wherein:

[0053] The second gate trench is also in a strip shape, and the length direction of the second gate trench is perpendicular to the length direction of the first gate trench;

[0054] For any gate second trench, two ends of the gate second trench are respectively connected to corresponding ends of the gate first trench, and the gate second trench is connected to the gate first trench;

[0055] The end of the second gate trench is connected to the end of the first gate trench to form a trench end node, and the second conductive type gate shield at least covers the bottom of the trench end node area;

[0056] The gate body in the second gate trench is connected to the gate body in the first gate trench as a whole, the gate body in the second gate trench is insulated and isolated from the inner wall of the second gate trench by the gate oxide layer in the second gate trench, and the gate body in the first gate trench is insulated and isolated from the inner wall of the first gate trench by the gate oxide layer in the first gate trench.

[0057] The advantages of the present invention are as follows: a second conductive type gate shield is arranged at least below the bottom of the first trench end of the gate, a second conductive type source shield is arranged below the bottom of the source trench, the second conductive type gate shield at least covers the bottom of the first trench end of the gate, the second conductive type source shield covers the bottom of the source trench, the second conductive type source shield is contacted and connected with the second conductive type gate shield through the second conductive type shielding first connector, and is contacted and connected with the second conductive type shielding second connector, so that the second conductive type gate shield, the second conductive type source shield and the source metal are electrically connected through the second conductive type shielding second connector and the ohmic contact with the source metal;

[0058] When the power device is in a reverse bias state, the peak value of the electric field strength is located at the PN junction below the first gate trench and the source trench, and the gate oxide layer in the first gate trench is protected by the depletion broadening of the second conductive type gate shield and will not withstand high electric field strength, thereby avoiding failure of the gate oxide layer. The gate oxide layer can also be effectively protected, thereby improving the reliability of the trench gate SiC power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 A top view of an embodiment of a SiC power device of the present invention.

[0060] Figure 2 to Figure 8 This is a cross-sectional view of a specific implementation process step of the SiC power device of the present invention, wherein:

[0061] Figure 2 This is a cross-sectional view of an embodiment of the present invention after a P-type shielding unit is prepared.

[0062] Figure 3 This is a cross-sectional view of an embodiment of the present invention after the N+ source region is prepared.

[0063] Figure 4 This is a cross-sectional view of an embodiment of the present invention after the first trench of the gate is prepared.

[0064] Figure 5 A cross-sectional view of an embodiment of the present invention after a gate body and a source body are prepared.

[0065] Figure 6 This is a cross-sectional view of an embodiment of the present invention after the source metal is prepared.

[0066] Figure 7 For along Figure 1 A cross-sectional view of an embodiment taken along the BB axis.

[0067] Figure 8 For along Figure 1 A cross-sectional view of an embodiment taken along the CC axis.

[0068] Explanation of the accompanying drawings: 1-gate first trench, 2-gate second trench, 3-P-type gate shield, 4-source trench, 5-P-type source shield, 6-P-type shielding first connector, 7-epitaxial base layer, 8-P-type shielding layer, 9-epitaxial layer body, 10-P-type base region, 11-N+ source region, 12-substrate epitaxial layer, 13-gate body, 14-gate oxide layer, 15-source metal, 16-insulating dielectric layer, 17-source body, 18-source oxide layer, 19-P-type shielding second connector. DETAILED DESCRIPTION

[0069] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0070] In order to effectively protect the gate oxide layer 14 and improve the reliability of the trench gate SiC power device, for the trench gate SiC power device, taking the first conductivity type as N type as an example, in one embodiment of the present invention, the SiC power device includes:

[0071] SiC substrate, N conductivity type;

[0072] The active area is located in the central area of ​​the SiC substrate, and includes a plurality of cells connected in parallel, wherein any cell includes a source trench 4, a gate first trench unit, and a P-type shielding unit;

[0073] The gate trench unit comprises a gate first trench 1 symmetrically distributed on both sides of the source trench 4, wherein the gate first trench 1 is in a strip shape, and the source trench 4 is located between the two ends of the gate first trench 1;

[0074] A gate body 13 is filled in the first gate trench 1, and the gate body 13 is insulated and isolated from the inner wall of the first gate trench 1;

[0075] Filling a source body 17 in the source trench 4, wherein the source body 17 is insulated and isolated from the inner wall of the source trench 4;

[0076] The P-type shielding unit comprises a P-type gate shielding body 3 at least covering the bottom of the end of the first gate trench 1 and a P-type source shielding body 5 at least covering the bottom of the source trench 4;

[0077] The P-type gate shield 3 and the P-type source shield 5 are electrically connected to the source metal 15 on the front surface of the SiC substrate;

[0078] The source metal 15 is electrically connected to the source body 17 in the source trench 4 , and the source metal 17 is insulated and isolated from the gate body 13 in the first gate trench 1 .

[0079] It is known to those skilled in the art that when the first conductivity type is N type, the second conductivity type is P type. The SiC substrate is of N conductivity type, and the condition of the SiC substrate can be consistent with the existing conditions. For power devices, an active region is generally prepared in the central region of the SiC substrate. The active region is the functional region of the power device. The active region generally includes a plurality of cells, and the cells in the active region are generally connected in parallel.

[0080] For any cell in the active area, in one embodiment of the present invention, it includes a source trench 4, a gate first trench unit and a P-type shielding unit. Generally, the source trench 4 and the gate first trench 1 in the gate first trench unit extend vertically from the front side of the SiC substrate to the back side. The source trench 4 and the gate first trench 1 in the gate trench unit have the same trench depth in the active area. At this time, the source trench 4 and the gate first trench 1 can be prepared by the same trench etching.

[0081] In a specific implementation, the gate trench unit includes at least two gate first trenches 1, both of which are long strips and parallel to each other, and the source trench 4 can be columnar, etc. The length of the source trench 4 is less than the length of the gate first trench 1. At this time, the source trench 4 is located between the two corresponding ends of the gate first trench 1. The length direction of the gate first trench 1 specifically refers to Figure 1 The direction of the length of the first trench 1 of the middle gate is Figure 1 A gate body 13 is filled in the first gate trench 1. The gate body 13 is distributed along the length direction of the first gate trench 1. The gate body 13 is generally made of conductive polysilicon. Of course, it can also be made of metal material. The specific situation of the gate body 13 can be selected according to actual application requirements.

[0082] A source body 17 is filled in the source trench 4. Similar to the gate body 13, the source body 17 can be made of conductive polysilicon or metal material. The material of the source body 17 can be the same as that of the gate body 13 or different, and can be selected according to needs. A source oxide layer 18 is provided on the inner wall of the source trench 4, and the source body 17 is insulated and isolated from the inner wall of the source trench 4 through the source oxide layer 18. Similarly, a gate oxide layer 14 is provided in the first gate trench 1, and the gate body 13 is insulated and isolated from the inner wall of the first gate trench 1 through the gate oxide layer 14. The gate oxide layer 14 and the source oxide layer 13 are silicon dioxide layers, which can generally be prepared by the same process.

[0083] In order to effectively protect the gate oxide layer 14 in the first gate trench 1, a P-type shielding unit is also prepared in the active area, wherein the P-type shielding unit includes a P-type gate shield 3 and a P-type source shield 5. The P-type gate shield 3 can be used to cover the bottom of the end of the first gate trench 1, and the P-type source shield 5 can be used to cover the bottom of the source trench 4, wherein the covering refers to contacting with the corresponding bottom of the trench to form an encirclement, such as the P-type source shield 5 covering the bottom of the source trench 4, specifically refers to the P-type source shield 5 contacting the bottom of the source trench 4 and forming an encirclement.

[0084] When the power device is a MOSFET device, a source metal 15 is generally prepared on the SiC substrate. In one embodiment of the present invention, the source metal 15 is electrically connected to at least the P-type gate shield 3, the P-type source shield 5, and the source body 17. At this time, the source metal 15 can be used to form the source electrode of the MOSFET device. Of course, when the power device is an IGBT device, the source metal 15 can be used to form the emitter of the IGBT device. The electrical connection with the source metal 15 specifically refers to the formation of a conductive connection state. As described above, when the source body 17 is made of conductive polysilicon, an ohmic contact is formed between the source metal 15 and the source body 17.

[0085] In addition, the gate body 13 is generally electrically connected to the gate metal above the front side of the SiC substrate. The gate metal is not shown in the drawings of the present invention. At this time, the gate metal can be used to form a gate electrode of a MOSFET type device, or a gate electrode of an IGBT type device.

[0086] In a specific implementation, the P-type gate shield 3, the P-type source shield 5 and the SiC substrate form a PN junction. When the power device is in a reverse bias state, the peak value of the electric field strength is located at the PN junction below the first gate trench 1 and the source trench 4, and the gate oxide layer 14 in the first gate trench is protected by the depletion broadening of the P-type gate shield 3 and will not withstand high electric field strength, thereby avoiding failure of the gate oxide layer 14, and effectively protecting the gate oxide layer 14, thereby improving the reliability of the trench gate SiC power device.

[0087] Figure 1 FIG. 4 shows a top view of a cell of the present invention, Figure 2 to Figure 6 Middle along Figure 1 Sectional view along AA direction, Figure 7 For along Figure 1 The cross-sectional view of BB, Figure 8 For along Figure 1 CC section view in.

[0088] Figure 1 In the embodiment, the gate trench unit further includes gate second trenches 2 symmetrically distributed on both sides of the source trench 4, wherein:

[0089] The second gate trench 2 is also in the shape of a long strip, and the length direction of the second gate trench 2 is perpendicular to the length direction of the first gate trench 1;

[0090] For any gate second trench 2, two ends of the gate second trench 2 are respectively connected to corresponding ends of the gate first trench 1, and the gate second trench 2 is connected to the gate first trench 1;

[0091] The end of the second gate trench 2 is connected to the end of the first gate trench 1 to form a trench end node, and the P-type gate shield 3 at least covers the bottom of the trench end node area;

[0092] The gate body 13 in the second gate trench 2 and the gate body 13 in the first gate trench 1 are connected to each other as a whole, and the gate body 13 in the second gate trench 2 is insulated and isolated from the inner wall of the second gate trench 2 by the gate oxide layer 14 in the second gate trench 2, and the gate body 13 in the first gate trench 1 is insulated and isolated from the inner wall of the first gate trench 1 by the gate oxide layer 13 in the first gate trench 1.

[0093] Figure 1 In the figure, the second gate trench 2 is also symmetrically distributed on both sides of the source trench 4. The second gate trench 2 and the first gate trench 1 are connected end to end in sequence to form a square or circular ring structure, and the source trench 4 is located in the center of the square or circular arc. Generally, the second gate trench 2 and the first gate trench 1 can be prepared by the same process, and the second gate trench 2 and the first gate trench 1 are interconnected. Of course, the second gate trench 2 generally needs to be provided with a gate oxide layer 14 and filled with a gate body 13. The gate body 13 in the second gate trench 2 and the gate body 13 in the first gate trench 1 are connected to each other as a whole. The situation of the gate body 13 and the gate oxide layer 14 in the second gate trench 2 can refer to the description in the first gate trench 1 above. The gate body 13 in the second gate trench 2 also needs to be electrically connected to the gate metal.

[0094] Figure 1 In the embodiment, the end connection portion of the first gate trench 2 corresponding to the first gate trench 1 forms a trench end node. At this time, the P-type gate shield 3 at least covers the bottom of the trench end node region, and the width of the P-type gate shield 3 is greater than the width of the trench end node. Figure 1 and Figure 6 shown.

[0095] In one embodiment of the present invention, the P-type shielding unit further includes a P-type shielding first connector 6 and a P-type shielding second connector 19, wherein:

[0096] The P-type source shield 5 is in contact and connected with the corresponding P-type gate shield 3 through the P-type shield first connector 6;

[0097] The P-type shielding second connector 19 covers the outer wall of the source trench 4 , the lower end of the P-type shielding second connector 19 is in contact with the P-type source shielding body 5 , and the upper end of the P-type shielding second connector 19 is in ohmic contact with the source metal 15 .

[0098] Figure 1 In the embodiment, four P-type gate shields 3 are arranged on the outer circle of the source trench 4. At this time, the source trench 4 is in contact with the corresponding P-type gate shield 3 through at least four P-type shielding first connectors 6. The contact connection is that one end of the P-type shielding first connector 6 is in contact with the P-type gate shield 3, and the other end of the P-type shielding first connector 6 is in contact with the P-type source shield 5. At this time, the P-type source shield 5 can be in contact with the corresponding P-type gate shield 3 through a P-type shielding first connector 6. Figure 1 In the embodiment, the P-type shielding first connector 6 is distributed obliquely. Generally, the P-type source shielding body 5, the P-type gate shielding body 3 and the P-type shielding first connector 6 can be prepared based on the same process steps.

[0099] Figure 7 In the embodiment, the P-type shielding second connector 19 covers the outer side wall of the source trench 4. At this time, the lower end of the P-type shielding second connector 19 is in contact and connection with the P-type source shield 5, and the upper end of the P-type shielding second connector 19 is in ohmic contact with the source metal 15. Thus, the source metal 15 is electrically connected to the P-type gate shield 3 and the P-type source shield 5 through the ohmic contact between the source metal 15 and the P-type shielding second connector 19.

[0100] As can be seen from the above description, the P-type gate shield 3 and the P-type source shield 5 form a mesh shielding form, which can effectively protect the corresponding gate oxide layer 14 in the first gate trench 1 and the second gate trench 2. Through the source trench 4 and the source body 17 in the source trench 4, when the source metal 15 is grounded, the P-type gate shield 3 and the P-type source shield 5 can be shortened to restore the corresponding response time, reduce switching losses, and enhance the stability of the power device.

[0101] In one embodiment of the present invention, a P-type base region 10 and an N+ source region 11 located in the P-type base region 10 are further provided in the active region, wherein:

[0102] The P-type base region 10 is located above the bottoms of the first gate trench 1, the second gate trench 2 and the source trench 4;

[0103] The N+ source region 11 is distributed on both sides of the first gate trench 1 and the second gate trench 2, and the N+ source region 11 is in contact with the corresponding outer sidewalls of the first gate trench 1 and the second gate trench 2;

[0104] The source metal 15 is in ohmic contact with the N+ source region 11 and the P-type base region 10 in the active region.

[0105] Generally, the P-type base region 10 is located in the substrate epitaxial layer 12, such as Figure 6 , Figure 7 and Figure 8 As shown, the P-type base region 10 generally traverses the active region, and the N+ source region 11 is located in the P-type base region 10 , and the P-type base region 10 is located above the corresponding bottoms of the first gate trench 1 , the second gate trench 2 , and the source trench 4 .

[0106] In a specific implementation, the length of the N+ source region 11 may be smaller than the length of the first gate trench 1. Figure 6 1 shows an embodiment in which the length of the N+ source region 11 is less than the length of the first gate trench 1. In this case, the N+ source region 11 may not be provided in the trench end node region formed at the corresponding ends of the first gate trench 1 and the second gate trench 2. Of course, in a specific implementation, the N+ source region 11 may also be distributed along the length of the first gate trench 1 and the second gate trench 2, such as Figure 8 As shown, you can choose according to your needs. Figure 6 In the embodiment, when the N+ source region 11 is not provided in the trench end node region, the channel distribution of the entire power device can be optimized, and the characteristic resistance can be reduced while ensuring the normal operation of the power device.

[0107] The above power device can be prepared by the following process steps. Specifically, the preparation method includes:

[0108] A SiC substrate having an N conductive type is provided, and a front cell process is performed on the front side of the SiC substrate, wherein:

[0109] When the front cell process is performed on the front side of the SiC substrate, an active area is prepared in the central area of ​​the SiC substrate, including a plurality of cells connected in parallel;

[0110] For any cell, it includes a source trench 4, a gate first trench unit and a P-type shielding unit;

[0111] The gate trench unit comprises a gate first trench 1 symmetrically distributed on both sides of the source trench 4, wherein the gate first trench 1 is in a strip shape, and the source trench 4 is located between the two ends of the gate first trench 1;

[0112] A gate body 13 is filled in the first gate trench 1, and the gate body 13 is insulated and isolated from the inner wall of the first gate trench 1;

[0113] Filling a source body 17 in the source trench 4, wherein the source body 17 is insulated and isolated from the inner wall of the source trench 4;

[0114] The P-type shielding unit comprises a P-type gate shielding body 3 at least covering the bottom of the end of the first gate trench 1 and a P-type source shielding body 5 at least covering the bottom of the source trench 4;

[0115] The P-type gate shield 13 and the P-type source shield 5 are electrically connected to the source metal 15 on the front surface of the SiC substrate;

[0116] The source metal 15 is electrically connected to the source body 17 in the source trench 4 , and the source metal 17 is insulated and isolated from the gate body 13 in the first gate trench 1 .

[0117] The conditions of SiC substrate, active area and cells in the active area can be referred to the above description. Figure 2 to Figure 8 The preparation process of the power device of the present invention is described. Specifically, the front cell process of the SiC substrate includes:

[0118] Performing P-type impurity ion implantation on the front side of the SiC substrate to form a P-type shielding layer 8 in the SiC substrate;

[0119] Performing an epitaxial process on the front side of the SiC substrate to prepare an epitaxial layer body 9 located on the front side of the SiC substrate, wherein the epitaxial layer body 9 covers the P-type shielding layer 8;

[0120] A P-type base region 10 and an N+ source region 11 located in the P-type base region 10 are prepared in the epitaxial layer 9, wherein the P-type base region 10 traverses the active region;

[0121] A trench etching process is performed to prepare at least a source trench 4 and gate first trenches 1 symmetrically distributed on both sides of the source trench 4, wherein the gate first trench 1 is in a long strip shape, and the source trench 4 is located between the two ends of the gate first trench 1, wherein the corresponding bottoms of the gate first trench 1 and the source trench 4 are located below the P-type base region 10, the N+ source region 11 is in corresponding contact with the corresponding outer sidewall of the gate first trench 1, a P-type shielding body is formed based on the P-type shielding layer 8, the P-type gate shielding body 3 at least covers the bottom of the end of the gate first trench 1, and the P-type source shielding body 5 at least covers the bottom of the source trench 4;

[0122] A gate body 13 is filled in the first gate trench 1, and a source body 17 is filled in the source trench 4, wherein the gate body 13 is insulated and isolated from the inner wall of the first gate trench 1, and the source body 17 is insulated and isolated from the inner wall of the source trench 4;

[0123] An insulating dielectric layer 16 is prepared on the epitaxial layer 9, wherein the insulating dielectric layer 16 covers the first gate trench 1 and the corresponding notches of the source trench 4;

[0124] Contact holes are etched on the insulating dielectric layer 16, and metal deposition is performed after the contact hole etching to prepare at least a source metal 15 and a gate metal, wherein the gate metal is electrically connected to the gate body 13 in all the first gate trenches 1, the source metal 15 is electrically connected to the source body 17 in the source trench 4, and the source metal 16 is electrically connected to the P-type gate shield 3 and the P-type source shield 5.

[0125] Figure 2 In the present invention, a SiC substrate generally includes an epitaxial base layer 7, and P-type impurity ions can be implanted on the epitaxial base layer 7. At this time, a P-type shielding layer 8 can be prepared. It can be seen from the above description that the P-type shielding layer 8 at least includes a P-type gate shield 3 and a P-type source shield 5, and the P-type gate shield 3 is distributed in the outer circle of the P-type source shield 5; the process conditions and process of preparing the P-type shielding layer 8 by the specific ion implantation process can be selected according to needs, so as to prepare the above-mentioned P-type gate shield 3 and P-type source shield 5.

[0126] Figure 3 In the embodiment, an epitaxial process is performed on the epitaxial base layer 7 to prepare an epitaxial layer body 9, and a substrate epitaxial layer 12 can be formed using the epitaxial base layer 7 and the epitaxial layer body 9. After the epitaxial layer body 9 is prepared, P-type impurity ion implantation and N-type impurity ion implantation can be performed in sequence to prepare a P-type base region 10 and an N+ source region 11 in sequence. The distribution of the P-type base region 10 and the N+ source region 11 can refer to the above description.

[0127] Figure 4 In the process, the epitaxial layer 9 is subjected to trench etching to prepare the source trench 4 and the first gate trench 1. Generally, the source trench 4 and the first gate trench 1 have the same trench depth. Preferably, the source trench 4 and the first gate trench 1 can be prepared by the same trench etching process. The process conditions and process of the trench etching can be consistent with the existing ones, and the source trench 4 and the first gate trench 1 can be prepared.

[0128] Figure 4 In the embodiment, the corresponding groove depths of the source groove 4 and the first gate groove 1 are greater than the thickness of the epitaxial layer 9. At this time, the corresponding groove bottoms of the source groove 4 and the first gate groove 1 enter the epitaxial base layer 7, so that the P-type source shield 5 can be used to at least cover the groove bottom of the source groove 4, and the P-type gate shield 3 can be used to at least cover the groove bottom of the end of the first gate groove 1; the situation in which the P-type gate shield 3 covers the groove bottom of the end of the first gate groove 1 can refer to the above description, which will not be repeated here.

[0129] Figure 5 In the embodiment, a gate oxide layer 14 and a source oxide layer 18 can be prepared by a thermal oxidation process, wherein the gate oxide layer 14 covers the corresponding inner wall of the first gate trench 1, and the source oxide layer 18 covers the corresponding inner wall of the source trench 4. The situation that the gate oxide layer 14 covers the corresponding inner wall of the second gate trench 2 is not shown. Thereafter, the gate body 13 is filled in the first gate trench 1, and the source body 17 is filled in the source trench 4. The specific situation of the gate body 13 and the source body 17 can refer to the above description.

[0130] Figure 6 In the process, an insulating dielectric layer 16 is prepared on the epitaxial layer body 9. The insulating dielectric layer 16 can be made of commonly used insulating dielectric materials. The specific material type can be selected according to needs. The insulating dielectric layer 16 covers the epitaxial layer body 9 and covers the corresponding notches of the source first trench 1 and the source trench 4.

[0131] In order to meet the corresponding electrical connection of the source metal 16, it is necessary to etch the contact hole of the insulating dielectric layer 16. The method and position of the contact hole etching can be selected according to the needs, so as to meet the electrical connection of the source metal 16. After the contact hole etching, the metal deposition is performed using the process commonly used in the technical field. At this time, the source metal 15 and the gate metal can be prepared, and the source metal 15 is electrically connected to the source body 17.

[0132] In one embodiment of the present invention, the P-type shielding unit further includes a P-type shielding first connector 6 and a P-type shielding second connector 19, wherein:

[0133] The P-type source shield 5 is in contact with and connected to the corresponding P-type gate shield 3 through the P-type shielding first connector 6, and the P-type source shield 5, the P-type gate shield 3 and the P-type shielding first connector 6 are prepared and formed based on the same process steps;

[0134] After the source trench 4 is prepared, P-type impurity ions are implanted in the source trench 4 to prepare a P-type shielding second connector 19, the P-type shielding second connector 19 covers the outer wall of the source trench 4, and the lower end of the P-type shielding second connector 19 contacts the P-type source shielding body 5;

[0135] An upper end portion of the P-type shielding second connection body 19 is in ohmic contact with the source metal 16 .

[0136] In specific implementation, when the P-type shielding layer 8 is prepared as described above, the P-type shielding first connector 6 can also be prepared at the same time. After the source trench 4 is prepared, P-type impurity ions are implanted in the source trench 4 to form the P-type shielding second connector 19. The conditions and process of implanting the P-type impurity ions in the source trench 4 can be selected as needed, so as to prepare the P-type shielding second connector 19.

[0137] As can be seen from the above description, when the P-type shielding second connector 19 is prepared, the source metal 15 is in ohmic contact with the P-type shielding second connector 19, and is in ohmic contact with the N+ source region 11 and the corresponding P-type base region 10. Figure 7 shown.

[0138] In one embodiment of the present invention, during the trench etching, second gate trenches 2 symmetrically distributed on both sides of the source trench are also prepared, wherein:

[0139] The second gate trench 2 is also in the shape of a long strip, and the length direction of the second gate trench 2 is perpendicular to the length direction of the first gate trench 1;

[0140] For any gate second trench 2, two ends of the gate second trench 2 are respectively connected to corresponding ends of the gate first trench 1, and the gate second trench 2 is connected to the gate first trench 1;

[0141] The end of the second gate trench 2 is connected to the end of the first gate trench 1 to form a trench end node, and the P-type gate shield 3 at least covers the bottom of the trench end node area;

[0142] The gate body 13 in the second gate trench 2 and the gate body 13 in the first gate trench 1 are connected to each other as a whole, and the gate body 13 in the second gate trench 2 is insulated and isolated from the inner wall of the second gate trench 2 by the gate oxide layer 14 in the second gate trench 2, and the gate body 13 in the first gate trench 1 is insulated and isolated from the inner wall of the first gate trench 1 by the gate oxide layer 13 in the first gate trench 1.

[0143] When the gate second trench 2 is included at the same time, the gate second trench 2 is generally prepared by the same trench etching process as the source trench 4 and the gate first trench 1. In addition, when the gate oxide layer 14 is prepared, the gate oxide layer 14 will cover the inner wall of the gate second trench 2 at the same time, and the gate body 13 will be filled in the gate second trench 2 covered with the gate oxide layer 14. The situation of the P-type gate shield 3 can refer to the above description, which will not be repeated here.

[0144] The above gives an embodiment of the front cell process. Of course, the front cell process can also be in other forms, subject to the ability to prepare the active area. After the front cell process is prepared, a back process needs to be performed on the back of the SiC substrate to prepare the back structure using the back process. The back process and the prepared back structure can be selected as needed to form the required power device.

Claims

1. A trench gate SiC power device, characterized in that: The SiC power device comprises: The SiC substrate is of a first conductivity type; The active area is located in the central area of ​​the SiC substrate and includes a plurality of cells connected in parallel, wherein any cell includes a source trench, a gate first trench unit and a second conductive type shielding unit; The gate trench unit comprises gate first trenches symmetrically distributed on both sides of the source trench, the gate first trench is in a strip shape, and the source trench is located between the two ends of the gate first trench; A gate body is filled in the first gate trench, and the gate body is insulated and isolated from the inner wall of the first gate trench; Filling a source body in the source trench, wherein the source body is insulated and isolated from an inner wall of the source trench; The second conductive type shielding unit comprises a second conductive type gate shield at least covering the bottom of the end of the first trench of the gate and a second conductive type source shield at least covering the bottom of the source trench; A second conductive type gate shield body and a second conductive type source shield body are electrically connected to a source metal on the front side of the SiC substrate; The source metal is electrically connected to the source body in the source trench, and the source metal is insulated and isolated from the gate body in the first gate trench; The second conductive type shielding unit further includes a second conductive type shielding first connecting body and a second conductive type shielding second connecting body, wherein: The second conductive type source shield body is in contact and connected with the corresponding second conductive type gate shield body through the second conductive type shielding first connector; The second conductive type shielding second connector covers the outer side wall of the source trench, the lower end of the second conductive type shielding second connector is in contact with the second conductive type source shielding body, and the upper end of the second conductive type shielding second connector is in ohmic contact with the source metal; The gate trench unit further includes gate second trenches symmetrically distributed on both sides of the source trench, wherein: The second gate trench is also in a strip shape, and the length direction of the second gate trench is perpendicular to the length direction of the first gate trench; For any gate second trench, two ends of the gate second trench are respectively connected to corresponding ends of the gate first trench, and the gate second trench is connected to the gate first trench; The end of the second gate trench is connected to the end of the first gate trench to form a trench end node, and the second conductive type gate shield at least covers the bottom of the trench end node area; The gate body in the second gate trench is connected to the gate body in the first gate trench as a whole, the gate body in the second gate trench is insulated and isolated from the inner wall of the second gate trench by the gate oxide layer in the second gate trench, and the gate body in the first gate trench is insulated and isolated from the inner wall of the first gate trench by the gate oxide layer in the first gate trench; the width of the second conductive type gate shield is greater than the width of the trench end node.

2. The trench gate SiC power device according to claim 1, characterized in that: The second conductive type source shield, the second conductive type gate shield and the second conductive type shielding first connection are prepared and formed based on the same process steps.

3. The trench gate SiC power device according to claim 1, characterized in that: A second conductive type base region and a first conductive type source region located in the second conductive type base region are also provided in the active region, wherein: The second conductive type base region is located above the corresponding bottoms of the first gate trench, the second gate trench and the source trench; The first conductive type source region is distributed on both sides of the first gate trench and the second gate trench, and the first conductive type source region is in contact with the corresponding outer side walls of the first gate trench and the second gate trench; The source metal is in ohmic contact with the first conductivity type source region and the second conductivity type base region in the active region.

4. The trench gate SiC power device according to any one of claims 1 to 3, characterized in that: The source trench and the gate first trench in the gate trench unit have the same trench depth in the active area.

5. A method for preparing a trench gate SiC power device, characterized in that it is used for Prepare the SiC power device according to any one of claims 1 to 4, the preparation method comprising: A SiC substrate having a first conductivity type is provided, and a front cell process is performed on the front surface of the SiC substrate, wherein: When the front cell process is performed on the front side of the SiC substrate, an active area is prepared in the central area of ​​the SiC substrate, including a plurality of cells connected in parallel; For any cell, it includes a source trench, a gate first trench unit and a second conductive type shielding unit; The gate trench unit comprises gate first trenches symmetrically distributed on both sides of the source trench, the gate first trench is in a strip shape, and the source trench is located between the two ends of the gate first trench; A gate body is filled in the first gate trench, and the gate body is insulated and isolated from the inner wall of the first gate trench; Filling a source body in the source trench, wherein the source body is insulated and isolated from an inner wall of the source trench; The second conductive type shielding unit comprises a second conductive type gate shield at least covering the bottom of the end of the first trench of the gate and a second conductive type source shield at least covering the bottom of the source trench; A second conductive type gate shield body and a second conductive type source shield body are electrically connected to a source metal on the front side of the SiC substrate; The source metal is electrically connected to the source body in the source trench, and the source metal is insulated and isolated from the gate body in the first gate trench; The front cell process of the SiC substrate includes: Performing second conductive type impurity ion implantation on the front surface of the SiC substrate to form a second conductive type shielding layer in the SiC substrate; Performing an epitaxial process on the front side of the SiC substrate to prepare an epitaxial layer body located on the front side of the SiC substrate, wherein the epitaxial layer body covers the second conductive type shielding layer; A second conductive type base region and a first conductive type source region located in the second conductive type base region are prepared in the epitaxial layer body, wherein the second conductive type base region traverses the active region; Performing a trench etching process to prepare at least a source trench and first gate trenches symmetrically distributed on both sides of the source trench, wherein the first gate trench is in a strip shape, and the source trench is located between the two ends of the first gate trench, wherein the corresponding bottoms of the first gate trench and the source trench are located below the second conductive type base region, the first conductive type source region is in corresponding contact with the corresponding outer sidewalls of the first gate trench, a second conductive type shielding body is formed based on the second conductive type shielding layer, the second conductive type gate shielding body at least covers the bottom of the end of the first gate trench, and the second conductive type source shielding body at least covers the bottom of the source trench; Filling a gate body in the above-mentioned first gate trench and filling a source body in the source trench, wherein the gate body is insulated and isolated from the inner wall of the first gate trench, and the source body is insulated and isolated from the inner wall of the source trench; Preparing an insulating dielectric layer on the epitaxial layer, wherein the insulating dielectric layer covers the first trench of the gate and the corresponding notches of the source trench; Performing contact hole etching on the insulating dielectric layer, and performing metal deposition after the contact hole etching, so as to prepare at least source metal and gate metal, wherein the gate metal is electrically connected to the gate bodies in all the first gate trenches, the source metal is electrically connected to the source bodies in the source trenches, and the source metal is electrically connected to the second conductive type gate shield and the second conductive type source shield; The second conductive type shielding unit further includes a second conductive type shielding first connecting body and a second conductive type shielding second connecting body, wherein: The second conductive type source shield is in contact with and connected to the corresponding second conductive type gate shield through the second conductive type shielding first connector, and the second conductive type source shield, the second conductive type gate shield and the second conductive type shielding first connector are prepared and formed based on the same process steps; After the source trench is prepared, second conductivity type impurity ions are implanted in the source trench to prepare a second conductivity type shielding second connector, the second conductivity type shielding second connector covers the outer side wall of the source trench, and the lower end of the second conductivity type shielding second connector contacts the second conductivity type source shielding body; The upper end of the second conductive type shielding second connection body is in ohmic contact with the source metal.

6. The method for preparing a trench gate SiC power device according to claim 5, wherein During the trench etching, second gate trenches symmetrically distributed on both sides of the source trench are also prepared, wherein: The second gate trench is also in a strip shape, and the length direction of the second gate trench is perpendicular to the length direction of the first gate trench; For any gate second trench, two ends of the gate second trench are respectively connected to corresponding ends of the gate first trench, and the gate second trench is connected to the gate first trench; The end of the second gate trench is connected to the end of the first gate trench to form a trench end node, and the second conductive type gate shield at least covers the bottom of the trench end node area; The gate body in the second gate trench is connected to the gate body in the first gate trench as a whole, the gate body in the second gate trench is insulated and isolated from the inner wall of the second gate trench by the gate oxide layer in the second gate trench, and the gate body in the first gate trench is insulated and isolated from the inner wall of the first gate trench by the gate oxide layer in the first gate trench.

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