A preparation method and structure for reducing the capacitance of a laser chip

Abstract

The application discloses a preparation method and structure for reducing the capacitance of a laser chip, and the method comprises the following steps: forming a passivated Pad layer on a P surface bonding area of a passivation layer of the chip, wherein the Pad layer is a medium layer with low adhesion to a gold layer; manufacturing a P surface electrode on the chip, and part of the P surface electrode is located on the Pad layer; based on the low adhesion between the passivated Pad layer and the gold layer, when a gold wire is bonded with the P surface electrode, the gold wire pulls up the part of the P surface electrode located on the Pad layer, and the gold wire and the P surface electrode remain connected. By filling a medium layer with low adhesion to the gold layer in the P surface electrode bonding area, the P electrode layer is pulled up when the gold wire is bonded through the bonding process, which is equivalent to greatly reducing the metal area of the P surface electrode, so that the capacitance of the chip electrode is greatly reduced.

Description

Technical Field

[0001] This invention belongs to the field of laser technology, and more specifically, relates to a method and structure for reducing the capacitance of a laser chip. Background Technology

[0002] Semiconductor lasers, also known as laser diodes, are lasers that use semiconductor materials as their active medium. Due to differences in material structure, the specific processes by which different types of active mediums generate laser light are quite unique. Commonly used active mediums include gallium arsenide (GaAs), cadmium sulfide (CdS), indium phosphide (InP), and zinc sulfide (ZnS). Excitation methods include electrical injection, electron beam excitation, and optical pumping. Semiconductor laser devices can be classified into several types, such as homojunction, single heterojunction, and double heterojunction lasers. Homojunction lasers and single heterojunction lasers are mostly pulsed devices at room temperature, while double heterojunction lasers can achieve continuous operation at room temperature.

[0003] Semiconductor lasers possess advantages such as small size, light weight, low cost, and ease of mass production, making them promising for applications in optical storage, optical communication, and defense. As the application of semiconductor laser devices becomes increasingly widespread, the requirements for their modulation rates are becoming more stringent. To improve the modulation rate of semiconductor lasers, besides increasing the differential gain at the epitaxial wafer structure level, the modulation bandwidth can also be increased by reducing the electrode capacitance during the electrode fabrication process. Reducing electrode capacitance typically involves shrinking the area of ​​the p-electrode and filling it with a low-dielectric-constant material. However, the p-electrode area cannot be continuously reduced; a certain area needs to be reserved for wire bonding. Furthermore, the process of filling with low-dielectric-constant material is complex, increasing mass production costs.

[0004] Therefore, overcoming the technical problems existing in the prior art is a pressing issue that needs to be addressed in this technical field. Summary of the Invention

[0005] One of the objectives of this invention is to overcome the technical problems existing in the prior art: in terms of reducing electrode capacitance, there is a limit to reducing the area of ​​the P electrode, while filling with low dielectric constant materials involves complex processes and increases mass production costs; this invention proposes a method and structure for reducing laser chip capacitance, by filling the bonding region of the P-side electrode with a dielectric layer that has low adhesion to the gold layer, and by performing gold wire bonding through a bonding process, the P-side electrode layer can be pulled up, which is equivalent to greatly reducing the metal area of ​​the P-side electrode, thereby greatly reducing the chip electrode capacitance.

[0006] To achieve the above objectives, the first aspect of the present invention provides a method for reducing the capacitance of a laser chip, comprising:

[0007] A passivated Pad layer is formed in the P-side bonding region on the passivation layer of the chip, and the Pad layer is a dielectric layer with low adhesion to the gold layer;

[0008] A P-side electrode is fabricated on the chip, a portion of which is located on the Pad layer;

[0009] Based on the low adhesion between the passivated Pad layer and the gold layer, when the gold wire is bonded to the P-side electrode, the gold wire pulls up the portion of the P-side electrode located on the Pad layer, while the gold wire and the P-side electrode remain connected.

[0010] In an optional embodiment, the Pad layer includes a photoresist passivation layer formed by high-temperature and high-pressure passivation of photoresist; the photoresist passivation layer is formed by high-solidification of EPG512 photoresist at a spin coating speed of 3000-4500 rad / s, a high temperature of 250 degrees Celsius, and a vacuum of less than 0.005 Pa.

[0011] In an optional embodiment, the P-side electrode includes a circular electrode pad disposed on the Pad layer, the electrode pad having a diameter of 70±5µm; the gold wire having a diameter of 25µm, and when the gold wire is bonded to the electrode pad, the resulting solder ball has a diameter of 50-60µm.

[0012] In one optional embodiment, the Pad layer thickness is 1-1.5 μm, the adhesion between the Pad layer and the gold layer is less than 10 CN; the adhesion between the P-side electrode and the gold wire after bonding is 30-50 CN; and the pull-back force after bonding the gold wire is greater than 15 CN.

[0013] In an optional implementation, the formation of the passivation layer specifically includes:

[0014] A double-groove ridge structure is formed on the epitaxial wafer of the chip using dry etching and wet etching processes.

[0015] A silicon dioxide dielectric film is grown on the epitaxial wafer as a passivation layer, and a current injection window is formed on the double-groove ridge structure by photolithography and dry etching processes.

[0016] In an optional embodiment, the epitaxial wafer includes a substrate and, from bottom to top, a buffer layer, a lower confinement layer, a multiple quantum well active layer, an upper confinement layer, an etch barrier layer, a capping layer, and an ohmic contact layer grown on the substrate.

[0017] The double-groove ridge structure is formed by removing two strip-shaped regions of the capping layer and the ohmic contact layer through dry etching and wet etching.

[0018] In an optional implementation, fabricating the P-side electrode on the chip specifically includes:

[0019] A P-side electrode is fabricated on the chip using a metal lift-off process, the P-side electrode extending from the Pad layer to cover the current injection window;

[0020] The gold layer thickness of the P-side electrode is increased to 3-5 μm through electroplating.

[0021] In an optional implementation, the method further includes: thinning the epitaxial wafer of the chip to complete the fabrication of the N-sided electrodes.

[0022] In one optional embodiment, after one end of the gold wire is bonded to the P-side electrode and pulled up, the other end of the gold wire is soldered to the substrate.

[0023] A second aspect of the present invention provides a structure for reducing the capacitance of a laser chip, which is fabricated using the method for reducing laser chip capacitance as described in the first aspect. The structure includes an epitaxial wafer, a passivation layer, a pad layer, a P-side electrode, an N-side electrode, and a gold wire, wherein:

[0024] The epitaxial wafer includes a substrate and, from bottom to top, a buffer layer, a lower confinement layer, a multi-quantum-well active layer, an upper confinement layer, an etching barrier layer, a capping layer, and an ohmic contact layer grown on the substrate; the capping layer and the ohmic contact layer are formed by removing two strip-shaped regions through dry etching and wet etching to form a double-groove ridge structure.

[0025] The passivation layer is located on the top of the epitaxial wafer, and the top of the double groove ridge structure is formed with a current injection window by photolithography and dry etching processes;

[0026] The Pad layer is located in the P-side bonding region on the passivation layer;

[0027] The P-side electrode extends from above the Pad layer and covers the current injection window;

[0028] The N-face electrode is located at the bottom of the epitaxial wafer;

[0029] One end of the gold wire is bonded to the P-side electrode and pulls up the portion of the P-side electrode on the Pad layer, while the other end of the gold wire is soldered to the substrate.

[0030] In summary, compared with existing technologies, the technical solutions conceived in this invention have the following beneficial effects: Conventional chip electrode capacitance reduction typically involves reducing the area of ​​the P-electrode and filling it with a low-dielectric-constant material. However, the P-electrode area cannot be continuously reduced; a certain area needs to be reserved for wire bonding. Furthermore, filling with a low-dielectric-constant material involves complex processes and increases manufacturing costs. This invention, by filling the P-side electrode bonding area with a dielectric layer that has low adhesion to the gold layer, pulls the P-electrode layer up during the gold wire bonding process, effectively reducing the metal area of ​​the P-side electrode and thus significantly reducing the chip electrode capacitance. In addition, this invention thickens the P-side electrode plating to 3-5 μm, compared to the conventional 1 μm thickness in existing technologies, ensuring that the gold layer remains intact during the wire bonding process. Attached Figure Description

[0031] Figure 1 This is a flowchart of a method for reducing the capacitance of a laser chip according to Embodiment 1 of the present invention;

[0032] Figure 2 This is a schematic diagram of the cross-section of the epitaxial wafer provided in Embodiment 3 of the present invention;

[0033] Figure 3 This is a schematic diagram of the double-groove ridge structure provided in Embodiment 3 of the present invention;

[0034] Figure 4 This is a schematic diagram of a chip cross-section provided in Embodiment 3 of the present invention;

[0035] Figure 5 This is a cross-sectional schematic diagram of the bonding between the gold wire and the chip provided in Embodiment 3 of the present invention;

[0036] Figure 6 This is a schematic diagram of the electrode pads when viewed from above, provided in Embodiment 3 of the present invention;

[0037] Figure 7 This is a schematic diagram of the gold wire provided in Embodiment 3 of the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0039] This invention is an architecture of a specific functional system. Therefore, the specific embodiments mainly describe the functional logic relationship of each structural module, and do not limit the specific software and hardware implementation methods.

[0040] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other, and the order of the steps can be changed as long as they are logical and do not conflict. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0041] Example 1:

[0042] like Figure 1 As shown, for reference Figure 5 The present invention provides a method for reducing the capacitance of a laser chip, comprising the following steps.

[0043] Step 100: A passivated Pad layer 3 is formed on the P-side bonding region of the passivation layer 2 of the chip. The Pad layer 3 is a dielectric layer with low adhesion to the gold layer. In this step of this embodiment, a double-groove ridge waveguide structure can first be formed on the epitaxial wafer 1 through photolithography, etching, and other processes. Then, a silicon dioxide dielectric film is grown on the epitaxial wafer 1 as the passivation layer 2. A current injection window is formed on the ridge through photolithography, dry etching, and other processes. Then, the Pad layer 3 is formed on the P-side bonding region through photolithography. The Pad layer 3 can be formed by passivation of photoresist under high temperature and high pressure.

[0044] Step 200: Fabricate a P-side electrode 4 on the chip, a portion of which is located on the Pad layer 3. In this embodiment, the P-side electrode 4 can be fabricated on the chip using a metal lift-off process; the gold layer thickness of the P-side electrode 4 is increased to 3-5 μm using an electroplating process. Afterwards, the epitaxial wafer 1 of the chip can be thinned to complete the fabrication of the N-side electrode 5.

[0045] Step 300: Based on the low adhesion between the passivated Pad layer 3 and the gold layer, when the gold wire 6 is bonded to the P-side electrode 4, the gold wire 6 pulls up the portion of the P-side electrode 4 located on the Pad layer 3, while maintaining connection between the gold wire 6 and the P-side electrode 4. In this step of this embodiment, after the epitaxial wafer 1 has undergone cleaving, coating, and characteristic screening, during the chip packaging bonding stage, due to the low adhesion between the passivated Pad layer 3 and the gold layer, when the gold wire 6 is bonded to the P-side electrode 4, the gold wire 6 pulls up one end of the P-side electrode 4, while maintaining connection between the gold wire 6 and the P-side electrode 4, thus completing the bonding process.

[0046] Through the above steps, this embodiment of the invention fills the bonding area of ​​the P-side electrode 4 with a dielectric layer that has low adhesion to the gold layer. When the gold wire bonding process is performed, the P-side electrode 4 is pulled up, which is equivalent to greatly reducing the metal area of ​​the P-side electrode 4, thereby greatly reducing the chip electrode capacitance.

[0047] In one specific embodiment of this preferred embodiment, the Pad layer 3 includes a photoresist passivation layer formed by high-temperature and high-pressure passivation of photoresist; the photoresist passivation layer is formed by high-solidification of EPG512 photoresist at a spin coating speed of 3000-4500 rad / s, a high temperature of 250 degrees Celsius, and a vacuum of less than 0.005 Pa. EPG512 photoresist is a conventionally available photoresist and is only used as an example here.

[0048] In one specific embodiment of this preferred embodiment, reference is made to Figure 6 As shown, the P-side electrode 4 includes a circular electrode pad disposed on the Pad layer 3. The diameter of the electrode pad is 70±5µm, and the diameter of the electrode pad is just slightly larger than the diameter of the solder ball; Reference Figure 7 As shown, the diameter of the gold wire 6 is 25um. The gold wire 6 generally has standard specifications. The 25um used here is for illustrative purposes only. When the gold wire 6 is bonded to the electrode pad, the diameter of the solder ball formed is 50-60um.

[0049] In one specific embodiment of this preferred embodiment, based on the above settings, the thickness of the Pad layer 3 is 1-1.5 μm (the film thickness depends on the rotation speed of the spin coating; in this embodiment, it is approximately 1-1.5 μm thick), and the adhesion between the Pad layer 3 and the gold layer is less than 10 CN; the adhesion between the P-side electrode 4 and the gold wire 6 after bonding is 30-50 CN; the pull-back force of the gold wire 6 after bonding is greater than 15 CN, so after bonding, the electrode pad, i.e., the P-side electrode 4, can be pulled up. It should also be noted that after one end of the gold wire 6 is bonded to the P-side electrode 4 and pulled up, the other end of the gold wire 6 is soldered to the substrate.

[0050] In one specific embodiment of this preferred embodiment, the formation of the passivation layer 2 specifically includes: forming a double-groove ridge structure 19 on the epitaxial wafer 1 of the chip by dry etching and wet etching processes; growing a silicon dioxide dielectric film on the epitaxial wafer 1 as the passivation layer 2; and forming a current injection window on the double-groove ridge structure 19 by photolithography and dry etching processes.

[0051] In one specific embodiment of this preferred embodiment, reference is made to Figure 2 As shown, the epitaxial wafer 1 includes a substrate 11 and, from bottom to top, a buffer layer 12, a lower confinement layer 13, a multi-quantum-well active layer 14, an upper confinement layer 15, an etching barrier layer 16, a capping layer 17, and an ohmic contact layer 18, grown sequentially on the substrate 11; Reference Figure 3 As shown, the double-groove ridge structure 19 is formed by removing two strip-shaped areas of the cover layer 17 and the ohmic contact layer 18 through dry etching and wet etching.

[0052] In one specific embodiment of this preferred embodiment, fabricating the P-side electrode 4 on the chip specifically includes: fabricating the P-side electrode 4 on the chip using a metal lift-off process, referring to... Figure 4 As shown, the P-side electrode 4 extends from the Pad layer 3 to cover the current injection window; the gold layer thickness of the P-side electrode 4 is increased to 3-5 μm through an electroplating process. The gold layer thickness of a conventional P-side electrode 4 is approximately 1 μm. This embodiment increases the gold layer thickness of the P-side electrode 4 to 3-5 μm. (Refer to...) Figure 5 As shown, this ensures that the gold layer of the P-side electrode 4 remains intact during the pulling process of the gold wire 6.

[0053] In summary, conventional methods for reducing electrode capacitance in chips typically involve reducing the area of ​​the P-electrode and filling it with a low-dielectric-constant material. However, the P-electrode area cannot be reduced indefinitely; a certain area needs to be reserved for wire bonding. Filling with a low-dielectric-constant material involves complex processes and increases manufacturing costs. This invention fills the bonding region of the P-side electrode with a dielectric layer that has low adhesion to the gold layer. During the gold wire bonding process, the P-electrode layer is pulled up, effectively reducing the metal area of ​​the P-side electrode and thus significantly lowering the chip's electrode capacitance. Furthermore, this invention thickens the P-side electrode plating to 3-5 μm, compared to the conventional 1 μm thickness in existing technologies, ensuring that the gold layer remains intact during the wire pulling process.

[0054] Example 2:

[0055] Based on the method provided in Embodiment 1, this Embodiment 2 provides a more specific implementation method to describe the method of the present invention in detail.

[0056] The method in this embodiment includes the following steps:

[0057] Step 1: Reference Figure 2 As shown, the epitaxial wafer 1 includes a substrate 11, and a buffer layer 12, a lower confinement layer 13, a multi-quantum well active layer 14, an upper confinement layer 15, an etching barrier layer 16, a capping layer 17 and an ohmic contact layer 18 sequentially grown on the surface of the substrate 11.

[0058] Step Two: Reference Figure 3 As shown, the two strip-shaped areas of the capping layer 17 and the ohmic contact layer 18 are removed by dry etching and wet etching to form a double-groove ridge structure 19.

[0059] Step 3: As Figure 4As shown, a silicon dioxide dielectric film is grown on the epitaxial wafer 1 as a passivation layer 2. A current injection window is formed on the ridge using photolithography and dry etching processes. A Pad layer 3 is formed in the P-side bonding region using photolithography. This Pad layer 3 can be passivated using photoresist under high temperature and high pressure. A P-side electrode 4 is fabricated on the chip using a metal lift-off process. The gold layer thickness of the P-side electrode 4 is increased to 3-5 μm using an electroplating process. The substrate 11 of the epitaxial wafer 1 is thinned to complete the fabrication of the N-side electrode 5. The epitaxial wafer 1 is then cleaved and coated to complete the chip fabrication.

[0060] Step Four: As Figure 5 As shown, in the chip packaging bonding process, due to the low adhesion between the passivated photoresist Pad layer 3 and the gold layer, when the gold wire 6 is pulled up, the P-side electrode 4 can be pulled up, and the gold wire 6 and the P-side electrode 4 remain connected, thus completing the bonding process.

[0061] In summary, conventional methods for reducing electrode capacitance in chips typically involve reducing the area of ​​the P-electrode and filling it with a low-dielectric-constant material. However, the P-electrode area cannot be reduced indefinitely; a certain area needs to be reserved for wire bonding. Filling with a low-dielectric-constant material involves complex processes and increases manufacturing costs. This invention fills the bonding region of the P-side electrode with a dielectric layer that has low adhesion to the gold layer. During the gold wire bonding process, the P-electrode layer is pulled up, effectively reducing the metal area of ​​the P-side electrode and thus significantly lowering the chip's electrode capacitance. Furthermore, this invention thickens the P-side electrode plating to 3-5 μm, compared to the conventional 1 μm thickness in existing technologies, ensuring that the gold layer remains intact during the wire pulling process.

[0062] Example 3:

[0063] Embodiment 3 of the present invention provides a structure for reducing the capacitance of a laser chip, which is prepared using the methods for reducing laser chip capacitance described in Embodiments 1 and 2, and is referred to [reference needed]. Figure 5 The structure includes an epitaxial wafer 1, a passivation layer 2, a pad layer 3, a P-side electrode 4, an N-side electrode 5, and a gold wire 6.

[0064] Among them, reference Figure 2 As shown, the epitaxial wafer 1 includes a substrate 11 and, from bottom to top, a buffer layer 12, a lower confinement layer 13, a multi-quantum well active layer 14, an upper confinement layer 15, an etching barrier layer 16, a capping layer 17, and an ohmic contact layer 18 grown on the substrate 11.

[0065] refer to Figure 3 As shown, the double-groove ridge structure 19 is formed by removing two strip-shaped areas at the cover layer 17 and the ohmic contact layer 18 through dry etching and wet etching.

[0066] refer to Figure 4 As shown, the passivation layer 2 is located on the top of the epitaxial wafer 1, and a silicon dioxide dielectric film is grown on the epitaxial wafer 1 as the passivation layer 2; and the top of the double groove ridge structure 19 forms a current injection window through photolithography and dry etching processes; the Pad layer 3 is located in the P-side bonding area on the passivation layer 2, and the P-side electrode 4 is fabricated on the chip through a metal lift-off process; the P-side electrode 4 extends from above the Pad layer 3 to cover the current injection window, and the gold layer thickness of the P-side electrode 4 is increased to 3-5 μm through an electroplating process; the N-side electrode 5 is located at the bottom of the epitaxial wafer 1.

[0067] refer to Figure 5 One end of the gold wire 6 is bonded to the P-side electrode 4 and pulls up the portion of the P-side electrode 4 on the Pad layer 3. The gold layer thickness of the conventional P-side electrode 4 is about 1 μm. In this embodiment, the gold layer thickness of the P-side electrode 4 is increased to 3-5 μm, which can ensure that the gold layer of the P-side electrode 4 remains unbroken during the pulling process of the gold wire 6. The other end of the gold wire 6 is soldered to the substrate, which is not shown in the substrate diagram.

[0068] refer to Figure 6 In the diagram, Pad layer 3 is the photoresist passivation layer. For the P-side electrode 4, the portion on the photoresist passivation layer includes circular electrode pads with a diameter of 70 μm. (Refer to...) Figure 7 The gold wire diameter is 25µm, and the solder ball diameter is 50-60µm. The photoresist passivation layer is made of EPG512, with a spin coating speed of 3000 rad / s, and is cured at a high temperature of 250 degrees Celsius and a vacuum within 0.005 Pa. The resulting photoresist passivation layer is about 1µm thick, and its adhesion to the gold layer is less than 10 CN, while the adhesion between the P-side electrode 4 and the gold wire 6 after bonding is above 30-50 CN. The pull-back force after bonding the gold wire 6 is above 15 CN, so the electrode pad can be pulled up after bonding. The bonding method of the gold wire 6 is as follows: first, the first solder joint is made on the electrode pad, and the electrode pad is pulled up by the pull-back of the gold wire 6. Then, the other end of the gold wire 6 is soldered to the substrate.

[0069] In summary, compared with existing technologies, the technical solutions conceived in this invention have the following beneficial effects: Conventional chip electrode capacitance reduction generally involves reducing the area of ​​the P-electrode and filling it with a low-dielectric-constant material. However, the P-electrode area cannot be continuously reduced; a certain area needs to be reserved for wire bonding. Furthermore, filling with a low-dielectric-constant material involves complex processes and increases manufacturing costs. This invention, by filling the P-side electrode bonding area with a dielectric layer that has low adhesion to the gold layer, pulls the P-electrode layer up during the gold wire bonding process, effectively reducing the metal area of ​​the P-side electrode and thus significantly reducing the chip electrode capacitance. In addition, this invention thickens the P-side electrode plating to 3-5 μm, compared to the conventional 1 μm thickness in existing technologies, ensuring that the gold layer remains intact during the wire bonding process.

[0070] Those skilled in the art will understand that all or part of the steps in the various methods of the embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0071] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention. Contents not described in detail in this specification are prior art known to those skilled in the art.

Claims

1. A method for reducing the capacitance of a laser chip, characterized in that, include: A passivated Pad layer (3) is formed on the P-side bonding region of the passivation layer (2) of the chip, wherein the Pad layer (3) is a dielectric layer with low adhesion to the gold layer; A P-side electrode (4) is fabricated on the chip, a portion of which is located on the Pad layer (3); Based on the low adhesion between the passivated Pad layer (3) and the gold layer, when the gold wire (6) is bonded to the P-side electrode (4), the gold wire (6) pulls up the part of the P-side electrode (4) located on the Pad layer (3), and the gold wire (6) and the P-side electrode (4) remain connected; wherein, the material of the P-side electrode (4) is the gold layer.

2. The method for reducing laser chip capacitance according to claim 1, characterized in that, The Pad layer (3) includes a photoresist passivation layer formed by photoresist passivation under high temperature and high pressure; the photoresist passivation layer is formed by EPG512 photoresist under high solidification conditions of 3000-4500 rad / s spin coating speed, 200-250 degrees Celsius, and 0.005 Pa vacuum.

3. The method for reducing laser chip capacitance according to claim 1, characterized in that, The P-side electrode (4) includes a circular electrode pad disposed on the Pad layer (3), the diameter of the electrode pad being 70±5um; the diameter of the gold wire (6) being 25um, and when the gold wire (6) is bonded to the electrode pad, the diameter of the solder ball formed is 50-60um.

4. The method for reducing laser chip capacitance according to claim 3, characterized in that, The Pad layer (3) has a thickness of 1-1.5 μm, and the adhesion between the Pad layer (3) and the gold layer is less than 10 CN; the adhesion between the P-side electrode (4) and the gold wire (6) after bonding is 30-50 CN; the pull-back force of the gold wire (6) after bonding is more than 15 CN.

5. The method for reducing laser chip capacitance according to claim 1, characterized in that, The formation of the passivation layer (2) specifically includes: A double-groove ridge structure (19) is formed on the epitaxial wafer (1) of the chip by dry etching and wet etching processes. A silicon dioxide dielectric film is grown on the epitaxial wafer (1) as a passivation layer (2), and a current injection window is formed on the double groove ridge structure (19) by photolithography and dry etching processes.

6. The method for reducing laser chip capacitance according to claim 5, characterized in that, The epitaxial wafer (1) includes a substrate (11) and a buffer layer (12), a lower confinement layer (13), a multi-quantum well active layer (14), an upper confinement layer (15), an etching barrier layer (16), a capping layer (17), and an ohmic contact layer (18) grown sequentially from bottom to top on the substrate (11). The double-groove ridge structure (19) is formed by removing two strip regions of the cover layer (17) and the ohmic contact layer (18) through dry etching and wet etching.

7. The method for reducing laser chip capacitance according to claim 1, characterized in that, The fabrication of P-side electrodes on the chip (4) specifically includes: A P-side electrode (4) is fabricated on the chip using a metal stripping process. The P-side electrode (4) extends from the Pad layer (3) and covers the current injection window. The gold layer thickness of the P-side electrode (4) is increased to 3-5 μm by electroplating.

8. The method for reducing laser chip capacitance according to any one of claims 1-7, characterized in that, It also includes: thinning the epitaxial wafer (1) of the chip to complete the fabrication of the N-side electrode (5).

9. The method for reducing laser chip capacitance according to any one of claims 1-7, characterized in that, After one end of the gold wire (6) is bonded to the P-side electrode (4) and pulled up, the other end of the gold wire (6) is soldered onto the substrate.

10. A structure for reducing laser chip capacitance, fabricated using the method for reducing laser chip capacitance as described in any one of claims 1-9, characterized in that, It includes an epitaxial wafer (1), a passivation layer (2), a pad layer (3), a P-side electrode (4), an N-side electrode (5), and a gold wire (6), wherein: The epitaxial wafer (1) includes a substrate (11) and, from bottom to top, a buffer layer (12), a lower confinement layer (13), a multi-quantum well active layer (14), an upper confinement layer (15), an etching barrier layer (16), a capping layer (17), and an ohmic contact layer (18) grown on the substrate (11); after removing two strip-shaped regions at the capping layer (17) and the ohmic contact layer (18) by dry etching and wet etching, a double-groove ridge structure (19) is formed. The passivation layer (2) is located on the top of the epitaxial wafer (1), and the top of the double groove ridge structure (19) is formed with a current injection window by photolithography and dry etching processes; The Pad layer (3) is located in the P-side bonding region on the passivation layer (2); The P-side electrode (4) extends from above the Pad layer (3) and covers the current injection window; The N-face electrode (5) is located at the bottom of the epitaxial wafer (1); One end of the gold wire (6) is bonded to the P-side electrode (4) and pulls up part of the P-side electrode (4) on the Pad layer (3), while the other end of the gold wire (6) is soldered to the substrate.

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