Signal selector, driving method thereof, display panel and display device

Abstract

The present disclosure relates to a signal selector and a driving method thereof, a display panel and a display device. In a data writing period, the signal selector loads a writing signal to a control terminal of a switch circuit, and the switch circuit is turned on in response to the writing signal loaded on the control terminal, so that the writing signal is loaded to a far end of an output signal line. In a pull-up period after the data writing period, a pull-up control signal is loaded to a control terminal of a pull-up circuit, and the pull-up circuit pulls up a voltage of an output terminal of the switch circuit in response to the pull-up control signal loaded on the second terminal. Therefore, the signal selector of the present disclosure can realize fast rising and fast falling of the voltage of the far end of the output data line (Source), so that the charging specification of a medium-large size and high resolution display panel can be achieved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a signal selector, a driving method thereof, a display panel and a display device. BACKGROUND

[0002] At present, display panels with large size and high resolution gradually become a development trend, but it brings a problem that the charging of the display panel with medium-large size and high resolution is difficult to achieve the charging specification.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] The present disclosure provides a signal selector, a driving method thereof, a display panel and a display device.

[0005] According to an aspect of the present disclosure, a signal selector is provided for distributing signals on input data lines to different output data lines, the output data lines being used to drive sub-pixels of a display panel, the signal selector comprising a plurality of switching units, any one switching unit comprising a switching circuit and a boosting circuit, the switching circuit being connected between an input data line and an output data line, the switching circuit being configured to be turned on in response to a write signal loaded on a control terminal thereof, the first terminal of the boosting circuit being electrically connected to an output terminal of the switching circuit; the boosting circuit being configured to pull up the voltage of the output terminal of the switching circuit in response to a boosting control signal loaded on a control terminal thereof.

[0006] In an embodiment of the present disclosure, the boosting circuit comprises a boosting transistor, the first terminal and / or the second terminal of the boosting transistor being electrically connected to the output terminal of the switching circuit as the first terminal of the boosting circuit; the control terminal of the boosting transistor being used to load the boosting control signal as the second terminal.

[0007] In an embodiment of the present disclosure, the boosting circuit comprises a boosting capacitor, one electrode plate of the boosting capacitor being electrically connected to the output terminal of the switching unit as the first terminal of the boosting circuit; the other electrode plate of the boosting capacitor being used to load the boosting control signal as the second terminal.

[0008] In an embodiment of the present disclosure, the plurality of switching units are divided into a plurality of switching unit groups, each switching unit group comprising at least three switching units, and the output data lines connected by different switching units are respectively connected to sub-pixels of different colors.

[0009] In an embodiment of the present disclosure, the signal selector comprises a plurality of input data lines, and one input data line is connected to one switching unit group.

[0010] In one embodiment of the present disclosure, the switching circuit is a switching transistor, the first end of the switching circuit is a source of the switching transistor, the second end of the switching circuit is a drain of the boosting transistor, and the control end of the switching circuit is a gate of the boosting transistor.

[0011] According to yet another aspect of the present disclosure, a display panel is provided, comprising the signal selector of any one of the above.

[0012] According to yet another aspect of the present disclosure, a display panel is provided, comprising a substrate and a driving circuit layer arranged on one side of the substrate, the driving circuit layer comprising a plurality of switching circuit regions, each of the switching circuit regions comprising an active layer, a gate layer and a source-drain metal layer, the active layer being arranged on one side of the substrate, the active layer comprising a first active part, a second active part, a third active part, a fourth active part and a fifth active part; the gate layer being arranged on a side of the active layer away from the substrate, the gate layer comprising a first control lead, a second control lead and a first input data line arranged along a second direction, a projection of the first control lead on the substrate overlapping a projection of the first active part on the substrate, a projection of the second control lead on the substrate overlapping a projection of the second active part on the substrate; the source-drain metal layer being arranged on a side of the gate layer away from the substrate, the source-drain metal layer comprising a first signal line, a second signal line arranged along a first direction, and a first conductive structure, a second conductive structure, a third conductive structure and an output data line arranged along the second direction, the second signal line being connected to the first control lead, and the first signal line being connected to the second control lead; the first conductive structure being connected to the first input data line, a projection of the first conductive structure on the substrate overlapping a projection of the third active part on the substrate, the first conductive structure being connected to the third active part, a projection of the second conductive structure on the substrate overlapping a projection of the fourth active part on the substrate, the second conductive structure being connected to the fourth active part, a projection of the third conductive structure on the substrate overlapping a projection of the fifth active part on the substrate, the third conductive structure being connected to the fifth active part, the third conductive structure being connected to the second conductive structure, and the second conductive structure and the third conductive structure being connected to the output data line.

[0013] In one embodiment of the present disclosure, in the first direction, a projection of the second conductive structure on the substrate is located between a projection of the first control lead on the substrate and a projection of the second control lead on the substrate, the projection of the second conductive structure on the substrate is located outside the projection of the first control lead on the substrate, and a projection of the third conductive structure on the substrate is located outside the projection of the second control lead on the substrate.

[0014] In one embodiment of the present disclosure, the display panel includes a plurality of groups of switch circuit regions, each group of switch circuit regions including at least three switch circuit regions, the at least three switch circuit regions being arranged at intervals along a first direction, each switch circuit region being connected to an output data line connected to a sub-pixel of one color, and adjacent two different sub-pixels having different polarities of driving ends.

[0015] In one embodiment of the present disclosure, the plurality of switch circuit regions are divided into a plurality of groups of switch circuit regions, each group of switch circuit regions including at least three switch circuit regions, the source-drain metal layer further including at least one first transfer line arranged along the first direction, one first transfer line being connected to each first conductive structure in one group of switch circuit regions, and the first input data line being transferred to the first transfer line.

[0016] In one embodiment of the present disclosure, the first input data line includes a first sub-input data line and a second sub-input data line, the first sub-input data line inputting a positive total data signal, and the second sub-input data line inputting a negative total data signal, the sub-pixel including, in sequence along the first direction, a first red sub-pixel, a first green sub-pixel, a first blue sub-pixel, a second red sub-pixel, a second green sub-pixel, and a third blue sub-pixel; the first sub-input data line and the second sub-input data line respectively corresponding to a group of first output data lines, a group of second output data lines, and a group of third output data lines, the first output data line corresponding to the first input data line being connected to the first red sub-pixel, the third output data line corresponding to the first input data line being connected to the first blue sub-pixel, the first output data line corresponding to the second input data line being connected to the second red sub-pixel, the third output data line corresponding to the second input data line being connected to the second blue sub-pixel, the display panel further including a third transfer line and a fourth transfer line, the second output data line corresponding to the first input data line being connected to the third transfer line, the third transfer line being connected to the second green sub-pixel, the second output data line corresponding to the second input data line being connected to the fourth transfer line, and the fourth transfer line being connected to the first green sub-pixel.

[0017] In one embodiment of the present disclosure, the first signal line includes a first sub-signal line, a third sub-signal line, and a fifth sub-signal line, the second signal line includes a second sub-signal line, a fourth sub-signal line, and a sixth sub-signal line, each group of switch circuit regions including three switch circuit regions, the second control lead of the first switch circuit region being connected to the first sub-signal line, the second control lead of the second switch circuit region being connected to the third sub-signal line, the second control lead of the third switch circuit region being connected to the fifth sub-signal line, the first control lead of the first switch circuit region being connected to the second sub-signal line, the first control lead of the second switch circuit region being connected to the fourth sub-signal line, and the first control lead of the third switch circuit region being connected to the sixth sub-signal line.

[0018] In one embodiment of the present disclosure, the gate layer further comprises a second input data line, a second transfer line and a touch signal line, the second transfer line is arranged along a first direction, the second input data line and the touch signal line are arranged along a second direction, the second transfer line connects the second input data line and the touch signal line, the touch signal on the second input data line is distributed to different touch signal lines, and the touch signal lines are used to drive touch electrodes of the display panel.

[0019] According to still another aspect of the present disclosure, there is provided a display device comprising the display panel of any one of the above.

[0020] According to still another aspect of the present disclosure, there is provided a display panel comprising a substrate and a drive circuit layer arranged on one side of the substrate, the drive circuit layer comprising a plurality of switching circuit regions, each of the switching circuit regions comprising an active layer, a gate layer and a source-drain metal layer, the active layer being arranged on one side of the substrate, the active layer comprising a first active part, a second active part and a third active part; the gate layer being arranged on a side of the active layer away from the substrate, the gate layer comprising a first control lead, a second control lead and an input data line, a projection of the first control lead on the substrate overlapping a projection of the first active part on the substrate; the source-drain metal layer being arranged on a side of the gate layer away from the substrate, the source-drain metal layer comprising a first signal line and a second signal line arranged along a first direction, and a first conductive structure, a second conductive structure, a third conductive structure and an output data line arranged along a second direction, the second signal line being connected to the first control lead, and the first signal line being connected to the second control lead; the first conductive structure being connected to the first input data line, a projection of the first conductive structure on the substrate overlapping a projection of the third active part on the substrate, the first conductive structure being connected to a source electrode of a switching transistor, a projection of the second conductive structure on the substrate overlapping a projection of the fourth active part on the substrate, the second conductive structure being connected to a drain electrode of the switching transistor, a projection of the third conductive structure on the substrate overlapping a projection of the second control line on the substrate, the third conductive structure and the second control line forming a storage capacitor, the third conductive structure being connected to the second conductive structure, and the second conductive structure and the third conductive structure being connected to the output data line.

[0021] In one embodiment of the present disclosure, a plurality of first through holes are arranged on the second conductive structure, and a plurality of second through holes are arranged on the third conductive structure, a projection of the second through holes on the substrate being located within a projection of the first through holes on the substrate.

[0022] According to still another aspect of the present disclosure, there is provided a driving method of a signal selector, the method comprising:

[0023] loading a write signal to a control end of the switching circuit during a data write period;

[0024] In the pull-up period after the data writing period, a boost control signal is loaded to the control end of the boost circuit.

[0025] In one embodiment of the present disclosure, the boost circuit comprises a boost transistor; the driving method further comprises: in the preparation period before the data writing period, a preparation voltage is loaded to the gate of the boost transistor, so that the Vgs of the boost transistor is not less than the Vth of the boost transistor.

[0026] In one embodiment of the present disclosure, the lag time of the falling edge of the write signal relative to the falling edge of the boost signal is at least greater than one pulse width of the write signal.

[0027] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0028] The drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure, and together with the specification, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0029] Figure 1 The circuit connection diagram of a signal selector related to an embodiment of the present disclosure.

[0030] Figure 2 The simulation waveform diagram of the first red sub-pixel R1, the second green sub-pixel G2, and the first blue sub-pixel B1 of a signal selector related to an embodiment of the present disclosure.

[0031] Figure 3 The simulation diagram of the charging process of a signal selector related to an embodiment of the present disclosure.

[0032] Figure 4 The circuit connection diagram of another signal selector related to an embodiment of the present disclosure.

[0033] Figure 5 The circuit connection diagram of the first red sub-pixel R1 of another signal selector when the boost circuit is a boost transistor in an embodiment of the present disclosure.

[0034] Figure 6 The circuit schematic diagram of the first red sub-pixel R1 of another signal selector related to an embodiment of the present disclosure.

[0035] Figure 7 The circuit connection diagram of the first red sub-pixel R1 of another signal selector when the boost circuit is a boost transistor in an embodiment of the present disclosure.

[0036] Figure 8 Flow chart of a driving method of a signal selector according to an embodiment of the present disclosure.

[0037] Figure 9 Schematic diagram of another coupling process of another signal selector according to an embodiment of the present disclosure.

[0038] Figure 10 Curve of relationship between gate voltage of a boost transistor and capacitance when the boost circuit is the boost transistor according to an embodiment of the present disclosure.

[0039] Figure 11 Schematic diagram of another coupling process of another signal selector according to an embodiment of the present disclosure.

[0040] Figure 12 Schematic diagram of a cross section of a display panel according to an embodiment of the present disclosure.

[0041] Figure 13 Schematic diagram of a structure of an active layer of a display panel in a non-display area according to an embodiment of the present disclosure.

[0042] Figure 14 Schematic diagram of a structure of a gate layer of a display panel in a non-display area according to an embodiment of the present disclosure.

[0043] Figure 15 Schematic diagram of a structure of a source-drain metal layer of a display panel in a non-display area according to an embodiment of the present disclosure.

[0044] Figure 16 Layout of a display panel according to an embodiment of the present disclosure.

[0045] Figure 17 Schematic diagram of a structure of an active layer of another display panel in a non-display area according to an embodiment of the present disclosure.

[0046] Figure 18 Schematic diagram of a structure of a gate layer of another display panel in a non-display area according to an embodiment of the present disclosure.

[0047] Figure 19 Schematic diagram of a structure of a source-drain metal layer of another display panel in a non-display area according to an embodiment of the present disclosure.

[0048] Figure 20 Layout of another display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations can be implemented in any

[0050] Although relative terms such as "upper," "lower," are used herein to describe one component's relationship to another component of a figure, such terminology is used herein for convenience only and is not intended to limit the scope of the disclosure in any way. It is to be understood that, when a figure is inverted, such relative terms as "upper" and "lower" are to be construed as "lower" and "upper," respectively, and vice versa. When a structure is "on" or "under" another structure, it can mean that the structure is formed directly on or directly under the other structure, or that the structure is "directly" on or "directly" under the other structure, or that the structure is "indirectly" on or "indirectly" under the other structure via other structure(s).

[0051] The terms "one," "a," "an," "the," and "at least one" are used to mean one or more elements / structures / components / etc.; the term "includes" and the term "including" means the inclusion of an element / structure / component / etc. by reference or substitution and does not exclude the inclusion of other elements / structures / components / etc.; the

[0052] The signal selector (MUX) can control the opening or closing of the MOS transistor by the level change of the control signal of the gate at different time periods, so as to realize the input of the driving signal of the driving chip (IC) to the display area, thereby controlling the brightness of the sub-pixels of different colors.

[0053] As shown in FIG. 2, the source and the drain of the switch transistor T1 are electrically connected to the first sub-input data line S1 or the input data line S2, and the gate of the switch transistor T1 is controlled by the corresponding first signal line. Figure 1 As shown in FIG. 2, the source and the drain of the switch transistor T1 are electrically connected to the first sub-input data line S1 or the input data line S2, and the gate of the switch transistor T1 is controlled by the corresponding first signal line.

[0054] The first input data line includes a first sub-input data line S1 and a second sub-input data line S2. The first sub-input data line S1 can provide signals to a first red sub-pixel R1, a second green sub-pixel G2 and a first blue sub-pixel B1 of the display area. The second sub-input data line S2 can provide signals to a second red sub-pixel R2, a first green sub-pixel G1 and a second blue sub-pixel B2 of the display area. The gates of different switch transistors T1 corresponding to different color sub-pixels are controlled by corresponding first signal lines. Specifically, the first red sub-pixel R1 is controlled by a first sub-signal line MUX1, the second green sub-pixel G2 is controlled by a second sub-signal line MUX2, and the first blue sub-pixel B1 is controlled by a third sub-signal line MUX2.

[0055] Figure 2 The simulation waveform diagram of the first red sub-pixel R1, the second green sub-pixel G2 and the second blue sub-pixel B1 is shown in FIG. 2. The output data line Source of a sub-pixel of a certain color is connected to the gate of the driving transistor. When the gate signal Gate of the driving transistor of the sub-pixel of the certain color overlaps with the data signal controlled and output by the first signal line, the sub-pixel is lit. Specifically, when the gate signal Gate of the driving transistor of the red sub-pixel R1 overlaps with the data signal controlled and output by the first sub-signal line MUX1, the red sub-pixel R1 is lit. The lighting modes of the second green sub-pixel G2 and the blue sub-pixel B1 are similar to that of the red sub-pixel, and thus will not be described again. It can be understood that the signal selector only plays a role of circuit selection in display.

[0056] If the opening time of the signal selector is sufficient or the RC loading is small, the final voltage at the far end of the output data line Source can be charged to the same voltage as the first input data line. However, for a display panel of medium or large size, high resolution and high refresh rate, the opening time of the MUX is greatly reduced, and the RC loading of the output data line Source is increased, resulting in that the final voltage at the far end of the output line is lower than the voltage on the first input data line, so that the display panel will have vertical lines, horizontal lines, split screens and other defects.

[0057] Taking a display panel of size 17D6, resolution 1600x2560 and MUX3 as an example, the role of the signal selector in the charging process of the display panel is further described. Since the display panel of 17D6 has high resolution and large size, it is difficult to meet the charging specification requirements of the display panel by using the existing signal selector.

[0058] Taking the red sub-pixel R1 as an example, the charging simulation of the display panel using the above signal selector is shown in FIG. 3. Figure 3As shown, the driving voltage provided by the first sub-signal line MUX1 is 5.3V, and the maximum voltage that can be charged on the output data line Source of the first red sub-pixel R1 is 4.984V, the charging rate of the display panel is 4.984 / 5.3=0.94, which is less than the required charging rate specification of 0.99 of the display panel, thus the display panel will have display defects such as horizontal lines, vertical lines, etc.

[0059] Based on this, the present disclosure provides a signal selector. As shown, the signal selector is used to distribute the signal on the first input data line to different output data lines Source, which are used to drive the sub-pixels of the display panel. The signal selector includes a plurality of switch units, any one of which includes a switch circuit and a boost circuit, the switch circuit is connected to the first input data line and one output data line Source, and the switch circuit is used to turn on in response to the write signal loaded on its control end; the first end of the boost circuit is electrically connected to the output end of the switch circuit; the boost circuit is used to pull up the voltage of the output end of the switch circuit in response to the boost control signal loaded on its control end. Figures 4 to 7 As shown, the signal selector is used to distribute the signal on the first input data line to different output data lines Source, which are used to drive the sub-pixels of the display panel. The signal selector includes a plurality of switch units, any one of which includes a switch circuit and a boost circuit, the switch circuit is connected to the first input data line and one output data line Source, and the switch circuit is used to turn on in response to the write signal loaded on its control end; the first end of the boost circuit is electrically connected to the output end of the switch circuit; the boost circuit is used to pull up the voltage of the output end of the switch circuit in response to the boost control signal loaded on its control end.

[0060] The signal selector loads the write signal to the control end of the switch circuit during the data write period, and the switch circuit turns on in response to the write signal loaded on its control end, so that the write signal is loaded to the far end of the output signal line. In the pull-up period after the data write period, the boost control signal is loaded to the control end of the boost circuit, and the boost circuit pulls up the voltage of the output end of the switch circuit in response to the boost control signal loaded on its control end. Therefore, the signal selector of the present disclosure can realize the rapid rise and rapid fall of the voltage at the far end of the output data line Source, so as to achieve the charging specification of the medium-large size and high-resolution display panel.

[0061] It should be noted that each switch unit can also include a first signal line and a second signal line, wherein the first signal line is electrically connected to the control end of the boost circuit for loading the boost control signal to the boost circuit, and the second signal line is electrically connected to the control end of the switch circuit for loading the write signal to the switch circuit.

[0062] The signal selector can include N first input data lines, one first input data line is connected to one switch unit group, each switch unit group includes M switch units, and N switch unit groups include MxN switch units in total.

[0063] The M switch units include M switch circuits, and the M switch circuits are connected to M output data lines, and the M output data lines are respectively connected to M sub-pixels of different colors. It should be noted that M is greater than or equal to 3.

[0064] The control ends of the boost circuits of the sub-pixels of the M colors are loaded with M different boost signals, so that M first signal lines are usually provided. The control ends of the switch circuits of the sub-pixels of the M colors are loaded with M different write signals, so that M second signal lines are usually provided. Therefore, the number of signal lines is usually 2M.

[0065] As shown in Figure 4 The signal selector can include two switch unit groups, and the two switch unit groups include six switch units, wherein three switch units drive the first red sub-pixel R1, the second green sub-pixel G2 and the first blue sub-pixel B1, and the other three switch units drive the second red sub-pixel R2, the first green sub-pixel G1 and the first blue sub-pixel B2. The first signal lines include a first sub-signal line MUX1, a third sub-signal line MUX3 and a fifth sub-signal line MUX5, and the second signal lines include a second sub-signal line MUX2, a fourth sub-signal line MUX4 and a sixth sub-signal line MUX6.

[0066] The six switch units include six switch circuits. The control ends of the switch circuits corresponding to the first red sub-pixel R1 and the second red sub-pixel R2 are electrically connected to the second sub-signal line MUX2, the control ends of the switch circuits corresponding to the first green sub-pixel G1 and the second green sub-pixel G2 are electrically connected to the fourth sub-signal line MUX4, and the control ends of the switch circuits corresponding to the first blue sub-pixel B1 and the first blue sub-pixel B2 are electrically connected to the sixth sub-signal line MUX6.

[0067] The first input data lines are provided as two, and the two first input data lines include a first sub-input data line S1 and a second sub-input data line S2. The first sub-input data line S1 can be electrically connected to the input ends of the switch circuits of the first red sub-pixel R1, the second green sub-pixel G2 and the first blue sub-pixel B1, and input total data signals to the first red sub-pixel R1, the second green sub-pixel G2 and the first blue sub-pixel B1 of the display area. The second sub-input data line S2 can be electrically connected to the input ends of the switch circuits of the second red sub-pixel R2, the first green sub-pixel G1 and the first blue sub-pixel B2, and input total data signals to the second red sub-pixel R2, the first green sub-pixel G1 and the first blue sub-pixel B2 of the display area.

[0068] There are six output data lines (Source). Three of them are connected to the first red sub-pixel R1, the second green sub-pixel G2, and the first blue sub-pixel B1, respectively, to input sub-data signals to the first red sub-pixel R1, the second green sub-pixel G2, and the first blue sub-pixel B1 in the display area. The other three are connected to the second red sub-pixel R2, the first green sub-pixel G1, and the first blue sub-pixel B2, respectively, to input sub-data signals to the second red sub-pixel R2, the first green sub-pixel G1, and the first blue sub-pixel B2 in the display area.

[0069] The six switching units include six boost circuits. The first terminal of the boost circuit of the first red sub-pixel R1 is electrically connected to the output terminal of the switching circuit of the first red sub-pixel R1; the first terminal of the boost circuit of the second red sub-pixel R2 is electrically connected to the output terminal of the switching circuit of the second red sub-pixel R2; the first terminal of the boost circuit of the first green sub-pixel G1 is electrically connected to the output terminal of the switching circuit of the first green sub-pixel G1; the first terminal of the boost circuit of the second green sub-pixel G2 is electrically connected to the output terminal of the switching circuit of the second green sub-pixel G2; the first terminal of the boost circuit of the first blue sub-pixel B1 is electrically connected to the output terminal of the switching circuit of the first blue sub-pixel B1; and the first terminal of the boost circuit of the first blue sub-pixel B2 is electrically connected to the output terminal of the switching circuit of the first blue sub-pixel B2.

[0070] The control terminal of the boost circuit of the first red sub-pixel R1 is electrically connected to the first sub-signal line MUX1. The control terminal of the boost circuit of the second red sub-pixel R2 is electrically connected to the first sub-signal line MUX1. The control terminal of the boost circuit of the first green sub-pixel G1 is electrically connected to the third sub-signal line MUX3. The control terminal of the boost circuit of the second green sub-pixel G2 is electrically connected to the third sub-signal line MUX3. The control terminal of the boost circuit of the first blue sub-pixel B1 is electrically connected to the fifth sub-signal line MUX5. The control terminal of the boost circuit of the first blue sub-pixel B2 is electrically connected to the fifth sub-signal line MUX5.

[0071] like Figure 5 As shown, the switching circuit may include a switching transistor T1, with the source of T1 being the first terminal of the switching circuit, the drain of T1 being the second terminal of the switching circuit, and the gate of T1 serving as the control terminal of the switching circuit. The control terminal of the switching circuit is electrically connected to the second signal line. The boost circuit may include a boost transistor T2, with its first and second terminals shorted to form the first terminal of the boost circuit. The first terminal of the boost circuit is electrically connected to the second terminal of the switching circuit. The gate of the boost transistor T2 serves as the control terminal of the boost circuit, which is used to load a boost control signal and is electrically connected to the first signal line.

[0072] The capacitor coupling effect generated by the voltage boosting transistor T2 can realize fast rising and fast falling of the voltage at the far end of the output data line Source, so that the charging specification of a display panel with large size and high resolution can be achieved. The voltage boosting transistor T2 has the advantages that the size of the capacitor of the voltage boosting transistor T2 can be adjusted by adjusting the size of the gate voltage, the voltage boosting transistor T2 does not affect the switching transistor T1 around it, and the use is relatively convenient. The voltage boosting transistor T2 can be arranged in the same layer as the switching transistor T1, without increasing the thickness of the display panel.

[0073] As shown in Figure 6 , the working principle of the signal selector is described by taking the first sub-signal line MUX1 for controlling the output of the first red sub-pixel R1 as an example. The capacitor C1 is the capacitor of the voltage boosting transistor, the capacitor C2 is the capacitor on the output data line Source connected with the first red sub-pixel R1, UA is the voltage of the voltage boosting transistor T2, UB is the voltage of the first sub-input data line S1, and U0 is the voltage of the output data line Source connected with the first red sub-pixel R1. When the voltage UA suddenly increases by ΔU, the voltage at the other end of the capacitor C1 also increases by ΔU because the voltage at both ends of the capacitor C1 cannot suddenly change. Since the capacitor C1 and the capacitor C2 are connected together, there is a flow of charges between the capacitor C1 and the capacitor C2. Finally, the voltages of the capacitor C1 and the capacitor C2 are consistent, and the voltage value of U1 after reaching equilibrium is:

[0074]

[0075] As shown in Figure 7 , in other embodiments of the present disclosure, the switching circuit can include a voltage boosting capacitor C3. One electrode plate of the voltage boosting capacitor C3 is electrically connected with the output end of the switching circuit as the first end of the voltage boosting circuit; and the other electrode plate of the voltage boosting capacitor is used to load the voltage boosting control signal as the second end of the voltage boosting circuit.

[0076] As shown in Figure 8 , the present disclosure further provides a driving method of the signal selector. When the voltage boosting circuit includes a voltage boosting transistor, the driving method can include:

[0077] In step S10, a preparation voltage is loaded to the gate of the voltage boosting transistor in a preparation period, so that the Vgs of the voltage boosting transistor is not less than the Vth of the voltage boosting transistor.

[0078] In step S20, a write signal is loaded to the control end of the switching circuit in a data writing period after the preparation period.

[0079] In step S30, a voltage boosting control signal is loaded to the control end of the voltage boosting transistor in a voltage boosting period after the data writing period.

[0080] As shown in Figure 9As shown, during the preparation period, the gate voltage Vg of the boost transistor T2 is increased from -8V to 0V, at this time, the Vgs voltage of the boost transistor T2 is greater than Vth, and the capacitance value of the boost transistor T2 reaches the maximum value. The voltage on the output data line Source connected with the first red sub-pixel R1 is increased from 0V to 0.4V by the driving of the driving chip electrically connected with the first sub-input data line S1.

[0081] The relationship curve between the capacitance C1 of the boost transistor T2 and the gate voltage Vg is as shown in Figure 10 As shown, when Vgs is greater than Vth, the capacitance C1 of the boost transistor T2 reaches the maximum value. During the pull-up period, the gate voltage Vg of the boost transistor T2 is increased from 0V to +8V, and the voltage on the output data line Source connected with the first red sub-pixel R1 is increased from 4V to 5.26V. The coupling effect of the boost transistor T2 mainly occurs in this stage.

[0082] It can be understood that, due to the coupling effect of the boost transistor T2, the maximum voltage that can be charged on the output data line Source connected with the first red sub-pixel R1 is 5.26V, and the charging rate of the display panel is 5.26 / 5.3=0.9924, which meets the required charging rate specification of 0.99 of the display panel.

[0083] It should be emphasized that, during the driving process of the signal selector, the lag time of the falling edge of the write signal relative to the falling edge of the boost signal is at least greater than the pulse width of the write signal, so as to prevent the falling edge of the boost signal from having a pull-down effect on the pixel voltage. Generally, the pulse width of the write signal is about 0.65μs.

[0084] It should be noted that Vgs is the voltage difference between the control end and the first end of the boost transistor T2, and Vth is the threshold voltage, which is generally 0V. The control end is the gate of the boost transistor T2, and the first end is the source of the boost transistor T2.

[0085] As shown in Figure 11 When the boost circuit includes a boost transistor, in the driving method of the signal selector of other embodiments of the present disclosure, the first sub-signal line MUX1 lags behind the second sub-signal line MUX2 to be turned on. The driving method first increases the voltage loaded on the second sub-signal line MUX2 from -8V to 8V, and the voltage on the output data line Source connected with the first red sub-pixel R1 is increased from 0V to 4.9V by the driving of the driving chip electrically connected with the first sub-input data line S1.

[0086] Then the voltage loaded on the first sub-signal line MUX1 is increased from -8V to 8V, under the capacitive coupling effect of the boosting transistor, the voltage of the output data line Source connected with the first red sub-pixel R1 is increased from 4.9V to 5.02V, which is only increased by 0.04V compared with 4.98V of the signal selector in the figure, and the promotion effect is not obvious, because when the first sub-signal line MUX1 is increased from -8V to 8V, the capacitance value of the boosting transistor reaches the maximum, so the coupling effect is poor.

[0087] The display panel provided by the present disclosure includes a substrate BP, a driving circuit layer and a color filter layer which are sequentially stacked. Figures 12 to 20 As shown in the figure, the display panel includes a substrate BP, a driving circuit layer and a color filter layer which are sequentially stacked. The color filter layer is provided with arrayed light filtering parts, and the driving circuit layer is provided with driving circuits corresponding to each sub-pixel. Each sub-pixel changes the rotation direction of liquid crystal molecules under the driving of the corresponding driving circuit, so as to control the emission of polarized light of each sub-pixel point and achieve the display purpose, thereby realizing the display of corresponding images.

[0088] In the driving circuit layer, the display panel can be provided with scan wires extending along a first direction and data wires extending along a second direction. The display panel can realize line-by-line scanning to display a picture. It should be noted that the first direction is generally taken as the row direction, and the second direction is generally taken as the column direction.

[0089] Referring to Figure 12 From the perspective of film layer stacking, the display panel of the present disclosure can include a substrate BP, a buffer layer Buffer and a driving circuit layer which are sequentially stacked. The substrate BP is provided with the buffer layer Buffer on one side, and the buffer layer Buffer is provided with the driving circuit layer on the side away from the substrate BP.

[0090] The substrate BP11 can be an inorganic material substrate BP or an organic material substrate BP. For example, in an embodiment of the present disclosure, the material of the substrate BP can be a glass material such as soda-lime glass, quartz glass, sapphire glass, or a metal material such as stainless steel, aluminum, nickel, etc.

[0091] In another embodiment of the present disclosure, the material of the substrate BP can be Polymethyl methacrylate (PMMA), Polyvinyl alcohol (PVA), Polyvinyl phenol (PVP), Polyether sulfone (PES), polyimide, polyamide, polyacetal, Poly carbonate (PC), Polyethylene terephthalate (PET), Polyethylene naphthalate (PEN), or a combination thereof.

[0092] In another embodiment of the present disclosure, the substrate BP can also be a flexible substrate BP, for example, the material of the substrate BP can be polyimide (PI). The substrate BP can also be a composite of multiple layers of materials, for example, in an embodiment of the present disclosure, the substrate BP can include a Bottom Film layer, a pressure sensitive adhesive layer, a first polyimide layer, and a second polyimide layer, which are sequentially stacked.

[0093] The driving circuit layer includes a plurality of driving circuit regions. Any one of the driving circuit regions can include a transistor and a storage capacitor. The transistor can be a thin film transistor, which can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor.

[0094] The material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, or other types of semiconductor material; the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.

[0095] The transistor can have a first end, a second end, and a control end, one of the first end and the second end can be the source of the transistor and the other can be the drain of the transistor, and the control end can be the gate of the transistor. It can be understood that the source and the drain of the transistor are two opposite and interchangeable concepts; when the working state of the transistor changes, for example, the current direction changes, the source and the drain of the transistor can be interchanged.

[0096] In the present disclosure, the drive circuit layer can include a transistor layer, an interlayer dielectric layer ILD and a source-drain metal layer LSD which are sequentially stacked on the substrate BP. The transistor layer is provided with an active layer and a gate of a transistor. The source-drain metal layer LSD is electrically connected to the source and the drain of the transistor. Optionally, the transistor layer can include an active layer Lpoly, a gate insulating layer GI and a gate layer LG which are sequentially stacked between the substrate BP and the interlayer dielectric layer ILD. The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor.

[0097] In some embodiments, the active layer Lpoly can be used to form the active layer of the transistor. The active layer of the semiconductor includes a channel region and a source and a drain located on both sides of the channel region. The channel region can maintain the semiconductor property, and the semiconductor material of the source and the drain is partially or completely conductive. The gate layer LG can be used to form the gate layer of the scan wire, and can also be used to form the gate of the transistor, and can also be used to form part or all of the electrode plate of the storage capacitor. The source-drain metal layer LSD can be used to form the data wire, the power supply wire and other source-drain metal layer wires.

[0098] Taking a top-gate thin film transistor as an example, in some embodiments of the present disclosure, the drive circuit layer can include an active layer Lpoly, a gate insulating layer GI, a gate layer LG, an interlayer dielectric layer ILD and a source-drain metal layer LSD which are sequentially stacked.

[0099] The display panel has a display area AA and a non-display area BB located at the periphery of the display area AA. Each drive circuit area includes a switch circuit area and a drive transistor. The switch circuit area is located in the non-display area BB, and the drive transistor is located in the display area AA. The switch circuit area includes a switch transistor. The control end of the drive transistor can be connected to the second end of the switch transistor.

[0100] When the display panel is an LCD, on the basis of the above, the drive circuit layer of the display area AA of the display panel can further include a planarization layer PLN. According to different situations, the planarization layer PLN can be provided as one layer or multiple layers. The planarization layer PLN can be provided on the side of the source-drain metal layer LSD of the drive transistor away from the substrate BP, and the surface of the planarization layer PLN away from the substrate BP is planar. The planarization layer PLN is provided with a plurality of first vias which expose the source-drain metal layer LSD of the drive transistor. The side of the planarization layer PLN away from the substrate BP can be provided with a common electrode LCOM. The common electrode LCOM is provided with a plurality of second vias. The orthographic projection of the second vias on the substrate BP is located within the orthographic projection of the first vias on the substrate BP.

[0101] A protective layer PVX is provided on the side of the common electrode LCOM away from the substrate BP. The protective layer PVX covers the side of the common electrode LCOM away from the substrate BP. The protective layer PVX extends from the portion of the common electrode LCOM where the second via is located and the portion of the planarization layer PLN where the first via is located, to the source / drain metal layer LSD of the driving transistor. The end of the protective layer PVX closest to the substrate BP partially covers the source / drain metal layer LSD of the driving transistor, forming an opening that exposes a portion of the source / drain metal layer LSD of the driving transistor. Multiple pixel electrodes LAn are provided on the side of the protective layer PVX away from the substrate BP. The pixel electrodes LAn are located within the opening and connected to the source / drain metal layer LSD of the driving transistor.

[0102] A liquid crystal layer (LCL) is disposed on the side of the pixel electrode LAn away from the source / drain metal layer LSD of the driving transistor. The liquid crystal layer LCL covers the protective layer PVX and the source / drain metal layer LSD of the driving transistor. Since the protective layer PVX is disposed between the pixel electrode LAn and the common electrode LCOM, and both the pixel electrode LAn and the common electrode LCOM have driving surfaces, the liquid crystal layer LCL can be considered to be located between the pixel electrode LAn and the common electrode LCOM.

[0103] A color filter layer CF is provided on the side of the liquid crystal layer LCL away from the substrate. An insulating layer IL can be provided on the side of the color filter layer CF in the display area AA and the planarization layer PLN in the non-display area BB away from the substrate BP. The insulating layer IL extends from the surface of the color filter layer CF away from the substrate BP to the side of the color filter layer CF, the side of the liquid crystal layer LCL, the side of the protective layer PVX and the side of the common electrode LCOM, and covers the side of the planarization layer PLN in the non-display area BB away from the substrate.

[0104] like Figures 13 to 16 As shown, in the non-display area of ​​the display panel, the active layer Lpoly includes a first active part T1A, a third active part T1S, and a fourth active part T1D.

[0105] The gate layer LG includes a first control lead GL1 and a first input data line disposed along the first direction H1. The orthographic projection of the first control lead GL1 on the substrate BP overlaps with the orthographic projection of the first active part T1A on the substrate BP, forming the gate of the switching transistor.

[0106] The source-drain metal layer LSD includes a first conductive structure ML1, a second conductive structure ML2 and an output data line Source arranged along the first direction H1. The first conductive structure ML1 is connected with the first input data line, and the orthogonal projection of the first conductive structure ML1 on the substrate BP overlaps and is connected with the orthogonal projection of the third active part T1S on the substrate BP, thereby forming the source electrode of the switching transistor. The orthogonal projection of the second conductive structure ML2 on the substrate BP overlaps and is connected with the orthogonal projection of the fourth active part T1D on the substrate BP, thereby forming the drain electrode of the switching transistor and the drain electrode of the boosting transistor. The second conductive structure ML2 is connected with the output data line Source.

[0107] The switching circuit area CC further includes a boosting circuit. When the boosting circuit of the display panel is a boosting transistor, the active layer Lpoly further includes a second active part T2A and a fifth active part T2S. The gate layer LG further includes a second control lead line GL2, and the orthogonal projection of the second control lead line GL2 on the substrate BP overlaps with the orthogonal projection of the second active part T2A on the substrate BP, thereby forming the gate electrode of the boosting transistor.

[0108] The source-drain metal layer LSD further includes a third conductive structure ML3, and the orthogonal projection of the third conductive structure ML3 on the substrate BP overlaps with the orthogonal projection of the fifth active part T2S on the substrate BP. The third conductive structure is connected with the fifth active part T2S, thereby forming the source electrode of the boosting transistor. The third conductive structure ML3 is connected with the second conductive structure ML2, and the third conductive structure ML3 and the second conductive structure ML2 are both connected with the output data line Source.

[0109] It should be noted that, in the first direction H1, the orthogonal projection of the second conductive structure ML2 on the substrate BP is located between the orthogonal projection of the first conductive structure ML1 on the substrate BP and the orthogonal projection of the third conductive structure ML3 on the substrate BP. The orthogonal projection of the second conductive structure ML2 on the substrate BP is located outside the orthogonal projection of the first control lead line GL1 on the substrate BP, and the orthogonal projection of the third conductive structure ML3 on the substrate BP is located outside the orthogonal projection of the second control lead line GL2 on the substrate BP.

[0110] In addition, the source-drain metal layer LSD can further include a first signal line and a second signal line arranged along the second direction H2. The second signal line is connected with the first control lead line GL1, and the first signal line is connected with the second control lead line.

[0111] Taking the signal selector of six sub-signal lines as an example, the number of the switch circuit regions CC is six. The six switch circuit regions CC are divided into two switch circuit region groups, each of which forms a switch circuit island, and each of the switch circuit islands includes three switch circuit regions CC which are sequentially arranged along the first direction H1, and the output data lines Source of the three switch circuit regions CC are respectively connected to the red sub-pixels, the green sub-pixels and the blue sub-pixels.

[0112] Specifically, in the three switch circuit regions CC in one switch circuit island, the output data line Source of the first switch circuit region CC is connected to the control end of the driving transistor corresponding to the red sub-pixel, the output data line Source of the second switch circuit region CC is connected to the control end of the driving transistor corresponding to the green sub-pixel, and the output data line Source of the third switch circuit region CC is connected to the control end of the driving transistor corresponding to the blue sub-pixel.

[0113] The source-drain metal layer LSD further includes a first transfer line TR1, one first transfer line TR1 is connected to each first conductive structure ML1 in one switch circuit region group, and the first sub-input data line S1 is connected to the first transfer line TR1. Another first transfer line TR1 is connected to each first conductive structure ML1 in another switch circuit region group, and the second sub-input data line S2 is connected to the second transfer line TR2.

[0114] The gate layer LG can further include a second input data line S3, a touch signal line TX and a second transfer line TR2, the second transfer line TR2 extends along the first direction H1, the second input data line S3 and the touch signal line TX extend along the second direction H2, the second input data line S3 is located on the side of the second transfer line TR2 close to the signal line, and the touch signal line TX is located on the side of the second transfer line TR2 away from the signal line. The second input data line S3 and the touch signal line TX are both connected to the second transfer line TR2 in the second direction, and the touch signal line TX can be provided as two, and the two touch signal lines TX are distributed on the two sides of the second input data line S3 along the first direction H1. The touch signals on the second input data line S3 are distributed to different touch signal lines TX, and the touch signal lines TX are used to drive the touch electrodes of the display panel.

[0115] In order to ensure the normal display of the display panel, it is usually necessary to ensure that the positive and negative polarities of the data signals of adjacent sub-pixels are different. Usually, the first sub-input data line S1 and the second sub-input data line S2 input positive total data signals and negative total data signals respectively, and in order to ensure that the positive and negative polarities of adjacent output sub-data signals are different, it is necessary to set a transfer line to adjust the positive and negative polarities of individual output sub-data signals.

[0116] For example, the first sub-input data line S1 inputs a positive total data signal, and the second sub-input data line S2 inputs a negative total data signal. The sub-pixels include a first red sub-pixel R1, a first green sub-pixel G1, a first blue sub-pixel B1, a second red sub-pixel R2, a second green sub-pixel G2, and a third blue sub-pixel B2, which are distributed sequentially along the first direction. The first sub-input data line S1 and the second sub-input data line S2 each correspond to a set of output data lines Source. The output data lines Source include a first output data line, a second output data line, and a third output data line.

[0117] The first output data line corresponding to the first input data line S1 is connected to the first red sub-pixel R1, the third output data line corresponding to the first input data line S1 is connected to the first blue sub-pixel, the first output data line corresponding to the second input data line S2 is connected to the second red sub-pixel, and the third output data line corresponding to the second input data line S2 is connected to the second blue sub-pixel.

[0118] The display panel also includes a third adapter cable TR3 and a fourth adapter cable TR4. The second output data line corresponding to the first input data line S1 is connected to the third adapter cable TR3. The third adapter cable TR3 is connected to the second green sub-pixel G2. The second output data line corresponding to the second input data line S2 is connected to the fourth adapter cable TR4. The fourth adapter cable TR4 is connected to the first green sub-pixel G1.

[0119] The third adapter line TR3 may include a first adapter segment TR31 and a second adapter segment TR32. The first adapter segment TR31 is connected to the output data line Source connected to the first green sub-pixel G1 and to the second adapter segment TR32. The second adapter segment TR32 is connected to the source of the driving transistor of the second green sub-pixel G2. The fourth adapter line TR4 may include a third adapter segment TR41 and a fourth adapter segment TR42. The third adapter segment TR41 is connected to the output data line Source connected to the second green sub-pixel G2 and to the fourth adapter segment TR52. The fourth adapter segment TR52 is connected to the source of the driving transistor of the first green sub-pixel G1.

[0120] In this way, the sub-data signals of the first red sub-pixel R1, the second green sub-pixel G2, the first blue sub-pixel B1, the second red sub-pixel R2, the first green sub-pixel G1, and the second blue sub-pixel B2 are "positive, negative, positive, negative, positive, negative" in sequence, which meets the display requirements of the display panel.

[0121] like Figures 17 to 20 As shown, this disclosure provides another display panel. This display panel is similar to... Figures 13 to 16 The difference in the display panel is that the boost circuit uses a boost capacitor.

[0122] When the boosting circuit is a boosting capacitor, the active layer Lpoly only includes the source T1S, the drain T1D and the first active part T1A of the switching transistor.

[0123] The gate layer LG includes a first control lead GL1, a second control lead GL2 and an input data line arranged along the first direction H1, the orthographic projection of the first control lead GL1 on the substrate base plate BP overlaps the first active part T1A, constituting the gate of the switching transistor.

[0124] The source-drain metal layer LSD includes a first conductive structure ML1, a second conductive structure ML2, a third conductive structure ML3 and an output data line Source arranged along the first direction H1, in the first direction H1, the second conductive structure ML2 is located between the first conductive structure ML1 and the third conductive structure ML3, and the second conductive structure ML2 and the third conductive structure ML3 are connected with the output data line Source.

[0125] The first conductive structure ML1 is connected with the input data line, the orthographic projection of the first conductive structure ML1 on the substrate base plate BP overlaps and is connected with the orthographic projection of the third active part T1S on the substrate base plate BP, constituting the source of the switching transistor. The orthographic projection of the second conductive structure ML2 on the substrate base plate BP overlaps and is connected with the orthographic projection of the fourth active part T1D on the substrate base plate BP, constituting the drain of the switching transistor and the drain of the boosting transistor.

[0126] In addition, the source-drain metal layer LSD can also include a first signal line and a second signal line arranged along the second direction H2, the second signal line is connected with the first control lead GL1, and the first signal line is connected with the second control lead.

[0127] In order to ensure the size of the capacitor, the area of the second control lead GL2 and the third conductive structure ML3 is usually not too small, in order to prevent the formation of a large piece of metal, a plurality of first through holes HA1 are arranged on the second conductive structure along the second direction H2, and a plurality of second through holes HA2 are arranged on the third conductive structure along the second direction H2, the orthographic projection of the second through hole HA2 on the substrate base plate BP is located within the orthographic projection of the first through hole HA1 on the substrate base plate BP, more specifically, the orthographic projection of the second through hole HA2 on the substrate base plate BP can coincide with the orthographic projection of the first through hole HA1 on the substrate base plate BP.

[0128] The edge between the driving back plate and the color film layer is usually cured by optical curing glue, light transmits through the first through hole HA1 and the second through hole HA2, which improves the curing effect of the optical curing glue, thereby affecting the fixing strength between the driving back plate and the color film layer CF. It should be noted that the optical curing glue can be UV glue.

[0129] This disclosure provides a display device. The display device includes the display panel described in any of the above embodiments of this disclosure. The specific structure and beneficial effects of this display device can also be referenced to the display panel, and will not be repeated here.

[0130] Display devices can be traditional electronic devices, such as mobile phones, computers, televisions, and video recorders, or emerging wearable devices, such as virtual reality devices and augmented reality devices, which will not be listed here.

[0131] It should be noted that, in addition to the display panel, the display device also includes other necessary components and parts. Taking a mobile phone as an example, these may include the casing, circuit board, etc. Those skilled in the art can make corresponding additions according to the specific usage requirements of the display device, which will not be elaborated here.

[0132] It should be noted that although the steps of the method for manufacturing the display panel in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0133] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, characterized in that, The system includes a substrate and a driving circuit layer disposed on one side of the substrate. The driving circuit layer includes multiple switching circuit regions, each of which includes: An active layer is disposed on one side of the substrate, and the active layer includes a first active portion, a second active portion, a third active portion, a fourth active portion and a fifth active portion; A gate layer is disposed on the side of the active layer away from the substrate. The gate layer includes a first control lead, a second control lead, and a first input data line disposed along a second direction. The orthographic projection of the first control lead on the substrate overlaps with the orthographic projection of the first active portion on the substrate. The orthographic projection of the second control lead on the substrate overlaps with the orthographic projection of the second active portion on the substrate. A source / drain metal layer is disposed on the side of the gate layer away from the substrate. The source / drain metal layer includes a first signal line and a second signal line disposed along a first direction, and a first conductive structure, a second conductive structure, a third conductive structure, and an output data line disposed along a second direction. The second signal line is connected to the first control lead, and the first signal line is connected to the second control lead. The first conductive structure is connected to the first input data line. The orthographic projection of the first conductive structure on the substrate overlaps with the orthographic projection of the third active portion on the substrate, and the first conductive structure is connected to the third active portion. The orthographic projection of the second conductive structure on the substrate overlaps with the orthographic projection of the fourth active portion on the substrate, and the second conductive structure is connected to the fourth active portion. The orthographic projection of the third conductive structure on the substrate overlaps with the orthographic projection of the fifth active portion on the substrate, and the third conductive structure is connected to the fifth active portion. The third conductive structure is connected to the second conductive structure, and the second and third conductive structures are connected to the output data line.

2. The display panel according to claim 1, characterized in that, In a first direction, the orthographic projection of the second conductive structure on the substrate is located between the orthographic projections of the first control lead and the second control lead on the substrate, the orthographic projection of the second conductive structure on the substrate is located outside the orthographic projection of the first control lead on the substrate, and the orthographic projection of the third conductive structure on the substrate is located outside the orthographic projection of the second control lead on the substrate.

3. The display panel according to claim 1, characterized in that, The display panel includes multiple switch circuit area groups, each group of switch circuit areas includes at least three switch circuit areas, the at least three switch circuit areas are arranged at intervals along a first direction, and the output data line connected to each switch circuit area is connected to a sub-pixel of a certain color, and the positive and negative polarities of the driving terminals of two adjacent different sub-pixels are different.

4. The display panel according to claim 1, characterized in that, The multiple switching circuits are divided into multiple switching circuit groups, each switching circuit group includes at least three switching circuits, and the source and drain metal layers also include at least one first adapter wire disposed along a first direction. One first adapter wire is connected to each of the first conductive structures in one of the switching circuit groups, and the first input data line is connected to the first adapter wire.

5. The display panel according to claim 3, characterized in that, The first input data line includes a first sub-input data line and a second sub-input data line. The first sub-input data line inputs a positive total data signal, and the second sub-input data line inputs a negative total data signal. The sub-pixel includes a first red sub-pixel, a first green sub-pixel, a first blue sub-pixel, a second red sub-pixel, a second green sub-pixel, and a third blue sub-pixel distributed sequentially along a first direction. The first sub-input data line and the second sub-input data line respectively correspond to a set of first output data lines, second output data lines, and third output data lines. The first output data line corresponding to the first input data line is connected to the first red sub-pixel, and the third output data line corresponding to the first input data line is connected to the first blue sub-pixel. The first output data line corresponding to the second sub-input data line is connected to the second red sub-pixel, and the third output data line corresponding to the second sub-input data line is connected to the second blue sub-pixel. The display panel also includes a third adapter cable and a fourth adapter cable. The second output data line corresponding to the first input data line is connected to the third adapter cable, and the third adapter cable is connected to the second green sub-pixel. The second output data line corresponding to the second sub-input data line is connected to the fourth adapter cable, and the fourth adapter cable is connected to the first green sub-pixel.

6. The display panel according to claim 3 or 4, characterized in that, The first signal line includes a first sub-signal line, a third sub-signal line, and a fifth sub-signal line. The second signal line includes a second sub-signal line, a fourth sub-signal line, and a sixth sub-signal line. Each switch circuit group includes three switch circuit regions. The second control lead of the first switch circuit region is connected to the first sub-signal line. The second control lead of the second switch circuit region is connected to the third sub-signal line. The second control lead of the third switch circuit region is connected to the fifth sub-signal line. The first control lead of the first switch circuit region is connected to the second sub-signal line. The first control lead of the second switch circuit region is connected to the fourth sub-signal line. The first control lead of the third switch circuit region is connected to the sixth sub-signal line.

7. The display panel according to claim 1, characterized in that, The gate layer further includes a second input data line, a second adapter line, and a touch signal line. The second adapter line is arranged along a first direction, and the second input data line and the touch signal line are arranged along a second direction. The second adapter line connects the second input data line and the touch signal line. The touch signal on the second input data line is distributed to different touch signal lines. The touch signal line is used to drive the touch electrodes of the display panel.

8. The display panel according to claim 1, characterized in that, The display panel further includes a signal selector for distributing signals on the input data lines to different output data lines, wherein the output data lines are used to drive sub-pixels of the display panel. The signal selector includes multiple switching units, and any one of the switching units includes: A switching circuit, the switching circuit being connected to the input data line and an output data line, the switching circuit being turned on in response to a write signal applied to its control terminal; A boost circuit, wherein the first terminal of the boost circuit is electrically connected to the output terminal of the switching circuit; the boost circuit is used to pull up the voltage at the output terminal of the switching circuit in response to a boost control signal applied to its control terminal; The boost circuit includes a boost transistor, with a first terminal and / or a second terminal of the boost transistor serving as the first terminal of the boost circuit and electrically connected to the output terminal of the switching circuit; the control terminal of the boost transistor serves as the second terminal of the boost circuit and is used to load a boost control signal. The switching circuit is a switching transistor, the first terminal of the switching circuit is the source of the switching transistor, the second terminal of the switching circuit is the drain of the switching transistor, and the control terminal of the switching circuit is the gate of the switching transistor. The orthographic projection of the first control lead on the substrate overlaps with the orthographic projection of the first active portion on the substrate, forming the gate of the switching transistor. The orthographic projection of the second control lead on the substrate overlaps with the orthographic projection of the second active portion on the substrate, forming the gate of the boost transistor. The orthographic projection of the first conductive structure on the substrate overlaps with and is connected to the orthographic projection of the third active portion on the substrate, forming the source of the switching transistor. The orthographic projection of the second conductive structure on the substrate overlaps with and is connected to the orthographic projection of the fourth active portion on the substrate, forming the drain of the switching transistor and the drain of the boost transistor. The orthographic projection of the third conductive structure on the substrate overlaps with the orthographic projection of the fifth active portion on the substrate, and the third conductive structure and the fifth active portion are connected, forming the source of the boost transistor.

9. The display panel according to claim 8, characterized in that, The multiple switching units are divided into multiple switching unit groups, and each switching unit group includes at least three switching units. The output data lines connected to different switching units are respectively connected to sub-pixels of different colors.

10. The display panel according to claim 9, characterized in that, The signal selector includes multiple input data lines, and each input data line is connected to one of the switch unit groups.

11. A display panel, characterized in that, The system includes a substrate and a driving circuit layer disposed on one side of the substrate. The driving circuit layer includes multiple switching circuit regions, each of which includes: An active layer is disposed on one side of the substrate, and the active layer includes a first active portion, a second active portion, a third active portion and a fourth active portion; A gate layer is disposed on the side of the active layer away from the substrate. The gate layer includes a first control lead, a second control lead, and an input data line. The orthographic projection of the first control lead on the substrate overlaps with the orthographic projection of the first active portion on the substrate. A source / drain metal layer is disposed on the side of the gate layer away from the substrate. The source / drain metal layer includes a first signal line and a second signal line disposed along a first direction, and a first conductive structure, a second conductive structure, a third conductive structure, and an output data line disposed along a second direction. The second signal line is connected to the first control lead, and the first signal line is connected to the second control lead. The first conductive structure is connected to the first input data line. The orthographic projection of the first conductive structure on the substrate overlaps with and is connected to the orthographic projection of the third active part on the substrate. The orthographic projection of the second conductive structure on the substrate overlaps with and is connected to the orthographic projection of the fourth active part on the substrate. The orthographic projection of the third conductive structure on the substrate overlaps with the orthographic projection of the second control line on the substrate. The third conductive structure and the second control line form a boost capacitor. The third conductive structure is connected to the second conductive structure. The second conductive structure and the third conductive structure are connected to the output data line.

12. The display panel according to claim 11, characterized in that, The second conductive structure is provided with a plurality of first through holes, and the third conductive structure is provided with a plurality of second through holes, wherein the orthogonal projection of the second through hole on the substrate is located within the orthogonal projection of the first through hole on the substrate.

13. The display panel according to claim 11, characterized in that, The display panel further includes a signal selector for distributing signals on the input data lines to different output data lines, wherein the output data lines are used to drive sub-pixels of the display panel. The signal selector includes multiple switching units, and any one of the switching units includes: A switching circuit, the switching circuit being connected to the input data line and an output data line, the switching circuit being turned on in response to a write signal applied to its control terminal; A boost circuit, wherein the first terminal of the boost circuit is electrically connected to the output terminal of the switching circuit; the boost circuit is used to pull up the voltage at the output terminal of the switching circuit in response to a boost control signal applied to its control terminal; The boost circuit includes a boost capacitor, one electrode plate of which serves as the first terminal of the boost circuit and is electrically connected to the output terminal of the switching unit; the other electrode plate of the boost capacitor serves as the second terminal for loading a boost control signal. The switching circuit is a switching transistor, the first terminal of the switching circuit is the source of the switching transistor, the second terminal of the switching circuit is the drain of the switching transistor, and the control terminal of the switching circuit is the gate of the switching transistor. The orthographic projection of the first control lead on the substrate overlaps with the orthographic projection of the first active portion on the substrate, forming the gate of the switching transistor. The orthographic projection of the first conductive structure on the substrate overlaps with and is connected to the orthographic projection of the third active portion on the substrate, forming the source of the switching transistor. The orthographic projection of the second conductive structure on the substrate overlaps with and is connected to the orthographic projection of the fourth active portion on the substrate, forming the drain of the switching transistor.

14. The display panel according to claim 13, characterized in that, The multiple switching units are divided into multiple switching unit groups, and each switching unit group includes at least three switching units. The output data lines connected to different switching units are respectively connected to sub-pixels of different colors.

15. The display panel according to claim 14, characterized in that, The signal selector includes multiple input data lines, and each input data line is connected to one of the switch unit groups.

16. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 15.

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