Display panel and display device

Abstract

The present application discloses a display panel and a display device, including a plurality of pixel units, wherein the pixel units include a driving module and a compensation module. During a period when the M-th row of pixel units in an N-th frame image is scanned, the driving module is used to receive a data signal for image display and drive a display medium to display the image according to the data signal. The compensation module is connected to the driving module and is used to receive the data signal from the driving module and to charge the module. Within a preset period after the scanning of the M-th row of pixel units is completed, the compensation module outputs a compensation voltage to the driving module to perform voltage compensation on the driving module, thereby eliminating the problems of light crosstalk and display unevenness caused by parasitic capacitance.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of liquid crystal display technology, narrow-frame display screens have become the main trend of high-quality display screens due to their simplicity, beauty, and large viewing area of ​​the same size. Liquid crystal display panels mainly drive the deflection of liquid crystal molecules by forming a voltage difference between the pixel electrodes on the array substrate and the common electrodes, thereby emitting light of different brightness to display images.

[0003] However, since parasitic capacitance exists between the data lines and liquid crystals, between data lines and between data lines and between data lines and scan lines in the array substrate, the data voltage will be affected by the parasitic capacitance when controlling the deflection of the liquid crystal, resulting in the output brightness being different from the preset brightness. Therefore, how to eliminate the influence of parasitic capacitance on pixel brightness is an urgent problem to be solved. Summary of the invention

[0004] In view of the shortcomings of the above technical problems, the present application provides a display panel and a display device that can effectively eliminate the influence of parasitic capacitance.

[0005] The embodiment of the present application discloses a display panel including an array substrate, a display medium layer and an opposite substrate which are stacked in sequence, wherein the array substrate is used to cooperate with the opposite substrate to drive the display medium in the display medium layer to display an image. The array substrate includes a plurality of pixel units arranged in an array, wherein the pixel unit includes a driving module and a compensation module, wherein during the period when the Mth row of pixel units in the Nth frame image is scanned, the driving module is used to receive a data signal for image display and drive the display medium to display an image according to the data signal, wherein the compensation module is connected to the driving module, and is used to receive the data signal from the driving module and charge the device, and within a preset period after the scanning of the Mth row of pixel units is completed, the compensation module outputs a compensation voltage to the driving module to perform voltage compensation on the driving module, wherein N and M are integers greater than 1 or equal to 1.

[0006] Optionally, the preset time period is a time period from the completion of scanning the Mth row of pixel units to the scanning of the Mth row of pixel units in the N+1th frame image display; or, the preset time period is a time period from the completion of scanning the M+Kth row of pixel units in the Nth frame image display to the scanning of the Mth row of pixel units in the N+1th frame image display, where M is an integer greater than 1; or, the preset time period is a waiting period at the end of the Nth frame image display to the scanning of the Mth row of pixel units in the N+1th frame image display, and the waiting period is a time period before a frame of image is displayed, and during the waiting period the data line suspends transmitting the data signal.

[0007] Optionally, the array substrate further includes a plurality of scan lines extending along the first direction and sequentially arranged along the second direction and a plurality of data lines extending along the second direction and sequentially arranged along the first direction;

[0008] The driving module is connected to the scan line and the data line, and is used to receive the data signal from the data line under the control of the scan signal output by the scan line and drive the display medium to perform image display according to the data signal. The compensation module is connected to the scan line and the driving module, and is used to receive the data signal from the driving module for charging under the control of the scan signal.

[0009] Optionally, the driving module includes a first switching tube, a first capacitor and a second capacitor, the gate of the first switching tube is connected to the scan line, the source of the first switching tube is connected to the data line, and the drain of the first switching tube is connected to the first capacitor and the second capacitor, and is used to be turned on under the control of the scan signal to transmit the data signal to the first capacitor and the second capacitor, and charge the first capacitor and the second capacitor.

[0010] Optionally, the array substrate further includes a plurality of scan lines extending along the first direction and arranged in sequence along the second direction and a plurality of data lines extending along the second direction and arranged in sequence along the first direction; the plurality of scan lines include a first scan line and a second scan line arranged adjacent to each other, the driving module is connected to the first scan line, the second scan line and the data line, and is used to receive the data signal from the data line under the control of a first scan signal output by the first scan line and a second scan signal output by the second scan line; the compensation module is connected to the first scan line and the driving module, and is used to receive the data signal from the driving module under the control of the first scan signal for charging.

[0011] Optionally, the driving module includes a first switch tube, a second switch tube, a first capacitor and a second capacitor, the gate of the first switch tube is connected to the first scan line, the source of the first switch tube is connected to the second switch tube, and the drain of the first switch tube is connected to the first capacitor and the second capacitor, and is used to be turned on under the control of the first scan signal to receive the data signal from the second switch tube; the gate of the second switch tube is connected to the second scan line, the source of the second switch tube is connected to the data line, and the drain of the second switch tube is connected to the source of the first switch tube, and is used to be turned on under the control of the second scan signal to transmit the data signal to the first switch tube, and transmit it to the first capacitor and the second capacitor via the first switch tube, so as to charge the first capacitor and the second capacitor.

[0012] Optionally, the compensation module includes a third switch tube and a compensation capacitor, the gate of the third switch tube is connected to the first scan line, the first conductive end of the third switch tube is connected to the drain of the first switch tube, and the second conductive end of the third switch tube is connected to the compensation capacitor, and is used to be turned on under the control of the first scan signal to receive the data signal from the first switch tube to charge the compensation capacitor.

[0013] Optionally, the compensation module also includes a fourth switch tube, the gate of the fourth switch tube is connected to the compensation control end, the first conductive end of the fourth switch tube is connected to the compensation capacitor, and the second conductive end of the fourth switch tube is connected to the first capacitor and the second capacitor; one end of the compensation capacitor is connected to the fourth switch tube, and the other end of the compensation capacitor is connected to the power supply voltage end, the first capacitor and the second capacitor are connected in parallel between the drain of the first switch tube and the common electrode, the voltage output by the power supply voltage end is greater than the voltage of the common electrode, and the fourth switch tube is used to be turned on under the control of the compensation control end to control the compensation capacitor to charge the first capacitor and the second capacitor.

[0014] Optionally, when the pixel unit performs a frame image display, it includes a continuous first period, a second period and a third period. In the first period, the first scanning signal and the second scanning signal are output simultaneously to control the first switch tube, the second switch tube and the third switch tube to be turned on, the first capacitor and the second capacitor receive the data signal to charge and drive the display medium to display the image, and the compensation capacitor receives the data signal to be charged. In the second period, the second scanning signal stops being output, the second switch tube is turned off, and the voltage of the first scanning signal gradually decreases to control the first switch tube and the third switch tube to be gradually turned off. The compensation capacitor is electrically connected to the first capacitor and the second capacitor through the third switch tube, and is used to maintain the voltage of the first capacitor and the second capacitor when the first switch tube and the third switch tube are gradually turned off. In the third period, the compensation control terminal controls the fourth switch tube to be turned on to control the compensation capacitor to compensate the voltage of the first capacitor and the second capacitor.

[0015] The present application also provides a display device, including a power module and the aforementioned display panel, wherein the power module is used to provide driving power for the display panel to display images.

[0016] Compared with the existing technical problems, the present application can effectively eliminate the influence of parasitic capacitance on the display medium by setting a compensation module in the pixel unit and controlling the compensation module to perform voltage compensation on the driving module during a preset period, thereby eliminating the problems of light crosstalk and uneven display and improving the image display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of the structure of a display device provided in the first embodiment of the present application;

[0019] Figure 2 for Figure 1 A schematic diagram of the side structure of the display device;

[0020] Figure 3 for Figure 2 A schematic diagram of the plane layout of an array substrate in the display panel shown;

[0021] Figure 4 for Figure 3 Schematic diagram of the parasitic capacitance circuit of the pixel unit;

[0022] Figure 5 for Figure 3 Schematic diagram of pixel voltage change of pixel unit;

[0023] Figure 6 A second embodiment of the present application provides a Figure 3 Schematic diagram of the circuit structure of the pixel unit;

[0024] Figure 7 A third embodiment of the present application provides a Figure 3 A circuit block diagram of a pixel unit;

[0025] Figure 8 for Figure 7 Mid scan signal output timing diagram.

[0026] Description of the accompanying drawings: display device-100, display panel-10, power module-20, support frame-30, display area-10a, non-display area-10b, array substrate-10c, opposite substrate-10d, display medium layer-10e, m data lines-S1~Sm, n scanning lines-G1~Gn, first direction-F1, second direction-F2, timing control circuit-11, data driving circuit-12, scanning driving circuit-13, backlight module-14, pixel unit-15, first parasitic capacitor-Cp1, second parasitic capacitor-Cp2 Generated capacitor-Cp2, storage capacitor-Cs, liquid crystal capacitor-Clc, first pixel unit-15A, second pixel unit-15B, data line-S, scan line-G, driving module-151, compensation module-152, first switch tube-T1, second switch tube-T2, third switch tube-T3, fourth switch tube-T4, compensation control terminal-K, first capacitor-C1, second capacitor-C2, compensation capacitor-C, power supply voltage terminal-VDD, common electrode-Vcom, first time period-t1, second time period-t2, third time period-t3. DETAILED DESCRIPTION

[0027] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0028] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be used to implement. The serial numbers for the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in the present application, unless otherwise specified, include direct and indirect connections (couplings). The directional terms mentioned in the present application, such as "upper", "lower", "front", "back", "left", "right", "inside", "outside", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0029] In the description of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be internal communication between two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances. It should be noted that the terms "first", "second", etc. in the specification, claims, and drawings of the present application are used to distinguish different objects, rather than to describe a specific order.

[0030] In addition, the terms "include", "may include", "contain", or "may include" used in the present application indicate the existence of the corresponding functions, operations, elements, etc. disclosed, and do not limit one or more other functions, operations, elements, etc. In addition, the terms "include" or "contain" indicate the existence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, and do not exclude the existence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusions. In addition, when describing the embodiments of the present application, "may" is used to indicate "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0032] See also Figure 1 , Figure 1The present invention is a schematic diagram of the structure of a display device 100 provided in the first embodiment of the present invention. The display device 100 includes a display panel 10, a power module 20 and a support frame 30. The display panel 10 and the power module 20 are fixed to the support frame 30. The power module 20 is arranged on the back of the display panel 10, that is, the non-display surface of the display panel 10. The power module 20 is used to provide a power supply voltage for the display panel 10 to display an image, and the support frame 30 provides a fixing and protection function for the display panel 10 and the power module 20.

[0033] See also Figure 2 , Figure 2 for Figure 1 Schematic diagram of the side structure of the display device 100.

[0034] like Figure 2 As shown, the display panel 10 includes an image display area 10a and a non-display area 10b. The display area 10a is used to perform image display, and the non-display area 10b is arranged around the display area 10a to set other auxiliary components or modules. Specifically, the display panel 10 includes an array substrate 10c and an opposite substrate 10d, and a display medium layer 10e sandwiched between the array substrate 10c and the opposite substrate 10d. In this embodiment, the display medium in the display medium layer 10e can be liquid crystal molecules, or can be LED, OLED, Micro-LED, etc.

[0035] Taking the liquid crystal display panel as an example, that is, the display medium layer 10e contains liquid crystal molecules, the display panel 10 also includes a backlight module 14, and the backlight module 14 is arranged on the side of the array substrate 10c away from the display medium layer 10e. The backlight module 14 is used to emit light to the array substrate 10c, and an electric field is formed between the array substrate 10c and the opposite substrate 10d to drive the liquid crystal molecules in the display medium layer 10e to deflect, so as to transmit the light emitted by the backlight module 14 to the side of the opposite substrate 10d to perform image display.

[0036] See also Figure 3 , Figure 3 for Figure 2 FIG. 1 is a schematic diagram of the planar layout of the array substrate 10c in the display panel 10. Figure 3 As shown, the array substrate 10c corresponding to the image display area 10a includes a plurality of pixel units 15 arranged in a matrix, m data lines S1-Sm, and n scanning lines G1-Gn, where m and n are natural numbers greater than 1.

[0037] The n scan lines G1-Gn extend along the first direction F1 and are insulated from each other and arranged in parallel along the second direction F2. The m data lines S1-Sm extend along the second direction F2 and are insulated from each other and arranged in parallel along the first direction F1. The first direction F1 is perpendicular to the second direction F2.

[0038] Corresponding to the non-display area 10b of the display panel 10 ( Figure 2 ), the display device 100 further includes a timing control circuit 11 for driving the pixel unit to display an image, a data driving circuit 12, and a scanning driving circuit 13 arranged on the array substrate 10c.

[0039] The timing control circuit 11 is electrically connected to the data driving circuit 12 and the scan driving circuit 13, and is used to control the working timing of the data driving circuit 12 and the scan driving circuit 13, that is, to output corresponding timing control signals to the data driving circuit 12 and the scan driving circuit 13, so as to control when to output corresponding scan signals and data signals. The timing control circuit 11 is connected to the scan driving circuit 13 through a plurality of clock lines CL, and is used to output clock signals to the scan driving circuit 13.

[0040] The data driving circuit 12 is electrically connected to the m data lines S1 -Sm, and is used to transmit data signals (Data) to be displayed to the plurality of pixel units 15 in the form of data voltages through the m data lines S1 -Sm.

[0041] The scan driving circuit 13 is electrically connected to the n scan lines G1-Gn, and is used to output scan signals through the n scan lines G1-Gn according to the received clock signal to control when the pixel unit 15 receives the data signal. The scan driving circuit 13 outputs scan signals from the n scan lines G1-Gn in sequence according to the scan period.

[0042] In this embodiment, the circuit elements in the scan driving circuit 13 and the pixel units 15 in the array substrate 10 c are manufactured in the array substrate 10 c in the same process, which is also the GOA (Gate Driver on Array) technology.

[0043] See also Figure 4 , Figure 4 for Figure 3 Schematic diagram of the parasitic capacitance circuit of pixel unit 15.

[0044] like Figure 4 As shown, there is a parasitic capacitor between the data line and the liquid crystal capacitor. Due to the existence of the parasitic capacitor, the liquid crystal capacitor is affected when the data line transmits a data signal, thereby affecting the deflection of the liquid crystal molecules, resulting in inaccurate brightness of the emitted light, and further causing crosstalk.

[0045] For example, a pixel unit 15 is arranged between the first data line S1 and the second data line S2, and the pixel unit 15 includes a first switch tube T1, a liquid crystal capacitor Clc and a storage capacitor Cst. The gate of the first switch tube T1 is connected to the first scan line G1, the source is connected to the first data line S1, and the drain is connected to the liquid crystal capacitor Clc and the storage capacitor Cst. The first switch tube T1 is used to be turned on under the control of the scan signal to transmit the data signal in the first data line S1 to the liquid crystal capacitor Clc and the storage capacitor Cst. The first ends of the liquid crystal capacitor Clc and the storage capacitor Cst are connected to the drain of the first switch tube T1, and the second ends of the liquid crystal capacitor Clc and the storage capacitor Cst are connected to the common electrode Vcom.

[0046] There is a first parasitic capacitor Cp1 between the liquid crystal capacitor Clc, the storage capacitor Cst and the first data line S1, and there is a second parasitic capacitor Cp2 between the liquid crystal capacitor Clc, the storage capacitor Cst and the second data line S2. Due to the existence of the first parasitic capacitor Cp1 and the second parasitic capacitor Cp2, the liquid crystal capacitor Clc and the storage capacitor Cst will be affected by the first parasitic capacitor Cp1 and the second parasitic capacitor Cp2 when driving the liquid crystal molecules to deflect, resulting in differences in display brightness.

[0047] In addition to the first parasitic capacitor Cp1 and the second parasitic capacitor Cp2, there are also parasitic capacitors between the scan line and the liquid crystal capacitor Clc and between the scan line and the data line, which will also have a certain impact on the liquid crystal molecules.

[0048] See also Figure 5 , Figure 5 for Figure 3 Schematic diagram of pixel voltage change of pixel unit.

[0049] like Figure 5 As shown, the first pixel unit 15A and the second pixel unit 15B are connected to the first data line S1 and are arranged adjacently. The first pixel unit 15A and the second pixel unit 15B have opposite polarities, that is, when the first pixel unit 15A is positive, the second pixel unit 15B is negative, and when the first pixel unit 15A is negative, the second pixel unit 15B is positive. When the first data line S1 charges the first pixel unit 15A, the first pixel unit 15A, due to the influence of the parasitic capacitance, reduces the voltage difference across the second capacitor C2, resulting in the brightness of the first pixel unit 15A being lower than the preset brightness. At the same time, since the second pixel unit 15B is negative, under the influence of the parasitic capacitance, the second pixel unit 15B is brighter than the preset brightness, resulting in crosstalk and uneven display.

[0050] See also Figure 6 , Figure 6 A second embodiment of the present application provides a Figure 3Schematic diagram of the circuit structure of the pixel unit.

[0051] like Figure 6 As shown, the pixel unit 15 includes a driving module 151 and a compensation module 152. In the period when the Mth row of pixel units is scanned in the Nth frame image display period, the driving module 151 is used to receive a data signal from the data line and drive the liquid crystal molecules to deflect according to the data signal in cooperation with the common electrode to emit light to perform image display. The compensation module 152 is connected to the driving module 151, and is used to receive the data signal from the driving module 151 and charge, and output a compensation voltage to the driving module 151 within a preset period of time to perform voltage compensation on the driving module, so as to offset the influence of the parasitic capacitance on the deflection angle of the liquid crystal molecules. Wherein, N is an integer greater than or equal to 1.

[0052] The preset time period may be after the scanning of the Mth row of pixel units in the Nth frame image is completed and before the scanning of the Mth row of pixel units in the N+1th frame image display.

[0053] For example, when M=1, that is, the first row of pixel units receives data signals for image display, the compensation module 152 in the first row of pixel units receives data signals for charging, and when the first row of pixel units stops receiving data signals, that is, when the second row of pixel units to the nth row of pixel units receive data signals, the compensation module 152 outputs a compensation voltage to the driving module 151 for voltage compensation of the driving module 151, and before the first row of pixel units in the N+1th frame of image display receives data signals, the compensation module 152 stops outputting the compensation voltage to the driving module 151.

[0054] The preset time period may also be after the scanning of the M+Kth row of pixel units in the Nth frame image display is completed and before the scanning of the Mth row of pixel units in the N+1th frame image display.

[0055] For example, when M=1 and K=100, that is, when the first row of pixel units in the Nth frame image receives data signals for image display, the compensation module 152 in the first row of pixel units receives data signals for charging, and the compensation module 152 in the first row of pixel units does not output compensation voltage to the driving module 151 from the time when the first row of pixel units stops receiving data signals to the time when the 101st row of pixel units receives data signals, and the compensation module 152 in the first row of pixel units starts to output compensation voltage to the driving module 151 from the time when the 101st row of pixel units starts receiving data signals to the time when the first row of pixel units in the N+1th frame image receives data signals, for voltage compensation of the driving module 151. K can be set according to specific needs, for example, it can be set to 200, 300, 500, etc., and the present application does not limit this.

[0056] Since the voltage of the driving module 151 will not drop significantly within a period of time after receiving the data signal, the current brightness can be maintained without the compensation module 152 compensating the driving module 151. After the driving module 151 is maintained for a period of time, the driving module 151 may be affected by parasitic capacitance or leakage, resulting in a voltage drop. At this time, the compensation module 152 compensates the driving module 151, thereby controlling the driving module 151 to continue to maintain the current voltage to control the pixel unit for image display. The preset time period can also be set after the last row of pixel units in the Nth frame image display is scanned, that is, after the Nth frame image display is completed to before the Mth row of pixel units in the N+1th frame image are scanned, that is, during the Nth frame image display period, the compensation module 152 only charges and does not output the compensation voltage to the driving module 151. During the waiting period after the Nth frame image display is completed to before the Mth row of pixel units in the N+1th frame image are scanned, the compensation module 152 outputs the compensation voltage to compensate the driving module 151.

[0057] Since the data line does not transmit data signals during the waiting period between the Nth frame and the N+1th frame image, the parasitic capacitance has a greater impact on the liquid crystal molecules, causing the deflection of the liquid crystal molecules to change, resulting in the pixel unit being unable to maintain the current brightness, thereby causing the brightness displayed by the pixel unit to be inaccurate. Therefore, it is necessary to control the compensation module 152 to compensate the driving module 151 during the waiting period to enhance the driving strength of the driving module 151 on the liquid crystal molecules.

[0058] The driving module 151 includes a first switch tube T1, a first capacitor C1 and a liquid crystal capacitor Cls, wherein the gate of the first switch tube T1 is connected to the first scan line G1, the source of the first switch tube T1 is connected to the data line S, and the drain of the first switch tube T1 is connected to the first capacitor C1 and the second capacitor C2. The first switch tube T1 is used to be turned on under the control of the scan signal output by the scan line G, so as to transmit the data signal in the data line S to the first capacitor C1 and the second capacitor C2 through the first switch tube T1, and to charge the first capacitor C1 and the second capacitor C2. The first end of the first capacitor C1 is connected to the drain of the first switch tube T1, the second end of the first capacitor C1 is connected to the common electrode Vcom, the first end of the second capacitor C2 is connected to the drain of the first switch tube T1, and the second end of the second capacitor C2 is connected to the common electrode Vcom. The first capacitor C1 can be a storage capacitor, and the second capacitor C2 can be a liquid crystal capacitor.

[0059] The compensation module 152 includes a third switch tube T3, a fourth switch tube T4 and a compensation capacitor C. The gate of the third switch tube T3 is connected to the scan line G, the first conductive end of the third switch tube T3 is connected to the drain of the first switch tube T1, and the second conductive end of the third switch tube T3 is connected to the compensation capacitor C. It is used to be turned on under the control of the scan signal to receive the data signal from the data line S to charge the compensation capacitor C.

[0060] The gate of the fourth switch tube T4 is connected to the compensation control terminal K, the first conductive terminal of the fourth switch tube T4 is connected to the compensation capacitor C, and the second conductive terminal of the fourth switch tube T4 is connected to the first capacitor C1 and the second capacitor C2, and is used to be turned on under the control of the compensation control terminal K to control the compensation capacitor C to charge the first capacitor C1 and the second capacitor C2. The compensation control terminal K can be a timing control circuit 11, and the timing control circuit 11 controls the fourth switch tube T4 in the corresponding row pixel unit to be turned on during a preset period according to the output timing of the scan signal.

[0061] Among them, the first conductive end of the third switch tube T3 and the fourth switch tube T4 can be a source, and the second conductive end can be a drain. Of course, the first conductive end can also be a drain and the second conductive end can be a source as needed, and this application does not limit this.

[0062] One end of the compensation capacitor C is connected to the second conductive end of the third switch tube T3 and the first conductive end of the fourth switch tube T4, and the other end is connected to the power supply voltage terminal VDD. The compensation voltage output by the compensation capacitor C can be adjusted by adjusting the value of VDD. The voltage output by the power supply voltage terminal VDD is greater than the common voltage, that is, the voltage of the common electrode Vcom. When the fourth switch tube T4 is turned on, the power supply voltage terminal VDD can effectively drive the compensation capacitor C to perform voltage compensation for the first capacitor C1 and the second capacitor C2.

[0063] When the scanning line G outputs the scanning signal, the first switch tube T1 and the third switch tube T3 are turned on at the same time, the first capacitor C1 and the second capacitor receive the data signal from the data line to drive the liquid crystal molecules to perform image display, and the compensation capacitor C receives the data signal from the data line S to charge. In a preset period, the compensation control terminal K controls the fourth switch tube T4 to be turned on, so as to control the compensation capacitor C to output the compensation voltage to the first capacitor C1 and the second capacitor C2, which is used to compensate the first capacitor C1 and the second capacitor C2 for insufficient charging of the first capacitor C1 and the second capacitor C2 and the influence of the parasitic capacitance on the deflection direction of the liquid crystal molecules, so that the deflection angle of the liquid crystal molecules is within a preset range, thereby eliminating crosstalk and display unevenness.

[0064] See also Figure 7 , Figure 7 A third embodiment of the present application provides a Figure 3 Schematic diagram of the circuit block diagram of the pixel unit.

[0065] like Figure 7 As shown, the pixel unit 15 includes a driving module 151 and a compensation module 152. In the period when the Mth row of pixel units is scanned in the Nth frame image display period, the driving module 151 is used to receive a data signal from the data line and drive the liquid crystal molecules to deflect according to the data signal in cooperation with the common electrode to emit light to perform image display. The compensation module 152 is connected to the driving module 151, and is used to receive the data signal from the driving module 151 and charge, and output a compensation voltage to the driving module 151 within a preset period of time to perform voltage compensation on the driving module, so as to offset the influence of the parasitic capacitance on the deflection angle of the liquid crystal molecules. Wherein, N is an integer greater than or equal to 1.

[0066] The preset time period may be after the Mth row of pixel units in the Nth frame image is scanned and before the Mth row of pixel units in the N+1th frame image is scanned.

[0067] For example, when M=1, that is, the first row of pixel units receives data signals for image display, the compensation module 152 in the first row of pixel units receives data signals for charging, and when the first row of pixel units stops receiving data signals, that is, when the second row of pixel units to the nth row of pixel units receive data signals, the compensation module 152 outputs a compensation voltage to the driving module 151 for voltage compensation of the driving module 151, and before the first row of pixel units in the N+1th frame of image display receives data signals, the compensation module 152 stops outputting the compensation voltage to the driving module 151.

[0068] The preset time period may also be after the scanning of the M+Kth row of pixel units in the Nth frame image is completed and before the scanning of the Mth row of pixel units in the N+1th frame image is performed, wherein M and N are integers greater than or equal to 1.

[0069] For example, when M=1 and K=100, that is, when the first row of pixel units in the Nth frame image receives data signals for image display, the compensation module 152 in the first row of pixel units receives data signals for charging, and the compensation module 152 in the first row of pixel units does not output compensation voltage to the driving module 151 from the time when the first row of pixel units stops receiving data signals to the time when the 101st row of pixel units receives data signals, and the compensation module 152 in the first row of pixel units starts to output compensation voltage to the driving module 151 from the time when the 101st row of pixel units starts receiving data signals to the time when the first row of pixel units in the N+1th frame image receives data signals, for voltage compensation of the driving module 151. K can be set according to specific needs, for example, it can be set to 200, 300, 500, etc., and the present application does not limit this.

[0070] Since the voltage of the driving module 151 will not drop significantly within a period of time after receiving the data signal, the compensation module 152 does not need to compensate the driving module 151 to maintain the current brightness. After the driving module 151 is maintained for a period of time, the driving module 151 may be affected by parasitic capacitance or leakage, resulting in a voltage drop. At this time, the compensation module 152 compensates the driving module 151, thereby controlling the driving module 151 to continue to maintain the current voltage to control the pixel unit for image display.

[0071] The preset period can also be set after the last row of pixel units is scanned, that is, after the Nth frame image is displayed, before the Mth row of pixel units in the N+1th frame image is scanned, that is, during the Nth frame image display period, the compensation module 152 only charges and does not output the compensation voltage to the driving module 151, and during the waiting period after the Nth frame image is displayed, before the Mth row of pixel units in the N+1th frame image is scanned, the compensation module 152 outputs the compensation voltage to compensate the driving module 151. The waiting period is the period before a frame of image is displayed, and during the waiting period, the data line suspends the transmission of data signals.

[0072] Since the data line does not transmit data signals during the waiting period between the Nth frame and the N+1th frame image, the parasitic capacitance has a greater impact on the liquid crystal molecules, causing the deflection of the liquid crystal molecules to change, thereby causing inaccurate brightness displayed by the pixel unit. Therefore, it is necessary to control the compensation module 152 to compensate the driving module 151 during the waiting period to enhance the driving strength of the driving module 151 on the liquid crystal molecules.

[0073] The driving module 151 includes a first switch tube T1, a second switch tube T2, a first capacitor C1 and a liquid crystal capacitor Cls, wherein the gate of the first switch tube T1 is connected to the first scan line G1, the source of the first switch tube T1 is connected to the drain of the second switch tube T2, and the drain of the first switch tube T1 is connected to the first capacitor C1 and the second capacitor C2. The first switch tube T1 is used to be turned on under the control of the scan signal output by the first scan line G1, the gate of the second switch tube T2 is connected to the second scan line G2, the source is connected to the data line S, and the drain is connected to the source of the first switch tube T1, and is used to be turned on under the control of the scan signal output by the second scan line G2, so as to transmit the data signal in the data line S to the first capacitor C1 and the second capacitor C2 through the first switch tube T1, so as to charge the first capacitor C1 and the second capacitor C2. The first end of the first capacitor C1 is connected to the drain of the first switch tube T1, the second end of the first capacitor C1 is connected to the common electrode Vcom, the first end of the second capacitor C2 is connected to the drain of the first switch tube T1, and the second end of the second capacitor C2 is connected to the common electrode Vcom. The first capacitor C1 may be a storage capacitor, and the second capacitor C2 may be a liquid crystal capacitor.

[0074] The compensation module 152 includes a third switch tube T3, a fourth switch tube T4 and a compensation capacitor C. The gate of the third switch tube T3 is connected to the first scan line G1, the first conductive end of the third switch tube T3 is connected to the drain of the first switch tube T1, and the second conductive end of the third switch tube T3 is connected to the compensation capacitor C. It is used to be turned on under the control of the scan signal output by the first scan line G1 to receive the data signal from the data line S to charge the compensation capacitor C.

[0075] The gate of the fourth switch tube T4 is connected to the compensation control terminal K, the first conductive end of the fourth switch tube T4 is connected to the compensation capacitor C, and the second conductive end of the fourth switch tube T4 is connected to the first capacitor C1 and the second capacitor C2, and is used to be turned on under the control of the compensation control terminal K to control the compensation capacitor C to charge the first capacitor C1 and the second capacitor C2, so that before the next frame of the image begins, the deflection angle of the liquid crystal molecules is restored to the preset position. Among them, the first conductive end of the third switch tube T3 and the fourth switch tube T4 can be a source electrode, and the second conductive end can be a drain electrode. Of course, the first conductive end can also be a drain electrode and the second conductive end can be a source electrode as needed, and the present application does not limit this.

[0076] One end of the compensation capacitor C is connected to the second conductive end of the third switch tube T3 and the first conductive end of the fourth switch tube T4, and the other end is connected to the power supply voltage terminal VDD. The compensation voltage output by the compensation capacitor C can be adjusted by adjusting the value of VDD. The voltage output by the power supply voltage terminal VDD is greater than the common voltage, that is, the voltage of the common electrode Vcom. When the fourth switch tube T4 is turned on, the power supply voltage terminal VDD can effectively drive the compensation capacitor C to perform voltage compensation for the first capacitor C1 and the second capacitor C2.

[0077] See also Figure 8 , Figure 8 for Figure 7 Mid scan signal output timing diagram.

[0078] like Figure 8 As shown, a frame image display period includes a continuous first period t1, a second period t2 and a third period t3, wherein in the first period t1, the i-th scan line Gi and the i+1-th scan line Gi+1 simultaneously output scan signals to control the first switch tube T1, the second switch tube T2 and the third switch tube T3 to be turned on, and the first capacitor C1, the second capacitor C2 and the compensation capacitor C receive the data signal from the data line S for charging.

[0079] In the second time period t2, the i+1th scan line Gi+1 stops outputting the scan signal, controls the second switch tube T2 to be turned off, and at the same time, the voltage of the scan signal in the i-th scan line Gi gradually decreases to control the first switch tube T1 and the third switch tube T3 to be gradually turned off. The compensation capacitor C is used to maintain the voltage of the first capacitor C1 and the second capacitor C2 when the first switch tube T1 and the third switch tube T3 are gradually turned off, so as to avoid the first scan signal being suddenly turned off, causing the parasitic capacitance to pull the liquid crystal molecules and cause brightness jumps, that is, to reduce the influence of the parasitic capacitance on the deflection direction of the liquid crystal molecules.

[0080] In the third time period t3, i.e., the preset time period, the compensation control terminal K outputs a control signal to control the fourth switch tube T4 to be turned on, and the power supply voltage terminal VDD drives the compensation capacitor C to output a compensation voltage to the first capacitor C1 and the second capacitor C2 through the fourth switch tube T4, so as to compensate the first capacitor C1 and the second capacitor C2.

[0081] For example, when i=1, the first scan line G1 and the second scan line G2 simultaneously output scan signals to control the first switch tube T1, the second switch tube T2 and the third switch tube T3 to be turned on, and the first capacitor C1, the second capacitor C2 and the compensation capacitor C receive the data signal from the data line S for charging.

[0082] In the second time period t2, the second scan line G2 stops outputting the scan signal, controls the second switch tube T2 to be cut off, and at the same time, the scan signal in the i-th scan line Gi gradually decreases in the second time period t2 to control the compensation capacitor C to maintain the voltage of the first capacitor C1 and the second capacitor C2, so as to avoid the first scan signal being instantly reduced and causing the parasitic capacitance to pull the liquid crystal molecules, that is, to reduce the influence of the parasitic capacitance on the deflection direction of the liquid crystal molecules.

[0083] In the third time period t3, the pixel units G2 in the second row to the pixel units Gn in the nth row receive data signals in sequence to display images, and at the same time, the compensation control terminal K outputs a control signal to control the fourth switch tube T4 to be turned on, and the compensation capacitor C outputs a compensation voltage to the first capacitor C1 and the second capacitor C2 via the fourth switch tube T4, so as to compensate the first capacitor C1 and the second capacitor C2.

[0084] In an exemplary embodiment, the third time period t3, i.e., the preset time period, can also be set to other time periods according to specific needs, for example, the preset time period is after the scanning of the M+Kth row of pixel units in the Nth frame image is completed to before the scanning of the Mth row of pixel units in the N+1th frame image. Or the preset time period can also be after the display of the Nth frame image is completed to before the scanning of the Mth row of pixel units in the N+1th frame image, that is, during the display period of the Nth frame image, the compensation module 152 only charges and does not output the compensation voltage to the driving module 151. During the waiting period after the display of the Nth frame image is completed to before the scanning of the Mth row of pixel units in the N+1th frame image, the compensation module 152 outputs the compensation voltage to compensate the driving module 151, thereby eliminating the influence of the parasitic capacitance on the deflection direction of the liquid crystal molecules, so that the deflection angle of the liquid crystal molecules is within the preset range, thereby eliminating crosstalk and display unevenness.

[0085] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A display panel, comprising an array substrate, a display medium layer and an opposite substrate stacked in sequence, wherein the array substrate is used to cooperate with the opposite substrate to drive the display medium in the display medium layer to display an image, characterized in that: The array substrate includes a plurality of pixel units arranged in an array, and the pixel units include a driving module and a compensation module. During a period when the Mth row of pixel units is scanned in an Nth frame image, the driving module is used to receive a data signal for image display and drive the display medium to display the image according to the data signal. The compensation module is connected to the driving module and is used to receive the data signal from the driving module and charge. During a scanning process from the Mth row of pixel units to the M+Kth row of pixel units in the Nth frame image display to the Mth row of pixel units in the N+1th frame image display, the compensation module outputs the compensation voltage to the driving module to control the driving module to maintain a current voltage, wherein N and M are integers greater than 1 or equal to 1, and K is an integer greater than 1.

2. The display panel according to claim 1, wherein: The array substrate further comprises a plurality of scan lines extending along the first direction and arranged in sequence along the second direction and a plurality of data lines extending along the second direction and arranged in sequence along the first direction; The driving module is connected to the scan line and the data line, and is used to receive the data signal from the data line under the control of the scan signal output by the scan line and drive the display medium to perform image display according to the data signal; The compensation module is connected to the scan line and the driving module, and is used for receiving the data signal from the driving module for charging under the control of the scan signal.

3. The display panel according to claim 2, wherein: The driving module includes a first switch tube, a first capacitor and a second capacitor. The gate of the first switch tube is connected to the scan line, the source of the first switch tube is connected to the data line, and the drain of the first switch tube is connected to the first capacitor and the second capacitor, and is used to be turned on under the control of the scan signal to transmit the data signal to the first capacitor and the second capacitor, and charge the first capacitor and the second capacitor.

4. The display panel according to claim 1, wherein: The array substrate further comprises a plurality of scan lines extending along the first direction and arranged in sequence along the second direction and a plurality of data lines extending along the second direction and arranged in sequence along the first direction; The plurality of scan lines include a first scan line and a second scan line that are adjacently arranged, the driving module is connected to the first scan line, the second scan line and the data line, and is used to receive the data signal from the data line under the control of a first scan signal output by the first scan line and a second scan signal output by the second scan line; The compensation module is connected to the first scanning line and the driving module, and is used for receiving the data signal from the driving module for charging under the control of the first scanning signal.

5. The display panel according to claim 4, wherein: The driving module includes a first switch tube, a second switch tube, a first capacitor and a second capacitor, wherein the gate of the first switch tube is connected to the first scan line, the source of the first switch tube is connected to the second switch tube, and the drain of the first switch tube is connected to the first capacitor and the second capacitor, and is configured to be turned on under the control of the first scan signal to receive the data signal from the second switch tube; The gate of the second switch tube is connected to the second scan line, the source of the second switch tube is connected to the data line, and the drain of the second switch tube is connected to the source of the first switch tube, and is used to be turned on under the control of the second scan signal to transmit the data signal to the first switch tube, and transmit it to the first capacitor and the second capacitor through the first switch tube, so as to charge the first capacitor and the second capacitor.

6. The display panel as claimed in claim 5, characterized in that The compensation module includes a third switch tube and a compensation capacitor, the gate of the third switch tube is connected to the first scan line, the first conductive end of the third switch tube is connected to the drain of the first switch tube, and the second conductive end of the third switch tube is connected to the compensation capacitor, and is used to be turned on under the control of the first scan signal to receive the data signal from the first switch tube to charge the compensation capacitor.

7. The display panel according to claim 6, wherein: The compensation module further includes a fourth switch tube, wherein the gate of the fourth switch tube is connected to the compensation control terminal, the first conductive end of the fourth switch tube is connected to the compensation capacitor, and the second conductive end of the fourth switch tube is connected to the first capacitor and the second capacitor; One end of the compensation capacitor is connected to the fourth switch tube, and the other end of the compensation capacitor is connected to the power supply voltage end. The first capacitor and the second capacitor are connected in parallel between the drain of the first switch tube and the common electrode. The voltage output by the power supply voltage end is greater than the voltage of the common electrode. The fourth switch tube is used to be turned on under the control of the compensation control end to control the compensation capacitor to charge the first capacitor and the second capacitor.

8. The display panel according to claim 7, wherein: The pixel unit includes a first period, a second period and a third period when performing a frame image display. In the first period, the first scanning signal and the second scanning signal are output simultaneously to control the first switch tube, the second switch tube and the third switch tube to be turned on. The first capacitor and the second capacitor receive the data signal to be charged and drive the display medium to display an image. At the same time, the compensation capacitor receives the data signal to be charged. In the second period, the second scan signal stops being output, the second switch tube is turned off, and the voltage of the first scan signal gradually decreases to control the first switch tube and the third switch tube to be gradually turned off, and the compensation capacitor is electrically connected to the first capacitor and the second capacitor through the third switch tube, so as to maintain the voltage of the first capacitor and the second capacitor when the first switch tube and the third switch tube are gradually turned off; In the third period, the compensation control terminal controls the fourth switch tube to be turned on, so as to control the compensation capacitor to perform voltage compensation on the first capacitor and the second capacitor.

9. A display device, characterized in that: It comprises a power supply module and a display panel as described in any one of claims 1 to 8, wherein the power supply module is used to provide driving power for the display panel to display images.

Images