Control method of high-gain image sensor

Abstract

The invention provides a control method of a high-gain image sensor, which is characterized in that a column bias current source and a column PMOS (P-channel Metal Oxide Semiconductor) amplifier tube are arranged in a column signal reading unit, the column bias current source is connected with a current output connecting line shared by a column, and a drain electrode of the column PMOS amplifier tube is connected with a current input connecting line shared by the column; the grid electrode of the column PMOS amplifier tube is connected with the common current output connecting line of the column directly or through a capacitor, and an amplified signal of a floating diffusion region of a read-out pixel unit can be obtained on the common current input connecting line of the column, so that the ultrahigh conversion gain is realized, and the dynamic range in a dark light scene is expanded; the size of a device structure in the column signal reading unit can be far larger than that of a transistor in a pixel, the process consistency is better, and the conversion gain can be adjusted more flexibly; the switching between the SHCG mode and the STD mode is realized by driving the switch module in the column signal reading unit, the impact on a power supply and the ground is smaller during operation, and the circuit stability is improved.

Description

Technical Field

[0001] The invention relates to a control method for a high-gain image sensor. Background Art

[0002] Standard image sensors have a limited dynamic range of approximately 60dB to 70dB. However, the dynamic range of real-world brightness is much larger. Natural scenes often span a range of 90dB and above. Image sensors have a single-frame high dynamic range (HDR) feature requirement in certain application scenarios, such as capturing moving objects or pursuing scenes with high frame rate capture readout.

[0003] In current CMOS image sensors, 3T or 4T pixel structures are commonly used ( Figure 1 The traditional 4T pixel is shown as an example), mainly because the amplifier tube M3 in the pixel is a source follower structure (source follower, SF), the pixel output voltage range is large and the reset voltage freedom is high, and its conversion gain is approximately inversely proportional to the FD node (M3 tube gate) capacitance. In order to achieve better noise performance under low illumination, another approach in the industry is to change the amplifier tube in the pixel to work in a common source amplifier structure, that is, the so-called capacitor feedback transimpedance amplifier (CTIA) pixel structure (such as Figure 2 As shown in Figure 1), its conversion gain is approximately inversely proportional to the capacitance between the gate and drain of the M3 tube. Therefore, CTIA pixels can achieve higher conversion gain than traditional 4T pixels. However, the main problem of CTIA pixels is that the operating range is small, a more precise reset voltage is required, the PVT robustness is poor, and the output voltage is easily saturated due to charge injection.

[0004] In order to combine the advantages of the above two structures, patent US10277848B2 proposes a hybrid pixel structure that combines the two structures. By switching the peripheral circuit, the pixel can switch between the SF and CTIA modes, but it requires an additional reference voltage and still cannot solve the problems of the CTIA pixel itself. Patent CN110537366A proposes a differential pixel structure, which can improve the problems of the single-ended CTIA pixel to a certain extent, but the working process and timing of the differential structure are relatively complicated, and the power consumption will also increase significantly, which will be limited in application. Patent CN107770461 proposes a dual-gain output pixel structure, combining the pixel and the amplifier in the column circuit to realize the signal output of the SF and CTIA modes, but this structure requires the addition of capacitors and transistors in the pixel and additional signal output lines, which increases the complexity of the pixel, and the amplifier in the column circuit will also increase the overall power consumption. Summary of the invention

[0005] The object of the present invention is to provide a control method for a high-gain image sensor, which can achieve a higher conversion gain through simple structural improvement and lower power consumption cost based on a traditional pixel structure.

[0006] Based on the above considerations, the present invention provides a control method for a high-gain image sensor, wherein the image sensor comprises a plurality of columns of pixel units arranged in an array, each column of pixel units having a column-common current input connection and a column-common current output connection, the gate of the source follower transistor of each pixel unit in each column is connected to its respective floating diffusion region, the drain of the source follower transistor is connected to the column-common current input connection, and the source of the source follower transistor is connected to the column-common current output connection directly or through its respective row selection transistor; the column-common current input connection and the column-common current output connection are connected to a column signal readout unit; the column signal readout unit comprises a column bias current source and a column PMOS amplifier tube, the column bias current source is connected to the column-common current output connection, the drain of the column PMOS amplifier tube is connected to the column-common current input connection, the gate of the column PMOS amplifier tube is connected to the column-common current output connection directly or through a capacitor, and an amplified signal of the floating diffusion region of the readout row pixel unit can be obtained on the column-common current input connection.

[0007] Preferably, when the gate of the column PMOS amplifier is connected to the current output connection shared by the column through a first capacitor, a second capacitor is arranged between the gate and the drain of the column PMOS amplifier, and by changing the ratio of the first capacitor to the second capacitor, the amplification factor of the floating diffusion area signal of the readout row pixel unit on the current input connection shared by the column by the column signal readout unit is changed.

[0008] Preferably, the column signal readout unit further includes a correlation power supply generating module, through which the first bias voltage is latched and the column second power supply voltage is output to the source of the column PMOS amplifier tube, so that the power supply of the column signal readout unit has correlation when sampling the reference signal and sampling the image signal, thereby eliminating the influence of power supply noise on the correlated double sampling.

[0009] Preferably, the related power supply generating module includes at least one source follower transistor, the drain of the source follower transistor of the related power supply generating module is connected to the first power supply voltage, the source is connected to the column second power supply voltage output terminal, and the gate samples and latches the first bias voltage before sampling the reference signal, thereby generating the column second power supply voltage required by the column signal readout unit that is correlated when sampling the reference signal and sampling the image signal.

[0010] Preferably, the gate of the source follower transistor of the relevant power generation module samples the first bias voltage through a seventh switch and holds it on a third capacitor, and performs sampling and holding on a row-by-row or frame-by-frame basis before sampling the reference signal.

[0011] Preferably, the column signal readout unit further includes a noise compensation module, which senses fluctuations in the first power supply voltage or the column second power supply voltage and generates a negative feedback signal to act on the column second power supply voltage to suppress fluctuations in the column second power supply voltage.

[0012] Preferably, the noise compensation module comprises a current mirror unit, a bias terminal of the current mirror unit is connected to the first power supply voltage output terminal via a fourth capacitor, and a drain of the current mirror unit is connected to the column second power supply voltage output terminal.

[0013] Preferably, the bias end of the current mirror unit also samples the second bias voltage through an eighth switch and holds it on a fifth capacitor, so as to perform row-by-row or frame-by-frame sampling and holding.

[0014] Preferably, the current mirror unit is a cascode current mirror.

[0015] Preferably, the noise compensation module includes an amplifying transistor, a gate of the amplifying transistor is connected to the second power supply voltage output terminal of the column through a sixth capacitor, a drain is connected to a current source, and is connected to the gate of a source follower transistor of the relevant power supply generating circuit through a seventh capacitor, a ninth switch is connected between the gate and the drain of the amplifying transistor, and a DC bias of the amplifying transistor can be achieved by closing the ninth switch row by row or frame by frame.

[0016] Preferably, the column signal readout unit further comprises a clamping module, and before sampling the reference signal and sampling the image signal, the voltage of the drain of the source follower transistor of the pixel unit is clamped to the same level by the clamping module respectively.

[0017] Preferably, the clamping module comprises a clamping transistor, a source of the clamping transistor is connected to the column second power supply voltage, a gate and a drain are connected to each other, and the drain is connected to the drain of the source follower transistor of the pixel unit through a tenth switch.

[0018] Preferably, the size of the clamping transistor is a fixed size or an array-adjustable size.

[0019] Preferably, each of the column signal readout units corresponds to a related power generation module, or a plurality of the column signal readout units correspond to a related power generation module.

[0020] Preferably, each of the column signal readout units corresponds to a noise compensation module, or a plurality of the column signal readout units correspond to a noise compensation module.

[0021] Preferably, each of the column signal readout units corresponds to a clamping module, or a plurality of the column signal readout units correspond to a clamping module.

[0022] Preferably, the control method of the high-gain image sensor includes: sampling the first reference signal output from the source of the source follower transistor of the pixel unit to the column signal readout unit; sampling the second reference signal output from the drain of the source follower transistor of the pixel unit to the column signal readout unit; turning on the transfer transistor of the pixel unit and sampling the image signal output from the pixel unit to the column signal readout unit.

[0023] Preferably, the step of sampling the image signal output by the pixel unit to the column signal readout unit includes: making a judgment based on the voltage signal read from the pixel unit; if the judgment result is a high illumination condition, sampling the first image signal output from the source of the source follower transistor of the pixel unit to the column signal readout unit, and the pixel unit has a first conversion gain; if the judgment result is a low illumination condition, sampling the second image signal output from the drain of the source follower transistor of the pixel unit to the column signal readout unit, and the pixel unit has a second conversion gain; the second conversion gain is higher than the first conversion gain.

[0024] Preferably, the step of judging based on the voltage signal read from the pixel unit includes: comparing the change amplitude of the voltage signal read from the pixel unit before and after opening the transfer transistor with the threshold voltage, if the change amplitude is less than or equal to the threshold voltage, it is a low illumination condition, if the change amplitude is greater than the threshold voltage, it is a high illumination condition.

[0025] Preferably, the falling interval of the ramp voltage of analog-to-digital conversion is used as the threshold voltage.

[0026] Preferably, the step of sampling the image signal output by the pixel unit to the column signal readout unit includes: sampling the second image signal output by the drain of the source follower transistor of the pixel unit to the column signal readout unit, the pixel unit having a second conversion gain; sampling the first image signal output by the source of the source follower transistor of the pixel unit to the column signal readout unit, the pixel unit having a first conversion gain; the second conversion gain is higher than the first conversion gain.

[0027] Preferably, when the source of the source follower transistor of the pixel unit is output to the column signal readout unit, the first conversion gain is adjusted by the dual conversion gain control transistor of the pixel unit.

[0028] Preferably, the step of adjusting the first conversion gain through the dual conversion gain control transistor of the pixel unit includes: turning on the dual conversion gain control transistor to obtain a relatively low first conversion gain, or turning off the dual conversion gain control transistor to obtain a relatively high first conversion gain.

[0029] Preferably, the source or drain of the source follower transistor of the pixel unit is controlled by a switch module to be output to the column signal readout unit.

[0030] Compared with the prior art, the internal structure of the pixel unit of the high-gain image sensor of the present invention is consistent with the traditional 3T or 4T pixel, and has good process compatibility; only by improving the circuit structure and connection method of the column signal readout unit, super high conversion gain (SHCG) can be achieved, and the dynamic range in the dark light scene is expanded without introducing additional reference voltages and power consumption caused by additional amplification circuits; the device structure size in the column signal readout unit can be much larger than the transistor in the pixel, the process consistency is better, and the conversion gain can be adjusted more flexibly; the switching between the SHCG mode and the STD mode (standard mode, i.e., the traditional source follower mode) can be achieved by driving the switch module in the column signal readout unit without driving the signal in the pixel array, and the impact on the power supply and ground during operation is smaller, thereby improving the circuit stability.

[0031] Preferably, the first bias voltage is latched by a related power generation module and the column second power supply voltage is output to the source of the column PMOS amplifier tube, so that the power supply of the column signal readout unit has correlation when sampling the reference signal and sampling the image signal, thereby eliminating the influence of power supply noise on the correlated double sampling and improving the imaging quality; the noise compensation module senses the fluctuation of the first power supply voltage or the column second power supply voltage and generates a negative feedback signal to act on the column second power supply voltage to suppress the fluctuation of the column second power supply voltage and further reduce the power supply noise; before sampling the reference signal and sampling the image signal, the voltage of the drain of the source follower transistor of the pixel unit is clamped to the same level by a clamping module respectively, thereby accelerating the signal stabilization speed, improving the consistency of establishing the reference signal and the image signal, and improving the image quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0033] Figure 1 A circuit diagram of a 4T pixel structure image sensor in the prior art; Figure 2A circuit diagram of a CTIA pixel structure image sensor of the prior art; Figure 3 A system schematic diagram of a high-gain image sensor of the present invention; Figure 4 It is a circuit diagram of a 4T pixel unit in the high-gain image sensor of the present invention; Figure 5 is a circuit diagram of a high-gain image sensor according to Embodiment 1 of the present invention; Figure 6 for Figure 5 Equivalent circuit diagram of high gain image sensor in STD mode; Figure 7 for Figure 5 Signal timing diagram of high gain image sensor in STD mode; Figure 8 for Figure 5 Equivalent circuit diagram of high gain image sensor in SHCG mode; Fig. 9 for Figure 5 Signal timing diagram of high gain image sensor in SHCG mode; Fig.10 for Figure 5 Conversion gain curves of high gain image sensor in two modes; Fig.11 is a circuit diagram of a high-gain image sensor according to Embodiment 2 of the present invention; Fig.12 is a circuit diagram of a high-gain image sensor according to Embodiment 3 of the present invention; Fig.13 for Fig.12 A flow chart of a control method for a high-gain image sensor; Fig.14 for Fig.13 Signal timing diagram of the control method under high illumination conditions; Fig.15 for Fig.13 The signal timing diagram of the control method under low illumination conditions; Fig.16 for Fig.12 Another schematic flow chart of a method for controlling a high-gain image sensor; Fig.17 for Fig.16 Signal timing diagram of the control method; Fig.18 is a circuit diagram of a high-gain image sensor according to a fourth embodiment of the present invention; Fig.19 for Fig.18A circuit diagram of a related power generation module and a noise compensation module in a high-gain image sensor; Fig. 20 for Fig.18 Another circuit schematic diagram of a related power generation module and a noise compensation module in a high-gain image sensor; Fig.21 for Fig. 20 The signal timing diagram of the related power generation module and the noise compensation module; Fig. 22 for Fig.18 A circuit diagram of a clamping module in a high-gain image sensor; Fig.23 for Fig. 22 Signal timing diagram of the high-gain image sensor in SHCG mode.

[0034] In the drawings, the same or similar reference numerals denote the same or similar devices (modules) or steps throughout different drawings. Implementation

[0035] In order to solve the above-mentioned problems in the prior art, the present invention provides a control method for a high-gain image sensor, by setting a column bias current source and a column PMOS amplifier tube in a column signal readout unit, the column bias current source is connected to the column common current output connection, the drain of the column PMOS amplifier tube is connected to the column common current input connection, and the gate of the column PMOS amplifier tube is directly or through a capacitor connected to the column common current output connection, so that an amplified signal of the floating diffusion area of ​​the readout row pixel unit can be obtained on the column common current input connection.

[0036] In the following specific description of the preferred embodiments, reference will be made to the attached drawings which constitute a part of the present invention. The attached drawings show by way of example specific embodiments that can implement the present invention. The illustrative embodiments are not intended to be exhaustive of all embodiments according to the present invention. It will be appreciated that other embodiments may be utilized, and structural or logical modifications may also be made without departing from the scope of the present invention. Therefore, the following specific description is not restrictive, and the scope of the present invention is limited by the appended claims.

[0037] The following is a detailed description with reference to specific embodiments.

[0038] like Figure 3 , Figure 4 , Figure 5As shown, the high gain image sensor according to the first embodiment of the present invention comprises a plurality of columns of pixel units 101 arranged in an array and a plurality of column signal readout units 201, each column signal readout unit 201 corresponds to one or more columns of pixel units 101 in the pixel array 100, and is used to read the output voltage signal ( Figure 5 A pixel unit P in the Mth column of pixel units is shown. <n>and its corresponding column signal readout unit M as an example).

[0039] Specifically, each pixel unit 101 includes a photodiode PD and a plurality of pixel transistors, namely, a transfer transistor M1, a reset transistor M2, a source follower transistor M3, and a row selection transistor M4. The photodiode PD is used to perform photoelectric conversion on incident light to obtain corresponding charges, the transfer transistor M1 is used to transfer the charges accumulated in the photodiode PD to the floating diffusion area FD, the reset transistor M2 is used to reset the potential of the floating diffusion area FD, the source follower transistor M3 is used to convert the charges of the floating diffusion area FD into corresponding voltage signals, and the row selection transistor M4 is used to output the voltage signals to the corresponding column signal readout unit 201.

[0040] Each column of pixel units 101 has a column-common current input connection 112 and a column-common current output connection 111. The gate of the source follower transistor M3 of each pixel unit 101 in each column is connected to the respective floating diffusion region FD, the drain of the source follower transistor M3 is connected to the column-common current input connection 112, and the source of the source follower transistor M3 is connected to the column-common current output connection 111 through the respective row selection transistor M4. It should be noted that in Figure 4 , Figure 5 In the 4T pixel structure shown, the row selection transistor M4 is connected between the source of the source follower transistor M3 and the current output connection 111 shared by the column. In other 4T pixel structures not shown, the row selection transistor M4 can also be connected between the drain of the source follower transistor M3 and the current input connection 112 shared by the column. In the 3T pixel structure, the row selection transistor M4 can also be omitted, so the source of the source follower transistor M3 is directly connected to the current output connection 111 shared by the column.

[0041] The column-common current input connection 112 and the column-common current output connection 111 are connected to the corresponding column signal readout unit 201, and the column signal readout unit 201 includes a column bias current source CS and a column PMOS amplifier tube M5. Here, one column PMOS amplifier tube M5 is shown as an example. It can be understood by those skilled in the art that in other embodiments not shown, there can be multiple column PMOS amplifier tubes M5. The column bias current source CS is connected to the column-common current output connection 111, the drain of the column PMOS amplifier tube M5 is connected to the column-common current input connection 112, and the gate of the column PMOS amplifier tube M5 is connected to the column-common current output connection 111. The amplified signal of the floating diffusion area of ​​the readout row pixel unit can be obtained on the column-common current input connection 112. In addition, the source of the column PMOS transistor M5 is connected to the first power supply voltage VDD1, which is used to provide a power supply voltage for the column PMOS transistor M5. The column PMOS amplifier tube M5 is used to amplify the signal of the floating diffusion area of ​​the read row pixel unit, which has the advantages of simple structure, low noise, large voltage margin, etc.

[0042] Preferably, when the gate of the column PMOS amplifier tube M5 is connected to the column common current output connection 111 through the first capacitor C1, a second capacitor C2 is arranged between the gate and the drain of the column PMOS amplifier tube M5. Specifically, the column common current output connection 111 is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is connected to the first end of the second capacitor C2 and the gate of the column PMOS amplifier tube M5, and the second end of the second capacitor C2 and the drain of the column PMOS amplifier tube M5 are connected to the column common current input connection 112. The second capacitor C2 can be a parasitic capacitor of the column PMOS amplifier tube M5, or it can be an independent capacitor device like the first capacitor C1. The first capacitor C1 and the second capacitor C2 can be fixed capacitors or variable capacitor arrays, so that by changing the ratio of the first capacitor C1 to the second capacitor C2, the amplification factor of the floating diffusion area signal of the row pixel unit read out by the column signal readout unit 201 on the column common current input connection 112 is changed, so as to flexibly adjust the conversion gain of the pixel unit. Preferably, the column signal readout unit 201 further includes a first switch S4 connected in parallel with the second capacitor C2, for performing a self-clearing operation on the column PMOS amplifier tube M5.

[0043] Based on the above structure, the column signal readout unit 201 can read the voltage signal V from the drain of the source follower transistor M3. HG The first capacitor C1, the second capacitor C2, the transconductance Gm of the column PMOS amplifier tube M5 and the load provide the floating diffusion area FD to the output node V HG The gain is increased to obtain a higher conversion gain than the standard mode (STD mode, i.e. the traditional source follower mode), so it can be called the Super High Conversion Gain (SHCG mode). Since the first capacitor C1, the second capacitor C2, and the column PMOS amplifier tube M5 are all located in the peripheral circuit, their size can be much larger than the transistor M3 in the pixel. Compared with the traditional CTIA pixel structure, the process consistency is better and the conversion gain can be adjusted more flexibly.

[0044] Further preferably, the source or drain of the source follower transistor M3 of the pixel unit 101 can be controlled by the switch module to output to the column signal reading unit 201, so as to realize the switching between the SHCG mode and the STD mode. Specifically, the column signal reading unit 201 further includes a first switch S1, a second switch S2, and a third switch S3, the column common current output connection 111 is connected to the first end of the first capacitor C1 through the first switch S1, the second end of the second capacitor C2 and the drain of the column PMOS amplifier tube M5 are connected to the column common current input connection 112 through the second switch S2, and the column common current input connection 112 is connected to the first power supply voltage VDD1 through the third switch S3.

[0045] Therefore, when the third switch S3 is closed, the first switch S1 and the second switch S2 are opened, the equivalent circuit of the image sensor working in the STD mode is as follows: Figure 6 As shown, the signal timing is as follows Figure 7 As shown, in this mode, the post-stage readout circuit 207 reads the first voltage signal V from the source of the source follower transistor M3. SF , which is equivalent to the traditional source follower mode, and the first conversion gain CG1 is relatively low at this time: .

[0046] When the third switch S3 is disconnected, the first switch S1 and the second switch S2 are closed, the equivalent circuit of the image sensor working in the SHCG mode is as follows: Figure 8 As shown, the signal timing is as follows Fig. 9 As shown, in this mode, the post-stage readout circuit 207 reads the second voltage signal V from the drain of the source follower transistor M3. HG , the second conversion gain CG2 at this time is relatively high: .

[0047] The conversion gain curves in the two modes are shown in Fig.10 .

[0048] like Fig.11 As shown, in another preferred embodiment of the image sensor of the present invention, the first capacitor C1, the second capacitor C2, and the fourth switch S4 may also be omitted, that is, the gate of the column PMOS amplifier tube M5 is directly connected to the column common current output connection 111. It should be noted that when such a structure omitting the capacitor is adopted, the connection mode of connecting the drain of the reset transistor M2 in the pixel unit 101 to the drain of the source follower transistor M3 (different from the drain of the reset transistor M2 connected to the third power supply voltage VDD3 in the first embodiment) should be matched accordingly, so as to realize self-clearing through the pixel unit.

[0049] Further preferably, the column signal readout unit 201 further includes a fifth switch S5 and a sixth switch S6, the column common current output connection 111 is connected to the gate of the column PMOS amplifier tube M5 through the fifth switch S5, and the gate of the column PMOS amplifier tube M5 is also connected to the ground voltage through the sixth switch S6.

[0050] Therefore, when the sixth switch S6 is closed and the fifth switch S5 is opened, the column PMOS amplifier tube M5 is turned on as a switch, the image sensor works in the STD mode, and the post-stage readout circuit 207 reads the first voltage signal V from the source of the source follower transistor M3. SF , which is equivalent to the traditional source follower mode, and the first conversion gain CG1 is relatively low at this time.

[0051] When the sixth switch S6 is opened and the fifth switch S5 is closed, the column PMOS amplifier tube M5 is used as an amplifier unit, the image sensor works in the SHCG mode, and the post-stage readout circuit 207 reads the second voltage signal V from the drain of the source follower transistor M3. HG At this time, the second conversion gain CG2 is higher.

[0052] In addition, existing variable conversion gain image sensors often use a dual conversion gain (DCG) design. This design introduces an external capacitor and adds a control switch, such as a metal oxide semiconductor field effect transistor (MOSFET). When a higher signal strength needs to be read, the switch is turned on to connect the FD to the capacitor to help extract the charge. At this time, the conversion gain is low (LCG mode); when a lower signal strength needs to be read, the switch is turned off to obtain a higher conversion gain (HCG mode) and improve the readout signal-to-noise ratio. This solution performs well in existing pixel designs and can effectively expand the dynamic range without changing the PD design.

[0053] The readout operation of the existing row-controlled dual conversion gain (row-DCG) image sensor includes four stages: sampling LCG reference signal, sampling HCG reference signal, sampling HCG image signal, sampling LCG image signal (i.e., LCG ref, HCG ref, HCGsig, LCG sig). The image signals output by the pixel unit under the two conversion gains need to be quantized and stored respectively, which is not conducive to high-speed operation. When the existing column-controlled dual conversion gain (col-DCG) image sensor performs a readout operation, each column readout circuit adjusts the conversion gain of the pixel unit according to the bit line voltage. However, since the control signal of each column of pixel units is shared, the column control circuit is overloaded, and there is a problem of excessive impact on the power supply when the control signal is flipped.

[0054] The high-gain image sensor of the present invention can be multiplexed with the traditional DCG scheme. For example, in extremely dark scenes, the drain output of the source follower transistor M3 is used (SHCG mode, the second conversion gain CG2), and in darker or brighter scenes, the source output of the source follower transistor M3 is used (STD mode, the first conversion gain CG1). In the STD mode, the row control circuit further adjusts the first conversion gain CG1 by turning on or off the DCG transistor according to the application scenario. Specifically, by turning on the DCG transistor to obtain a relatively low first conversion gain (Low-CG1), or turning off the DCG transistor to obtain a relatively high first conversion gain (High-CG1), a relatively high HCG or a relatively low LCG readout mode is selected to further expand the dynamic range.

[0055] Below Fig.12 Based on the circuit structure of the present invention, this paper describes in detail how to use the control method of the high-gain image sensor of the present invention to achieve a high dynamic range by adjusting the conversion gain of the pixel unit, while reducing the impact of the switching operation, improving the circuit stability, and improving the reading efficiency.

[0056] Among them, the floating diffusion area FD is connected to a DCG control transistor M0. The equivalent capacitance of the FD point of the DCG control transistor M0 is different when it is turned on and off. When M0 is turned on, the FD capacitance increases, and more electrons can be collected from the PD tube to expand the dynamic range. The connection methods of other transistors are all existing technologies, and the details are not repeated here. The third switch S3 is controlled by the signal SHCG_ENB, and the first switch S1 and the second switch S2 are controlled by the signal SHCG_EN. The high level represents that the switch is closed, and the low level represents that the switch is open; the signals SHCG_EN and SHCG_ENB are reverse digital control signals, which are automatically output by the post-stage readout circuit 207 according to the input signal size.

[0057] like Fig.13 As shown, a process of a conversion gain control method of a high-gain image sensor of the present invention includes: Step S11: sampling a first reference signal outputted from the source of the source follower transistor of the pixel unit to the column signal reading unit; Step S12: sampling a second reference signal outputted from the drain of the source follower transistor of the pixel unit to the column signal reading unit; Step S13: turning on the transfer transistor of the pixel unit; Step S14: determining the light intensity of the pixel unit according to the voltage signal read from the pixel unit; Step S15: based on the judgment result, sampling the image signal output by the pixel unit to the column signal reading unit (step S151: under high illumination conditions, the source of the source follower transistor of the sampling pixel unit is output to the first image signal of the column signal reading unit; or step S152: under low illumination conditions, the drain of the source follower transistor of the sampling pixel unit is output to the second image signal of the column signal reading unit).

[0058] Specifically, Fig.14 yes Fig.13 The timing diagram of the embodiment shown in the figure under high illumination conditions includes four stages: (1) STD_ref stage The SHCG_EN signal is at a low level, the third switch S3 is closed, the first switch S1 and the second switch S2 are opened, and the column PMOS amplifier tube M5 is not connected to the pixel circuit. HG The voltage is connected to the first power supply voltage VDD1 through the third switch S3, and the column signal reading unit 201 is in the STD mode. In this mode, the output node of the pixel unit 101 is the source of the source follower transistor M3, and the voltage V SF It is a valid signal input to the post-stage readout circuit 207. In the pixel unit 101, SEL becomes high to select this row, DCG and RST signals are high at the same time, and the FD point in the pixel unit 101 is reset. Then the RST signal becomes low, and DCG has two states, maintaining high or becoming low, which respectively represent that the STD mode can support the LCG mode or the HCG mode, and the dynamic range can be selected more flexibly; the post-stage readout circuit 207 quantizes V SF The voltage readout STD_ref resets the information, ie, completes the step of sampling the first reference signal STD_ref outputted from the source of the source follower transistor M3 of the pixel unit 101 to the column signal reading unit 201 .

[0059] (2) SHCG_ref stage The SHCG_EN signal becomes high level, the third switch S3 is disconnected, the first switch S1 and the second switch S2 are closed, and the column PMOS amplifier tube M5 is connected to the pixel circuit to form a closed loop, and V SF The voltage is disconnected from the post-stage readout circuit 207, and the column signal reading unit 201 is in the SHCG mode. In this mode, the output node of the pixel unit 101 is the drain of the source follower transistor M3, and the voltage V HG is the effective signal input to the subsequent readout circuit 207; since the column PMOS amplifier tube M5 has a negative gain -AV, the Miller effect causes most of the electrons flowing out of the PD tube in the pixel unit 101 to flow to the capacitor C GD Thus, a higher conversion gain is obtained compared with the STD mode; the subsequent readout circuit 207 quantizes V HG The voltage reads out the SHCG_ref reset information, ie, completes the step of sampling the second reference signal SHCG_ref outputted from the drain of the source follower transistor M3 of the pixel unit 101 to the column signal reading unit 201 .

[0060] (3) Flag judgment stage The circuit is still in SHCG mode, the TX signal in the pixel unit 101 becomes high level, the electrons in the PD tube flow out through the open transfer transistor M1, and V HG The signal generates a voltage corresponding to the number of electrons.

[0061] Next, a judgment is made based on the voltage signal read from the pixel unit. A reference threshold voltage V is required to judge the intensity of light. flag , the V flag The voltage can be designed to be adjustable to achieve the best image effect. In this embodiment, the ramp voltage (V ramp ) as the threshold voltage V flag In other embodiments not shown, a new threshold voltage may also be introduced. The voltage signal V read from the pixel unit 101 before and after the transfer transistor M1 is turned on is HG The change range of the threshold voltage V flag For comparison, if V HG The change amplitude is less than or equal to the threshold voltage V flag It is a low illumination condition. If V HG The change amplitude is greater than the threshold voltage V flag This is a high illumination condition.

[0062] Taking the judgment result of high illumination condition as an example, a relatively low conversion gain can be selected, thus entering the STD_sig stage.

[0063] (4) STD_sig stage SHCG_EN signal goes low and the circuit switches to STD mode. HG The signal is connected to VDD1, and the subsequent readout circuit 207 quantizes V SF The signal reads out the image information related to the light intensity, that is, samples the source of the source follower transistor M4 of the pixel unit and outputs the first image signal STD_sig to the column signal reading unit 201. According to the first image signal STD_sig and the first reference signal STD_ref, the pixel unit 101 has a first conversion gain CG1.

[0064] Fig.15 yes Fig.13 The timing diagram of the embodiment shown in the figure under low illumination conditions also includes four stages, wherein the first two stages are Fig.14 The difference lies in the last two stages: (3) Flag judgment stage The circuit is still in SHCG mode, the TX signal in the pixel unit 101 becomes high level, the electrons in the PD tube flow out through the open transfer transistor M1, and V HG The signal generates a voltage corresponding to the number of electrons.

[0065] Next, a judgment is made based on the voltage signal read from the pixel unit. The ramp voltage (V ramp ) as the threshold voltage V flag , the voltage signal V read from the pixel unit 101 before and after the transfer transistor M1 is turned on HG The change range of the threshold voltage V flag For comparison, V HG The change amplitude is less than or equal to the threshold voltage V flag The result is low illumination condition, which requires a higher conversion gain to obtain good image quality, so it enters the SHCG_sig stage.

[0066] (4) SHCG_sig stage The SHCG_EN signal remains high, the circuit is still in SHCG mode, and the subsequent readout circuit 207 quantizes V HG The signal reads out image information related to light intensity, that is, samples the second image signal SHCG_sig output from the drain of the source follower transistor M3 of the pixel unit to the column signal reading unit 201. According to the second image signal SHCG_sig and the second reference signal SHCG_ref, the pixel unit 101 has a second conversion gain CG2, and the second conversion gain CG2 is greater than the first conversion gain CG1.

[0067] like Figure 13-15 As shown, in the above embodiment, the first reference signal STD_ref output from the source of the source follower transistor of the pixel unit to the column signal reading unit and the second reference signal SHCG_ref output from the drain of the source follower transistor to the column signal reading unit are sampled respectively, and then the light intensity of the pixel unit is judged according to the voltage signal read from the pixel unit, and then the appropriate readout architecture is automatically selected to sample the second image signal SHCG_sig output from the drain of the source follower transistor or the first image signal STD_sig output from the source, so as to adaptively adjust the conversion gain of the image sensor to achieve a high dynamic range, especially the SHCG readout mode output by the drain of the source follower transistor can expand the dynamic range in the dark light scene, and when adjusting the conversion gain of the pixel unit, it is not necessary to drive the signal in the pixel array, but only to drive the switch module in the column signal reading unit, and the impact on the power supply and ground during the switching operation is smaller, thereby improving the circuit stability. At the same time, in the reading cycle of each pixel unit, only the reference signal ref and the image signal sig need to be read twice, which is conducive to improving the reading efficiency and generating HDR images at a higher frame rate.

[0068] In addition, the SHCG_EN signal of the high-gain image sensor of the present invention can also be switched to the global control of the column circuit, and then read out in conjunction with the row control signal, which can support the following: Fig.17 The readout timing is to perform the four processes of STD ref, SHCGref, SHCGsig, and STD sig in sequence to generate an HDR image. Fig.15 As shown, another process of the conversion gain control method of the high-gain image sensor of the present invention includes: Step S21: sampling the first reference signal outputted from the source of the source follower transistor of the pixel unit to the column signal reading unit (STD_ref stage); Step S22: sampling the drain of the source follower transistor of the pixel unit to output a second reference signal to the column signal reading unit (SHCG_ref stage); Step S23: turning on the transfer transistor of the pixel unit; Step S24: sampling a second image signal outputted from the drain of the source follower transistor of the pixel unit to the column signal reading unit, wherein the pixel unit has a second conversion gain (SHCG_sig stage); Step S25: sampling the first image signal output from the source of the source follower transistor of the pixel unit to the column signal reading unit, the pixel unit having a first conversion gain, the second conversion gain being higher than the first conversion gain (STD_sig stage).

[0069] The circuit principle and switching process of each stage are similar to those of the above-mentioned embodiment and will not be described in detail here.

[0070] It should be noted that the specific circuits and signal timings of the various embodiments of the present invention are only used as examples. Technical personnel can make other modifications or have other implementation methods based on the common knowledge in the field. For example, the source or drain of the source follower transistor of the pixel unit is controlled to be output to the column signal reading unit through other forms of switching modules. As long as the first reference signal output from the source of the source follower transistor of the pixel unit to the column signal reading unit and the second reference signal output from the drain of the source follower transistor to the column signal reading unit are sampled respectively, and then the image signal output from the pixel unit to the column signal reading unit is sampled as needed, so as to achieve a high dynamic range by adjusting the conversion gain of the pixel unit, it can be used to achieve the purpose of the present invention and should be included in the protection scope of the present invention.

[0071] In addition, since the column PMOS amplifier M5 is introduced in the column signal readout unit, it is more dependent on the low-noise analog power supply. In actual image sensors, most of them adopt the column readout circuit structure and share the analog power supply VDD1. However, in the quantization process, the image signals of each column are inconsistent in size, flip points, dynamic currents, and the time and amplitude of the power supply impact are also different. The fluctuations caused by the power supply impact will in turn affect the quantization of the column signal; in addition, the noise of the power supply input will also be coupled into the readout circuit, affecting the quantization result of the correlated double sampling, resulting in various image anomalies such as horizontal stripes and tailing.

[0072] In addition, because V HG The output impedance is greater than V in STD mode. SF Output impedance, V HG The signal settling time is relatively slow. Too long a settling time will affect the readout frame rate and image quality of the image sensor. Before reading the ref signal, the S4 switch is activated. Due to the channel charge injection effect and the clock feedthrough effect, the gate voltage of the column PMOS amplifier tube M5 will fluctuate, resulting in the V on the column common current input connection 112. HG voltage fluctuations; and before reading the sig signal, the switching action of the transfer transistor M1 in the pixel will also cause the voltage fluctuation of the FD point in the pixel, resulting in V HG Voltage fluctuations.

[0073] In order to further solve the above problems, the inventors of the present application found through research that Fig.18 In another preferred embodiment shown, a correlation power generation module 205 may be added to the column signal readout unit 201, and the first bias voltage Vbias is latched by the correlation power generation module 205 and the column second power voltage VDD2 is output to the column PMOS amplifier tube M5, so that the power supply of the column PMOS amplifier tube M5 has correlation when sampling the reference signal and sampling the image signal, thereby eliminating the influence of power supply noise on the correlated double sampling and improving the imaging quality; Preferably, a noise compensation module 206 may be added to the column signal readout unit 201, and the noise compensation module 206 senses the fluctuation of the first power supply voltage VDD1 or the column second power supply voltage VDD2 and generates a negative feedback signal to act on the column second power supply voltage VDD2, so as to suppress the fluctuation of the column second power supply voltage VDD2 and further reduce the power supply noise; Preferably, a clamping module 203 may be added to the column signal readout unit 201. Before sampling the reference signal and sampling the image signal, the voltage of the drain of the source follower transistor M3 of the pixel unit is clamped to the same level by the clamping module 203, thereby accelerating the signal stabilization speed, improving the consistency of establishing the reference signal and the image signal, and improving the image quality.

[0074] Specifically, Fig.19 for Fig.18 A circuit diagram of a related power generation module 205 and a noise compensation module 206 in a high-gain image sensor.

[0075] The related power generation module 205 includes a source follower transistor M7, the drain of the source follower transistor M7 is connected to the first power supply voltage VDD1, the source is connected to the column second power supply voltage output terminal VDD2, and the gate samples and latches the first bias voltage Vbias before the time of sampling the reference signal, and generates the column second power supply voltage VDD2 required by the column signal readout unit that has correlation when sampling the reference signal and sampling the image signal. In other embodiments not shown, those skilled in the art can also choose to use a combination of multiple source follower transistors as a source follower as needed, so as to realize the function of the related power generation module 205. The related power generation circuit 205 is realized by a source follower transistor, and the circuit structure is simple, the area consumption is small, and the output voltage is easy to program and control.

[0076] Preferably, the gate of the source follower transistor M7 of the related power generation module 205 samples the first bias voltage Vbias through the seventh switch S7 and holds it on the third capacitor C3, and performs row-by-row or frame-by-frame sampling and holding before sampling the reference signal.

[0077] The noise compensation module 206 includes a current mirror unit 208 with feedback. The bias end of the current mirror unit 208 is connected to the output end of the first power supply voltage VDD1 through the fourth capacitor C4, and the drain of the current mirror unit 208 is connected to the output end of the column second power supply voltage VDD2. Its working principle is that the bias end of the current mirror unit 208 receives the fluctuation of the first power supply voltage VDD1 to change the current size of the outflowing column second power supply voltage VDD2, thereby affecting the voltage fluctuation of the column second power supply voltage VDD2, forming negative feedback compensation.

[0078] Preferably, the current mirror unit 208 in this embodiment is a cascode current mirror, which is composed of NMOS M8 and M9. The common-gate tube M9 is used to increase the output resistance of the current mirror unit and reduce the influence of the drain voltage change on the current of the current mirror unit. The gate Vnbin of the amplifier tube M8 is connected to the second bias voltage Nbias through the eighth switch S8. S8 is turned on once per row or frame to sample the second bias voltage Nbias and keep it on the fifth capacitor C5; Vnbin is also coupled to the first power supply voltage VDD1 through the fourth capacitor C4. When there is an upward disturbance on the input first power supply voltage VDD1, there will also be an upward disturbance on the second power supply voltage VDD2. However, through the processing of the aforementioned related power generation module 205, the disturbance amplitude on the second power supply voltage VDD2 will be greatly attenuated; the Vnbin voltage is coupled to the first power supply voltage VDD1 by the fourth capacitor C4, and the current of the amplifier tube M8 controlled by Vnbin increases accordingly, the current flowing out of the node VDD2 increases, and the voltage of VDD2 decreases accordingly, forming a negative feedback compensation, further suppressing the slight disturbance on VDD2; vice versa.

[0079] Fig. 20 for Fig.18 Another circuit diagram of the related power generation module 205 and the noise compensation module 206 in the high gain image sensor.

[0080] In this embodiment, the structure of the relevant power generation module 205 is Fig.19 The difference is that the noise compensation circuit 206 includes an amplifier transistor M10, capacitors C6, C7, a switch S9 and a current source CS2, and its working timing is shown in FIG. Fig.21 The gate of the amplifier transistor M10 is connected to the output terminal of the column second power supply voltage VDD2 through the sixth capacitor C6, the drain is connected to the current source CS2, and is connected to the gate of the source follower transistor M7 of the relevant power generation circuit through the seventh capacitor C7. A ninth switch S9 is connected between the gate and the drain of the amplifier transistor M10, and the DC bias of the amplifier transistor M10 can be achieved by closing the ninth switch S9 row by row or frame by frame.

[0081] like Fig.21 As shown, the gate voltage of the source follower transistor M7 in the relevant power generation module 205 is sampled when the seventh switch S7 is turned on, and the ninth switch S9 in the noise compensation circuit 206 samples the first bias voltage Vbias in the time period t1'~t2', and the amplifier transistor M10 performs a reset operation at the same time. The sixth capacitor C6 and the seventh capacitor C7 have a voltage DC isolation function, which can make the gate of the amplifier transistor M10 at a suitable voltage bias; after t2', the seventh switch S7 is disconnected, and the gate voltage of the M7 tube is sampled, and then after t3', the ninth switch S9 is disconnected, and the closed-loop negative feedback circuit composed of the M7 tube and the M10 tube works; under the action of voltage negative feedback, the output impedance of the column second power supply voltage VDD2 node is greatly reduced, further reducing the influence of power supply noise on the column second power supply voltage VDD2 node.

[0082] Fig. 22 for Fig.18 A circuit diagram of a clamping module in a high-gain image sensor. In this embodiment, the clamping module 203 includes a clamping transistor M6 and a tenth switch S10. The source of the clamping transistor M6 is connected to the second power supply voltage VDD2 of the column; the gate and the drain are connected together, and the drain is connected to the column common current input connection 112 (V HG ). The clamp transistor M6 may be of a fixed size or a variable array with an adjustable array size.

[0083] Fig.23 for Fig. 22 The signal timing diagram of the high-gain image sensor in SHCG mode. First, Fig.23 In the timing sequence shown, the first switch S1 is always turned on, and the third switch S3 is always turned off.

[0084] During the time period t1 to t2, the reset transistor M2 in the pixel unit 101 is turned on to reset the FD to the first power supply voltage VDD1, and the fourth switch S4 of the column amplifier PMOS tube M5 is turned on to reset the column amplifier PMOS tube M5; During the time period t2 to t3, the column amplifier PMOS tube M5 completes the reset, and the fourth switch S4 is disconnected after t3; During the time period t3 to t4, the switch S10 is turned on, the switch S2 is turned off, and the clamping module 203 applies a voltage V HG After t4, the clamping is completed, the switch S10 is turned off, the switch S2 is turned on, and the column common current input connection 112 (V HG ) Establish the reset signal ref of SHCG mode; During the time period from t4 to t7, the ref signal of the SHCG mode is sampled and quantized; During the time period t8 to t10, the transfer transistor M1 in the pixel unit 101 is turned on and then turned off. Similarly, at this time, the clamping module 203 is connected to V HG Clamping is performed to the same preset fixed voltage; In the time period of t11~t12, the sig signal of the SHCG mode is quantified.

[0085] Therefore, before sampling the reference signal and sampling the image signal, the voltage of the drain of the source follower transistor of the pixel unit is clamped to the same level by the clamping module, which can speed up the signal stabilization speed, improve the consistency of the reference signal and the image signal, and improve the image quality.

[0086] It should be noted that in the above embodiments, each of the column signal readout units corresponds to a related power generation module, each of the column signal readout units corresponds to a noise compensation module, and each of the column signal readout units corresponds to a clamping module. In other embodiments not shown, those skilled in the art can select an appropriate number of column signal readout units corresponding to a related power generation module, a plurality of column signal readout units corresponding to a noise compensation module, and a plurality of column signal readout units corresponding to a clamping module for setting as needed.

[0087] In summary, the internal structure of the pixel unit of the high-gain image sensor of the present invention is consistent with the traditional 3T or 4T pixel, and has good process compatibility; only by improving the circuit structure and connection method of the column signal readout unit, an ultra-high conversion gain can be achieved, and the dynamic range in the dark light scene can be expanded without introducing additional reference voltages and power consumption caused by additional amplification circuits; the device structure size in the column signal readout unit can be much larger than the transistor in the pixel, the process consistency is better, and the conversion gain can be adjusted more flexibly; the switching between the SHCG mode and the STD mode can be achieved by driving the switch module in the column signal readout unit without driving the signal in the pixel array, and the impact on the power supply and ground during operation is smaller, thereby improving the circuit stability.

[0088] Preferably, the first bias voltage is latched and the second power supply voltage is output to the source of the column PMOS amplifier tube through the relevant power supply generation module, so that the power supply of the column signal readout unit has correlation when sampling the reference signal and sampling the image signal, thereby eliminating the influence of power supply noise on the correlated double sampling and improving the imaging quality. The noise compensation module senses the fluctuation of the first power supply voltage or the second power supply voltage of the column and generates a negative feedback signal to act on the second power supply voltage of the column to suppress the fluctuation of the second power supply voltage of the column and further reduce the power supply noise. Before sampling the reference signal and sampling the image signal, the voltage of the drain of the source follower transistor of the pixel unit is clamped to the same level through the clamping module respectively, so as to accelerate the signal stabilization speed, improve the consistency of the reference signal and the image signal, and improve the image quality.

[0089] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, in any case, the embodiments should be considered exemplary and non-restrictive. In addition, it is clear that the term "comprising" does not exclude other elements and steps, and the wording "a" does not exclude the plural. Multiple elements stated in a device claim may also be implemented by one element. The words first, second, etc. are used to indicate names and do not indicate any particular order.< / n>

Claims

1. A control method for a high-gain image sensor, characterized in that: The image sensor comprises a plurality of columns of pixel units arranged in an array, each column of pixel units having a column-common current input connection and a column-common current output connection, the gate of the source follower transistor of each pixel unit in each column is connected to the respective floating diffusion region, the drain of the source follower transistor is connected to the column-common current input connection, and the source of the source follower transistor is connected to the column-common current output connection directly or through the respective row selection transistors; The column-common current input connection and the column-common current output connection are connected to a column signal readout unit; The column signal readout unit includes a column bias current source and a column PMOS amplifier tube, wherein the column bias current source is connected to the common current output connection of the column, the drain of the column PMOS amplifier tube is connected to the common current input connection of the column, and the gate of the column PMOS amplifier tube is directly or through a capacitor connected to the common current output connection of the column, so that an amplified signal of the floating diffusion area of ​​the readout row pixel unit can be obtained on the common current input connection of the column.

2. The control method of the high gain image sensor according to claim 1, characterized in that: When the gate of the column PMOS amplifier tube is connected to the current output connection shared by the column through the first capacitor, a second capacitor is set between the gate and the drain of the column PMOS amplifier tube. By changing the ratio of the first capacitor to the second capacitor, the amplification factor of the floating diffusion area signal of the readout row pixel unit on the current input connection shared by the column by the column signal readout unit is changed.

3. The control method of the high gain image sensor according to claim 1, characterized in that: The column signal readout unit also includes a correlation power supply generation module, through which the first bias voltage is latched and the column second power supply voltage is output to the source of the column PMOS amplifier tube, so that the power supply of the column signal readout unit has correlation when sampling the reference signal and sampling the image signal, thereby eliminating the influence of power supply noise on the correlated double sampling.

4. The control method of the high gain image sensor according to claim 3, characterized in that: The related power generation module includes at least one source follower transistor, the drain of the source follower transistor of the related power generation module is connected to the first power supply voltage, the source is connected to the column second power supply voltage output terminal, and the gate samples and latches the first bias voltage before sampling the reference signal, thereby generating the column second power supply voltage required by the column signal readout unit and having correlation when sampling the reference signal and sampling the image signal.

5. The control method of the high-gain image sensor according to claim 4, characterized in that: The gate of the source follower transistor of the related power generation module samples the first bias voltage through the seventh switch and holds it on the third capacitor, and performs sampling and holding on a row-by-row or frame-by-frame basis before sampling the reference signal.

6. The control method of the high-gain image sensor according to claim 3, characterized in that: The column signal readout unit further includes a noise compensation module, which senses fluctuations of the first power supply voltage or the column second power supply voltage and generates a negative feedback signal to act on the column second power supply voltage to suppress fluctuations of the column second power supply voltage.

7. The control method of the high-gain image sensor according to claim 6, characterized in that: The noise compensation module comprises a current mirror unit, a bias terminal of the current mirror unit is connected to the first power supply voltage output terminal via a fourth capacitor, and a drain of the current mirror unit is connected to the second power supply voltage output terminal of the column.

8. The control method of the high-gain image sensor according to claim 7, characterized in that: The bias end of the current mirror unit also samples the second bias voltage through the eighth switch and holds it on the fifth capacitor to perform row-by-row or frame-by-frame sampling and holding.

9. The control method of the high-gain image sensor according to claim 7, characterized in that: The current mirror unit is a cascode current mirror.

10. The control method of the high gain image sensor according to claim 6, characterized in that: The noise compensation module includes an amplifier transistor, the gate of the amplifier transistor is connected to the second power supply voltage output terminal of the column through a sixth capacitor, the drain is connected to a current source, and is connected to the gate of a source follower transistor of the relevant power supply generating circuit through a seventh capacitor. A ninth switch is connected between the gate and the drain of the amplifier transistor, and a DC bias of the amplifier transistor can be achieved by closing the ninth switch row by row or frame by frame.

11. The control method of the high gain image sensor according to claim 1, characterized in that: The column signal readout unit further comprises a clamping module, and before sampling the reference signal and sampling the image signal, the voltage of the drain of the source follower transistor of the pixel unit is clamped to the same level by the clamping module respectively.

12. The control method of the high gain image sensor according to claim 11, characterized in that: The clamp module comprises a clamp transistor, a source of the clamp transistor is connected to the column second power supply voltage, a gate and a drain are connected to each other, and the drain is connected to the drain of the source follower transistor of the pixel unit through a tenth switch.

13. The control method of the high gain image sensor according to claim 12, characterized in that: The size of the clamp transistor is a fixed size or an array adjustable size.

14. The control method of the high gain image sensor according to claim 3, characterized in that: Each of the column signal readout units corresponds to a related power generation module, or a plurality of the column signal readout units correspond to a related power generation module.

15. The control method of the high gain image sensor according to claim 6, characterized in that: Each of the column signal readout units corresponds to a noise compensation module, or a plurality of the column signal readout units correspond to a noise compensation module.

16. The control method of the high gain image sensor according to claim 11, characterized in that: Each of the column signal readout units corresponds to a clamping module, or a plurality of the column signal readout units correspond to a clamping module.

17. The control method of the high gain image sensor according to claim 1, characterized in that: include: sampling a first reference signal outputted from a source of a source follower transistor of the pixel unit to the column signal readout unit; sampling a second reference signal outputted from the drain of the source follower transistor of the pixel unit to the column signal readout unit; The transfer transistor of the pixel unit is turned on, and the image signal outputted from the pixel unit to the column signal readout unit is sampled.

18. The control method of the high gain image sensor according to claim 17, characterized in that: The step of sampling the image signal output by the pixel unit to the column signal readout unit comprises: Making a judgment according to a voltage signal read from the pixel unit; If the judgment result is a high illumination condition, sampling the first image signal output from the source of the source follower transistor of the pixel unit to the column signal readout unit, the pixel unit having a first conversion gain; If the result of the determination is a low illumination condition, sampling the drain of the source follower transistor of the pixel unit to output a second image signal to the column signal readout unit, the pixel unit having a second conversion gain; The second conversion gain is higher than the first conversion gain.

19. The control method of the high gain image sensor according to claim 18, characterized in that: The step of judging according to the voltage signal read from the pixel unit comprises: The change amplitude of the voltage signal read from the pixel unit before and after the transfer transistor is turned on is compared with the threshold voltage. If the change amplitude is less than or equal to the threshold voltage, it is a low illumination condition; if the change amplitude is greater than the threshold voltage, it is a high illumination condition.

20. The control method of the high gain image sensor according to claim 19, characterized in that: The falling interval of the ramp voltage converted by analog to digital conversion is used as the threshold voltage.

21. The control method of the high gain image sensor according to claim 17, characterized in that: The step of sampling the image signal output by the pixel unit to the column signal readout unit comprises: sampling a second image signal outputted from a drain of a source follower transistor of the pixel unit to the column signal readout unit, the pixel unit having a second conversion gain; sampling a first image signal outputted from a source electrode of a source follower transistor of the pixel unit to the column signal readout unit, the pixel unit having a first conversion gain; The second conversion gain is higher than the first conversion gain.

22. The control method of the high gain image sensor according to claim 18 or 21, characterized in that: When the source of the source follower transistor of the pixel unit is output to the column signal readout unit, the first conversion gain is adjusted by the dual conversion gain control transistor of the pixel unit.

23. The control method of the high gain image sensor according to claim 22, characterized in that: The step of adjusting the first conversion gain by the dual conversion gain control transistor of the pixel unit comprises: The dual conversion gain control transistor is turned on to obtain a relatively low first conversion gain, or the dual conversion gain control transistor is turned off to obtain a relatively high first conversion gain.

24. The control method of the high-gain image sensor according to claim 17, characterized in that: The source or drain of the source follower transistor of the pixel unit is controlled by a switch module to be output to the column signal readout unit.

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