A method of connecting a resistor element and a semiconductor device structure

Abstract

The application discloses a wiring method of a resistance element and a semiconductor device structure. The method comprises the following steps: forming a resistance element covered with a hard mask layer above a substrate with source-drain and gate; and then forming source-drain and gate contacts. The method can avoid damaging the source-drain and gate contacts. In the selective metal deposition process, the hard mask layer reserved on the bottom surface of the resistance element lead-out groove is used to protect the resistance element, so that the selective metal deposition is realized only in the source-drain lead-out groove and the gate lead-out groove. The source-drain lead-out contact hole and the gate lead-out contact hole are formed first, and then the hard mask layer on the bottom surface of the resistance element lead-out groove is removed to break the isolation between the resistance element lead-out groove and the resistance element, and the CVD metal is filled to form the resistance element lead-out contact hole with low resistance contact. The application can reduce the device height and improve the device performance.

Claims

1. A wiring method for a resistive element, characterized in that, include: Provides a substrate for forming the active drain and gate; An isolation layer, a resistive element layer, and a hard mask layer are sequentially formed on the substrate; A resistive element pattern covered by the hard mask layer is formed on the isolation layer other than the source and drain; A first dielectric layer is covered on the isolation layer and the hard mask layer; Source / drain contact trenches and gate contact trenches are formed from the surface of the first dielectric layer downwards, and the contact metal is filled. The first dielectric layer is thinned and stopped at the hard mask layer to form source / drain contact and gate contact structures; A capping layer and a second dielectric layer are sequentially formed on the first dielectric layer and the hard mask layer; Resistive element lead-out trenches, source-drain lead-out trenches, and gate lead-out trenches are formed from the surface of the second dielectric layer downwards, and stop at the hard mask layer, the source-drain contact, and the gate contact, respectively. Selective growth of the first lead-out metal is performed in the source / drain lead-out trench and the gate lead-out trench; Remove the hard mask layer located on the bottom surface of the lead-out trench of the resistor element to expose the surface of the resistor element; The second lead metal is filled into the lead trench of the resistive element; The second dielectric layer is thinned to form resistive element lead-out contact holes, source / drain lead-out contact holes, and gate lead-out contact holes.

2. The wiring method for the resistive element according to claim 1, characterized in that, Before filling the contact metal, a diffusion barrier layer and a seed layer are sequentially formed on the inner wall of the source / drain contact trench and the inner wall of the gate contact trench, respectively.

3. The wiring method for the resistive element according to claim 1, characterized in that, The contact metal includes cobalt.

4. The wiring method for the resistive element according to claim 1, characterized in that, The capping layer is used as an etch stop layer when forming the resistive element lead-out trench, the source / drain lead-out trench, and the gate lead-out trench.

5. The wiring method for the resistive element according to claim 1, characterized in that, When selectively growing the first lead metal, the hard mask layer exposed on the bottom surface of the resistor element lead trench is used as a protective layer for the resistor element and a growth barrier layer for the first lead metal, so that the growth and filling of the first lead metal is achieved only in the source / drain lead trench and the gate lead trench.

6. The wiring method for the resistive element according to claim 1, characterized in that, A full etching method is used to remove the hard mask layer located on the bottom surface of the resistor element lead-out trench, forming a filling window that connects to the surface of the resistor element below the bottom surface of the resistor element lead-out trench.

7. The wiring method for the resistive element according to claim 1, characterized in that, Using the CVD method, a diffusion barrier layer and a seed layer are first formed sequentially on the inner wall of the lead-out trench of the resistor element and on the exposed surface of the resistor element, and then the second lead-out metal is filled.

8. The wiring method for the resistive element according to claim 1, characterized in that, The first lead-out metal and / or the second lead-out metal includes W.

9. A semiconductor device structure, characterized in that, include: A substrate for forming the active drain and gate; An isolation layer is formed on the substrate; A resistive element formed on the isolation layer other than the source and drain, and a hard mask layer covering the resistive element, and a first dielectric layer formed on the isolation layer other than the resistive element and the hard mask layer, wherein the hard mask layer has a filling window communicating with the surface of the resistive element; Source and drain contacts are formed downward from the surface of the first dielectric layer on the source and drain, and gate contacts are formed on the gate. A capping layer and a second dielectric layer are sequentially formed on the first dielectric layer and the hard mask layer; Source and drain lead-out contact holes are formed downward from the surface of the second dielectric layer on the source and drain contacts, gate lead-out contact holes are formed on the gate contacts, and resistor element lead-out contact holes are formed on the surface of the resistor element through the filling window on the hard mask layer. The source / drain lead-out contact hole and the gate lead-out contact hole are provided with a first lead-out metal filled in a first manner, and the resistor element lead-out contact hole is provided with a second lead-out metal filled in a second manner different from the first manner.

10. The semiconductor device structure according to claim 9, characterized in that, The first method includes a selective metal growth method; wherein, when performing the first method, the first lead metal is filled only in the source / drain lead contact hole and the gate lead contact hole, and when performing the second method, the filling window is formed, so that the second lead metal filled only in the resistor element lead contact hole is in contact with the surface of the resistor element to form an ohmic contact.

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