Packaging substrates and electronic devices

Abstract

A packaging substrate and an electronic device are disclosed. The packaging substrate includes a substrate, multiple reference layers, multiple routing layers, a dielectric layer, and interconnect vias. At least one of the multiple signal lines includes multiple signal segments, which are located in at least two routing layers. Each pad is connected to the signal line. The interconnect vias are located between different routing layers, and the signal segments located in different routing layers are electrically connected through the pads and the interconnect vias. The distance between the two points with the largest distance on the edge of the pad's orthographic projection on the substrate is the maximum pad size, and the ratio of the maximum pad size to the linewidth of the signal segment is greater than 4. This disclosure, by setting a single signal line originally located in one routing layer as multiple signal segments located in different routing layers, connecting the signal segments in different layers through interconnect vias and pads, and simultaneously increasing the maximum pad size, can effectively reduce the characteristic impedance of the signal lines in the packaging substrate.

Description

TECHNICAL FIELD

[0001] The present disclosure at least one embodiment relates to a packaging substrate and an electronic device. BACKGROUND

[0002] With the continuous development of modern technology, impedance matching technology is widely used in the field involving energy transmission from the source end to the load end, such as acoustic systems, optical systems and mechanical systems. Impedance matching is part of microwave electronics, mainly used on transmission lines to achieve the goal that all high-frequency microwave signals can be transmitted to the load point without signal reflection back to the source point, thereby improving energy efficiency.

[0003] At present, the main methods to reduce the characteristic impedance of the signal transmission line include increasing the line width of the transmission line, increasing the thickness of the transmission line, increasing the dielectric constant of the dielectric layer, and reducing the distance from the transmission line to the reference plane. SUMMARY

[0004] The present disclosure at least one embodiment provides a packaging substrate and an electronic device.

[0005] The present disclosure embodiment provides a packaging substrate, comprising a substrate, a plurality of reference layers, a plurality of trace layers, a dielectric layer and a connection via. The plurality of reference layers are stacked on the substrate along a first direction perpendicular to the substrate; the plurality of trace layers are stacked along the first direction, and one reference layer is arranged between two adjacent trace layers, the plurality of trace layers are provided with a plurality of signal lines and a plurality of pads, at least one signal line in the plurality of signal lines comprises a plurality of signal line segments, the plurality of signal line segments are located in at least two trace layers, the plurality of signal line segments all extend along a second direction, each pad in the plurality of pads is connected with the signal line, and the second direction intersects with the first direction; the dielectric layer is located between the reference layer and the trace layer; the connection via is arranged in the dielectric layer, and the signal line segments of different trace layers are electrically connected through the pad and the connection via; wherein the distance between the two points with the maximum distance on the edge of the orthographic projection of the pad on the substrate is the maximum pad size, and the ratio of the maximum pad size to the line width of the signal line segment is greater than 4.

[0006] For example, according to an embodiment of the present disclosure, the plurality of signal lines comprises a first signal line and a second signal line, the first signal line and the second signal line are arranged in a third direction parallel to the substrate, the first signal line and the second signal line are insulated from each other, and the third direction intersects the second direction; the first signal line comprises a plurality of first signal sub-lines, and the second signal line comprises a plurality of second signal sub-lines, wherein, in the same trace layer of at least one of the trace layers, the first signal sub-lines and the second signal sub-lines are staggered in the second direction, and a projection of each first signal sub-line on a plane perpendicular to the third direction partially overlaps or does not overlap with a projection of the second signal sub-line on the plane perpendicular to the third direction.

[0007] For example, according to an embodiment of the present disclosure, among the first signal sub-lines and the second signal sub-lines in the same trace layer of at least one of the trace layers, a projection of a pad connected to the first signal sub-line on a plane perpendicular to the third direction does not overlap with a projection of a pad connected to the second signal sub-line on the plane perpendicular to the third direction.

[0008] For example, according to an embodiment of the present disclosure, in the second direction, the plurality of first signal sub-lines in the same trace layer are arranged at equal intervals, and the plurality of second signal sub-lines in the same trace layer are arranged at equal intervals.

[0009] For example, according to an embodiment of the present disclosure, the packaging substrate further comprises a plurality of reference vias and a plurality of reference pads, the reference vias are arranged in the dielectric layer, the reference pads are electrically connected to the reference vias, at least one reference pad connected to a same reference via is electrically connected to the reference layer, and each connection via corresponds to at least one reference via, and the reference via is configured to form a signal reflow path with the connection via.

[0010] For example, according to an embodiment of the present disclosure, a projection area of one pad connected to the connection via on the substrate is greater than a projection area of one reference pad connected to the reference via on the substrate.

[0011] For example, according to an embodiment of the present disclosure, a minimum distance between each connection via and the reference via corresponding thereto is 5-25 μm.

[0012] For example, according to an embodiment of the present disclosure, the at least one signal line includes a first signal line segment, a second signal line segment, and a third signal line segment, the at least two trace layers include a first trace layer and a second trace layer, the first signal line segment and the second signal line segment are both located on the first trace layer and are spaced apart, and the third signal line segment is located on the second trace layer, wherein the connection via includes a first connection via and a second connection via, the pad includes a first pad and a second pad, the first signal line segment and the third signal line segment are electrically connected through the first connection via and the first pad, and the second signal line segment and the third signal line segment are electrically connected through the second connection via and the second pad.

[0013] For example, according to an embodiment of the present disclosure, the orthographic projection of the first signal line segment on the substrate, the orthographic projection of the second signal line segment on the substrate, and the orthographic projection of the third signal line segment on the substrate do not overlap.

[0014] For example, according to an embodiment of the present disclosure, the orthographic projection of at least one of the first signal line segment and the second signal line segment on the substrate at least partially overlaps with the orthographic projection of the third signal line segment on the substrate.

[0015] For example, according to an embodiment of the present disclosure, the at least one signal line includes a first signal line segment and a second signal line segment, and the at least two trace layers include a first trace layer and a second trace layer; the first signal line segment is located on the first trace layer, and the second signal line segment is located on the second trace layer; the orthographic projection of the second signal line segment on the substrate falls within the orthographic projection of the first signal line segment on the substrate, wherein the first signal line segment and the second signal line segment are electrically connected through at least one connection via and at least one pad.

[0016] For example, according to an embodiment of the present disclosure, the first trace layer and the second trace layer are adjacent trace layers.

[0017] For example, according to an embodiment of the present disclosure, the first trace layer and the second trace layer are separated by at least one trace layer.

[0018] For example, according to an embodiment of the present disclosure, the distance between the two points with the maximum distance on the edge of the orthographic projection of the reference pad on the substrate is a maximum reference pad size, and the maximum pad size is 1.1-3.5 times the maximum reference pad size.

[0019] For example, according to an embodiment of the present disclosure, the at least one reference via corresponding to each connection via includes a first reference via and a second reference via, and the projections of the first reference via and the second reference via on the substrate are symmetrically distributed with respect to a plane extending along the second direction and passing through the center of the connection via.

[0020] For example, according to an embodiment of the present disclosure, the maximum dimension of the reference layer between the two adjacent trace layers in the second direction is at least 3-4 times the length of at least one signal line segment in the two adjacent trace layers.

[0021] An electronic device is provided according to an embodiment of the present disclosure, including any of the package substrates described above. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only related to some embodiments of the present disclosure, and not limit the present disclosure.

[0023] Figure 1 A schematic diagram of a stripline structure.

[0024] Figure 2 A schematic diagram of a microstrip line structure.

[0025] Figure 3 A partial cross-sectional view of a package substrate provided by at least one embodiment of the present disclosure.

[0026] Figure 4 Another partial cross-sectional view of a package substrate provided by at least one embodiment of the present disclosure.

[0027] Figure 5 A plan view of a trace layer in a package substrate provided by at least one embodiment of the present disclosure.

[0028] Figure 6 Another plan view of a trace layer in a package substrate provided by at least one embodiment of the present disclosure.

[0029] Figure 7 Another partial cross-sectional view of a package substrate provided by at least one embodiment of the present disclosure.

[0030] Figure 8 Another partial cross-sectional view of a package substrate provided by at least one embodiment of the present disclosure.

[0031] Figure 9 Another partial cross-sectional view of a package substrate provided by at least one embodiment of the present disclosure.

[0032] Figure 10Yet another partial cross-sectional view of a package substrate is provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0034] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include" or "contain" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects.

[0035] The features "vertical" and "same" and the like used in the embodiments of the present disclosure include the strict "vertical", "same" and the like, and the "approximately vertical", "approximately same" and the like with a certain error, which, considering the measurement and the error related to the measurement of a specific value (that is, the limitation of the measurement system), represents the acceptable deviation range for the specific value determined by those of ordinary skill in the art. The "center" in the embodiments of the present disclosure can include the position strictly located at the geometric center and the position approximately at the center within a small area around the geometric center. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0036] Impedance matching is mainly used on the transmission line to achieve the purpose that all high-frequency signals can be transmitted to the load point, thereby improving the transmission efficiency. The internal resistance of the signal source is equal in size and phase to the characteristic impedance of the connected transmission line, which is referred to as the input end of the transmission line being in an impedance matching state. The characteristic impedance of the transmission line is equal in size and phase to the size of the connected load impedance, which is referred to as the output end of the transmission line being in an impedance matching state. When the input end or the output end of the transmission line is in an impedance matching state, it is simply referred to as impedance matching.

[0037] The telegraph equation of the transmission line can represent the relationship between the interaction of the various distributed parameters of the transmission line and the signal, and the solution of the telegraph equation can indicate the transmission mode of the electromagnetic wave inside the transmission line. Based on the transmission line model of the telegraph equation, the characteristic impedance of the transmission line can be represented by the following formula:

[0038]

[0039] R represents the resistance per unit length; L represents the inductance per unit length; G represents the conductance per unit length of the dielectric; C represents the capacitance per unit length.

[0040] Currently, the transmission line structures on packaging substrates are mainly striplines and microstrip lines.

[0041] Figure 1 A schematic diagram of a stripline structure; Figure 2 This is a schematic diagram of a microstrip line structure.

[0042] like Figure 1 As shown, the stripline structure includes reference planes 011 and 012 stacked together, and a transmission signal line 014 placed between the two reference planes. An insulating medium 013 fills the space between each reference plane and the transmission signal line 014. For example, reference planes 011 and 012 can be ground planes or power planes. w1 represents the linewidth of the transmission signal line 014; h1 represents the distance from the transmission signal line 014 to the reference plane 012; and h2 represents the thickness of the transmission signal line 014.

[0043] like Figure 2 As shown, the microstrip line structure includes a reference plane 021, and the transmission signal line 023 is separated from the reference plane by an insulating medium 022. w2 represents the linewidth of the transmission signal line 023; h3 represents the distance from the transmission signal line 023 to the reference plane 021; and h4 represents the thickness of the transmission signal line 023.

[0044] As the voltage of I / O (Input / Output) in modern electronic products (e.g., chips) becomes increasingly lower, the driving resistance of I / O will gradually decrease in order to increase the driving capability of electronic product I / O. This results in a requirement for the characteristic impedance of the transmission signal lines to become smaller and smaller, thereby optimizing the signal integrity.

[0045] This study found that, in general process design, methods to reduce the characteristic impedance of striplines and microstrip lines in packaging substrates are mainly implemented at the two-dimensional level. These methods include reducing the distance from the transmission signal line to the reference plane (e.g., the thickness of the dielectric layer), increasing the thickness of the transmission signal line, increasing the dielectric constant of the dielectric layer, and increasing the linewidth of the transmission signal line. However, the distance from the transmission signal line to the reference plane and the thickness of the transmission signal line are usually limited by the packaging substrate fabrication process. The dielectric constant of the dielectric layer is an inherent characteristic of the dielectric material and is therefore difficult to adjust and cannot be arbitrarily changed. Therefore, increasing the linewidth of the transmission signal line becomes a more easily implemented adjustment method. However, adjusting the linewidth of the transmission signal line may increase crosstalk between transmission signal lines.

[0046] This disclosure provides at least one embodiment of a packaging substrate and an electronic device. The packaging substrate includes a substrate, multiple reference layers, multiple routing layers, a dielectric layer, and interconnect vias. Multiple reference layers are stacked on the substrate along a first direction perpendicular to the substrate; multiple routing layers are stacked along the first direction, with a reference layer disposed between adjacent routing layers; multiple routing layers have multiple signal lines and multiple pads, at least one of the signal lines includes multiple signal segments, the signal segments are located in at least two routing layers, and all signal segments extend along a second direction intersecting the first direction; each of the multiple pads is connected to a signal line; a dielectric layer is located between the reference layers and the routing layers; interconnect vias are located in the dielectric layer, and signal segments located in different routing layers are electrically connected through pads and interconnect vias. The distance between the two points with the largest distance on the edge of the orthographic projection of the pad on the substrate is the maximum pad size, and the ratio of the maximum pad size to the linewidth of the signal segment is greater than 4.

[0047] This embodiment of the present disclosure sets a single signal line in a single trace layer as multiple signal line segments located in different trace layers, and connects the signal line segments in different layers of the same signal line through connecting vias and pads, while increasing the maximum pad size, thereby effectively reducing the characteristic impedance of the signal line in the package substrate from the three-dimensional level of the transmission signal line.

[0048] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, but this disclosure is not limited to these specific embodiments.

[0049] Figure 3 A partial cross-sectional view of a packaging substrate provided for at least one embodiment of this disclosure; Figure 4 Another partial cross-sectional view of a packaging substrate provided in at least one embodiment of this disclosure; Figure 5 This is a plan view of a wiring layer in a packaging substrate provided in at least one embodiment of the present disclosure; Figure 6 This is a plan view of a wiring layer in another packaging substrate provided in at least one embodiment of the present disclosure.

[0050] For example, Figure 3 It can be in Figure 5 A partial cross-sectional view along line AA'. Figure 4 It can be in Figure 5 A partial cross-sectional view along line BB'. For example, for a concise and clear illustration, Figure 3 Only shown Figure 5 A partial cross-sectional view of the portion extending in the X direction along line AA'. Figure 4 Only shown Figure 5 A partial cross-sectional view of the portion extending in the Y direction along line BB'.

[0051] like Figure 3 As shown, at least one embodiment of this disclosure provides a packaging substrate 01, including a substrate 10, a plurality of reference layers 11, a plurality of wiring layers 12, a dielectric layer 14, and a connection via 18. The plurality of reference layers 11 are stacked on the substrate 10 perpendicular to a first direction Z; the plurality of wiring layers 12 are stacked along the first direction Z, with a reference layer 11 disposed between two adjacent wiring layers 12; the plurality of wiring layers 12 have a plurality of signal lines 15 and a plurality of pads 17; at least one of the signal lines 15 includes a plurality of signal segments 16, which are located in at least two wiring layers 12, and all signal segments 16 extend along a second direction X; each pad 17 is connected to a signal line 15; the dielectric layer 14 is located between the reference layers 11 and the wiring layers 12; the connection via 18 is disposed in the dielectric layer 14, and the signal segments 16 located in different wiring layers 12 are electrically connected through the pads 17 and the connection via 18.

[0052] like Figure 3 and Figure 4 As shown, the distance between the two points with the largest distance on the edge of the orthographic projection of the pad 17 on the substrate 10 is the maximum pad size M1. The ratio of the maximum pad size M1 to the line width M2 of the signal line segment 16 is greater than 4. The first direction Z is perpendicular to the substrate 10, and the second direction X intersects the first direction Z.

[0053] This embodiment of the present disclosure sets a single signal line in a single trace layer as multiple signal line segments in different trace layers, and connects the signal line segments in different layers of the same signal line through connecting vias and pads. At the same time, it increases the maximum pad size, which can effectively reduce the characteristic impedance of the signal lines in the package substrate.

[0054] For example, such as Figure 3 As shown, the signal lines in the embodiments of this disclosure can be stripline structures or microstrip line structures. A plurality of routing layers 12 are disposed in the package substrate 01, and signal lines 15 are disposed in the routing layers 12. A reference layer 11 is disposed between two adjacent routing layers 12. For example, when a routing layer 12 is located between two adjacent reference layers 11, a dielectric layer 14 fills the space between the routing layer 12 and the two adjacent reference layers 11, thereby forming a stripline structure. For example, the same routing layer 12 corresponds to one reference layer 11, and a dielectric layer 14 fills the space between the routing layer 12 and the two adjacent reference layers 11, thereby forming a microstrip line structure, but this is not limited to these examples.

[0055] For example, such as Figure 3As shown, in the package substrate 01, multiple signal lines 15 are disposed in multiple routing layers 12. According to actual design requirements, the same signal line 15 in the package substrate 01 can be configured for layer-swapping routing and connected via layer-swapping vias. Unlike layer-swapping routing, embodiments of this disclosure propose configuring the signal line 15 originally located in the same routing layer 12 as multiple signal line segments 16 located in different routing layers 12. That is, multiple signal line segments 16 are separated by multiple routing layers 12, and then connected to the signal line segments 16 in different routing layers 12 through connecting vias 18 to reduce the impedance of the signal line 15. For example, at least one of the multiple signal lines 15 may include a signal line 15 that is configured as multiple signal line segments 16 located in different routing layers 12, instead of the original signal line 15 located in the same routing layer 12. For example, at least one of the multiple signal lines 15 may include multiple signal lines 15 in which each signal line 15 originally located in the same routing layer 12 is respectively configured as multiple signal line segments 16 located in different routing layers 12, but is not limited thereto. For example, the multiple signal lines 15 may be insulated from each other.

[0056] For example, such as Figure 3 As shown, the package substrate 01 also includes a plurality of reference vias 19 and a plurality of reference pads 20. The reference vias 19 are disposed in the dielectric layer 14, and the reference pads 20 are electrically connected to the reference vias 19. At least one reference pad 20 connected to the same reference via 19 is electrically connected to the reference layer 11. Each connection via 18 corresponds to at least one reference via 19, and the reference vias 19 are configured to form a signal return path with the connection vias 18.

[0057] For example, multiple reference vias 19 can be disposed near a connecting via 18 to form a signal return path. For example, the multiple reference vias 19 can be evenly distributed relative to the connecting via 18, but are not limited thereto; the embodiments of this disclosure do not limit the number and distribution of the reference vias 19. For example, the same reference via 19 can be connected to two reference pads 20, and the two reference pads 20 can be located on opposite sides of the reference via 19 in the Z direction. For example, of the two reference pads 20 connected to the same reference via 19, one reference pad 20 can be located in the reference layer 11, and the other reference pad 20 can be located in the routing layer 12, but are not limited thereto.

[0058] For example, such as Figure 3As shown, the same via 18 can be connected to two pads 17, and the two pads 17 are located on opposite sides of the via 18 in the Z direction. For example, the pad 17 can be located at the end of a signal line segment 16 and integrally formed with the signal line segment 16, but is not limited thereto. For example, the orthographic projection of the pad 17 on the substrate 10 can be a circle, an ellipse, a polygon, or a regular polygon, etc. The embodiments of this disclosure do not limit the shape of the pad 17.

[0059] For example, refer to Figure 3 and Figure 4 The first direction Z can be perpendicular to the substrate 10, the second direction X can be perpendicular to the first direction Z, and the third direction Y is perpendicular to the first direction Z and perpendicular to the second direction X. For example, the second direction X is the extension direction of the signal line 15, which can be the length direction of the signal line 15; the third direction Y can represent the width direction of the signal line 15. For example, the distance M1 between the two points with the largest distance on the edge of the orthographic projection of the pad 17 on the substrate 10 (i.e., the maximum pad size) can be the maximum size of the pad 17 in the third direction Y, and the line width of the signal line segment 16 is M2.

[0060] For example, refer to Figure 3 and Figure 4 The signal line width M2 can be 12-30 μm. For example, the signal line width M2 can be 15-25 μm. For example, the signal line width M2 can be 13-20 μm. For example, the signal line width M2 can be 10-18 μm, but it is not limited thereto. The embodiments of this disclosure do not limit the signal line width M2. For example, the ratio of the maximum pad size M1 to the signal line width M2 of the signal line segment 16 can be greater than 4-6. For example, the ratio of the maximum pad size M1 to the signal line width M2 of the signal line segment 16 can be 4.5-5.5. For example, the ratio of the maximum pad size M1 to the signal line width M2 of the signal line segment 16 can be 5-6.5.

[0061] refer to Figure 3 and Figure 4By configuring the same signal line 15, originally located on the same trace layer 12, as multiple signal segments 16 located on different signal layers 12 in the package substrate provided in this embodiment, and connecting adjacent signal segments 16 through connecting vias 18 and pads 17, the number of connecting vias 18 and reference vias 19 in the package substrate 01 can be increased, and the coupling capacitance between the connecting vias 18 and the reference layer 11 can be increased, thereby reducing the characteristic impedance of the signal line 15 (for example, the relationship between capacitance and characteristic impedance can be found in the above formula). At the same time, by making the ratio between the maximum pad size M1 of the connecting via 18 and the line width M2 greater than 4, such as by maximizing the size of the pad 17 connected to the connecting via 18, the coupling capacitance between the pad 17 and the reference layer 11 can be increased, thereby effectively reducing the characteristic impedance of the signal line 15.

[0062] For example, refer to Figure 3 , Figure 5 The multiple signal lines 15 include a first signal line 101 and a second signal line 102, which are arranged at intervals along a third direction Y. The first signal line 101 and the second signal line 102 are insulated from each other. The first signal line 101 includes multiple first signal sub-segments 151, and the second signal line 102 includes multiple second signal sub-segments 152.

[0063] For example, refer to Figure 3 , Figure 5 In the same routing layer 12 of at least one routing layer 12, the first signal sub-segment 151 and the second signal sub-segment 152 are staggered along the second direction X. The orthographic projection of each first signal sub-segment 151 on a plane perpendicular to the third direction Y partially overlaps or does not overlap with the orthographic projection of the second signal sub-segment 152 on a plane perpendicular to the third direction Y.

[0064] For example, refer to Figure 3 , Figure 5 The first signal line 101 and the second signal line 102 can be two adjacent signal lines extending along the second direction X. The multiple first signal sub-segments 151 in the first signal line 101 and the multiple second signal sub-segments 152 in the second signal line 102 are insulated from each other.

[0065] For example, refer to Figure 3 and Figure 5 The multiple first signal sub-segments 151 in the first signal line 101 and the multiple second signal sub-segments 152 in the second signal line 102 can be distributed in different routing layers 12. Figure 5The dashed lines other than the center cutoff lines AA' and BB' can represent structures distributed in routing layers 12 (not shown). For example, multiple first signal sub-segments 151 and multiple second signal sub-segments 152 can be distributed in at least two routing layers 12, but are not limited thereto. For example, first signal sub-segments 151 and second signal sub-segments 152 located in different routing layers 12 are electrically connected via pads 17 and connection vias 18. For example, at least one reference via 19 is also provided around each connection via 18 to form a signal return path with the connection via 18. For example, multiple reference vias 19 can be distributed around multiple connection vias 18. For example, when the first signal sub-segment 151 and the second signal sub-segment 152 are staggered along the second direction X, the distance between the first signal sub-segment 151 and the second signal sub-segment 152 in the second direction X can be less than the length of the first signal sub-segment 151, equal to the length of the first signal sub-segment 151, or greater than the length of the first signal sub-segment 151. The embodiments of this disclosure do not limit this, and can be set according to product requirements.

[0066] This configuration increases the number of connecting vias 18 and reference vias 19, increases the coupling capacitance between connecting vias 18 and reference vias 19, and also increases the coupling capacitance between connecting vias 18 and reference layer 11, thereby reducing the characteristic impedance of signal line 15. Simultaneously, in at least one routing layer 12, multiple first signal sub-segments 151 and multiple second signal sub-segments 152 are staggered along the second direction X, such that the orthographic projection of the first signal sub-segment 151 onto a plane perpendicular to the third direction Y overlaps with the orthographic projection of the second signal sub-segment 152 onto a plane perpendicular to the third direction Y. This reduces the capacitance between adjacent signal sub-segments in the third direction Y and reduces the probability of crosstalk occurring at the connecting vias 18.

[0067] Figure 6 Another example of an embodiment of this disclosure is shown. Figure 6 The signal lines shown are Figure 5 The difference between the signal lines is that the arrangement of multiple signal line segments in adjacent signal lines 15 is different; the other characteristics are the same, and will not be described in detail here.

[0068] For example, refer to Figure 3 and Figure 6The multiple signal lines 15 include a first signal line 103 and a second signal line 104, which are spaced apart along a third direction Y. The first signal line 103 and the second signal line 104 are insulated from each other. The first signal line 103 includes multiple first signal sub-segments 153, and the second signal line 104 includes multiple second signal sub-segments 154. In at least one routing layer 12, the first signal sub-segments 153 and the second signal sub-segments 154 are staggered along a second direction X, and the orthographic projection of each first signal sub-segment 153 in the routing layer 12 onto a plane perpendicular to the third direction Y does not overlap with the orthographic projection of each second signal sub-segment 154 onto a plane perpendicular to the third direction Y.

[0069] For example, in Figure 6 In the routing layer 12 shown, in the second direction X, the distance R1 between two adjacent first signal segments 153 is greater than the size R2 of the second signal segment 154. The distance between two adjacent second signal segments 154 is also greater than the size of the first signal segment 153.

[0070] Therefore, by setting a single signal line 15 originally located on the same trace layer 12 as multiple signal line segments located on different signal layers 12, and connecting adjacent signal line segments using vias 18 and pads 17, the characteristic impedance can be reduced, and the spatial arrangement of adjacent signal lines 15 can be optimized. This allows multiple signal sub-segments of signal line 15 to be staggered in the second direction X and spaced apart in the third direction Y, which helps to reduce crosstalk between multiple signal line segments and improve signal transmission quality.

[0071] For example, refer to Figure 3 , Figure 5 and Figure 6 In the first signal sub-segment 151 and the second signal sub-segment 152 of the same routing layer 12 at least one routing layer 12, the orthographic projection of the pad 17 connected to the first signal sub-segment 151 on the plane perpendicular to the third direction Y does not overlap with the orthographic projection of the pad 17 connected to the second signal sub-segment 152 on the plane perpendicular to the third direction Y.

[0072] For example, refer to Figure 3 and Figure 5 The orthographic projection of a pad 17 connected to one end of a first signal sub-segment 151 onto a plane perpendicular to the third direction Y lies between the orthographic projections of the pads 17 connected to the two adjacent second signal sub-segments 152 onto a plane perpendicular to the third direction Y. The orthographic projection of a pad 17 connected to one end of a second signal sub-segment 152 onto a plane perpendicular to the third direction Y lies between the orthographic projections of the pads 17 connected to the two adjacent first signal sub-segments 151 onto a plane perpendicular to the third direction Y.

[0073] For example, in Figure 6 In the shown trace layer 12, in the second direction X, the distance R3 between the pads 17 connected to two adjacent first signal sub-segments 153 is greater than the maximum distance R4 between the far ends of the pads 17 connected to the same second signal sub-segment 154. The distance between the pads 17 connected to two adjacent second signal sub-segments 154 is also greater than the maximum distance between the far ends of the pads 17 connected to the same first signal sub-segment 153.

[0074] It should be noted that the arrangement of the multiple signal line segments in the multiple signal lines provided in the above embodiments is merely exemplary and is not intended to limit the scope of this disclosure.

[0075] By ensuring that the orthographic projection of the pad 17 connected to the first signal sub-segment on the plane perpendicular to the third direction Y does not overlap with the orthographic projection of the pad 17 connected to the second signal sub-segment on the plane perpendicular to the third direction Y, the probability of crosstalk between the connecting vias 18 used to connect signal sub-segments located in different routing layers can be reduced, thereby reducing the characteristic impedance of the signal line 15 while ensuring good transmission performance.

[0076] For example, refer to Figure 3 and Figure 5 In the second direction X, multiple first signal sub-segments 151 located in the same routing layer 12 are arranged at equal intervals, and multiple second signal sub-segments 152 located in the same routing layer 12 are arranged at equal intervals.

[0077] For example, refer to Figure 3 and Figure 5 Within the same routing layer 12, the spacing between any two adjacent first signal sub-segments 151 is L1, and the spacing between any two adjacent second signal sub-segments 152 is L2. For example, L1 can be equal to L2 to make the arrangement of multiple signal sub-segments in the second direction X more uniform. Alternatively, L1 can be unequal to L2 to flexibly adapt to the spatial design of different routing layers 12, without limitation.

[0078] By setting the multiple signal segments of the signal lines in the same routing layer 12 at equal intervals, the uniformity of the signal line segments in the routing layer 12 can be improved, thereby reducing the probability of crosstalk and optimizing the signal transmission effect.

[0079] For example, refer to Figure 3 and Figure 6 In the packaging substrate 01, the orthogonal projection area of ​​a pad 17 on the substrate 10 is greater than the orthogonal projection area of ​​a reference pad 20 on the substrate 10.

[0080] For example, refer to Figure 3 , Figure 4 and Figure 6 The distance between the two points on the edge of the orthographic projection of the reference pad 20 onto the substrate 10 that are the largest distance apart is the maximum reference pad size M3. The ratio of the maximum reference pad size M3 to the line width of the signal line is less than 4. For example, the above size can be 2-3.5. For example, the above size can be 2.5-3. For example, the above size can be 2.8-3.2. For example, the above size can be 3.1-3.4.

[0081] By making the orthogonal projection area of ​​the pad 17 connected to the via 18 on the substrate 10 larger than the orthogonal projection area of ​​the reference pad 20 connected to the reference via 19 on the substrate 10, the coupling capacitance between the pad 17 connected to the via 18 and the reference layer 11 can be increased, thereby reducing the characteristic impedance of the signal line 15 and reducing the difficulty and cost of design and operation.

[0082] For example, refer to Figure 3 and Figure 6 The minimum distance H between each connection via 18 and its corresponding reference via 19 in the package substrate 01 is 5-25 μm. For example, the minimum distance can be 10-20 μm. For example, the minimum distance can be 15-25 μm. For example, the minimum distance can be 12-18 μm. For example, the minimum distance can be 8-17 μm. For example, the minimum distance can be 16-24 μm. For example, the minimum distance can be 19-23 μm.

[0083] By reasonably setting the minimum distance between the connecting via 18 and its corresponding reference via 19, the coupling capacitance between the connecting via 18 and its corresponding reference via 19 can be controlled, thereby effectively reducing the characteristic impedance of the signal line segment.

[0084] For example, refer to Figure 3 , Figure 4 and Figure 6 The maximum pad size M3 of reference pad 20 is 1.1-3.5 times the maximum reference pad size M2.

[0085] For example, the maximum reference pad size M3 of the reference via 19 can be 60-90 μm. For example, the maximum pad size of the pad 17 connected to the connecting via 18 can be 100-300 μm, but is not limited thereto. The embodiments of this disclosure do not limit the specific dimensions of the pad 20 connected to the reference via 19 and the pad 17 connected to the connecting via 18.

[0086] By designing the maximum pad size M3 to be 1.1-3.5 times the maximum reference pad size M2, the manufacturing precision requirements of the connection via 18 can be reduced, thereby simplifying the manufacturing process and saving operating costs.

[0087] For example, refer to Figure 3 , Figure 4 and Figure 6 Each connection via 18 includes at least one reference via 19, which includes a first reference via 191 and a second reference via 192. The orthographic projections of the first reference via 191 and the second reference via 192 on the substrate 10 are symmetrically distributed with respect to a plane that extends along the second direction X and passes through the center of the connection via 18.

[0088] For example, refer to Figure 3 , Figure 4 and Figure 6 The reference via 19 corresponding to the connecting via 18 can be the reference via closest to the connecting via 18. For example, each connecting via 18 can correspond to two reference vias, namely a first reference via 191 and a second reference via 192. Of course, each connecting via 18 can also form a signal return path with other reference vias 19. In the embodiments of this disclosure, the center of the connecting via 18 can be the center of symmetry of the connecting via 18. Therefore, the plane extending along the second direction X and passing through the center of the connecting via 18 can be a plane passing through the center of symmetry of the connecting via 18 and perpendicular to the third direction Y.

[0089] By making the orthographic projections of the first reference via 191 and the second reference via 192 corresponding to each connection via 18 on the substrate 10 symmetrically distributed with respect to the plane extending along the second direction X and passing through the center of the connection via 18, it is beneficial to improve the uniformity of the signal return path between the connection via 18 and each reference via, reduce signal fluctuations, and thus improve the transmission effect of the signal line.

[0090] Figure 7 A partial cross-sectional view of another packaging substrate provided in at least one embodiment of this disclosure; Figure 8 A partial cross-sectional view of another packaging substrate provided in at least one embodiment of the present disclosure; Figure 9 A partial cross-sectional view of yet another packaging substrate provided in at least one embodiment of this disclosure; Figure 10 This is a partial cross-sectional view of another packaging substrate provided in at least one embodiment of the present disclosure.

[0091] For example, refer to Figure 7At least one signal line 15 includes a first signal segment 111, a second signal segment 112, and a third signal segment 113. At least two routing layers 12 include a first routing layer 121 and a second routing layer 122. The first signal segment 111 and the second signal segment 112 are both located on the first routing layer 121 and are spaced apart. The third signal segment 113 is located on the second routing layer 122.

[0092] For example, refer to Figure 7 The via 18 includes a first via 181 and a second via 182. The pad 17 includes a first pad 171 and a second pad 172. The first signal segment 111 and the third signal segment 113 are electrically connected through the first via 181 and the first pad 171. The second signal segment 112 and the third signal segment 113 are electrically connected through the second via 182 and the second pad 172.

[0093] For example, refer to Figure 7 The first routing layer 121 and the second routing layer 122 can be adjacent routing layers, with a reference layer 11 disposed between them. The first signal segment 111, the second signal segment 112, and the third signal segment 113 are distributed in different routing layers 12. The first pad 171 includes two parts located at both ends of the first connecting via 181 and electrically connected through the first connecting via 181. These two parts are located in the first routing layer 121 and the second routing layer 122, respectively. The part located in the first routing layer 121 is connected to one end of the first signal segment 111, and the other part located in the second routing layer 122 is connected to one end of the third signal segment 113. Thus, the connection between the first signal segment 111 located in the first routing layer 121 and the third signal segment 113 located in the second routing layer 122 is achieved. Similarly, the connection between the second signal segment 112 and the third signal segment 113 can be achieved through the second connecting via 182.

[0094] For example, refer to Figure 7 Near the first and second connection vias 181 and 182, reference vias 19 are also provided. One reference pad 20 connected to the reference via 19 is located in the reference layer 11, and the other reference pad 20 is located in the routing layer 122. The reference pad 20 in the routing layer 122 and the pad connected to the connection via 18 are located on the same routing layer and are adjacent to each other. This helps to increase the coupling capacitance between the reference via 19 and the connection via 18, thereby reducing the characteristic impedance of the signal line 15. For example, the number and arrangement of the reference vias 19 can be adjusted according to actual design requirements, and the embodiments of this disclosure are not limited in this regard. This arrangement can reduce the characteristic impedance of the signal line 15, thereby improving the signal transmission effect.

[0095] For example, refer to Figure 7The orthographic projections of the first signal segment 111, the second signal segment 112, and the third signal segment 113 on the substrate 10 do not overlap. The first signal segment 111, the second signal segment 112, and the third signal segment 113 are sequentially connected through the first connecting via 181 and the second connecting via 182, thereby forming a signal path from the end of the first signal segment 111 away from the second signal segment 112, through the third signal segment 113, and then to the end of the second signal segment 112 away from the first signal segment 111. At this time, this path can be used as a single signal path to realize signal transmission.

[0096] For example, refer to Figure 8 The orthographic projection of the third signal segment 113 on the substrate 10 at least partially overlaps with the orthographic projection of at least one of the first signal segment 111 and the second signal segment 112 on the substrate 10.

[0097] For example, refer to Figure 8 The third signal segment 113 may include a portion located between the second pad 172 and the first pad 171, and another portion located on the second pad 172 away from the first pad 171. At this time, the orthographic projection of the third signal segment 113 on the substrate 10 at least partially overlaps with the orthographic projection of the second signal segment 112 on the substrate 10.

[0098] For example, refer to Figure 8 This can form a signal path from the end of the first signal segment 111 away from the second signal segment 112, through the first connecting via 181 to the portion of the third signal segment 113 located between the second pad 172 and the first pad 171, and then through the second connecting via 182 to the end of the second signal segment 112 away from the first signal segment 111; and another signal path from the end of the first signal segment 111 away from the second signal segment 112, through the first connecting via 181 to the portion of the third signal segment 113 located between the second pad 172 and the first pad 171, and then through the second pad 172 to the end of the third signal segment 113 away from the first signal segment 111.

[0099] For example, refer to Figure 8 The third signal segment 113 may also include a portion of the first pad 171 located away from the second pad 172 and a portion located between the second pad 172 and the first pad 171. In this case, the orthographic projection of the first signal segment 111 on the substrate 10 and the orthographic projection of the third signal segment 113 on the substrate 10 at least partially overlap.

[0100] For example, refer to Figure 8At this time, a signal path can be formed from one end of the first signal segment 111 away from the second signal segment 112, through the first connecting via 181 to a portion of the third signal segment 113 located on the first pad 171 away from the second pad 172, and then through the second connecting via 182 to one end of the second signal segment 112 away from the first signal segment 111; and another signal path can be formed from one end of the third signal segment 113 away from the second signal segment 112, through the first pad 171 to a portion of the third signal segment 113 located between the second pad 172 and the first pad 171, and then through the second connecting via 182 to one end of the second signal segment 112 away from the first signal segment 111.

[0101] For example, refer to Figure 8 The third signal segment 113 may include a portion of the first pad 171 located away from the second pad 172, a portion located between the second pad 172 and the first pad 171, and another portion of the second pad 172 located away from the first pad 171. At this time, the orthographic projections of the first signal segment 111 and the second signal segment 112 on the substrate 10 at least partially overlap with the orthographic projections of the third signal segment 113 on the substrate 10.

[0102] For example, refer to Figure 8 This can form a signal path that runs from the end of the first signal segment 111 away from the second signal segment 112, through the first connecting via 181 to a portion of the third signal segment 113 located between the second pad 172 and the first pad 171, and then through the second connecting via 182 to the end of the second signal segment 112 away from the first signal segment 111; another signal path runs from the end of the third signal segment 113 away from the second signal segment 112, through the first pad 171, through the second connecting via 182 into the second signal segment 112, and finally flows to the end of the second signal segment 112 away from the first signal segment 111; and yet another signal path runs directly from the end of the third signal segment 113 away from the second signal segment 112, through the first pad 171 and the second pad 172, and then flows to the end of the third signal segment 113 away from the first signal segment 111.

[0103] This configuration reduces the characteristic impedance of signal line 15 while increasing the capacitance of the transmission line, which is beneficial to improving the signal transmission effect of signal line 15.

[0104] For example, refer to Figure 9At least one signal line 15 includes a first signal line segment 114 and a second signal line segment 115, and at least two routing layers 12 include a first routing layer 123 and a second routing layer 124. The first signal line segment 114 is located in the first routing layer 123, and the second signal line segment 115 is located in the second routing layer 124. The orthographic projection of the second signal line segment 115 on the substrate 10 falls into the orthographic projection of the first signal line segment 114 on the substrate 10. The first signal line segment 114 and the second signal line segment 115 are electrically connected through at least one connection via 18 and at least one pad 17.

[0105] For example, refer to Figure 9 The first routing layer 123 and the second routing layer 124 can be adjacent routing layers 12, with a reference layer in between, but not limited to this.

[0106] For example, refer to Figure 9 The second signal segment 115 may include a portion located between the second pad 172 and the first pad 171. In this case, a signal path can be formed from the end of the first signal segment 114 furthest from the second connection via 182, through the first connection via 181 into the second signal segment 115, and finally through the second connection via 182 to the end of the first signal segment 114 furthest from the first connection via 181; and another signal path from the end of the first signal segment 114 furthest from the second connection via 182, through the first pad 171 and the second pad 172, directly to the end of the first signal segment 114 furthest from the first connection via 181.

[0107] For example, refer to Figure 9The third signal segment 115 may also include a portion located between the second pad 172 and the first pad 171, and a portion located on the first pad 171 away from the second pad 172. In this case, a signal path can be formed from the end of the first signal segment 114 away from the second connection via 182, through the first connection via 181, into the portion of the second signal segment 115 located between the second pad 172 and the first pad 171, and finally through the second connection via 182 to the end of the first signal segment 114 away from the first connection via 181; another signal path flows directly from the end of the first signal segment 114 away from the second connection via 182, through the first pad 171 and the second pad 172, to the end of the first signal segment 114 away from the first connection via 181; and yet another signal path flows from the second signal segment... One end of the second signal segment 115 away from the second connection via 182 enters the first signal segment 114 through the first connection via 181, and finally flows out of the first signal segment 114 away from the first connection via 181 through the second pad 172; and another signal path from the end of the second signal segment 115 away from the second connection via 182 through the first pad 171 to a portion of the second signal segment 115 located between the second pad 172 and the first pad 171, and then enters the first signal segment 114 through the second connection via 182, and finally flows out of the end of the first signal segment 114 away from the first connection via 181.

[0108] For example, refer to Figure 9 The third signal segment 115 may also include a portion located between the second pad 172 and the first pad 171, and a portion located on the second pad 172 away from the first pad 171. For example, the third signal segment 115 may also include a portion located between the second pad 172 and the first pad 171, a portion located on the first pad 171 away from the second pad 172, and a portion located on the second pad 172 away from the first pad 171. Thus, various different forms of signal paths can be formed. Detailed descriptions of the signal paths are similar to the principles in the above embodiments and will not be repeated here.

[0109] Of course, for reference Figure 9 The first signal segment 114 and the second signal segment 115 may include only one connecting via 18, or the first signal segment 114 and the second signal segment 115 may include three or more connecting vias 18, thereby forming a signal path different from that in the above embodiments. The embodiments of this disclosure do not limit the number of connecting vias 18 between the first signal segment 114 and the second signal segment 115, and can be determined according to design requirements.

[0110] Therefore, while reducing the characteristic impedance of signal line 15, various signal path forms can be achieved according to the multiple arrangement methods of multiple signal line segments, so as to increase the capacitance of the transmission line and improve the signal transmission effect of signal line 15.

[0111] For example, refer to Figure 10 There is at least one routing layer between the first routing layer 125 and the second routing layer 126. For example... Figure 10 As shown, at least one routing layer also includes routing layer 127.

[0112] For example, refer to Figure 10 At least one signal line 15 includes a first signal segment 116 and a second signal segment 117. The first signal segment 116 is located in the first routing layer 125, and the second signal segment 117 is located in the second routing layer 126. The first signal segment 116 and the second signal segment 117 are connected by two connecting vias 18 to form diverse signal paths (see the relevant descriptions of the above embodiments for different signal path forms). Compared to setting the first routing layer 125 and the second routing layer 126 as adjacent routing layers, the maximum size of the connecting via 18 in the first direction Z is increased when there is at least one routing layer between the first routing layer 125 and the second routing layer 126. This allows it to be used to connect multiple signal segments that are far apart in the first direction Z, thereby enriching the application scenarios of signal transmission lines and optimizing the space through different routing forms of multiple signal segments.

[0113] For example, the number of routing layers between the first routing layer 125 and the second routing layer 126 can be determined according to actual design requirements, and the embodiments of this disclosure do not limit this.

[0114] For example, refer to Figure 7 In the package substrate 01, along the second direction X, the maximum size K1 of the reference layer 11 located between two adjacent wiring layers 12 is at least 3-4 times the length K2 of at least one signal line segment 16 in the two adjacent wiring layers 12.

[0115] For example, refer to Figure 7 Multiple reference layers 11 and multiple trace layers 12 are stacked together, and at least one end of the reference via 19 is electrically connected to the reference layer 11. Therefore, in the second direction X, the reference layer 11 should have a relatively long dimension to accommodate the placement of the reference via 19, thereby forming a good signal return path and improving the transmission effect of the signal line.

[0116] For example, along the second direction X, the maximum size K1 of the reference layer 11 located between two adjacent routing layers 12 can be 3-3.5 times the length K2 of at least one signal segment 16 in the two adjacent routing layers 12. For example, the aforementioned size can be 3.4-3.8 times. For example, the aforementioned size can be 3.6-3.9 times, but is not limited to these. For example, the reference layer 11 can be laid out as a whole to allow for flexible arrangement of reference vias 19 near each connecting via 18 according to design requirements.

[0117] Another embodiment of this disclosure provides an electronic device including any of the above-described packaging substrates. The electronic device provided in this disclosure designs the signal lines located in the packaging substrate by configuring one signal line in one routing layer as multiple signal segments located in different routing layers, and connecting the signal segments in different layers of the same signal line through connecting vias and pads. Simultaneously, increasing the maximum pad size effectively reduces the characteristic impedance of the signal lines in the packaging substrate, thereby optimizing the signal line transmission performance and enhancing market competitiveness. For example, the packaging substrate provided in this disclosure may include signal lines with relatively low transmission rates and high characteristic impedance requirements, such as the CA (Command or Address) lines of DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), but is not limited to this. The embodiments of this disclosure do not limit the types of signal lines in the packaging substrate.

[0118] For example, the electronic device provided in the embodiments of this disclosure can be a display device, such as an organic light-emitting diode display device.

[0119] For example, the electronic device can be any product or component with a display function, such as a mobile phone, tablet computer, laptop computer, or navigator with an under-display camera; this embodiment is not limited to this.

[0120] The following points need to be explained:

[0121] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0122] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0123] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A package substrate, comprising: a substrate; a plurality of reference layers stacked along a first direction perpendicular to the substrate on the substrate; a plurality of routing layers stacked along the first direction, and one reference layer is disposed between any two adjacent routing layers, the plurality of routing layers are provided with a plurality of signal lines and a plurality of pads, at least one of the plurality of signal lines comprises a plurality of signal line segments, the plurality of signal line segments are located in at least two routing layers, and each of the plurality of signal line segments extends along a second direction, the second direction intersects the first direction; a dielectric layer located between the reference layers and the routing layers along the first direction; a connection via disposed in the dielectric layer, and signal line segments of different routing layers are electrically connected through the pads and the connection via; wherein a distance between two points with the largest distance on the edge of the normal projection of the pad on the substrate is a maximum pad size, and a ratio of the maximum pad size to a line width of the signal line segment is greater than 4.

2. The package substrate of claim 1, wherein, The plurality of signal lines comprises a first signal line and a second signal line, the first signal line and the second signal line are arranged at intervals along a third direction parallel to the substrate, the first signal line and the second signal line are insulated from each other, and the third direction intersects the second direction; the first signal line comprises a plurality of first signal sub-line segments, and the second signal line comprises a plurality of second signal sub-line segments, wherein in the same routing layer of at least one of the routing layers, the first signal sub-line segments and the second signal sub-line segments are distributed staggered along the second direction, and a normal projection of each first signal sub-line segment on a plane perpendicular to the third direction partially overlaps or does not overlap with a normal projection of the second signal sub-line segment on the plane perpendicular to the third direction.

3. The package substrate of claim 2, wherein, Among the first signal sub-line segments and the second signal sub-line segments in the same routing layer of at least one of the routing layers, a normal projection of a pad connected to the first signal sub-line segment on a plane perpendicular to the third direction does not overlap with a normal projection of a pad connected to the second signal sub-line segment on the plane perpendicular to the third direction.

4. The package substrate of claim 2, wherein, In the second direction, the plurality of first signal sub-line segments in the same routing layer are arranged at equal intervals, and the plurality of second signal sub-line segments in the same routing layer are arranged at equal intervals. 5.The package substrate of claim 1, further comprising a plurality of reference vias and a plurality of reference pads, the reference vias are disposed in the dielectric layer, the reference pads are electrically connected with the reference vias, and at least one reference pad connected with a same reference via is electrically connected with the reference layer, wherein each connection via corresponds to at least one reference via, and the reference via is configured to form a signal reflow path with the connection via.

6. The package substrate of claim 5, wherein, An area of a normal projection of one pad connected with the connection via on the substrate is greater than an area of a normal projection of one reference pad connected with the reference via on the substrate.

7. The package substrate of claim 5, wherein, A minimum distance between each connection via and its corresponding reference via is 5-25 μm.

8. The package substrate of claim 1, wherein, The at least one signal line includes a first signal line segment, a second signal line segment, and a third signal line segment, and the at least two trace layers include a first trace layer and a second trace layer, The first signal line segment and the second signal line segment are both located on the first trace layer and are spaced apart, and the third signal line segment is located on the second trace layer, The connection via includes a first connection via and a second connection via, the pad includes a first pad and a second pad, the first signal line segment and the third signal line segment are electrically connected through the first connection via and the first pad, and the second signal line segment and the third signal line segment are electrically connected through the second connection via and the second pad.

9. The package substrate of claim 8, wherein, The orthographic projection of the first signal line segment on the substrate, the orthographic projection of the second signal line segment on the substrate, and the orthographic projection of the third signal line segment on the substrate do not overlap.

10. The package substrate of claim 8, wherein, The orthographic projection of at least one of the first signal line segment and the second signal line segment on the substrate at least partially overlaps with the orthographic projection of the third signal line segment on the substrate.

11. The package substrate of claim 1, wherein, The at least one signal line includes a first signal line segment and a second signal line segment, and the at least two trace layers include a first trace layer and a second trace layer; The first signal line segment is located on the first trace layer, the second signal line segment is located on the second trace layer, and the orthographic projection of the second signal line segment on the substrate falls within the orthographic projection of the first signal line segment on the substrate, The first signal line segment and the second signal line segment are electrically connected through at least one connection via and at least one pad.

12. The package substrate of any one of claims 8-11, wherein, The first trace layer and the second trace layer are adjacent trace layers.

13. The package substrate of any one of claims 8-11, wherein, There is at least one trace layer between the first trace layer and the second trace layer.

14. The package substrate of claim 7, wherein, The distance between the two points with the maximum distance on the edge of the orthographic projection of the reference pad on the substrate is a maximum reference pad size, and the maximum pad size is 1.1-3.5 times the maximum reference pad size.

15. The package substrate of claim 5, wherein, The at least one reference via corresponding to each connection via includes a first reference via and a second reference via, and the orthographic projection of the first reference via and the second reference via on the substrate is symmetrically distributed with respect to a plane extending along the second direction and passing through the center of the connection via.

16. The package substrate of claim 1, wherein, In the second direction, the maximum size of the reference layer between the adjacent two trace layers is at least 3-4 times the length of at least one signal line segment in the adjacent two trace layers.

17. An electronic device comprising the package substrate of any one of claims 1-16.

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