A hybrid symmetrical five-level inverter and its control method and inverter device

Abstract

This invention discloses a SiC / Si hybrid symmetrical five-level inverter. Each phase topology of the inverter consists of a three-level DC / DC converter and an H-bridge inverter circuit. The high-frequency module is a three-level DC / DC circuit structure composed of low-voltage high-frequency SiC power transistors S1 to S4, and the high-voltage module is an H-bridge inverter circuit composed of high-voltage low-frequency Si power transistors S5 to S8. The invention also discloses its control method and inverter equipment. This solves the contradiction between the device withstand voltage and the switching frequency, and at the same time greatly reduces the cost of the five-level circuit.

Description

Technical Field

[0001] This invention belongs to the field of power electronic equipment technology, and relates to inverters, particularly to a SiC / Si hybrid symmetrical five-level inverter, as well as its control method and inverter equipment. Background Technology

[0002] The five-level topology, which is widely used in industry today, faces the challenge of a sharp increase in the number of clamping devices and difficulty in balancing the midpoint voltage.

[0003] In order to significantly improve the equivalent switching frequency, the present invention proposes a hybrid multilevel topology by organically combining different multilevel topologies. Summary of the Invention

[0004] One of the objectives of this invention is to provide a SiC / Si hybrid symmetrical five-level inverter topology.

[0005] The technical solution adopted by this invention to solve its technical problem is: a SiC / Si hybrid symmetrical five-level inverter, including a high-frequency module and a high-voltage module; the high-frequency module is a three-level DC / DC circuit structure, and all power transistors used are SiC power transistors, including SiC power transistors S1 to S4 connected in series. The drain of power transistor S1 is connected to the positive terminal of the first capacitor C1 on the DC bus side. The connection between the collector of power transistor S2 and the drain of power transistor S3 is connected to the connection between the first capacitor C1 and the second capacitor C2 on the DC bus side. The collector of power transistor S4 is connected to the negative terminal of the second capacitor C2; the high-voltage module... The block is an H-bridge inverter circuit, using Si power transistors, including Si power transistors S5 to S8. Power transistors S5 and S7 are connected in series, and power transistors S6 and S8 are connected in series. The collectors of power transistors S5 to S6 are connected to the power transistors S1 to S2, and the emitters of power transistors S7 to S8 are connected to the power transistors S3 to S4. Power transistors S1 and S2 are complementary in conduction, power transistors S3 and S4 are complementary in conduction, power transistors S5 and S7 are complementary in conduction, and power transistors S6 and S8 are complementary in conduction. Each SiC power transistor and each Si power transistor is connected in anti-parallel with a fast recovery diode.

[0006] The second objective of this invention is to provide a control method for a SiC / Si hybrid symmetrical five-level inverter, which adjusts the switching on and off of each Si power transistor in the high-voltage module according to the fundamental frequency required by the inverter, and controls the switching on and off of each SiC power transistor in the high-frequency module through dual-carrier phase shift control, including the following steps:

[0007] When the reference fundamental voltage is greater than zero, power transistors S5 and S8 are turned on while power transistors S6 and S7 are turned off; otherwise, power transistors S5 and S8 are turned off while power transistors S6 and S7 are turned on.

[0008] When the reference modulation voltage is greater than zero, power transistors S5 and S8 are turned on; otherwise, they are turned off. When the reference modulation voltage is less than zero, power transistors S6 and S7 are turned on; otherwise, they are turned off.

[0009] Furthermore, the carrier voltage is a continuous waveform with a phase difference of half a cycle. When the reference modulation voltage is greater than the first triangular carrier voltage, power transistor S1 is turned on and power transistor S2 is turned off; otherwise, power transistor S1 is turned off and power transistor S2 is turned on. When the reference modulation voltage is greater than the second carrier voltage, power transistor S3 is turned on and power transistor S4 is turned off; otherwise, power transistor S3 is turned on and power transistor S4 is turned off.

[0010] Furthermore, during the positive half-cycle of the reference voltage, power transistors S5 and S8 remain on, while the SiC power transistors S1 to S4 of the high-frequency module continuously switch on and off. When the DC side voltage is 2E, the output level is 2E, E, and 0. During the negative half-cycle of the reference voltage, power transistors S6 and S7 remain on, while the SiC power transistors S1 to S4 of the high-frequency module continuously switch on and off. When the DC side voltage is 2E, the output level is -2E, -E, and 0.

[0011] The third objective of this invention is to provide an inverter device, including the above-mentioned hybrid symmetrical five-level inverter.

[0012] Compared with the prior art, the beneficial effects of the present invention are:

[0013] 1. In this invention, the devices in the high-voltage unit form an H-bridge circuit. The H-bridge operates in a bipolar modulation state, while the preceding high-frequency unit is a three-level DC / DC converter. The highest output voltage is the voltage of all bus lines. Therefore, it can be known that the maximum static voltage that the silicon devices in the subsequent high-voltage unit can withstand should be the voltage of all bus lines.

[0014] 2. The devices in the high-frequency unit of this invention need to be turned on and off within the carrier cycle to realize the PWM modulation strategy. That is, the switching frequency of the devices in the front-end high-frequency unit is the carrier frequency of the topology control, i.e., the PWM frequency. The H-bridge circuit of the subsequent high-voltage unit is responsible for the polarity modulation of the output voltage. It only needs to operate once per fundamental cycle. That is, the switching frequency of the devices in the high-frequency unit is the fundamental frequency of the output.

[0015] 3. The devices in the high-frequency unit of this invention need to operate at a higher switching frequency of the PWM frequency, but only need to withstand one-quarter of the bus voltage. The devices in the subsequent high-voltage unit need to withstand the full bus voltage, but only need to switch at the fundamental frequency. That is, the topology converter separates the requirements for the withstand voltage level and the switching frequency level of the devices, so that the price advantage of silicon devices and the performance advantage of SiC devices can be utilized in different circuit units respectively, thereby increasing the inverter switching frequency while suppressing costs. Attached Figure Description

[0016] Figure 1 This is the topology of the inverter of the present invention. Detailed Implementation

[0017] The present disclosure will be further described below with reference to the accompanying drawings and embodiments.

[0018] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this disclosure. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

[0019] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0020] Where there is no conflict, the embodiments and features described herein can be combined with each other. Example 1

[0021] Reference Figure 1 As shown, the present invention discloses a SiC / Si hybrid symmetrical five-level inverter, which includes a high-frequency module and a high-voltage module; both the high-frequency module and the high-voltage module include multiple power transistors.

[0022] The high-frequency module is a three-level DC / DC circuit structure, and all the power transistors used are SiC power transistors, including SiC power transistors S1 to S4 connected in series. The drain of power transistor S1 is connected to the positive terminal of the first capacitor C1 on the DC bus side. The connection between the collector of power transistor S2 and the drain of power transistor S3 is connected to the connection between the first capacitor C1 and the second capacitor C2 on the DC bus side. The collector of power transistor S4 is connected to the negative terminal of the second capacitor C2.

[0023] The high-voltage module is an H-bridge inverter circuit, using Si power transistors, including Si power transistors S5 to S8. Power transistors S5 and S7 are connected in series, and power transistors S6 and S8 are connected in series. The collectors of power transistors S5 to S6 are connected to the lines between power transistors S1 and S2, and the emitters of power transistors S7 to S8 are connected to the lines between power transistors S3 and S4. Power transistors S1 and S2 are complementary in conduction, as are power transistors S3 and S4, S5 and S7, and S6 and S8. Each SiC power transistor and each Si power transistor is connected in anti-parallel to a fast recovery diode. The SiC power transistors are silicon carbide metal-oxide-semiconductor field-effect transistors.

[0024] like Figure 1 As shown, the single-phase five-level inverter has a first capacitor C1 and a second capacitor C2 on the upper and lower sides of the DC bus. These two bus capacitors are shared by the three-phase bridge arms. Each bridge arm contains two DC capacitors Cf and eight power transistors. All power transistors are connected in anti-parallel to a fast recovery diode. The high voltage operates in bipolar modulation mode, meaning that both S5 and S8 are simultaneously turned on. Each phase bridge arm outputs five voltage levels: 2E, E, 0, -E, and -2E. Levels E, 0, and -E all have redundant switching states. The inverter switching state table is shown below. 1 indicates on, and 0 indicates off.

[0025] .

[0026] As shown in Table 1, when the output level is positive, both power transistors S5 and S8 are in the on state; when the output level is negative, both power transistors S5 and S8 are in the off state. Power transistors S1 to S4 frequently switch between on and off. To further improve the power density and efficiency of the system, SiC MOSFET devices are considered.

[0027] The present invention has the following outstanding advantages.

[0028] 1. It has a high number of output levels, good harmonic performance, and high equivalent switching frequency, which can significantly improve the fundamental frequency of the output voltage, making it suitable for ultra-high speed motor drive applications.

[0029] 2. High voltage level: When the output phase voltage is nine levels, existing switching devices can be used for motors of 3kV and below.

[0030] 3. This circuit topology achieves the integration and optimized utilization of novel SiC devices and traditional silicon-based devices. High-frequency units operate under high-frequency, low-voltage stress conditions, allowing the use of low-voltage, high-speed SiC devices to reduce switching losses. However, replacing all units with higher-performance SiC devices would result in excessively high costs per device, hindering widespread adoption. Therefore, this circuit topology fully leverages the advantages of both types of devices, achieving higher system efficiency while simultaneously reducing costs.

[0031] The five-level inverter of this invention consists of a three-level DC / DC converter and an H-bridge circuit. The DC / DC converter only needs to be composed of high-frequency devices with low withstand voltage (such as SiC MOSFETs), and the H-bridge circuit can be composed of low-frequency devices with high withstand voltage (such as high-voltage IGBTs). This solves the contradiction that it is difficult to meet the device withstand voltage and switching frequency at the same time. Example 2

[0032] This invention discloses a control method for a SiC / Si hybrid symmetrical five-level inverter, which adjusts the on / off state of each Si power transistor in the high-voltage module according to the fundamental frequency required by the inverter, and controls the on / off state of the SiC power transistor in the high-frequency module through dual carrier phase shift control, including the following steps.

[0033] When the reference fundamental voltage is greater than zero, power transistors S5 and S8 are turned on while power transistors S6 and S7 are turned off; otherwise, power transistors S5 and S8 are turned off while power transistors S6 and S7 are turned on.

[0034] The carrier voltage is a continuous waveform with a phase difference of half a cycle. When the reference modulation voltage is greater than the first triangular wave voltage, power transistor S1 is turned on and power transistor S2 is turned off; otherwise, power transistor S1 is turned off and power transistor S2 is turned on. When the reference modulation voltage is greater than the second carrier voltage, power transistor S3 is turned on and power transistor S4 is turned off; otherwise, power transistor S3 is turned on and power transistor S4 is turned off.

[0035] When the reference modulation voltage is greater than zero, power transistors S5 and S8 are turned on; otherwise, they are turned off. When the reference modulation voltage is less than zero, power transistors S6 and S7 are turned on; otherwise, they are turned off.

[0036] During the positive half-cycle of the reference voltage, power transistors S5 and S8 remain on, while the SiC power transistors S1 to S4 of the high-frequency module continuously turn on and off. When the DC side voltage is 2E, the output level is 2E, E, and 0. During the negative half-cycle of the reference voltage, power transistors S6 and S7 remain on, while the SiC power transistors S1 to S4 of the high-frequency module continuously turn on and off. When the DC side voltage is 2E, the output level is -2E, -E, and 0.

[0037] Third-generation wide-bandgap semiconductor devices, represented by SiC, have promising application prospects. Compared with traditional Si-based semiconductors, SiC devices have a wider bandgap, higher electron mobility, higher breakdown field strength, and higher melting point temperature, and the switching speed can be increased by 5 to 10 times. Example 3

[0038] An inverter device includes the aforementioned hybrid symmetrical five-level inverter.

[0039] This invention achieves the combination and optimized utilization of wide-bandgap semiconductor devices and traditional silicon-based devices. The high-frequency unit operates under high-frequency, low-voltage stress conditions, allowing the use of low-voltage, high-speed SiC / GaN devices to reduce switching losses; the high-voltage unit operates under high-voltage, fundamental-frequency conditions, allowing the use of high-voltage, low-on-drop silicon-based devices to reduce conduction losses. Therefore, this circuit topology can fully utilize the advantages of both types of devices, resulting in higher system efficiency.

[0040] The above embodiments are merely illustrative of the principles and effects of the present invention, as well as some of the application examples. For those skilled in the art, various modifications and improvements can be made without departing from the inventive concept of the present invention, and these all fall within the protection scope of the present invention.

Claims

1. A control method for a hybrid symmetrical five-level inverter, characterized in that, The five-level inverter includes a high-frequency module and a high-voltage module. The high-frequency module includes SiC power transistors S1 to S4 connected in series. The drain of power transistor S1 is connected to the positive terminal of the first capacitor C1 on the DC bus side. The connection between the source of power transistor S2 and the drain of power transistor S3 is connected to the connection between the first capacitor C1 and the second capacitor C2 on the DC bus side. The drain of power transistor S4 is connected to the negative terminal of the second capacitor C2. The high-voltage module includes Si power transistors S5 to S8. Power transistor S5 is connected in series with power transistor S7. Transistor S6 is connected in series with power transistor S8. The collectors of power transistors S5-S6 are connected to the lines between power transistors S1-S2. The emitters of power transistors S7-S8 are connected to the lines between power transistors S3-S4. Power transistors S1 and S2 are complementary in conduction; power transistors S3 and S4 are complementary in conduction; power transistors S5 and S7 are complementary in conduction; and power transistors S6 and S8 are complementary in conduction. Each SiC power transistor and each Si power transistor is connected in anti-parallel with a fast recovery diode. The emitters of power transistors S5 and S6 serve as the output. The process includes the following steps: When the reference fundamental voltage is greater than zero, power transistors S5 and S8 are turned on while power transistors S6 and S7 are turned off; otherwise, power transistors S5 and S8 are turned off while power transistors S6 and S7 are turned on. When the reference modulation voltage is greater than zero, power transistors S5 and S8 are turned on; otherwise, they are turned off. When the reference modulation voltage is less than zero, power transistors S6 and S7 are turned on; otherwise, power transistors S6 and S7 are turned off. The carrier voltage is a continuous waveform with a phase difference of half a cycle. When the reference modulation voltage is greater than the first triangular wave voltage, power transistor S1 is turned on and power transistor S2 is turned off. Otherwise, power transistor S1 is turned off and power transistor S2 is turned on; when the reference modulation voltage is greater than the second carrier voltage, power transistor S3 is turned on and power transistor S4 is turned off, otherwise power transistor S3 is turned on and power transistor S4 is turned off; during the positive half-cycle of the reference voltage, power transistors S5 and S8 remain on, and power transistors S1 to S4 are continuously turned on and off; during the negative half-cycle of the reference voltage, power transistors S6 and S7 remain on, and power transistors S1 to S4 are continuously turned on and off.

2. An inverter device, characterized in that, This includes a hybrid symmetrical five-level inverter controlled by the control method described in claim 1.

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