Network node device of local area network and operation method thereof

Abstract

The present disclosure relates to enhancing Ethernet timestamps over RGMII using existing DLLs. A network node device of a regional network includes: a physical layer (PHY) circuit configured to send and receive data frames via a communication link of the communication network; a medium access layer (MAC) circuit; a receiving interface between the PHY circuit and the MAC circuit; and a timestamp circuit. The receiving interface includes a receiving clock signal and a DLL. The timestamp circuit is configured to use the DLL and a local clock signal of the network node to generate a plurality of sampling signals derived from the receiving clock signal, and to use the plurality of sampling signals to generate a timestamp offset. The timestamp offset represents an instantaneous phase offset between the local clock of the network node and the local clock of an adjacent node of the network node.

Description

Technical Field

[0001] This document relates to switching networks and, more particularly, to clock synchronization between nodes of the network. Background Art

[0002] A local area network (e.g., a wide area network (WAN) or a local area network (LAN)) consists of multiple network nodes. Information can be communicated between the nodes of the network by sending packets according to a protocol (e.g., the Ethernet protocol). A local area network can be distributed and include many network nodes that need to exchange time-sensitive data. One challenge is to synchronize the nodes in the network. A synchronized network helps ensure that the data distributed between the network nodes is the same age, or that the network nodes know the age of the data distributed between the nodes. Summary of the invention

[0003] According to one aspect of the present disclosure, a network node device of a regional network is provided, the network node device comprising: a physical layer (PHY) circuit, configured to send and receive data frames via a communication link of the communication network; a medium access layer (MAC) circuit; a receiving interface between the PHY circuit and the MAC circuit, wherein the receiving interface comprises a receiving clock signal and a delay locked loop (DLL); and a timestamp circuit, configured to: use the DLL and a local clock signal of the network node to generate a plurality of sampling signals derived from the receiving clock signal; and use the plurality of sampling signals to generate a timestamp offset, wherein the timestamp offset represents an instantaneous phase offset between the local clock of the network node and the local clock of an adjacent node of the network node.

[0004] According to another aspect of the present disclosure, a method for operating a network node of an area network is provided, the method comprising: receiving a receive clock signal of a receive interface, the receive interface being included in a receive path between a physical layer (PHY) circuit of the network node and a media access layer (MAC) circuit of the network node; generating a plurality of sampling signals from the receive clock signal using a DLL of the receive interface and a local clock signal of the network node; generating a timestamp offset using the plurality of sampling signals, wherein the timestamp offset represents an offset between a local clock of the network node and a local clock of an adjacent node of the network node; and including the timestamp offset in a timestamp of a timing frame to be sent by the network node through a process of the network node.

[0005] According to another aspect of the present disclosure, a network node device of a regional network is provided, the network node device comprising: a medium access layer (MAC) circuit; a reduced gigabit media independent interface (RGMII) operatively coupled to the MAC circuit, wherein the RGMII comprises a delay locked loop (DLL) circuit and receives a receive clock signal having a first frequency from a physical layer (PHY); and a timestamp circuit configured to: generate a delayed receive clock signal using the DLL circuit of the RGMII, and generate a slow receive clock signal having a frequency lower than the first frequency; sample the receive clock signal, the delayed receive clock signal and the slow receive clock signal to generate a plurality of sampling signals; generate a timestamp offset using the plurality of sampling signals, wherein the timestamp offset represents an offset between a local clock of the network node and a local clock of an adjacent node of the network node; and wherein the MAC circuit is configured to include the timestamp offset in a timestamp for a timing frame sent by the network node device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the accompanying drawings, which are not necessarily drawn to scale, like numbers may describe similar parts in different views. Like numbers with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed in this document by way of example and not by way of limitation.

[0007] Figure 1 A block diagram of a portion of an example of a regional network.

[0008] Figure 2 is a circuit diagram of an example of a timestamp circuit for a network node.

[0009] Figure 3 is a diagram of a sampled signal used to generate a timestamp offset.

[0010] Figure 4 is a flow diagram of an example of operating a network node of an area network.

[0011] Figure 5 is a circuit diagram of another example of a timestamp circuit for a network node.

[0012] Figure 6A-6B Signal waveforms associated with a 100Base-TX type physical layer are shown. DETAILED DESCRIPTION

[0013] As mentioned earlier, it is a challenge to make the nodes of a distributed area network work together synchronously. One way to achieve synchronization is the Precision Time Protocol (PTP). In PTP, subordinate nodes synchronize their time to the master node (GM). Subordinate nodes periodically exchange delay measurement frames to calculate network delays, and receive and forward synchronization frames from GM nodes to calculate and correct synchronization errors. These timing frames include timestamps that network nodes use to calculate propagation delays, relative local clock frequencies, and synchronization offsets. Propagation delays are used to calculate peer delays and synchronization parameters. Slave nodes can use timestamps to calculate the time difference between the GM clock and local clock of the slave node. Slave nodes can use the calculated time difference to adjust their local clocks to converge with the GM time.

[0014] The network node includes a physical layer (PHY) and a media access control layer (MAC). The specific timing of the actual timestamp sent by the network node is with respect to the internal local clock of the network node. The local clock operates the MAC and any synthetic clock hardware of the network node. Timestamped messages are received and sent on the network according to the communication clock. Depending on the specifics of the PHY, the configuration of the PHY, and the design of the board including the PTP instance, the communication clock may or may not have any common source with the local clock of the network node.

[0015] As the complexity of time-sensitive systems increases, it may be desirable to improve the accuracy of timestamping in time-sensitive or time-critical systems. For example, the network topology in a factory automation application may be a line topology with up to 64 bridges connected in a daisy-chain manner to forward time-critical control and status traffic between connected nodes. Synchronization is critical for both time-sensitive network timing and practical applications of network node management (e.g., motor control, actuators, sensors, etc.). Each bridge in the line will introduce some error to the synchronization quality, and improved timestamping can be used to reduce the impact of the error.

[0016] Improvements in timestamp accuracy for a network node are dependent on the quality of timestamps from its neighboring nodes. For example, if a network node's link neighbor timestamps transmitted frames with 40 nanosecond (40nsec) accuracy, the resulting error in calculating peer delay or synchronization acquisition time is applied to the quality of the timestamp captured locally by the network node. To maximize accuracy, increases in timestamp accuracy should be applied to improve timing accuracy relative to one or more clocks used by the PTP stack.

[0017] Figure 11 is a block diagram of a portion of an example of a regional network. The example includes two adjacent network nodes connected by a communication link (e.g., cable 102) of the network. Each network node includes a switch portion or switch and a physical layer (PHY). The PHY includes a medium dependent interface (MDI) to the communication link and sends and receives data frames via the communication link.

[0018] The network node 104 on the left includes a switch 106 and a PHY 108. The network node 110 on the right includes a switch 144 and a PHY 112. Each network node includes a transmit port (Tx port) and a receive port (Rx port). The Tx port 116 of the network node 104 uses a media access control layer MAC 118 and a reduced gigabit media independent interface (RGMII) 120 to send information to the PHY 108 in the network node 104. The PHY 108 sends information to the PHY 112 of the network node 110 over a communication link. The Rx port 122 of the network node 110 receives information via the RGMII 124 and MAC 126 of the network node 110. Information in the other direction flows from the Tx port 130 of the network node 110 to the Rx port 132 of the network node 104.

[0019] Each neighbor node uses the timestamp from another neighbor node to improve timing, and each neighbor node provides timestamps to its neighbors. Timing information included in timing frames (e.g., delayed timing frames and synchronization frames) can be used to determine the offset in the local clock of the neighboring node. The offset can be added to the timestamp to improve the accuracy of the timestamp (e.g., by being added to the least significant half byte of the timestamp). To improve timestamp accuracy, the timing of neighbors can be sampled using a gigahertz clock, but this consumes power. In order to keep power consumption low, it is desirable to keep the frequency of the clock signal low.

[0020] An improved method is to use a sampling clock generated from the receive clock signal (Rx Clk) of RGMII 124 to sample the timing of the neighboring nodes. Each neighboring node includes a timestamp circuit 134. The receive side of the switch of the network node is driven by the PHY. This includes a receive clock that is continuously driven by the PHY. The internal local clock of the network node can be 125 megahertz (125MHz). The timestamp circuit 134 uses the local internal clock to generate multiple clock samples derived from the receive clock signal of RGMII 124. Clock sampling is used to generate a timestamp offset. The timestamp offset represents the instantaneous phase offset between the local clock of the network node and the local clock of its neighboring node, which is the clock used to generate the timestamp. The timestamp offset can be included in the timing frame by the process running on the network node. For example, the MAC circuit on the transmitting side of the network node can include the timestamp offset in the timestamp of the synchronization frame sent to the neighboring node, and the neighboring node can use the timestamp to adjust its timing.

[0021] Figure 2 is the network node that generates the timestamp offset (e.g. Figure 1 1. A circuit diagram of an example of a timestamp circuit 134 of a network node 110 in FIG. 1. The timestamp circuit 134 receives a receive clock (RxClk) signal from the RGMII 124 of the network node. The RGMII 124 includes a delay locked loop circuit (DLL) 240 that generates a delayed receive clock signal RxClk_d. The delay added to RxClk has a nominal period of two nanoseconds (2nsec) and is applied to the rising and falling edges of RxClk. The RxClk and RxClk_d signals are fed to a first set of flip-flops 242 to generate a slow receive clock signal RxClk_A and a slow delayed receive clock signal RxClk_d_A. If the RxClk signal has a frequency of 125 MHz, then RxClk_A and RxClk_d_A have a reduced frequency of 62.5 MHz.

[0022] The local clock signal of the network node can have the same frequency as the RxClk signal (e.g., 125MHz). The slow signals RxClk_A and RxClk_d_A are sampled using a metastable flip-flop 244 at the rising and falling edges of the internal 125MHz clock signal. Each edge (rising and falling) on ​​the output of the metastable flip-flop 244 represents a rising edge on the input signal. The result is a sampled signal RxClk_A_samp, RxClk_A_samp_n, RxClk_d_A_samp, and RxClk_d_A_samp_n generated by the RxClk and RxClk_d signals, where "n" represents an inverted signal. The resolution of the sampled signal is 4nsec. The combination of the sampled signal with the original input and the delayed input provides an additional 2nsec resolution.

[0023] The sampled signal is used to generate a timestamp offset. The timestamp offset can be a receive timestamp offset or a transmit timestamp offset. To generate a receive timestamp offset, the sampled signal is fed to a receive timestamp offset register 246. The timestamp circuit 134 includes a logic circuit 248 that captures the states of RxClk_A_samp, RxClk_A_samp_n, RxClk_d_A_samp, and RxClk_d_A_samp_n of the next clock after detecting a receive start packet delimiter command (Rx SMD).

[0024] Capturing the state of the sampled signal in the receive timestamp offset register 246 generates a four-bit (or half-byte) code vector in the register. The value of the code vector captured in the register is the timestamp offset that can be included in the least significant half-byte of the timestamp. Both the rising and falling edges of RxClk_A and RxClk_d_A are used to calculate the timestamp offset. This generates two possible measurements for each error offset, generating eight valid code vector combinations for the four offset estimation results.

[0025] Figure 3 is a description of the sampling of the RxClk_A and RxClk_d_A signals. Figure 3 The top of the figure shows the signal waveforms RxClk, RxClk_d, RxClk_A and RxClk_d_A signals. The signal waveforms below are waveforms of the internal local clock signal of the network node for eight different error offsets of the local clock signal and the RxClk signal. Eight valid coding vector combinations corresponding to the eight different error offsets are also shown.

[0026] exist Figure 3In the lower part of the , the vertical lines descending from the RxClk and RxClk_d waveforms indicate the values ​​that will be sampled on the edge of the internal clock. These values ​​will result in sampling one of the eight encoding vectors in the timestamp offset register. Each encoding vector represents a specific alignment of the internal 125MHz clock with the receive clock input RxClk and the delayed receive clock input RxClk_d. Because the encoding vector has four bits, there are sixteen possible vector values, but only eight of the possible vectors are valid encoding vector values. The other eight values ​​are invalid. The eight valid encoding vectors are 0b0111, 0b1111, 0b1110, 0b1100, 0b1100, 0b1100, 0b1100, and 0b1100.

[0027] For example, in the figure, the lower clock pulse labeled "Vector 0b1100" represents a specific alignment of the internal local clock with the RxClk signal and the RxClk_d signal. At the rising edge 305 of the internal local clock, the signals RxClk_A and RxClk_d_A are high or "1". At the falling edge 310 of the internal local clock, RxClk_A and RxClk_d_A are low or "0". This corresponds to vector 0b1100. A comparison of the rising edge 315 of RxClk and the rising edge 305 of the internal local clock shows that the corresponding error offset of vector 0b1100 is 6-8nsec. It should be noted that the inverse vector "Vector 0b0011" is a valid vector value and also corresponds to an error offset of 6-8 nanoseconds.

[0028] Table 1 below lists eight valid code vectors, their corresponding timestamp adjustments, and eight invalid code vector values.

[0029] Table 1

[0030]

[0031]

[0032] The 4 bits of the vector represent samples of RxClk coming in at 2n second intervals. Figure 2 The organization of the flip-flops and their clocks in the circuit means that a rising edge sample is taken 8nsec before loading the timestamp offset register (246 or 250), while a falling edge flip-flop is sampled 4nsec before loading the timestamp offset register.

[0033] If the timestamp sent by the network node has a specific number of bits, the 4 bits of the vector can be the least significant 4 bits of the timestamp and can be considered as an offset relative to the high-order bits of the timestamp that captured the internal local clock. If the high-order bits of the timestamp were captured at time "t", the offset of the 4 bits of the vector is relative to time t. If the 4 bits of the vector were captured on a clock before time t, the value of the encoded vector is represented as follows:

[0034] The rising edge sample on RxClk_d_A represents RxClk at time t-2nsec.

[0035] • The rising edge sample on RxClk_A represents the state of RxClk at time t nsec.

[0036] The falling edge sample on RxClk_d_A represents the state of RxClk at time t+2nsec.

[0037] The falling edge sample on RxClk_A represents the state of RxClk at time t+4nsec.

[0038] The code vector captured in the timestamp offset register 246 can be used to generate an offset that is added to the measured timestamp to give the desired accuracy. By centering the timestamp adjustment within the error range, a practical accuracy of + / - 1 nanosecond can be achieved. The timing of the capture of the timestamp and the capture of the code vector will have the timing relationship described above.

[0039] return Figure 2 , the same mechanism can be used to measure errors in the clock of the transmission path of a network node. In order to generate a transmit timestamp offset, the sampled signal can be fed to the transmit timestamp offset register 250. The timestamp circuit 134 includes a logic circuit 252 that captures the states of the RxClk_A_samp, RxClk_A_samp_n, RxClk_d_A_samp, and RxClk_d_A_samp_n signals when a transmit start mPacket Delimiter command (Tx SMD) is detected. The transmit clock (TxClk) is not used to determine the offset because the transmit clock is generated directly from the internal local clock and has no guaranteed phase relationship with the communication transmit timing. Therefore, the offset of the internal local clock relative to the adjacent node is still derived from the RxClk and RxClk_d signals, but the offset encoding vector is captured based on the timing of the Tx SMD on the transmit path. This technique is applicable to calculating the receive or transmit timestamp offset of a 1000Base-T type PHY, regardless of whether the PHY is a clock master or clock slave node on the network link.

[0040] For completeness, Figure 4400 is a flow chart of an example of a technique for determining an improved timestamp offset of a network node. The network node includes a PHY and a switch. At block 405, the switch receives a receive clock signal from the PHY. The receive clock signal may be included in a receive interface (e.g., RGMII) of a receive path between the PHY and a MAC of the switch.

[0041] At block 410, a plurality of sampling signals are generated from a received clock signal using a local clock signal of a network node. Figure 2 As in the example of , the sampling signals RxClk_A_samp, RxClk_A_samp_n, RxClk_d_A_samp, and RxClk_d_A_samp_n may be generated from the reception clock signal RxClk.

[0042] At block 415, a timestamp offset is generated using the plurality of sampled signals. The timestamp offset represents an instantaneous phase offset between a local clock of the network node and a local clock of a neighboring node of the network node. At block 420, the MAC of the switch includes the timestamp offset in a timestamp of a synchronization frame. The timestamp may be a received timestamp sent to a neighboring node or a transmitted timestamp sent to a neighbor or a local process.

[0043] Although the techniques described herein can improve the accuracy of timestamping the receive and transmit paths of a network node to a resolution of 2 nsec, the results may depend on the sampling accuracy of the timestamping circuitry. The sampling accuracy may be a function of one or more of the timing relationships of the paths (rising and falling edges) of the RxClk and RxClk_d signals through the synchronization flip-flops 242 and 244, the quality of the internal local clock, the quality of the DLL 240, and the timing relationships of the paths (rising and falling edges) of the RxClk and RxClk_d signals.

[0044] For Figure 1 In a network node with RGMII 124, DLL 240 is available, and the receive clock RxClk and the delayed receive clock RxClk_d can be used to generate the sampling signal. For MII, the transmit clock TxClk can be obtained from PHY 112. In this case, a second DLL can be added to generate the delayed transmit clock TxClk_d, and TxClk, TxClk_d and the internal local clock can be used to generate the sampling signal and the encoding vector.

[0045] For 100Base-TX type PHYs, some modifications to the described techniques are required. There are two important differences between 1000Base-T type PHYs and 100Base-TX type PHYs; a lower clock frequency and different clocks used for the transmit and receive paths of the PHY.

[0046] The difference in frequency is equivalent to a period on the sampled signal that is several times the internal local clock sampling frequency. Therefore, some samples are around the edge and some are not. If both edges of the sampling clock fall within a period where both input signals are unchanged, it does not necessarily provide information for calculating the offset. In these cases, more information is needed to determine whether to update the timestamp offset calculation.

[0047] For a 100Base-TX type PHY, there is not enough information to determine the timestamp offset for the coded vectors 0b0000 and 0b1111. This is because there will be multiple instances of one or more of the other vectors between each edge of the sampled signal. However, these coded vectors should not be ignored because the internal local clock may indeed be running at a 2-4nsec offset from RxClk.

[0048] Figure 5 is a circuit diagram of an example of a timestamp circuit 534 that generates a timestamp offset for a network node having a 100Base-TX type PHY. The timestamp circuit 534 includes additional logic circuit 556 for tracking the value of the previous sampled vector in the timestamp offset register (246 or 250). The additional logic circuit 556 checks the status of the current sampled vector value and the previous sampled vector value. If the sampled vector value (register 246 or 250) is all 0 and the previous sampled vector value is all 1, the current vector value register (558 or 560) is set to all 0. If the sampled vector value (register 246 or 250) is all 1 and the previous sampled vector value is all 0, the current vector value register (558 or 560) is set to all 1. If the sampled vector value (register 246 or 250) is not all 0 or all 1, the current vector value register (558 or 560) is set to the sampled vector value.

[0049] Figure 6A-6B The signal waveforms of a 100Base-TX type PHY are shown for various cases of offset between the internal local clock and the RxClk_A and RxClk_d_A signals. The encoding vector values ​​corresponding to the offsets are also shown. The cases where the sample signal crosses the transition of all 0s or all 1s show the dependence on the value of the previous encoding vector.

[0050] Another difference in the 100Base-TX case is that the transmit clock TxClk and the receive clock RxClk are not related. When the PHY of the network node is a 100Base-TX type PHY, a common clock source should be used for the internal local clocks of the switch 114 and PHY 112 of the network node so that they have a fixed phase relationship. One option is to use the code vector method described herein to improve the accuracy of the timestamp on the receive path and use the internal local clock without offset adjustment for the timestamp on the transmit path.

[0051] For 10Base-T type PHY, the technology needs to be modified similar to the 100Base-TX case. Figure 5 Additional logic circuits 556, 558, 560 are used for sampling vector values ​​of 0b0000 and 0b1111. Similar to the case of 100Base TX, the coding vector is used to determine the offset to enhance the timestamp of the receive path, but not the transmit path.

[0052] For 10Base-T1L PHY, the clock scheme is similar to 100Base-T PHY and the transmit clock TxClk and receive clock RxClk are related. The coded vector technique can be used to determine the offset of the timestamp of the enhanced receive path and the offset of the timestamp of the enhanced transmit path. For the sample vector values ​​of 0b0000 and 0b1111, Figure 5 Additional logic circuits 556, 558, 560.

[0053] Additional Notes and Examples

[0054] Example 1 includes a subject matter (e.g., a network node device of a regional network), including: a physical layer (PHY) circuit configured to send and receive data frames via a communication link of the communication network; a medium access layer (MAC) circuit; a receiving interface between the PHY circuit and the MAC circuit, wherein the receiving interface includes a receiving clock signal and a delay locked loop (DLL); and a timestamp circuit. The timestamp circuit is configured to: generate a plurality of sampling signals derived from the receiving clock signal using the DLL and a local clock signal of the network node; and generate a timestamp offset using the plurality of sampling signals, wherein the timestamp offset represents an instantaneous phase offset between the local clock of the network node and the local clock of a neighboring node of the network node.

[0055] In Example 2, the subject matter of Example 1 optionally includes: a timestamp circuit configured to: generate a delayed receive clock signal and generate a slow receive clock signal having a lower frequency than the receive clock signal; sample the delayed and slow receive clock signals using a local clock of the network node to generate the multiple sampling signals; and determine the timestamp offset using the multiple sampling signals.

[0056] In Example 3, the subject matter of Example 2 optionally includes: the receiving interface is a Reduced Gigabit Media Independent Interface (RGMII), and the DLL is included in the RGMII, and the timestamp circuit is configured to generate the delayed receiving clock signal using the DLL of the RGMII.

[0057] In Example 4, the subject matter of one or both of Examples 2 and 3 optionally includes: the timestamp circuit is configured to: generate a slow delayed receive clock signal; sample the slow delayed receive clock signal, the delayed receive clock signal, and the slow delayed receive clock signal to generate the multiple sampling signals; use the multiple sampling signals to generate a coding vector; and use the coding vector to determine the timestamp offset.

[0058] In Example 5, the subject matter of Example 4 optionally includes: a timestamp offset register, and a timestamp circuit configured to detect a start frame delimiter sent by the PHY circuit and store the encoding vector in the timestamp offset register in response to detection of the start frame delimiter.

[0059] In Example 6, the subject matter of one or both of Examples 4 and 5 optionally includes: the timestamp circuit is configured to determine the timestamp offset using a current value of the encoding vector and a previous value of the encoding vector.

[0060] In Example 7, the subject matter of one or any combination of Examples 1-6 optionally includes: the timestamp circuit is configured to: detect a transmit start frame delimiter transmitted by the PHY circuit; use the multiple sampling signals of the receive clock signal to generate a transmit timestamp offset; and in response to detecting the transmit start frame delimiter, store the transmit timestamp offset.

[0061] In Example 8, the subject matter of one or any combination of Examples 1-7 optionally includes: a timestamp circuit configured to: detect a receive start frame delimiter transmitted by the PHY circuit; generate a receive timestamp offset using the multiple sampling signals of the receive clock signal; and store the receive timestamp offset in response to the detected transmit start frame delimiter.

[0062] In Example 9, the subject matter of one or any combination of Examples 1-8 may optionally include a frequency of a local clock signal of the network node being 125 MHz, and a resolution of the timestamp offset being two nanoseconds.

[0063] In Example 10, the subject matter of one or any combination of Examples 1-9 may optionally include a MAC circuit configured to include a timestamp offset in a timing frame to be sent by the network node device.

[0064] Example 11 includes subject matter (e.g., a method of operating a network node of an area network, or may be optionally combined with one or any combination of Examples 1-10 to include such subject matter, including: receiving a receive clock signal of a receive interface, the receive interface included in a receive path between a physical layer (PHY) circuit of the network node and a medium access layer (MAC) circuit of the network node; generating a plurality of sampling signals from the receive clock signal using a DLL of the receive interface and a local clock signal of the network node; using the plurality of sampling signals to generate a timestamp offset, wherein the timestamp offset represents an offset between a local clock of the network node and a local clock of a neighboring node of the network node; and including, by a process of the network node, the timestamp offset in a timestamp of a timing frame to be sent by the network node.

[0065] In Example 12, the subject matter of Example 11 optionally includes: generating a delayed receive clock signal and a slow receive clock signal; sampling the delayed and slow receive clock signals using a local clock of the network node to generate the multiple sampling signals; and determining the timestamp offset using the multiple sampling signals.

[0066] In Example 13, the subject matter of Example 12 may optionally include receiving a clock signal of a Reduced Gigabit Media Independent Interface (RGMII), and generating the delayed received clock signal using a delay locked loop (DLL) of the RGMII.

[0067] In Example 14, the subject matter of one or both of Examples 12 and 13 optionally includes generating a slow receive clock signal, a delayed receive clock signal, and a slow delayed receive clock signal; sampling the slow receive clock signal, the delayed receive clock signal, and the slow delayed receive clock signal to produce the multiple sampled signals; using the multiple sampled signals to generate a coding vector; and using the coding vector to determine a timestamp offset.

[0068] In Example 15, the subject matter of Example 14 may optionally include storing the encoding vector in response to detecting a start frame delimiter sent by the PHY circuitry to the MAC circuitry.

[0069] In Example 16, the subject matter of one or both of Examples 14 and 15 optionally includes determining the timestamp offset using a current value of the encoding vector and a previous value of the encoding vector.

[0070] In Example 17, the subject matter of one or any combination of Examples 11-16 may optionally include generating a transmit timestamp offset using a plurality of sampling signals.

[0071] In Example 18, the subject matter of one or any combination of Examples 11-17 may optionally include generating a receive timestamp offset using a plurality of sampled signals.

[0072] Example 19 includes a subject matter (e.g., a network device of a regional network), or may be optionally combined with one or any combination of Examples 1-18 to include such a subject matter, including: a medium access layer (MAC) circuit; a reduced gigabit media independent interface (RGMII) operatively coupled to the MAC circuit, wherein the RGMII includes a delay locked loop (DLL) circuit and receives a receive clock signal having a first frequency from a physical layer (PHY); and a timestamp circuit. The timestamp circuit is configured to generate a delayed receive clock signal using the DLL circuit of the RGMII and generate a slow receive clock signal having a frequency lower than the first frequency; sample the receive clock signal, the delayed receive clock signal, and the slow receive clock signal to generate a plurality of sampled signals; use the plurality of sampled signals to generate a timestamp offset, wherein the timestamp offset represents an offset between a local clock of the network node and a local clock of a neighboring node of the network node; and wherein the MAC circuit is configured to include the timestamp offset in a timestamp for a timing frame sent by the network node device.

[0073] In Example 20, the subject matter of Example 19 optionally includes: a timestamp circuit configured to generate a coding vector using the plurality of sampled signals; and determine the timestamp offset using the coding vector.

[0074] These non-limiting examples may be combined in any arrangement or combination. The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The accompanying drawings illustrate specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples". All publications, patents, and patent documents mentioned in this document are incorporated herein by reference in their entirety, as if individually incorporated by reference. If there is an inconsistency between the usage of this document and the document incorporated by reference, the usage in the incorporated reference shall be deemed to supplement the usage of this document; for irreconcilable inconsistencies, the usage in this document shall prevail.

[0075] In this document, the terms "a" or "an" are used to include one or more, independent of any other instances or uses of "at least one" or "one or more", which are common in patent documents, and unless otherwise stated, "A or B" includes "A but not B", "B but not A", and "A and B". In the appended claims, the terms "including" and "it" are used as the plain English equivalents of the respective terms "comprising" and "wherein". In addition, the terms "including" and "comprising" in the following claims are open-ended, that is, systems, devices, articles, processes including elements other than those listed after such terms in the claim are still considered to fall within the scope of the claim. In addition, in the following claims, the terms "first", "second", and "third", etc. are used merely as labels and are not intended to impose numerical requirements on their objects. The method examples described herein may be at least partially implemented by a machine or computer.

[0076] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as by a person of ordinary skill in the art when reviewing the above description. The abstract is provided to comply with the provisions of Section 1.72 (b) of Volume 37 of the Code of Federal Regulations, enabling readers to quickly determine the nature of the technical disclosure. It is submitted with an understanding that this document is not used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be grouped together to simplify the present disclosure. This should not be interpreted as an intention to make unclaimed public features essential to any claim. On the contrary, the subject matter of the present invention may be less than all the features of a particular disclosed embodiment. Therefore, the following claims are incorporated herein into the detailed description, and each claim is independently used as a separate embodiment. The scope of the present invention should be determined with reference to the appended claims and the full scope of equivalents to which these claims are entitled.

Claims

1. A network node device of a regional network, the network node device comprising: a physical layer (PHY) circuit configured to transmit and receive data frames via a communication link of the area network; Media Access Control (MAC) circuits; a receive interface between the PHY circuit and the MAC circuit, wherein the receive interface includes a receive clock signal and a delay locked loop (DLL); and The timestamp circuit is configured as follows: generating a plurality of sampled signals derived from the received clock signal using the DLL and a local clock signal of the network node; and A timestamp offset is generated using the plurality of sampled signals, wherein the timestamp offset represents an instantaneous phase offset between a local clock signal of the network node and a local clock signal of a neighboring node of the network node.

2. The network node device according to claim 1, wherein the timestamp circuit is configured as: generating a delayed receiving clock signal and generating a slow receiving clock signal having a lower frequency than the receiving clock signal; Sampling the delayed receiving clock signal and the slow receiving clock signal using a local clock signal of the network node to generate the plurality of sampled signals; and The timestamp offset is determined using the plurality of sampled signals.

3. The network node device according to claim 2, wherein the receiving interface is a Reduced Gigabit Media Independent Interface (RGMII), and the DLL is included in the RGMII; and The timestamp circuit is configured to generate the delayed receiving clock signal using the DLL of the RGMII.

4. The network node device according to claim 2, wherein the timestamp circuit is configured to: generating a slow delayed receiving clock signal; Sampling the slow receiving clock signal, the delayed receiving clock signal and the slow delayed receiving clock signal to generate the plurality of sampling signals; Using the plurality of sampled signals to generate a code vector; and The timestamp offset is determined using the code vector generated using the plurality of sampled signals.

5. The network node device according to claim 4, comprising: Timestamp offset register; and The timestamp circuit is configured to detect a start frame delimiter sent by the PHY circuit and store the encoding vector in the timestamp offset register in response to detecting the start frame delimiter.

6. The network node device of claim 4, wherein the timestamp circuit is configured to determine the timestamp offset using a current value of the encoding vector and a previous value of the encoding vector.

7. The network node device according to claim 1, wherein the timestamp circuit is configured to: detecting a transmission start frame delimiter sent by the PHY circuit; generating a transmit timestamp offset using the plurality of samples of the receive clock signal; and In response to detecting the transmit start frame delimiter, the transmit timestamp offset is stored.

8. The network node device according to claim 1, wherein the timestamp circuit is configured to: detecting a receive start frame delimiter sent by the PHY circuit; generating a receive timestamp offset using the plurality of samples of the receive clock signal; and In response to detecting the transmit start frame delimiter, the receive timestamp offset is stored.

9. The network node device according to claim 1, wherein the frequency of the local clock signal of the network node is 125 MHz and the resolution of the timestamp offset is two nanoseconds.

10. The network node device according to claim 1, wherein the MAC circuit is configured to include the timestamp offset in a timing frame to be sent by the network node device.

11. A method of operating a network node of a regional network, the method comprising: receiving a receive clock signal of a receive interface included in a receive path between a physical layer (PHY) circuit of the network node and a medium access control layer (MAC) circuit of the network node; generating a plurality of sampling signals from the receive clock signal using a delay locked loop (DLL) of the receive interface and a local clock signal of the network node; generating a timestamp offset using the plurality of sampled signals, wherein the timestamp offset represents an offset between a local clock signal of the network node and a local clock of a neighboring node of the network node; and The timestamp offset is included, by a process of the network node, in a timestamp of a timing frame to be sent by the network node.

12. The method of claim 11, wherein generating the timestamp offset comprises: generating a delayed receiving clock signal and a slow receiving clock signal; Sampling the delayed receiving clock signal and the slow receiving clock signal using a local clock signal of the network node to generate the plurality of sampled signals; and The timestamp offset is determined using the plurality of sampled signals.

13. The method according to claim 12, wherein receiving the receive clock signal of the receive interface comprises receiving a clock signal of a Reduced Gigabit Media Independent Interface (RGMII); and The generating the delayed receiving clock signal includes generating the delayed receiving clock signal using a delay locked loop (DLL) of the RGMII.

14. The method according to claim 12, wherein generating the delayed version and the slow version of the receive clock signal comprises generating a slow receive clock signal, a delayed receive clock signal, and a slow delayed receive clock signal; wherein the sampling comprises sampling the slow receiving clock signal, the delayed receiving clock signal and the slow delayed receiving clock signal to generate the plurality of sampling signals; and using the plurality of sampling signals to generate a coding vector; and Determining the timestamp offset includes determining the timestamp offset using the encoding vector generated using the plurality of sampling signals.

15. The method of claim 14, wherein generating the encoding vector comprises storing the encoding vector in response to detecting a start frame delimiter sent by the PHY circuitry to the MAC circuitry.

16. The method of claim 14, wherein determining the timestamp offset comprises determining the timestamp offset using a current value of the encoding vector and a previous value of the encoding vector.

17. The method of claim 11, wherein generating the timestamp offset comprises generating a transmit timestamp offset using the plurality of sampled signals.

18. The method of claim 11, wherein generating the timestamp offset comprises generating a receive timestamp offset using the plurality of sampled signals.

19. A network node device of a regional network, the network node device comprising: Media Access Control (MAC) circuits; a Reduced Gigabit Media Independent Interface (RGMII) operatively coupled to the MAC circuitry, wherein the RGMII includes a delay locked loop (DLL) circuit and receives a receive clock signal having a first frequency from a physical layer (PHY); and The timestamp circuit is configured as: generating a delayed receiving clock signal using the DLL circuit of the RGMII, and generating a slow receiving clock signal having a frequency lower than the first frequency; Sampling the receiving clock signal, the delayed receiving clock signal and the slow receiving clock signal to generate a plurality of sampling signals; generating a timestamp offset using the plurality of sampled signals, wherein the timestamp offset represents an offset between a local clock signal of the network node and a local clock signal of a neighboring node of the network node; and The MAC circuit is configured to include the timestamp offset in a timestamp for a timing frame sent by the network node device.

20. The network node device according to claim 19, wherein the timestamp circuit is configured to: generating a code vector using the plurality of sampled signals; and The timestamp offset is determined using the code vector generated using the plurality of sampled signals.

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