Semiconductor structure and method of manufacturing the same

Abstract

This application relates to a semiconductor structure and its fabrication method. The semiconductor structure includes: a substrate; a plurality of spaced-apart capacitor contact structures formed on the substrate; an isolation structure; the isolation structure is located on the substrate and between adjacent capacitor contact structures; the top surface of the isolation structure is not higher than the top surface of the capacitor contact structures; and an isolation groove; the isolation groove extends from the top surface of the isolation structure into the isolation structure, and there is a gap between the isolation groove and the capacitor contact structures. By providing the isolation groove extending from the top surface of the isolation structure into the isolation structure, this semiconductor structure avoids the problem of mutual interference and short circuits caused by oxidized capacitor contact material remaining between adjacent capacitor contact structures. Subsequently formed capacitors will not interfere with each other. Therefore, it can improve the production yield and reliability of capacitors, thereby improving the production yield and electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and its preparation method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, consisting of many repeating memory cells. Each memory cell typically includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line.

[0003] In dynamic random access memory (DRAM), capacitors are electrically connected to landing pads via their lower electrodes, forming access paths with the transistor drain. As memory device integration becomes increasingly smaller, capacitor sizes shrink, and consequently, the size of the landing pads also decreases. However, during the fabrication process, byproducts of the landing pad material from dry etching and acid washing remain between adjacent landing pads, causing them to interfere with each other and create short circuits. Subsequent capacitors formed on these residues also interfere with each other, leading to reduced memory device production yield and impacting the device's reliability and electrical performance. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the shortcomings of existing technologies.

[0005] On one hand, according to some embodiments, this application provides a semiconductor structure, including:

[0006] A substrate; a plurality of spaced-apart capacitor contact structures are formed on the substrate;

[0007] An isolation structure is located on the substrate and between adjacent capacitive contact structures; the top surface of the isolation structure is not higher than the top surface of the capacitive contact structure.

[0008] An isolation groove; the isolation groove extends from the top surface of the isolation structure into the isolation structure, and there is a gap between the isolation groove and the capacitor contact structure.

[0009] In some embodiments, the plurality of capacitive contact structures are arranged in a multi-row, multi-column array, with the plurality of capacitive contact structures in the same column arranged at intervals along a first direction, and the plurality of capacitive contact structures in the same row arranged at intervals along a second direction, the second direction intersecting the first direction;

[0010] The isolation groove includes a plurality of first isolation grooves arranged at intervals, the first isolation grooves extending along the first direction and located between two adjacent columns of the capacitor contact structures.

[0011] In some embodiments, the isolation groove includes a plurality of spaced-apart second isolation grooves, the second isolation grooves extending along the second direction and located between two adjacent rows of the capacitive contact structures, and penetrating the plurality of first isolation grooves.

[0012] In some embodiments, the semiconductor structure further includes a plurality of capacitor structures located on the substrate and in contact with the capacitor contact structures one by one.

[0013] In some embodiments, the semiconductor structure further includes a support structure, the support structure including a first support layer, a second support layer and a third support layer stacked sequentially from bottom to top; the support structure is provided with a plurality of capacitor holes penetrating the first support layer, the second support layer and the third support layer, the capacitor holes are provided one-to-one with the capacitor contact structure, and the capacitor holes expose the capacitor contact structure;

[0014] The isolation groove also penetrates the first support layer along the thickness direction;

[0015] The capacitor structure includes:

[0016] The lower electrode is located on the side wall and bottom of the capacitor hole, and is connected to the first support layer, the second support layer and the third support layer, and is in contact with the capacitor contact structure.

[0017] A capacitor dielectric layer; the capacitor dielectric layer is located on the surface of the lower electrode and within the isolation groove;

[0018] Upper electrode; the upper electrode is located on the surface of the capacitor dielectric layer.

[0019] In some embodiments, a gap is further provided between the upper electrodes; the capacitor structure further includes:

[0020] A conductive layer is filled in the gap.

[0021] On the other hand, according to some embodiments, this application also provides a method for fabricating a semiconductor structure, including:

[0022] Provide a base;

[0023] A plurality of spaced-apart capacitive contact structures are formed within the substrate; the capacitive contact structures include those protruding from the upper surface of the substrate;

[0024] An isolation structure is formed to fill the gap between adjacent capacitor contact structures, and the top surface of the isolation structure is not higher than the top surface of the capacitor contact structure;

[0025] An isolation groove is formed; the isolation groove extends from the top surface of the isolation structure into the isolation structure and has a gap with the capacitor contact structure.

[0026] In some embodiments, the plurality of capacitive contact structures are distributed in multiple rows and columns, the plurality of capacitive contact structures located in the same column are arranged at intervals along a first direction, and the plurality of capacitive contact structures located in the same row are arranged at intervals along a second direction, the second direction intersecting the first direction;

[0027] The formation of the isolation groove includes:

[0028] A first patterned mask layer is formed on the capacitor contact structure and the isolation structure; the first patterned mask layer includes a plurality of parallel spaced first mask patterns, the first mask patterns extend along a first direction, and the orthographic projection of the gap between adjacent first mask patterns on the upper surface of the substrate is located between two adjacent columns of capacitor contact structures.

[0029] The isolation structure is etched based on the first patterned mask layer to form a plurality of spaced first isolation grooves; the first isolation grooves extend along the first direction and are located between two adjacent columns of the capacitor contact structures.

[0030] In some embodiments, forming a first patterned mask layer on the substrate includes:

[0031] A first mask layer is formed on the capacitor contact structure and the isolation structure;

[0032] Multiple parallel-spaced first sub-mask patterns are formed on the upper surface of the first mask layer and extend along the first direction;

[0033] A first sacrificial pattern is formed on the sidewall of the first sub-mask pattern, and the first sub-mask pattern is removed to retain a plurality of first sacrificial patterns arranged in parallel and extending along the first direction.

[0034] A first filling mask layer is formed; the first filling mask layer fills the gap between adjacent first sacrificial patterns, and the upper surface of the first filling mask layer is not higher than the upper surface of the first sacrificial pattern;

[0035] Remove the first sacrificial pattern to form a first initial trench between adjacent first filler mask layers;

[0036] The first mask layer is etched along the first initial trench to obtain the first patterned mask layer.

[0037] In some embodiments, forming a first sacrificial pattern on the sidewall of the first sub-mask pattern includes:

[0038] A first sacrificial material layer is formed on the upper surface of the first mask layer exposed between adjacent first sub-mask patterns, the sidewalls of the first sub-mask patterns, and the top of the first sub-mask patterns;

[0039] The first sacrificial material layer, which is exposed on the upper surface of the first mask layer between adjacent first sub-mask patterns and on top of the first sub-mask pattern, is removed. The first sacrificial material layer remaining on the sidewall of the first sub-mask pattern is the first sacrificial pattern.

[0040] In some embodiments, forming the first filling mask layer includes:

[0041] A first filler material layer is formed on the first mask layer; the first filler material layer fills the gap between adjacent first sacrificial patterns and covers the first sacrificial patterns;

[0042] The first filler material layer is etched back to remove the first filler material layer on top of the first sacrificial pattern, and the first filler material layer located between adjacent first sacrificial patterns is retained as the first filler mask layer.

[0043] In some embodiments, forming the isolation groove further includes:

[0044] A second patterned mask layer is formed on the capacitor contact structure and the isolation structure; the second patterned mask layer includes a plurality of parallel spaced second mask patterns, the second mask patterns extend along a second direction, the second direction intersects with the first direction, and the orthographic projection of the gap between adjacent second mask patterns on the upper surface of the substrate is located between two adjacent rows of capacitor contact structures;

[0045] The isolation structure is etched based on the second patterned mask layer to form a plurality of spaced second isolation grooves; the second isolation grooves extend along the second direction and are located between two adjacent rows of the capacitor contact structures, and penetrate the plurality of first isolation grooves.

[0046] In some embodiments, before forming the isolation groove on the capacitive contact structure and the isolation structure, the method further includes: forming a pattern transfer material layer;

[0047] Before etching the isolation structure, the first mask pattern and the second mask pattern are transferred to the pattern transfer material layer to form a pattern transfer layer;

[0048] The isolation structure is etched based on the first patterned mask layer, the second patterned mask layer and the pattern transfer layer to form a plurality of spaced first isolation grooves and second isolation grooves.

[0049] In some embodiments, after forming the isolation groove, the method further includes:

[0050] Multiple capacitor structures are formed on the substrate, and each capacitor structure makes contact with a capacitor contact structure in a one-to-one correspondence.

[0051] In some embodiments, forming a plurality of capacitor structures on the substrate includes:

[0052] A first support layer is formed on the upper surface of the isolation structure; the first support layer covers the top surface of the capacitive contact structure, and the isolation groove penetrates the first support layer along the thickness direction;

[0053] After the isolation groove is formed, a first capacitor sacrificial layer is formed on the first support layer; the first capacitor sacrificial layer fills the isolation groove.

[0054] A second support layer is formed on the upper surface of the first capacitor sacrificial layer;

[0055] A second capacitor sacrificial layer is formed on the upper surface of the second support layer;

[0056] A third support layer is formed on the upper surface of the second capacitor sacrificial layer;

[0057] Multiple capacitor holes are formed; the capacitor holes penetrate the third support layer, the second capacitor sacrificial layer, the second support layer, the first capacitor sacrificial layer and the first support layer to expose the capacitor contact structure;

[0058] A lower electrode is formed on the sidewall and bottom of the capacitor hole;

[0059] Remove the first capacitor sacrificial layer and the second capacitor sacrificial layer;

[0060] A capacitor dielectric layer is formed on the surface of the lower electrode and within the isolation groove;

[0061] An upper electrode is formed on the surface of the capacitor dielectric layer.

[0062] In some embodiments, there is a gap between the upper electrodes; after forming the upper electrodes, the method further includes:

[0063] A conductive filling layer is formed, wherein the conductive filling layer at least fills the gap.

[0064] The semiconductor structure and its fabrication method provided in this application have at least the following beneficial effects:

[0065] In the semiconductor structure provided in this application, an isolation structure is provided between adjacent capacitor contact structures to avoid short circuits. During the fabrication of the capacitor contact structure, the capacitor contact material used to form the capacitor contact structure is easily oxidized and remains between adjacent capacitor contact structures, causing mutual interference and short circuits. However, the semiconductor structure provided in this application further avoids the problem of mutual interference and short circuits caused by oxidized capacitor contact material remaining between adjacent capacitor contact structures by providing isolation grooves extending from the top surface of the isolation structure into the isolation structure. Capacitors subsequently formed on top of this groove will not interfere with each other. Therefore, the semiconductor structure provided in this application can improve the production yield and reliability of capacitors, thereby improving the production yield and electrical performance of the semiconductor structure.

[0066] The semiconductor structure fabrication method provided in this application avoids short circuits between adjacent capacitor contact structures by filling the gaps between them with an isolation structure. During the fabrication of capacitor contact structures, the capacitor contact material used to form these structures is easily oxidized, leaving byproducts between adjacent contact structures, causing interference and short circuits. However, the semiconductor structure fabrication method provided in this application further avoids short circuits caused by byproducts of the capacitor contact material remaining between adjacent contact structures by forming an isolation groove extending from the top surface of the isolation structure into the isolation structure. Capacitors subsequently formed on this groove will also not interfere with each other. Therefore, the semiconductor structure fabrication method provided in this application can improve the production yield and reliability of capacitors, thereby improving the production yield and electrical performance of the semiconductor structure. Attached Figure Description

[0067] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0068] Figures 1 to 5 This is a schematic flowchart illustrating the method for fabricating semiconductor structures provided in some embodiments of this application;

[0069] Figure 6 A schematic diagram of the cross-sectional structure of the semiconductor structure obtained in step S300 in the method for fabricating the semiconductor structure provided in some embodiments of this application;

[0070] Figure 7 Figure (a) in the middle and Figure 8 Figure (a) is a schematic cross-sectional view of the structure obtained in step S413 in the method for preparing a semiconductor structure provided in some embodiments of this application; Figure 7 Figure (b) in the middle and Figure 8 Figure (b) is a top view of the structure obtained in step S413 in the method for preparing a semiconductor structure provided in some embodiments of this application;

[0071] Figure 9 and Figure 10 Figure (a) is a schematic cross-sectional view of the structure obtained in step S414 in the method for preparing a semiconductor structure provided in some embodiments of this application; Figure 10 Figure (b) is a top view of the structure obtained in step S414 in the method for preparing a semiconductor structure provided in some embodiments of this application;

[0072] Figure 11 Figure (a) is a schematic cross-sectional view of the structure obtained in step S415 in the method for preparing a semiconductor structure provided in some embodiments of this application; Figure 11 Figure (b) is a top view of the structure obtained in step S415 in the method for preparing a semiconductor structure provided in some embodiments of this application;

[0073] Figure 12 A schematic diagram of the cross-sectional structure of the semiconductor structure obtained in step S416 in the method for fabricating the semiconductor structure provided in some embodiments of this application;

[0074] Figure 13 Figure (a) is a schematic cross-sectional view of the structure obtained in step S400 in the method for preparing a semiconductor structure provided in some embodiments of this application; Figure 13 Figure (b) is a top view of the structure obtained in step S400 in the method for preparing a semiconductor structure provided in some embodiments of this application;

[0075] Figures 14 to 22 This is a schematic cross-sectional view of the structure obtained in the fabrication method of the semiconductor structure provided in some embodiments of this application; wherein, Figure 22 This is also a cross-sectional schematic diagram of the semiconductor structure provided in some embodiments of this application.

[0076] Explanation of reference numerals in the attached figures:

[0077] 100. Capacitor contact structure; 100a. Residual capacitor contact material; 110. Sidewall dielectric layer; 200. Isolation structure; 300. Isolation groove; 310. First patterned mask layer; 311. First mask layer; 312. First sub-mask pattern; 313. First sacrificial material layer; 314. First sacrificial pattern; 315. First filling material layer; 316. First filling mask layer; 317. First initial trench; 400. Capacitor structure; 411. 421. First support layer; 422. First capacitor sacrificial layer; 413. Second support layer; 424. Second capacitor sacrificial layer; 415. Third support layer; 430. Capacitor hole; 440. Lower electrode; 450. Capacitor dielectric layer; 460. Upper electrode; 470. Filling conductive layer; 510. Mask stack; 511. First mask material layer; 512. Second mask material layer; 513. Third mask material layer; 520. Photoresist layer; 530. Capacitor opening hole. Detailed Implementation

[0078] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0079] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0080] It should be understood that when an element or layer is referred to as "on," "between," or "connected to," it may be directly located on, between, or connected to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion; for example, a first isolation recess may be referred to as a second isolation recess, and similarly, a second isolation recess may be referred to as a first isolation recess; the first isolation recess and the second isolation recess are different isolation recesses.

[0081] It should also be understood that, in addition to the orientations shown in the figures, spatial relational terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, the description of the "upper surface" would be oriented as the "lower surface." Therefore, the exemplary term "upper" can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0082] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0083] Embodiments of the invention are described herein with reference to cross-sectional views illustrating preferred embodiments (and intermediate structures) of this application, thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this application.

[0084] According to some embodiments, this application provides a method for fabricating a semiconductor structure.

[0085] Please see Figure 1 In some embodiments, the method for fabricating the semiconductor structure may include the following steps:

[0086] S100: Provides a substrate.

[0087] S200: A plurality of spaced capacitor contact structures are formed within the substrate; the capacitor contact structures include those protruding from the upper surface of the substrate.

[0088] S300: Forms an isolation structure to fill the gap between adjacent capacitor contact structures, and the top surface of the isolation structure is not higher than the top surface of the capacitor contact structure.

[0089] S400: Forming an isolation groove; the isolation groove extends from the top surface of the isolation structure into the isolation structure and has a gap with the capacitor contact structure.

[0090] The semiconductor structure fabrication method provided in the above embodiments avoids short circuits between adjacent capacitor contact structures by filling the gaps between them with an isolation structure. During the fabrication of the capacitor contact structure, the capacitor contact material used to form it is easily oxidized, leaving byproducts between adjacent capacitor contact structures, causing mutual interference and short circuits. However, the semiconductor structure fabrication method provided in this application also avoids short circuits caused by mutual interference between adjacent capacitor contact structures due to byproducts of the capacitor contact material remaining between them by forming an isolation groove extending from the top surface of the isolation structure into the isolation structure. The capacitors subsequently formed on top of this groove will not interfere with each other. Therefore, the semiconductor structure fabrication method provided in this application can improve the production yield and reliability of capacitors, thereby improving the production yield and electrical performance of the semiconductor structure.

[0091] In some embodiments, multiple capacitor contact structures are distributed in multiple rows and columns, with multiple capacitor contact structures in the same column arranged at intervals along a first direction, and multiple capacitor contact structures in the same row arranged at intervals along a second direction, the second direction intersecting the first direction.

[0092] Please see Figure 2 In some embodiments, step S400, forming the isolation groove, may include the following steps:

[0093] S410: A first patterned mask layer is formed on the capacitor contact structure and the isolation structure; the first patterned mask layer includes a plurality of parallel spaced first mask patterns, the first mask patterns extend along a first direction, and the orthographic projection of the gap between adjacent first mask patterns on the upper surface of the substrate is located between two adjacent columns of capacitor contact structures.

[0094] S420: Based on the first patterned mask layer, an isolation structure is etched to form a plurality of spaced first isolation grooves; the first isolation grooves extend along a first direction and are located between two adjacent columns of capacitor contact structures.

[0095] Please see Figure 3 In some embodiments, step S410, which involves forming a first patterned mask layer on the substrate, may include the following steps:

[0096] S411: A first mask layer is formed on the capacitor contact structure and the isolation structure.

[0097] S412: A plurality of first sub-mask patterns are formed on the upper surface of the first mask layer, which are arranged in parallel intervals and extend along the first direction.

[0098] S413: A first sacrificial pattern is formed on the sidewall of the first sub-mask pattern, and the first sub-mask pattern is removed to retain a plurality of parallel-spaced first sacrificial patterns that extend along the first direction.

[0099] S414: Form a first filling mask layer; the first filling mask layer fills the gap between adjacent first sacrificial patterns, and the upper surface of the first filling mask layer is not higher than the upper surface of the first sacrificial pattern.

[0100] S415: Remove the first sacrificial pattern to form a first initial trench between adjacent first fill mask layers.

[0101] S416: Etch the first mask layer along the first initial trench to obtain the first patterned mask layer.

[0102] Please see Figure 4 In some embodiments, step S400, which forms the isolation groove, may further include the following steps:

[0103] S430: A second patterned mask layer is formed on the capacitor contact structure and the isolation structure; the second patterned mask layer includes a plurality of parallel and spaced second mask patterns, the second mask patterns extend along a second direction, the second direction intersects with the first direction, and the orthographic projection of the gap between adjacent second mask patterns on the upper surface of the substrate is located between two adjacent rows of capacitor contact structures.

[0104] S440: Based on the second patterned mask layer, an isolation structure is etched to form a plurality of spaced second isolation grooves; the second isolation grooves extend along the second direction and are located between two adjacent rows of capacitor contact structures, and penetrate the plurality of first isolation grooves.

[0105] In some embodiments, after forming the isolation groove in step S400, the method further includes forming a plurality of capacitor structures on the substrate. The capacitor structures and capacitor contact structures are in one-to-one contact.

[0106] In some embodiments, before forming the isolation groove in step S400, the method further includes forming a first support layer on the upper surface of the isolation structure.

[0107] Please see Figure 5 In some embodiments, after forming the isolation groove in step S400, multiple capacitor structures can be formed using the following steps:

[0108] S511: A first support layer is formed on the upper surface of the isolation structure; the first support layer covers the top surface of the capacitor contact structure, and the isolation groove penetrates the first support layer along the thickness direction.

[0109] S512: After forming the isolation groove, a first capacitor sacrificial layer is formed on the first support layer; the first capacitor sacrificial layer fills the isolation groove.

[0110] S513: A second support layer is formed on the upper surface of the first capacitor sacrificial layer.

[0111] S514: A second capacitor sacrificial layer is formed on the upper surface of the second support layer.

[0112] S515: A third support layer is formed on the upper surface of the second capacitor sacrificial layer.

[0113] S516: Form multiple capacitor holes; the capacitor holes penetrate the third support layer, the second capacitor sacrificial layer, the second support layer, the first capacitor sacrificial layer and the first support layer to expose the capacitor contact structure.

[0114] S517: A lower electrode is formed on the sidewall and bottom of the capacitor hole.

[0115] S518: Remove the first capacitor sacrificial layer and the second capacitor sacrificial layer.

[0116] S519: A capacitor dielectric layer is formed on the surface of the lower electrode and in the isolation groove.

[0117] S520: An upper electrode is formed on the surface of the capacitor dielectric layer.

[0118] To more clearly illustrate the preparation method in the embodiments of this application, please refer to the following... Figures 6 to 22 Some embodiments of this application are explained.

[0119] In step S100, a substrate is provided.

[0120] This application does not specifically limit the material of the substrate. As an example, the substrate material may include, but is not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), or silicon carbide (SiC), etc.

[0121] Please see Figure 6In step S200, on the substrate ( Figure 6 Multiple capacitor contact structures 100 are formed within the (not shown) spaced apart. Figure 6 As shown, the upper surface of the capacitor contact structure 100 can protrude from the upper surface of the substrate.

[0122] This application does not specifically limit the material of the capacitor contact structure 100. As an example, the material of the capacitor contact structure 100 may include, but is not limited to, related semiconductor conductive materials such as tungsten (W) or copper (Cu).

[0123] In some embodiments, a sidewall dielectric layer 110 may be formed on at least one sidewall of the capacitive contact structure 100.

[0124] In the preparation method provided in the above embodiments, the formation of the sidewall dielectric layer 110 can prevent the capacitor contact structure 100 from diffusing in a high-temperature environment, which would cause mutual interference between adjacent capacitor contact structures 100 and short circuits. This avoids short circuits between adjacent capacitors subsequently formed on top of it, further improving the production yield and reliability of the product obtained by the preparation method.

[0125] This application does not specifically limit the material of the sidewall dielectric layer 110. As an example, the material of the sidewall dielectric layer 110 may include, but is not limited to, metal silicides.

[0126] Please continue reading. Figure 6 In step S300, an isolation structure 200 is formed to fill the gap between adjacent capacitor contact structures 100. For example... Figure 6 As shown, the top surface of the isolation structure 200 is not higher than the top surface of the capacitor contact structure 100, so that the top surface of the capacitor contact structure 100 can be exposed.

[0127] In this embodiment, the adjacent capacitor contact structures 100 can be insulated from each other by filling the gap between them with an isolation structure 200 to prevent short circuits.

[0128] This application does not specifically limit the material of the isolation structure 200. As an example, the material of the isolation structure 200 may include, but is not limited to, insulating materials such as monocrystalline silicon, polycrystalline silicon, silicon dioxide (SiO2), or silicon nitride (SiN).

[0129] Please see Figures 7 to 12 In step S400, an isolation groove 300 is formed. The isolation groove 300 extends from the top surface of the isolation structure 200 into the isolation structure 200 and has a gap with the capacitor contact structure 100.

[0130] according to Figure 12As can be seen in this embodiment, the isolation groove 300 can effectively cut off the residual capacitor contact material 100a between adjacent capacitor contact structures 100. Thus, the residual capacitor contact material 100a will not cause adjacent capacitor contact structures 100 to interfere with each other, resulting in a short circuit. Subsequent capacitors formed on top of this will also not interfere with each other.

[0131] In some embodiments, multiple capacitor contact structures 100 are arranged in multiple rows and columns, with multiple capacitor contact structures 100 located in the same column arranged at intervals along a first direction, and multiple capacitor contact structures 100 located in the same row arranged at intervals along a second direction.

[0132] In this embodiment of the application, the second direction intersects with the first direction.

[0133] In some embodiments, the isolation groove 300 formed in step S400 may include a plurality of first isolation grooves arranged at intervals.

[0134] As an example, step S400 may specifically include steps S410 to S420 to form a first isolation groove.

[0135] In step S410, please refer to Figures 7 to 12 A first patterned mask layer 310 is formed on the capacitor contact structure 100 and the isolation structure 200.

[0136] The first patterned mask layer 310 may include a plurality of first mask patterns arranged in parallel at intervals. The first mask patterns extend along a first direction, and the orthographic projection of the gap between adjacent first mask patterns onto the upper surface of the substrate should be located between two adjacent columns of capacitive contact structures 100.

[0137] In step S420, please continue reading. Figures 7 to 12 Based on the first patterned mask layer 310, the isolation structure 200 is etched to form a plurality of spaced first isolation grooves.

[0138] The first isolation groove extends along the first direction and is located between two adjacent columns of capacitor contact structures 100.

[0139] In some embodiments, the isolation groove 300 formed in step S400 may further include a plurality of second isolation grooves arranged at intervals.

[0140] In some embodiments, step S400 may further include steps S430 to S440 to form a second isolation groove.

[0141] In step S430, a second patterned mask layer is formed on the capacitor contact structure 100 and the isolation structure 200.

[0142] The second patterned mask layer may include a plurality of parallel spaced second mask patterns, which extend along a second direction that intersects with the first direction. The orthographic projection of the gap between adjacent second mask patterns onto the upper surface of the substrate is located between two adjacent rows of capacitive contact structures 100.

[0143] In step S440, the isolation structure 200 is etched based on the second patterned mask layer to form a plurality of spaced second isolation grooves.

[0144] The second isolation groove extends along the second direction and is located between two adjacent rows of capacitor contact structures 100, and penetrates multiple first isolation grooves.

[0145] In some embodiments, a second patterned mask layer may be formed after the first patterned mask layer 310 is formed.

[0146] It should be noted that, in the embodiments of this application, there is no order restriction between the steps of forming the first isolation groove and the steps of forming the second isolation groove, that is, it is permissible for either step to be performed first or simultaneously.

[0147] As an example, the materials of the first patterned mask layer 310 and the second patterned mask layer may include, but are not limited to, silicon oxynitride (SiO2).

[0148] In some embodiments, the first isolation groove and the second isolation groove may be formed in the following manner. For example:

[0149] Before forming the first patterned mask layer 310 and the second patterned mask layer, a pattern transfer material layer is formed. Before etching the isolation structure 200, the first mask pattern and the second mask pattern are transferred to the pattern transfer material layer to form a pattern transfer layer.

[0150] Based on the first patterned mask layer 310, the second patterned mask layer and the pattern transfer layer, an isolation structure 200 is etched to form a plurality of spaced first isolation grooves and second isolation grooves.

[0151] As an example, step S410 may specifically include steps S411 to S416 as follows.

[0152] In step S411, as Figure 7 Figure (a) in the middle and Figure 7 As shown in Figure (b), a first mask layer 311 is formed on the capacitor contact structure 100 and the isolation structure 200.

[0153] In step S412, as Figure 7 Figure (a) in the middle and Figure 7As shown in Figure (b), a plurality of first sub-mask patterns 312 are formed on the upper surface of the first mask layer 311, arranged in parallel and spaced intervals and extending along the first direction.

[0154] In step S413, a first sacrificial pattern 314 is formed on the sidewall of the first sub-mask pattern 312; the first sub-mask pattern 312 is removed, as shown below. Figure 8 Figure (a) in the middle and Figure 8 As shown in Figure (b), multiple first sacrificial patterns 314 are retained, arranged in parallel intervals and extending along the first direction.

[0155] In step S414, as Figures 9 to 10 As shown, a first filling mask layer 316 is formed; the first filling mask layer 316 fills the gap between adjacent first sacrificial patterns 314, and the upper surface of the first filling mask layer 316 is not higher than the upper surface of the first sacrificial pattern 314.

[0156] In step S415, as Figure 11 Figure (a) in the middle and Figure 11 As shown in Figure (b), the first sacrificial pattern 314 is removed to form a first initial trench 317 between adjacent first filler mask layers 316.

[0157] In step S416, as Figure 12 As shown, the first mask layer 311 is etched along the first initial trench 317 to obtain the first patterned mask layer 310.

[0158] This application does not specifically limit the material of the first sub-mask pattern 312 formed in step S412. As an example, the material of the first sub-mask pattern 312 may include, but is not limited to, photoresist.

[0159] For step S413, in some embodiments, the first sacrificial pattern 314 can be formed using the following steps:

[0160] like Figure 7 As shown in Figure (a), a first sacrificial material layer 313 is formed on the upper surface of the first mask layer 311 exposed between adjacent first sub-mask patterns 312, the sidewalls of the first sub-mask patterns 312, and the top of the first sub-mask patterns 312.

[0161] like Figure 7 As shown in Figure (b), the first sacrificial material layer 313, which is exposed between adjacent first sub-mask patterns 312, and the first sacrificial material layer 313, which is located on the top of the first sub-mask pattern 312, are removed, and the first sacrificial material layer 313, which is retained on the sidewall of the first sub-mask pattern 312, is the first sacrificial pattern 314.

[0162] As an example, the material of the first sacrifice graphic 314 may include, but is not limited to, oxides.

[0163] This application does not specifically limit the method of removing the first sacrificial material layer 313 in the above steps. As an example, carbon tetrafluoride (also known as tetrafluoromethane, chemical formula CF4) gas or perfluorobutadiene (C4F6) gas can be used to etch and remove the first sacrificial material layer 313.

[0164] Between step S413 and step S414, a step of removing the first sub-mask pattern 312 may also be included.

[0165] As an example, the first sub-mask pattern 312 can be removed by means of oxygen (O2) plasma or silica dry cleaning, but is not limited to.

[0166] For step S414, in some embodiments, the first filling mask layer 316 can be formed using the following steps:

[0167] like Figure 9 As shown, a first filler material layer 315 is formed on the first mask layer 311. The first filler material layer 315 should at least fill the gap between adjacent first sacrificial patterns 314. Optionally, the first filler material layer 315 may also cover the first sacrificial patterns 314.

[0168] like Figure 10 Figure (a) in the middle and Figure 10 As shown in Figure (b), the first filler material layer 315 is etched back to remove the first filler material layer 315 on top of the first sacrificial pattern 314, and the first filler material layer 315 located between adjacent first sacrificial patterns 314 is retained, which is the first filler mask layer 316.

[0169] This application does not specifically limit the method for removing the first sacrificial pattern 314 in step S415. As an example, a wet etching process can be used to remove the first sacrificial pattern 314.

[0170] This application does not specifically limit the material of the first filling mask layer 316 formed in the above steps. As an example, the material of the first filling mask layer 316 may include, but is not limited to, carbide.

[0171] It is understood that in the embodiments of this application, the method of forming the second patterned mask layer in step S430 can refer to the steps of forming the first patterned mask layer 310 described above, and will not be repeated here.

[0172] Please see Figure 13 Figure (a) in the middle and Figure 13In Figure (b), in some embodiments, the first patterned mask layer 310 and the first filler mask layer 316 may be removed after the isolation groove 300 is formed.

[0173] Please see Figures 14 to 22 In some embodiments, after the isolation groove 300 is formed in step S400, a plurality of capacitor structures 400 may be formed on the substrate.

[0174] like Figure 22 As shown, the capacitor structure 400 can make contact with the capacitor contact structure 100 in a one-to-one correspondence.

[0175] As an example, forming the capacitor structure 400 may specifically include the following steps S511 to S520.

[0176] In step S511, please refer to Figure 13 A first support layer 411 is formed on the upper surface of the isolation structure 200. The first support layer 411 covers the top surface of the capacitor contact structure 100, and the isolation groove 300 penetrates the first support layer 411.

[0177] In step S512, please refer to Figure 14 A first capacitor sacrificial layer 421 is formed on the first support layer 411, and the first capacitor sacrificial layer 421 fills the isolation groove 300.

[0178] In step S513, please refer to... Figure 14 A second support layer 412 is formed on the upper surface of the first capacitor sacrificial layer 421.

[0179] In step S514, please continue reading. Figure 14 A second capacitor sacrificial layer 422 is formed on the upper surface of the second support layer 412.

[0180] In step S515, please refer to... Figure 14 A third support layer 413 is formed on the upper surface of the second capacitor sacrificial layer 422.

[0181] In step S516, please refer to Figure 15 Multiple capacitor holes 430 are formed. The capacitor holes 430 penetrate the third support layer 413, the second capacitor sacrificial layer 422, the second support layer 412, the first capacitor sacrificial layer 421 and the first support layer 411 to expose the capacitor contact structure 100.

[0182] In step S517, please refer to Figure 16 A lower electrode 440 is formed on the sidewall and bottom of the capacitor hole 430.

[0183] In step S518, please refer to Figures 17 to 21Remove the first capacitor sacrificial layer 421 and the second capacitor sacrificial layer 422.

[0184] In step S519, please refer to Figure 22 A capacitor dielectric layer 450 is formed on the surface of the lower electrode 440 and within the isolation groove 300.

[0185] In step S520, please refer to Figure 22 An upper electrode 460 is formed on the surface of the capacitor dielectric layer 450.

[0186] For ease of description, in this embodiment, the surface of the lower electrode 440 located above the third support layer 413 is referred to as the top surface of the lower electrode 440.

[0187] In some embodiments, step S511 may specifically include the following steps. For example:

[0188] like Figures 6 to 11 As shown, before forming the isolation groove 300, a first support material layer 411a is formed on the upper surface of the isolation structure 200. The first support material layer 411a covers the top surface of the capacitive contact structure 100.

[0189] like Figures 12 to 13 As shown, during the formation of the isolation groove 300, the isolation groove 300 penetrates the first support material layer 411a. The retained first support material layer 411a serves as the first support layer 411.

[0190] This application does not specifically limit the materials of the first support layer 411 formed in step S511 and the second support layer 412 formed in step S513.

[0191] In some embodiments, the material of the first support layer 411 and the material of the second support layer 412 both include silicon nitride.

[0192] This application does not specifically limit the materials of the first capacitor sacrificial layer 421 formed in step S512 and the second capacitor sacrificial layer 422 formed in step S514.

[0193] As an example, the material of the first capacitor sacrificial layer 421 may include, but is not limited to, silicon phosphide glass (PSG) or borosilicate glass (BPSG), etc.

[0194] As an example, the material of the second capacitor sacrificial layer 422 may include, but is not limited to, oxides.

[0195] This application does not specify the materials of the lower electrode 440, capacitor dielectric layer 450 and upper electrode 460 formed in the above steps.

[0196] As an example, the material of the lower electrode 440 may be a compound formed from one or both of metal nitrides and metal silicides, including but not limited to.

[0197] As an example, the material of the capacitor dielectric layer 450 may include, but is not limited to, zirconium oxide (ZrO2). x ), Hafnium oxide (HfO) x ), zirconium titanium oxide (ZrTiO) x ), Ruthenium oxide (RuO) x ), antimony oxide (SbO) x ) or aluminum oxide (AlO x Any one of the following: ) etc.

[0198] As an example, the material of the upper electrode 460 may include, but is not limited to, polycrystalline silicon.

[0199] In some embodiments, step S518 may specifically include the following steps. For example:

[0200] like Figure 17 As shown, a mask stack 510 is formed. The mask stack 510 covers the top surface of the lower electrode 440 and seals the capacitor hole 430.

[0201] Please continue reading. Figure 17 A photoresist layer 520 is formed on the upper surface of the mask stack 510, and the photoresist layer 520 is patterned to form a photoresist pattern 520a on the photoresist layer 520, the photoresist pattern 520a exposing part of the upper surface of the mask stack 510.

[0202] The photoresist layer 520 is used to etch the mask stack 510, forming multiple openings within the mask stack 510, which expose portions of the third support layer 413. For example... Figure 18 As shown, the top surface of the lower electrode 440 is removed, and the pattern of the opening is transferred to the third support layer 413 to form a capacitor opening hole 530. The capacitor opening hole 530 exposes a portion of the second capacitor sacrificial layer 422.

[0203] like Figure 19 As shown, the second capacitor sacrificial layer 422 is removed to expose the second support layer 412.

[0204] like Figure 20 As shown, the pattern of the capacitor opening hole 530 is transferred to the second support layer 412 to expose part of the first capacitor sacrificial layer 421.

[0205] like Figure 21 As shown, the first capacitor sacrificial layer 421 is removed to expose the first support layer 411.

[0206] This application does not specifically limit the structure of the mask stack 510.

[0207] Please continue reading. Figure 17 In some embodiments, the mask stack 510 may include a first mask material layer 511, a second mask material layer 512 and a third mask material layer 513 stacked sequentially from bottom to top.

[0208] As an example, the first mask material layer 511 may include, but is not limited to, a silicon dioxide layer; the second mask material layer 512 may include, but is not limited to, a crystalline carbon layer or an amorphous carbon layer; and the third mask material layer 513 may include, but is not limited to, a silicon oxynitride layer.

[0209] This application does not specify the method of removing the second capacitor sacrificial layer 422 or the first capacitor sacrificial layer 421.

[0210] As an example, the second capacitor sacrificial layer 422 can be removed using the following steps:

[0211] After a portion of the second capacitor sacrificial layer 422 is exposed through the capacitor opening hole 530, acid is injected into the second capacitor sacrificial layer 422 through the capacitor opening hole 530 to dissolve and remove the second capacitor sacrificial layer 422.

[0212] As an example, the first capacitor sacrificial layer 421 can be removed using the following steps, for example:

[0213] After the pattern of the capacitor opening hole 530 is transferred to the second support layer 412, exposing part of the first capacitor sacrificial layer 421, acid is injected into the first capacitor sacrificial layer 421 to dissolve and remove the first capacitor sacrificial layer 421.

[0214] In some embodiments, there is a gap between the upper electrodes 460.

[0215] As an example, please continue reading Figure 22 After forming the upper electrode 460 in step S520, the step of forming a filled conductive layer 470 may be included.

[0216] The conductive layer 470 can at least fill the gaps between the upper electrodes 460 in this application.

[0217] It should be understood that, although Figures 1 to 5 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 1 to 5At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0218] This application also provides a semiconductor structure according to some embodiments.

[0219] Please continue reading. Figure 22 In some embodiments, the semiconductor structure may include a substrate, an isolation structure 200, and an isolation recess 300.

[0220] The substrate has multiple spaced-apart capacitor contact structures 100. An isolation structure 200 is located on the substrate and between adjacent capacitor contact structures 100; the top surface of the isolation structure 200 should not be higher than the top surface of the capacitor contact structure 100. An isolation groove 300 extends from the top surface of the isolation structure 200 into the isolation structure 200, and there is a gap between the isolation groove 300 and the capacitor contact structure 100.

[0221] In the semiconductor structure provided in the above embodiments, by providing an isolation structure 200 between adjacent capacitor contact structures 100, the problem of short circuits between adjacent capacitor contact structures 100 is avoided. During the fabrication process of the capacitor contact structure 100, the capacitor contact material used to form the capacitor contact structure 100 is easily oxidized, and by-products remain between adjacent capacitor contact structures 100, causing mutual interference between adjacent capacitor contact structures 100 and resulting in short circuits. However, the semiconductor structure provided in this application also avoids the problem of mutual interference between adjacent capacitor contact structures 100 and resulting in short circuits due to by-products of the capacitor contact material remaining between adjacent capacitor contact structures 100 by providing an isolation groove 300 extending from the top surface of the isolation structure 200 into the isolation structure 200. The capacitors subsequently formed on this structure will not interfere with each other. Therefore, the semiconductor structure provided in this application can improve the production yield and reliability of capacitors, thereby improving the production yield and electrical performance of the semiconductor structure.

[0222] In some embodiments, the isolation groove 300 may include a plurality of first isolation grooves arranged at intervals. The first isolation grooves extend along a first direction and are located between two adjacent columns of capacitive contact structures 100.

[0223] In some embodiments, the isolation groove 300 may further include a plurality of second isolation grooves arranged at intervals. The second isolation grooves extend along a second direction and are located between two adjacent rows of capacitive contact structures 100, and penetrate the plurality of first isolation grooves.

[0224] In some embodiments, the semiconductor structure may further include a plurality of capacitor structures 400. The capacitor structures 400 are located on the substrate and are in contact with the capacitor contact structures 100 in a one-to-one correspondence.

[0225] In some embodiments, the semiconductor structure may further include a support structure.

[0226] Please continue reading. Figure 22 The support structure may include a first support layer 411, a second support layer 412, and a third support layer 413 stacked sequentially from bottom to top. Figure 22 (Not shown in the image). The support structure is provided with a plurality of capacitor holes 430 that penetrate the first support layer 411, the second support layer 412 and the third support layer 413. The capacitor holes 430 are provided one-to-one with the capacitor contact structure 100, and the capacitor holes 430 expose the capacitor contact structure 100.

[0227] At this time, the isolation groove 300 also penetrates the first support layer 411 along the thickness direction.

[0228] In some embodiments, please continue reading Figure 22 The capacitor structure 400 may include a lower electrode 440, a capacitor dielectric layer 450, and an upper electrode 460.

[0229] The lower electrode 440 is located on the sidewall and bottom of the capacitor hole 430, and is connected to the first support layer 411, the second support layer 412, and the third support layer 413, and is in contact with the capacitor contact structure 100. The capacitor dielectric layer 450 is located on the surface of the lower electrode 440 and within the isolation groove 300. The upper electrode 460 is located on the surface of the capacitor dielectric layer 450.

[0230] In some embodiments, please continue reading Figure 22 There is also a gap between the upper electrodes 460.

[0231] In some embodiments, please continue reading Figure 22 The capacitor structure 400 may further include a conductive filler layer 470. The conductive filler layer 470 may fill the gap between the upper electrodes 460.

[0232] As an example, the conductive layer 470 is electrically connected to the upper electrode 460 to achieve connection with the metal interconnects on the capacitor structure 400.

[0233] It should be noted that the semiconductor structure preparation methods in the embodiments of this application can all be used to prepare the corresponding semiconductor structures. Therefore, the technical features between the method embodiments and the structure embodiments can be substituted and supplemented for each other without conflict, so that those skilled in the art can understand the technical content of this application.

[0234] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0235] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized by, include: Base; Multiple spaced capacitor contact structures are formed on the substrate, and byproducts of capacitor contact material remain between adjacent capacitor contact structures. Isolation structure; The isolation structure is located on the substrate and between adjacent capacitive contact structures; the top surface of the isolation structure is not higher than the top surface of the capacitive contact structure. Isolation groove; The isolation groove extends from the top surface of the isolation structure into the isolation structure, and there is a gap between the isolation groove and the capacitor contact structure. The isolation groove cuts off the by-products of capacitor contact material remaining between adjacent capacitor contact structures.

2. The semiconductor structure of claim 1, wherein, The multiple capacitor contact structures are arranged in a multi-row, multi-column array. The multiple capacitor contact structures located in the same column are arranged at intervals along a first direction, and the multiple capacitor contact structures located in the same row are arranged at intervals along a second direction, which intersects with the first direction. The isolation groove includes a plurality of first isolation grooves arranged at intervals, the first isolation grooves extending along the first direction and located between two adjacent columns of the capacitor contact structures.

3. The semiconductor structure of claim 2, wherein, The isolation groove includes a plurality of second isolation grooves arranged at intervals, the second isolation grooves extending along the second direction and located between two adjacent rows of the capacitor contact structures, and penetrating the plurality of first isolation grooves.

4. The semiconductor structure of any one of claims 1 to 3, wherein, It also includes multiple capacitor structures, which are located on the substrate and make contact with the capacitor contact structures one by one.

5. The semiconductor structure of claim 4, wherein, It also includes a support structure, which includes a first support layer, a second support layer and a third support layer stacked sequentially from bottom to top; the support structure is provided with a plurality of capacitor holes penetrating the first support layer, the second support layer and the third support layer, and the capacitor holes are provided one-to-one with the capacitor contact structure, and the capacitor holes expose the capacitor contact structure; The isolation groove also penetrates the first support layer along the thickness direction; The capacitor structure includes: The lower electrode is located on the side wall and bottom of the capacitor hole, and is connected to the first support layer, the second support layer and the third support layer, and is in contact with the capacitor contact structure. A capacitor dielectric layer; the capacitor dielectric layer is located on the surface of the lower electrode and within the isolation groove; Upper electrode; the upper electrode is located on the surface of the capacitor dielectric layer.

6. The semiconductor structure according to claim 5, characterized in that, The upper electrodes also have a gap between them; the capacitor structure further includes: A conductive layer is filled in the gap.

7. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; Multiple spaced-apart capacitor contact structures are formed within the substrate; The capacitor contact structure includes a protrusion on the upper surface of the substrate, and byproducts of capacitor contact material remain between adjacent capacitor contact structures; An isolation structure is formed to fill the gap between adjacent capacitor contact structures, and the top surface of the isolation structure is not higher than the top surface of the capacitor contact structure; Forming an isolation groove; The isolation groove extends from the top surface of the isolation structure into the isolation structure and has a gap with the capacitor contact structure. The isolation groove cuts off the by-products of capacitor contact material remaining between adjacent capacitor contact structures.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The multiple capacitor contact structures are distributed in multiple rows and columns. The multiple capacitor contact structures located in the same column are arranged at intervals along a first direction, and the multiple capacitor contact structures located in the same row are arranged at intervals along a second direction, the second direction intersecting the first direction. The formation of the isolation groove includes: A first patterned mask layer is formed on the capacitor contact structure and the isolation structure; the first patterned mask layer includes a plurality of parallel spaced first mask patterns, the first mask patterns extend along a first direction, and the orthographic projection of the gap between adjacent first mask patterns on the upper surface of the substrate is located between two adjacent columns of capacitor contact structures. The isolation structure is etched based on the first patterned mask layer to form a plurality of spaced first isolation grooves; the first isolation grooves extend along the first direction and are located between two adjacent columns of the capacitor contact structures.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The process of forming a first patterned mask layer on the substrate includes: A first mask layer is formed on the capacitor contact structure and the isolation structure; Multiple parallel-spaced first sub-mask patterns are formed on the upper surface of the first mask layer and extend along the first direction; A first sacrificial pattern is formed on the sidewall of the first sub-mask pattern, and the first sub-mask pattern is removed to retain a plurality of first sacrificial patterns arranged in parallel and extending along the first direction. A first filling mask layer is formed; the first filling mask layer fills the gap between adjacent first sacrificial patterns, and the upper surface of the first filling mask layer is not higher than the upper surface of the first sacrificial pattern; Remove the first sacrificial pattern to form a first initial trench between adjacent first filler mask layers; The first mask layer is etched along the first initial trench to obtain the first patterned mask layer.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The process of forming a first sacrificial pattern on the sidewall of the first sub-mask pattern includes: A first sacrificial material layer is formed on the upper surface of the first mask layer exposed between adjacent first sub-mask patterns, the sidewalls of the first sub-mask patterns, and the top of the first sub-mask patterns; The first sacrificial material layer, which is exposed on the upper surface of the first mask layer between adjacent first sub-mask patterns and on top of the first sub-mask pattern, is removed. The first sacrificial material layer remaining on the sidewall of the first sub-mask pattern is the first sacrificial pattern.

11. The method for preparing a semiconductor structure according to claim 9, characterized in that, The formation of the first filling mask layer includes: A first filler material layer is formed on the first mask layer; the first filler material layer fills the gap between adjacent first sacrificial patterns and covers the first sacrificial patterns; The first filler material layer is etched back to remove the first filler material layer on top of the first sacrificial pattern, and the first filler material layer located between adjacent first sacrificial patterns is retained as the first filler mask layer.

12. The method for preparing a semiconductor structure according to claim 8, characterized in that, The method of forming the isolation groove also includes: A second patterned mask layer is formed on the capacitor contact structure and the isolation structure; the second patterned mask layer includes a plurality of parallel and spaced second mask patterns, the second mask patterns extend along a second direction, the second direction intersects with the first direction, and the orthographic projection of the gap between adjacent second mask patterns on the upper surface of the substrate is located between two adjacent rows of capacitor contact structures; The isolation structure is etched based on the second patterned mask layer to form a plurality of spaced second isolation grooves; the second isolation grooves extend along the second direction and are located between two adjacent rows of the capacitor contact structures, and penetrate the plurality of first isolation grooves.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, Before forming the isolation groove on the capacitor contact structure and the isolation structure, the method further includes: forming a pattern transfer material layer. Before etching the isolation structure, the first mask pattern and the second mask pattern are transferred to the pattern transfer material layer to form a pattern transfer layer; The isolation structure is etched based on the first patterned mask layer, the second patterned mask layer and the pattern transfer layer to form a plurality of spaced first isolation grooves and second isolation grooves.

14. The method for preparing a semiconductor structure according to any one of claims 7 to 13, characterized in that, After forming the isolation groove, the method further includes: Multiple capacitor structures are formed on the substrate, and each capacitor structure makes contact with a capacitor contact structure in a one-to-one correspondence.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, Forming multiple capacitor structures on the substrate includes: A first support layer is formed on the upper surface of the isolation structure; the first support layer covers the top surface of the capacitive contact structure, and the isolation groove penetrates the first support layer along the thickness direction; After the isolation groove is formed, a first capacitor sacrificial layer is formed on the first support layer; the first capacitor sacrificial layer fills the isolation groove. A second support layer is formed on the upper surface of the first capacitor sacrificial layer; A second capacitor sacrificial layer is formed on the upper surface of the second support layer; A third support layer is formed on the upper surface of the second capacitor sacrificial layer; Multiple capacitor holes are formed; the capacitor holes penetrate the third support layer, the second capacitor sacrificial layer, the second support layer, the first capacitor sacrificial layer and the first support layer to expose the capacitor contact structure; A lower electrode is formed on the sidewall and bottom of the capacitor hole; Remove the first capacitor sacrificial layer and the second capacitor sacrificial layer; A capacitor dielectric layer is formed on the surface of the lower electrode and within the isolation groove; An upper electrode is formed on the surface of the capacitor dielectric layer.

16. The method for preparing a semiconductor structure according to claim 15, characterized in that, The upper electrodes have gaps between them; after forming the upper electrodes, the process further includes: A conductive filling layer is formed, wherein the conductive filling layer at least fills the gap.

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