Fault diagnosis circuit, electronic circuit, physical quantity detection circuit and sensor

Abstract

A failure diagnosis circuit, an electronic circuit, a physical quantity detection circuit, and a sensor can reduce the possibility of erroneously determining that a circuit generating a reference voltage has failed even if the reference voltage temporarily varies. A failure diagnosis circuit performs failure diagnosis of a reference voltage generation circuit that supplies a reference voltage to an analog / digital conversion circuit, the timing of the failure diagnosis being different from the timing of the temporary variation of the reference voltage with the operation of the analog / digital conversion circuit, the timing of the temporary variation being the timing at which the analog / digital conversion circuit starts sampling or the timing at which the analog / digital conversion circuit ends the sampling.

Description

[0001] This invention patent application is a divisional application of the invention patent application entitled "Physical Quantity Detection Circuit, Physical Quantity Sensor and Fault Diagnosis Method Thereof", filed on January 22, 2021, with application number "202110088020.9". Technical Field

[0002] This invention relates to fault diagnosis circuits, electronic circuits, physical quantity detection circuits, and physical quantity sensors. Background Technology

[0003] Currently, gyroscopes (detecting angular velocity) and accelerometers (detecting acceleration), capable of detecting various physical quantities, are widely used in various systems and electronic devices. In recent years, for example, to construct systems requiring high reliability, such as those used in vehicles, physical quantity sensors are sometimes required to have the ability to diagnose their own faults. Furthermore, in recent years, to build highly reliable systems, physical quantity sensors that output the detected physical quantity information as noise-resistant digital data have been used. Typically, such physical quantity sensors have a physical quantity detection element and a physical quantity detection circuit. The detection circuit generates an analog signal corresponding to the detected physical quantity based on the signal output from the physical quantity detection element, which is then converted into a digital signal by an A / D converter circuit and processed digitally.

[0004] Patent Document 1 discloses a power monitoring device for a vehicle electronic circuit that monitors the output voltage of the power circuit and outputs a power fault signal when the output voltage deviates from a predetermined range. Patent Document 2 discloses a fault detection device comprising multiple sensors, an analog-to-digital converter (ADC) that converts the output voltages of the multiple sensors into digital values, a reference voltage supply unit that provides a reference voltage to the multiple sensors and the ADC, and a unit that determines that the reference voltage supply unit has malfunctioned when at least two of the ADC conversion values ​​of the output voltages of the multiple sensors are detected to be outside the predetermined range.

[0005] For example, by applying the power monitoring device described in Patent Document 1 and the fault detection device described in Patent Document 2, physical quantity sensors that can diagnose their own faults can be realized.

[0006] Patent Document 1: Japanese Patent Application Publication No. 58-54830

[0007] Patent Document 2: Japanese Patent Application Publication No. 4-81615

[0008] However, in physical quantity sensors that employ the power monitoring device described in Patent Document 1 or the fault detection device described in Patent Document 2, the operation of the signal processing circuit that processes the signal output from the physical quantity detection element and the analog / digital conversion circuit that converts the output signal of the signal processing circuit into a digital signal may lead to the erroneous judgment that the circuit generating the reference voltage has malfunctioned when the reference voltage temporarily fluctuates and falls outside the specified range. Summary of the Invention

[0009] The fault diagnosis circuit of the present invention performs fault diagnosis on the reference voltage generation circuit that provides a reference voltage to the analog-to-digital conversion circuit. The timing of the fault diagnosis is different from the timing of the reference voltage temporarily changing with the operation of the analog-to-digital conversion circuit. The timing of the temporary change is the timing when the analog-to-digital conversion circuit starts sampling or the timing when the sampling ends.

[0010] The electronic circuit of the present invention includes: the aforementioned fault diagnosis circuit; the analog-to-digital conversion circuit; and the reference voltage generation circuit.

[0011] Alternatively, the fault diagnosis circuit of the present invention performs fault diagnosis on a reference voltage generation circuit that provides a reference voltage to a physical quantity signal processing circuit. The physical quantity signal processing circuit generates a detection signal based on the output signal of the physical quantity detection element. The timing of the fault diagnosis is different from the timing of the reference voltage that temporarily changes with the operation of the physical quantity signal processing circuit. The timing of the temporary change is the timing of at least one of the rising edge and falling edge of the drive signal that drives the physical quantity detection element.

[0012] Alternatively, the fault diagnosis circuit of the present invention performs fault diagnosis on a reference voltage generation circuit that provides a reference voltage to a physical quantity signal processing circuit. The physical quantity signal processing circuit generates a detection signal based on the output signal of the physical quantity detection element. The timing of the fault diagnosis is different from the timing of the reference voltage that temporarily changes with the operation of the physical quantity signal processing circuit. The timing of the temporary change is the timing of at least one of the rising edge and falling edge of the control signal of the control circuit that controls the physical quantity signal processing circuit.

[0013] The physical quantity detection circuit of the present invention includes: the aforementioned fault diagnosis circuit; the physical quantity signal processing circuit; the reference voltage generation circuit; and the control circuit.

[0014] The physical quantity sensor of the present invention includes: the physical quantity detection circuit; and the physical quantity detection element. Attached Figure Description

[0015] Figure 1 This is a functional block diagram of the physical quantity sensor in the first embodiment.

[0016] Figure 2 This is a diagram illustrating an example of the structure of a selection circuit and an analog-to-digital conversion circuit.

[0017] Figure 3 This is a diagram illustrating an example of a channel structure for time-division processing performed by an analog-to-digital converter circuit.

[0018] Figure 4 This is a diagram showing a portion of the reference voltage generation circuit and a structural example of the fault diagnosis circuit in the first embodiment.

[0019] Figure 5 This is a diagram showing an example of the waveforms of various signals when the reference voltage generation circuit in the first embodiment does not malfunction.

[0020] Figure 6 This is a diagram showing an example of the waveforms of various signals when the reference voltage generation circuit malfunctions in the first embodiment.

[0021] Figure 7 This is a flowchart illustrating an example of the steps of the fault diagnosis method of the first embodiment.

[0022] Figure 8 This is a functional block diagram of the physical quantity sensor in the second embodiment.

[0023] Figure 9 This is a diagram showing a portion of the reference voltage generation circuit and a structural example of the fault diagnosis circuit in the second embodiment.

[0024] Figure 10 This is a diagram showing an example of the waveforms of various signals when the reference voltage generation circuit in the second embodiment does not malfunction.

[0025] Figure 11 This is a diagram showing an example of the waveforms of various signals when the reference voltage generation circuit malfunctions in the second embodiment.

[0026] Figure 12 This is a flowchart illustrating an example of the steps of the fault diagnosis method according to the second embodiment.

[0027] Label Explanation

[0028] 1: Physical quantity sensor; 2: Physical quantity detection circuit; 3: Angular velocity detection element; 4X: Acceleration detection element; 4Y: Acceleration detection element; 10: Angular velocity signal processing circuit; 11: Drive circuit; 12: Detection circuit; 20: Acceleration signal processing circuit; 21: Drive circuit; 22X: Detection circuit; 22Y: Detection circuit; 30: Temperature sensor; 40: Reference voltage generation circuit; 50: Selection circuit; 51p, 51n, 52p, 52n, 53p, 53n, 54p, 54n, 55p, 55n: Low-pass filter; 56: Multiplexer; 60: Analog-to-digital converter circuit; 61: Pre-charge circuit; 62: Programmable gain amplifier; 63: Successive approximation analog-to-digital converter; 64: SAR control circuit; 7 0: Digital signal processing circuit; 80: Fault diagnosis circuit; 81: Anomaly detection circuit; 82: Fault diagnosis signal output circuit; 90: Control circuit; 100: Storage unit; 110: Interface circuit; 120: Oscillator circuit; 130: Fault diagnosis circuit; 131: Anomaly detection circuit; 132: Fault diagnosis signal output circuit; 141: Bandgap reference circuit; 142: Resistor; 143: Resistor; 144: Operational amplifier; 145: Bandgap reference circuit; 146: Resistor; 147: Resistor; 148: Operational amplifier; 181: Comparator; 182: Comparator; 183: Logic OR circuit; 184: D-type flip-flop; 200: Logic circuit; 231: Comparator; 232: Comparator; 233: Logic OR circuit; 234: D-type flip-flop. Detailed Implementation

[0029] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Furthermore, the embodiments described below are not intended to unduly limit the scope of the invention as defined in the claims. Additionally, not all structures described below are necessarily essential elements of the present invention.

[0030] The following explanation will be based on a physical quantity sensor that detects angular velocity and acceleration as physical quantities.

[0031] 1. Physical quantity sensor

[0032] 1-1. First Implementation Method

[0033] 1-1-1. Structure of a physical quantity sensor

[0034] Figure 1 This is a functional block diagram of the physical quantity sensor according to the first embodiment. The physical quantity sensor 1 of the first embodiment includes a physical quantity detection circuit 2, an angular velocity detection element 3, an acceleration detection element 4X, and an acceleration detection element 4Y.

[0035] Acceleration detection elements 4X and 4Y are physical quantity detection elements that detect acceleration as a physical quantity. Acceleration detection element 4X detects acceleration in the X-axis direction, and acceleration detection element 4Y detects acceleration in the Y-axis direction, which is perpendicular to the X-axis. For example, acceleration detection elements 4X and 4Y can be elements that have an electrostatic capacitor with a drive electrode and a detection electrode (not shown), the charge of the electrostatic capacitor changing according to the acceleration, and outputting a signal corresponding to the amount of charge. Acceleration detection elements 4X and 4Y can also be MEMS (Micro Electro Mechanical Systems) elements, for example.

[0036] Angular velocity detection element 3 is a physical quantity detection element that detects angular velocity as a physical quantity. In this embodiment, angular velocity detection element 3 detects the angular velocity about the Z-axis, which is perpendicular to the X-axis and Y-axis. For example, angular velocity detection element 3 can be an element having a vibrating plate with a drive electrode and a detection electrode (not shown), the magnitude of which varies according to the angular velocity, and outputting a signal corresponding to the magnitude of the vibration. Angular velocity detection element 3 can also be, for example, an element with a so-called double-T-shaped quartz vibrating plate, which has two T-shaped drive vibrating arms.

[0037] The physical quantity detection circuit 2 includes an angular velocity signal processing circuit 10, an acceleration signal processing circuit 20, a temperature sensor 30, a reference voltage generation circuit 40, a selection circuit 50, an analog-to-digital conversion circuit 60, a digital signal processing circuit 70, a fault diagnosis circuit 80, a control circuit 90, a storage unit 100, an interface circuit 110, and an oscillation circuit 120. The physical quantity detection circuit 2 can also be implemented using a single-chip integrated circuit, for example. Furthermore, the physical quantity detection circuit 2 can be configured by omitting or modifying some of these elements, or by adding other elements.

[0038] The reference voltage generation circuit 40 generates various reference voltages based on the power supply voltage VDD and ground voltage VSS provided externally from the physical quantity detection circuit 2. In this embodiment, the reference voltage generation circuit 40 generates the power supply voltage VGR and the common voltage VCMGR as reference voltages provided to the angular velocity signal processing circuit 10. Additionally, the reference voltage generation circuit 40 generates the power supply voltage VCC and the common voltage VCMACC as reference voltages provided to the acceleration signal processing circuit 20. Furthermore, the reference voltage generation circuit 40 generates the full-scale voltage VFSAD and the common voltage VCMAD as reference voltages provided to the analog-to-digital conversion circuit 60. Additionally, the reference voltage generation circuit 40 generates the power supply voltage VTS and the common voltage VCMTS as reference voltages provided to the temperature sensor 30. Furthermore, the reference voltage generation circuit 40 generates the power supply voltage VLGC as a reference voltage provided to the logic circuit 200. Finally, the reference voltage generation circuit 40 generates the power supply voltage VOSC as a reference voltage provided to the oscillation circuit 120.

[0039] The oscillation circuit 120 operates based on the power supply voltage VOSC provided from the reference voltage generation circuit 40 to generate a clock signal MCK. The oscillation circuit 120 may also be configured as a ring oscillator or a CR oscillation circuit, for example.

[0040] The angular velocity signal processing circuit 10 includes a drive circuit 11 and a detection circuit 12, and operates based on the power supply voltage VGR and the common voltage VCMGR provided from the reference voltage generation circuit 40.

[0041] The drive circuit 11 generates a drive signal DRVGR for exciting the angular velocity detection element 3 to vibrate, and provides it to the angular velocity detection element 3. For example, the drive signal DRVGR is a rectangular wave signal that sets the power supply voltage VGR to a high level and the ground voltage VSS to a low level. Additionally, the drive circuit 11 receives an oscillating current generated by the excited vibration of the angular velocity detection element 3, and performs feedback control on the amplitude level of the drive signal to keep the amplitude of the oscillating current constant. When the angular velocity detection element 3 is subjected to an angular velocity about the Z-axis under excited vibration conditions, it detects the angular velocity and outputs a signal corresponding to that angular velocity. In this embodiment, the signal output from the angular velocity detection element 3 is a differential signal.

[0042] The detection circuit 12 is a detection signal generation circuit that generates a detection signal corresponding to the angular velocity around the Z-axis based on the output signal of the angular velocity detection element 3. Specifically, the detection circuit 12 detects the angular velocity component contained in the signal output from the angular velocity detection element 3, generates and outputs an angular velocity detection signal GRO1 whose voltage level corresponds to the magnitude of the angular velocity component. Additionally, the detection circuit 12 detects the vibration leakage component contained in the signal output from the angular velocity detection element 3, generates and outputs a vibration leakage signal GRO2 whose voltage level corresponds to the magnitude of the vibration leakage component. In this embodiment, the angular velocity detection signal GRO1 and the vibration leakage signal GRO2 are differential signals based on a common voltage VCMGR.

[0043] Thus, the angular velocity signal processing circuit 10 is a physical quantity signal processing circuit that outputs the drive signal DRVGR to drive the angular velocity detection element 3 and generates a detection signal corresponding to the angular velocity around the Z-axis, which is one of the physical quantities, based on the output signal of the angular velocity detection element 3.

[0044] The acceleration signal processing circuit 20 includes a drive circuit 21, a detection circuit 22X, and a detection circuit 22Y, and operates based on the power supply voltage VCC and the common voltage VCMACC provided from the reference voltage generation circuit 40. Furthermore, the acceleration signal processing circuit 20 is controlled based on n control signals CTL1 to CTLn provided from the control circuit 90. n is an integer greater than or equal to 1.

[0045] The drive circuit 21 generates a drive signal DRVCC and outputs it to the acceleration detection elements 4X and 4Y to drive them. For example, the drive signal DRVCC is a rectangular wave signal that sets the power supply voltage VCC to a high level and the ground voltage VSS to a low level. When an acceleration in the X-axis direction is applied in this state, the acceleration detection element 4X detects the acceleration and outputs a signal corresponding to the acceleration. Similarly, when an acceleration in the Y-axis direction is applied, the acceleration detection element 4Y detects the acceleration and outputs a signal corresponding to the acceleration. In this embodiment, the signals output from the acceleration detection elements 4X and 4Y are differential signals.

[0046] The detection circuit 22X is a detection signal generation circuit that generates a detection signal corresponding to the acceleration in the X-axis direction based on the output signal of the acceleration detection element 4X. Specifically, the detection circuit 22X detects the acceleration component contained in the signal output from the acceleration detection element 4X, generates an X-axis acceleration detection signal AXO with a voltage level corresponding to the magnitude of the acceleration component, and outputs it. In this embodiment, the X-axis acceleration detection signal AXO is a differential signal based on a common voltage VCMACC.

[0047] The detection circuit 22Y is a detection signal generation circuit that generates a detection signal corresponding to the acceleration in the Y-axis direction based on the output signal of the acceleration detection element 4Y. Specifically, the detection circuit 22Y detects the acceleration component contained in the signal output from the acceleration detection element 4Y, generates a Y-axis acceleration detection signal AYO with a voltage level corresponding to the magnitude of the acceleration component, and outputs it. In this embodiment, the Y-axis acceleration detection signal AYO is a differential signal based on a common voltage VCMACC.

[0048] Thus, the acceleration signal processing circuit 20 is a physical quantity signal processing circuit that outputs a drive signal DRVACC to drive the acceleration detection elements 4X and 4Y, and generates a detection signal corresponding to the acceleration in the X-axis direction, which is one of the physical quantities, based on the output signal of the acceleration detection element 4X, and generates a detection signal corresponding to the acceleration in the Y-axis direction, which is one of the physical quantities, based on the output signal of the acceleration detection element 4Y.

[0049] Temperature sensor 30 detects temperature based on the power supply voltage VTS and common voltage VCMTS provided by reference voltage generation circuit 40, and outputs a temperature detection signal TSO with a voltage level corresponding to the temperature. Temperature sensor 30 may, for example, be a circuit utilizing the temperature characteristics of a bandgap reference circuit. In this embodiment, the temperature detection signal TSO is a differential signal referenced to the common voltage VCMTS.

[0050] The selection circuit 50 selects and outputs any one of the following signals based on the selection signal SEL from the control circuit 90: angular velocity detection signal GRO1, vibration leakage signal GRO2, X-axis acceleration detection signal AXO, Y-axis acceleration detection signal AYO, and temperature detection signal TSO. In this embodiment, the output signal MXO of the selection circuit 50 is a differential signal.

[0051] The analog-to-digital converter 60 operates based on the full-scale voltage VFSAD and the common voltage VCMAD provided by the reference voltage generation circuit 40. The analog-to-digital converter 60 converts the output signal MXO of the selection circuit 50 into a digital signal ADO and outputs it based on various control signals provided by the control circuit 90. Specifically, the analog-to-digital converter 60 uses the voltage difference between the full-scale voltage VFSAD and the ground voltage VSS as the full-scale value, and converts the signal MXO, which is a differential signal, into the digital signal ADO.

[0052] The digital signal processing circuit 70 processes the digital signal ADO output from the analog-to-digital converter circuit 60 based on various control signals provided by the control circuit 90. For example, the digital signal processing circuit 70 outputs a digital signal DSPO after digital filtering or correction processing of the digital signal ADO.

[0053] The fault diagnosis circuit 80 monitors the common voltage VCMAD, performs fault diagnosis on the reference voltage generation circuit 40, and outputs a fault diagnosis signal FLG2 indicating the result of the fault diagnosis. In particular, in this embodiment, the fault diagnosis circuit 80 performs fault diagnosis on the reference voltage generation circuit 40 at a predetermined timing that differs from the timing at which the common voltage VCMAD temporarily changes with the operation of the analog-to-digital conversion circuit 60.

[0054] For example, the timing of the temporary fluctuation of the common voltage VCMAD could be the timing at which the analog-to-digital converter 60 begins sampling the output signal MXO of the selection circuit 50, and the fault diagnosis circuit 80 performs fault diagnosis at a predetermined timing different from this timing. Alternatively, for example, the timing of the temporary fluctuation of the common voltage VCMAD could be the timing at which the analog-to-digital converter 60 ends sampling the output signal MXO of the selection circuit 50, and the fault diagnosis circuit 80 performs fault diagnosis at a predetermined timing different from this timing.

[0055] In this embodiment, the fault diagnosis circuit 80 includes an anomaly determination circuit 81 and a fault diagnosis signal output circuit 82.

[0056] The anomaly detection circuit 81 determines whether the common voltage VCMAD is abnormal and outputs an anomaly detection signal FLG1 indicating the detection result. For example, the anomaly detection signal FLG1 can be a flag signal that goes high when the common voltage VCMAD is abnormal and goes low when the common voltage VCMAD is normal.

[0057] The fault diagnosis signal output circuit 82 receives the abnormality determination signal FLG1 at a predetermined timing and outputs the fault diagnosis signal FLG2. For example, the fault diagnosis signal FLG2 can also be a flag signal that becomes high when the reference voltage generation circuit 40 malfunctions and low when the reference voltage generation circuit 40 does not malfunction. In this embodiment, the fault diagnosis signal output circuit 82 receives the abnormality determination signal FLG1 at the rising edge of the clock signal WCK provided from the control circuit 90 and outputs the fault diagnosis signal FLG2. As will be described later, the timing of the rising edge of the clock signal WCK is a predetermined timing that differs from the timing of the common voltage VCMAD, which temporarily varies with the operation of the analog-to-digital conversion circuit 60.

[0058] The control circuit 90 generates and outputs various control signals, clock signal WCK, selection signal SEL, and control signals CTL1 to CTLn for controlling the operation of the analog-to-digital conversion circuit 60, digital signal processing circuit 70, etc.

[0059] The storage unit 100 includes a non-volatile memory (not shown) that stores various trimming data for the angular velocity signal processing circuit 10, the acceleration signal processing circuit 20, etc., as well as coefficient data for processing by the digital signal processing circuit 70. The non-volatile memory can be configured as, for example, a MONOS (Metal Oxide Nitride Oxide Silicon) type memory or an EEPROM (Electrically Erasable Programmable Read-Only Memory). Furthermore, the storage unit 100 can also be configured to include a register (not shown) in which various data stored in the non-volatile memory are transferred and stored in the register when the physical quantity detection circuit 2 is powered on, i.e., when the voltage at the VDD terminal rises from 0V to a desired voltage. The data stored in the register is then provided to the respective circuits.

[0060] The interface circuit 110 processes requests from external devices to output digital signal DSPO or fault diagnosis signal FLG2. Additionally, based on requests from external devices in the physical quantity detection circuit 2, the interface circuit 110 performs processes such as reading and outputting data stored in the non-volatile memory or register of the storage unit 100, and writing data input from external devices into the non-volatile memory or register of the storage unit 100. The interface circuit 110 may be, for example, an interface circuit for an SPI (Serial Peripheral Interface) bus, or an I... 2 The interface circuit of the C (Inter-Integrated Circuit) bus.

[0061] The digital signal processing circuit 70, the fault diagnosis signal output circuit 82, the control circuit 90, the storage unit 100, and the interface circuit 110 constitute the logic circuit 200. The logic circuit 200 operates based on the power supply voltage VLGC provided from the reference voltage generation circuit 40 and according to the clock signal MCK. 1-1-2. Structure of the selection circuit and the analog / digital conversion circuit

[0062] Figure 2 This is a diagram illustrating an example of the structure of the selection circuit 50 and the analog-to-digital conversion circuit 60. Figure 2 In the example, the selection circuit 50 includes 10 low-pass filters 51p, 51n, 52p, 52n, 53p, 53n, 54p, 54n, 55p, 55n and a multiplexer 56.

[0063] The differential signals GRO1_P and GRO1_N that constitute the angular velocity detection signal GRO1 are low-pass filtered by low-pass filters 51p and 51n respectively and then input to multiplexer 56.

[0064] The differential signals GRO2_P and GRO2_N that constitute the vibration leakage signal GRO2 are low-pass filtered by low-pass filters 52p and 52n respectively and then input to multiplexer 56.

[0065] The differential signals AXO_P and AXO_N that constitute the X-axis acceleration detection signal AXO are low-pass filtered by low-pass filters 53p and 53n respectively and then input to multiplexer 56.

[0066] The differential signals AYO_P and AYO_N that constitute the Y-axis acceleration detection signal AYO are low-pass filtered by low-pass filters 54p and 54n respectively and then input to multiplexer 56.

[0067] The differential signals TSO_P and TSO_N that constitute the temperature detection signal TSO are low-pass filtered by low-pass filters 55p and 55n respectively and then input to the multiplexer 56.

[0068] The multiplexer 56 selects any one of the following differential signals after low-pass filtering: GRO1_P, GRO1_N, GRO2_P, GRO2_N, AXO_P, AXO_N, AYO_P, AYO_N, and TSO_P, TSO_N, and outputs them as differential signals MXO_P and MXO_N, based on the selection signal SEL.

[0069] exist Figure 2 In the example, the analog-to-digital conversion circuit 60 includes a pre-charge circuit 61, a programmable gain amplifier 62, a successive approximation register (SAR) analog-to-digital converter 63, and a SAR control circuit 64.

[0070] The pre-charge circuit 61 charges the input node of the programmable gain amplifier 62 before the successive approximation analog-to-digital converter 63 begins conversion processing, based on the control signal provided from the control circuit 90, thereby assisting in charging based on the differential signals MXO_P and MXO_N.

[0071] The programmable gain amplifier 62 outputs differential signals PO_P and PO_N, which are amplified from the differential signals MXO_P and MXO_N. The gain of the programmable gain amplifier 62 can be variably set according to the type of differential signal, which is selected as differential signals MXO_P and MXO_N according to the control signal provided from the control circuit 90.

[0072] The successive approximation analog-to-digital converter 63 uses the voltage difference between the full-scale voltage VFSAD and the ground voltage VSS as the full-scale value, and converts the voltage difference between the differential signals PO_P and PO_N into a digital signal ADO and outputs it.

[0073] The SAR control circuit 64 operates according to the clock signal MCK, and performs timing based on successive comparisons by the successive approximation analog-to-digital converter 63, and selects the voltage as the comparison reference based on the comparison result.

[0074] 1-1-3. Channel Structure for Time-Division Processing

[0075] As described above, the analog-to-digital converter 60 converts the differential signal selected by the selection circuit 50 based on the selection signal SEL into a digital signal ADO and outputs it. That is, the analog-to-digital converter 60 performs time-division processing on the angular velocity detection signal GRO1, the vibration leakage signal GRO2, the X-axis acceleration detection signal AXO, the Y-axis acceleration detection signal AYO, and the temperature detection signal TSO and converts them into digital signals respectively.

[0076] Figure 3 This is a diagram illustrating an example of the channel structure for time-division processing performed by the analog-to-digital conversion circuit 60.

[0077] like Figure 3 As shown, in the first channel, the 3-bit selection signal SEL is "000", and the selection circuit 50 selects the angular velocity detection signal GRO1 as the input signal to the analog-to-digital converter 60. Therefore, during the first channel, the analog-to-digital converter 60 converts the angular velocity detection signal GRO1 (specifically, the voltage difference between the differential signals GRO1_P and GRO1_N) into the digital signal ADO. Thus, processing of the angular velocity detection signal GRO1 is performed in the first channel.

[0078] In the second channel following the first channel, the 3-bit selection signal SEL is "001", and the selection circuit 50 selects the vibration leakage signal GRO2 as the input signal to the analog-to-digital converter 60. Therefore, during the second channel, the analog-to-digital converter 60 converts the vibration leakage signal GRO2 (specifically, the voltage difference between the differential signals GRO2_P and GRO2_N) into the digital signal ADO. Thus, processing of the vibration leakage signal GRO2 is performed in the second channel.

[0079] In the third channel following the second channel, the 3-bit selection signal SEL is "010", and the selection circuit 50 selects the X-axis acceleration detection signal AXO as the input signal for the analog-to-digital converter 60. Therefore, during the third channel, the analog-to-digital converter 60 converts the X-axis acceleration detection signal AXO (specifically, the voltage difference between the differential signals AXO_P and AXO_N) into the digital signal ADO. Thus, processing of the X-axis acceleration detection signal AXO is performed in the third channel.

[0080] In the fourth channel following the third channel, the 3-bit selection signal SEL is "011", and the selection circuit 50 selects the Y-axis acceleration detection signal AYO as the input signal for the analog-to-digital converter 60. Therefore, during the fourth channel, the analog-to-digital converter 60 converts the Y-axis acceleration detection signal AYO (specifically, the voltage difference between the differential signals AYO_P and AYO_N) into the digital signal ADO. Thus, processing of the Y-axis acceleration detection signal AYO is performed in the fourth channel.

[0081] In the fifth channel, following the fourth channel, the 3-bit selection signal SEL is "100", and the selection circuit 50 selects the temperature detection signal TSO as the input signal to the analog-to-digital converter 60. Therefore, during the fifth channel, the analog-to-digital converter 60 converts the temperature detection signal TSO (specifically, the voltage difference between the differential signals TSO_P and TSO_N) into the digital signal ADO. Thus, processing of the temperature detection signal TSO is performed in the fifth channel.

[0082] After channel 5, it returns to channel 1. That is, multiple periods from channel 1 to channel 5 are repeated sequentially. In the digital signal processing circuit 70, the order or coefficient value of the digital filter, the type or coefficient value of the correction operation, etc., are changed according to the correspondence between each channel and the signal to be processed.

[0083] 1-1-4. Structure of Fault Diagnosis Circuit

[0084] Figure 4 This is a diagram illustrating a portion of the reference voltage generation circuit 40 and a structural example of the fault diagnosis circuit 80. Figure 4 In the example, the reference voltage generation circuit 40 includes a bandgap reference circuit 141, resistors 142 and 143, and an operational amplifier 144.

[0085] The bandgap reference circuit 141 is a circuit that uses the bandgap voltage of a semiconductor element to generate a constant full-scale voltage VFSAD that is stable relative to variations in temperature or power supply voltage VDD. Since the structure of the bandgap reference circuit is well-known, its illustration and description are omitted.

[0086] Resistors 142 and 143 have the same resistance value R. The voltage obtained by dividing the full-scale voltage VFSAD by 1 / 2 through resistors 142 and 143 is provided to the non-inverting input terminal of operational amplifier 144.

[0087] The inverting input terminal of operational amplifier 144 is connected to the output terminal of operational amplifier 144, which functions as a voltage follower. Therefore, the output terminal of operational amplifier 144 is half of the full-scale voltage VFSAD, which is output from the reference voltage generation circuit 40 as the common voltage VCMAD.

[0088] The fault diagnosis circuit 80 includes comparators 181 and 182, a logic OR circuit 183, and a D-type flip-flop 184.

[0089] A common voltage VCMAD is provided to the inverting input terminal of comparator 181, and a specified threshold voltage VL is provided to the non-inverting input terminal of comparator 181. When the common voltage VCMAD is above the threshold voltage VL, the output terminal of comparator 181 is at a low level; when the common voltage VCMAD is below the threshold voltage VL, the output terminal of comparator 181 is at a high level.

[0090] A common voltage VCMAD is provided to the non-inverting input terminal of comparator 182, and a predetermined threshold voltage VH, which is higher than the threshold voltage VL, is provided to the inverting input terminal of comparator 182. When the common voltage VCMAD is below the threshold voltage VH, the output terminal of comparator 182 is at a low level, and when the common voltage VCMAD is above the threshold voltage VH, the output terminal of comparator 182 is at a high level.

[0091] The logic OR circuit 183 is input to the output signals of comparator 181 and comparator 182, and outputs a logic OR signal of these signals. That is, the output signal of the logic OR circuit 183 is low when both the output signals of comparator 181 and comparator 182 are low, and high when at least one of the output signals of comparator 181 and comparator 182 is high.

[0092] Therefore, when the common voltage VCMAD is above the threshold voltage VL and below the threshold voltage VH, the output signal of the OR circuit 183 is low; when the common voltage VCMAD is below the threshold voltage VL or above the threshold voltage VH, the output signal of the OR circuit 183 is high. The comparators 181 and 182, along with the OR circuit 183, constitute the anomaly determination circuit 81. The output signal of the OR circuit 183 becomes the anomaly determination signal FLG1. That is, when the common voltage VCMAD is above the threshold voltage VL and below the threshold voltage VH, the anomaly determination circuit 81 determines that the common voltage VCMAD is normal; when the common voltage VCMAD is below the threshold voltage VL or above the threshold voltage VH, it determines that the common voltage VCMAD is abnormal and outputs the anomaly determination signal FLG1 indicating the determination result.

[0093] In addition, the threshold voltages VL and VH can be fixed values ​​or can be variably set in the storage unit 100.

[0094] In the D-type flip-flop 184, the data input terminal D is input with an abnormality determination signal FLG1, and the clock input terminal is input with a clock signal WCK. At the rising edge of the clock signal WCK, the D-type flip-flop 184 takes in the abnormality determination signal FLG1 and outputs the fault diagnosis signal FLG2.

[0095] exist Figure 4 In the example, the common voltage VCMAD is obtained by dividing the full-scale voltage VFSAD into half through resistors 142 and 143. Therefore, if the full-scale voltage VFSAD is always abnormal, the common voltage VCMAD will also always be abnormal, and the fault detection signal FLG1 will always be high. Thus, whether the operational amplifier 144 malfunctions and the common voltage VCMAD is always abnormal, or the bandgap reference circuit 141 malfunctions and the full-scale voltage VFSAD is always abnormal, the fault diagnosis signal FLG2 will be high, and the fault diagnosis circuit 80 can diagnose that the reference voltage generation circuit 40 has malfunctioned.

[0096] Figure 5 This is a diagram illustrating an example of the waveforms of various signals, including the common voltage VCMAD, the fault determination signal FLG1, and the fault diagnosis signal FLG2, when the reference voltage generation circuit 40 is functioning correctly. Additionally, Figure 6 This is a diagram illustrating an example of the waveforms of various signals, including the common voltage VCMAD, the fault determination signal FLG1, and the fault diagnosis signal FLG2, when the reference voltage generation circuit 40 malfunctions.

[0097] exist Figure 5 as well as Figure 6In the example, during the sampling period when the analog-to-digital converter 60 samples the voltage of the output signal MXO of the selection circuit 50, the status signal CONV is low; during the conversion period when the voltage sampled by the analog-to-digital converter 60 is held and converted into the digital signal ADO, the status signal CONV is high. Figure 5 and Figure 6 As shown, the analog-to-digital conversion circuit 60 alternates between the sampling period and the conversion period in a repetitive and synchronous manner with channels 1 through 5. Additionally, in the preceding... Figure 1 and Figure 2 The diagram of the status signal CONV is omitted in the text.

[0098] In this embodiment, to reduce the area of ​​the reference voltage generation circuit 40, it is assumed that the capability to provide the full-scale voltage VFSAD relative to the analog-to-digital converter circuit 60 may not be sufficient. Therefore, during the switching between the sampling and conversion periods of the analog-to-digital converter circuit 60, the full-scale voltage VFSAD varies considerably, accompanied by, as Figure 5 as well as Figure 6 As shown, the common voltage VCMAD also varies considerably. The timing for switching from the conversion period to the sampling period is the timing when the analog / digital converter 60 begins sampling the output signal MXO of the selection circuit 50. Conversely, the timing for switching from the sampling period to the conversion period is the timing when the analog / digital converter 60 ends sampling the output signal MXO of the selection circuit 50.

[0099] exist Figure 5 In the example, during the periodic switching between sampling and conversion periods, the common voltage VCMAD falls below the threshold voltage VL. As a result, the fault detection signal FLG1 periodically goes high during one cycle of the clock signal MCK. Even though the common voltage VCMAD is temporarily below the threshold voltage VL during the switching between sampling and conversion periods, the operation of the analog-to-digital converter 60 is unaffected; therefore, the reference voltage generation circuit 40 is not faulty. However, assuming that the fault detection signal FLG1 temporarily goes high during a temporary fluctuation in the common voltage VCMAD, the fault diagnosis signal output circuit 82 takes in the fault detection signal FLG1 and outputs a high-level fault diagnosis signal FLG2. Furthermore, if an external device reads the high-level fault diagnosis signal FLG2 via the interface circuit 110, the external device will mistakenly determine that the reference voltage generation circuit 40 has malfunctioned.

[0100] In addition, Figure 6 In the example, the reference voltage generation circuit 40 malfunctions, and the common voltage VCMAD is higher than the threshold voltage VH. In fact, with... Figure 5Similarly, during the switching between sampling and conversion periods in the analog-to-digital conversion circuit 60, the common voltage VCMAD fluctuates significantly, thus temporarily placing it between the threshold voltage VL and the threshold voltage VH. Therefore, in Figure 6 In the example, with Figure 5 Conversely, during the timing switch between sampling and conversion, the fault determination signal FLG1 temporarily goes low. Therefore, assuming the fault diagnosis signal output circuit 82 receives the fault determination signal FLG1 at the timing when it temporarily goes low, it outputs a low-level fault diagnosis signal FLG2. Furthermore, if an external device reads the low-level fault diagnosis signal FLG2 via interface circuit 110, it will mistakenly determine that the reference voltage generation circuit 40 has not malfunctioned.

[0101] In contrast, in this embodiment, the timing of the fault diagnosis signal output circuit 82 acquiring the abnormal judgment signal FLG1, i.e., the rising edge of the clock signal WCK, does not overlap with the timing of the temporary fluctuation of the common voltage VCMAD. In this embodiment, the control circuit 90 has a counter (not shown) that generates a control signal for the analog-to-digital conversion circuit 60 based on the counter's count value CNT. Figure 5 and Figure 6 In the example, the count value CNT is initialized to 0 in each channel and then increments from 0 to N one by one. The operation of the analog-to-digital converter 60 is controlled based on the count value CNT. Furthermore, the timing of the change of the count value CNT from k-1 to k, which is a timing that does not overlap with the timing of the switching between the sampling period and the conversion period of the analog-to-digital converter 60, i.e., the timing of the temporary change of the common voltage VCMAD, is set as the timing of the rising edge of the clock signal WCK.

[0102] Therefore, in Figure 5 In this example, the fault diagnosis signal output circuit 82 does not pick up the fault diagnosis signal FLG1 at the timing point when the fault diagnosis signal FLG1 temporarily becomes high, and the fault diagnosis signal FLG2 remains low. Therefore, even if the external device reads the fault diagnosis signal FLG2 through the interface circuit 110 at any timing, it can correctly determine that the reference voltage generation circuit 40 is not faulty.

[0103] In addition, Figure 6 In this example, the fault diagnosis signal output circuit 82 does not pick up the fault diagnosis signal FLG1 at the timing point when the fault diagnosis signal FLG1 temporarily goes low, and the fault diagnosis signal FLG2 remains at a high level. Therefore, even if the external device reads the fault diagnosis signal FLG2 through the interface circuit 110 at any timing, it can correctly determine that the reference voltage generation circuit 40 has failed.

[0104] 1-1-5. Steps in Fault Diagnosis Methods

[0105] The fault diagnosis method of the physical quantity sensor 1 in the first embodiment includes a fault diagnosis step of monitoring the common voltage VCMAD, which is one of the reference voltages, and performing fault diagnosis of the reference voltage generation circuit 40 to output a fault diagnosis signal FLG2 indicating the result of the fault diagnosis. In the fault diagnosis step, the fault diagnosis is performed at a predetermined timing that is different from the timing at which the common voltage VCMAD temporarily changes with the operation of the analog-to-digital conversion circuit 60.

[0106] Figure 7 This is a flowchart illustrating an example of the steps in the fault diagnosis method for the physical quantity sensor 1 according to the first embodiment. Additionally, in Figure 7 In the flowchart, the processing of each step can also be changed appropriately.

[0107] like Figure 7 As shown, when the common voltage VCMAD is within the specified voltage range ("Yes" in step S1), that is, when the common voltage VCMAD is above the threshold voltage VL and below the threshold voltage VH, the anomaly determination circuit 81 of the physical quantity sensor 1 sets the anomaly determination signal FLG1 to no anomaly (step S2). Specifically, the anomaly determination circuit 81 sets the anomaly determination signal FLG1 to a low level.

[0108] On the other hand, when the common voltage VCMAD is not within the specified voltage range (No in step S1), that is, when the common voltage VCMAD is lower than the threshold voltage VL or higher than the threshold voltage VH, the abnormality determination circuit 81 of the physical quantity sensor 1 sets the abnormality determination signal FLG1 to be abnormal (step S3). Specifically, the abnormality determination circuit 81 sets the abnormality determination signal FLG1 to a high level.

[0109] Before the fault diagnosis timing, which is set to a predetermined time, arrives (No in step S4), the anomaly determination circuit 81 repeats the processing of steps S1, S2, and S3. Then, when the fault diagnosis timing arrives (Yes in step S4), the fault diagnosis signal output circuit 82 of the physical quantity sensor 1 takes in the anomaly determination signal FLG1 and outputs the fault diagnosis signal FLG2 (step S5), and the anomaly determination circuit 81 repeats the processing of steps S1, S2, and S3 again.

[0110] in addition, Figure 7Steps S1 to S5 are equivalent to fault diagnosis steps. Furthermore, steps S1, S2, and S3 are fault determination steps where the fault determination circuit 81 determines whether the common voltage VCMAD, which is one of the reference voltages, is abnormal, and outputs an fault determination signal FLG1 indicating the determination result. Additionally, steps S4 and S5 are fault diagnosis signal output steps where the fault diagnosis signal output circuit 82 takes the abnormal determination signal FLG1 at a predetermined timing and outputs a fault diagnosis signal FLG2.

[0111] 1-1-6. Effects

[0112] In the first embodiment described above, the physical quantity detection circuit 2 includes a fault diagnosis circuit 80. This fault diagnosis circuit 80 monitors the common voltage VCMAD generated by the reference voltage generation circuit 40 and supplied to the analog-to-digital conversion circuit 60, performs fault diagnosis on the reference voltage generation circuit 40, and outputs a fault diagnosis signal FLG2 indicating the result of the fault diagnosis. The fault diagnosis circuit 80 performs fault diagnosis at a predetermined timing different from the timing at which the common voltage VCMAD temporarily changes with the operation of the analog-to-digital conversion circuit 60. According to this embodiment, since the fault diagnosis circuit 80 performs fault diagnosis at a predetermined timing different from the timing at which the common voltage VCMAD temporarily changes with the operation of the analog-to-digital conversion circuit 60, the possibility of erroneously judging that the reference voltage generation circuit 40 has failed can be reduced even if the common voltage VCMAD temporarily changes. For example, even if the supply capability based on the common voltage VCMAD of the reference voltage generation circuit 40 is low, the possibility of the fault diagnosis circuit 80 making an incorrect judgment can be reduced, thus the size of the reference voltage generation circuit 40 can be reduced, which is beneficial for cost reduction.

[0113] In particular, in this embodiment, the fault diagnosis circuit 80 performs fault diagnosis at a predetermined timing that is different from the timing at which the analog / digital conversion circuit 60 starts or ends sampling when the common voltage VCMAD changes temporarily. Therefore, even if the common voltage VCMAD changes temporarily, the possibility of mistakenly judging that the reference voltage generation circuit 40 has failed can be reduced.

[0114] Furthermore, in this embodiment, the fault diagnosis circuit 80 includes: an anomaly determination circuit 81, which determines whether the common voltage VCMAD is abnormal and outputs an anomaly determination signal FLG1 indicating the determination result; and a fault diagnosis signal output circuit 82, which takes in the anomaly determination signal FLG1 at a predetermined timing different from the timing at which the common voltage VCMAD temporarily changes with the operation of the analog / digital conversion circuit 60, and outputs a fault diagnosis signal FLG2. Therefore, according to this embodiment, even if the anomaly determination circuit 81 temporarily outputs the anomaly determination signal FLG1 indicating that the common voltage VCMAD is abnormal when the common voltage VCMAD temporarily changes, the fault diagnosis signal output circuit 82 can reduce the possibility of mistakenly outputting the fault diagnosis signal FLG2 indicating that the reference voltage generation circuit 40 has malfunctioned, instead of taking in the anomaly determination signal FLG1 indicating that the common voltage VCMAD is abnormal.

[0115] Thus, according to this embodiment, the possibility of erroneously judging that the reference voltage generation circuit 40 has failed can be reduced, thereby improving the reliability of fault diagnosis of the physical quantity detection circuit 2 and the physical quantity sensor 1.

[0116] 1-2. Second Implementation Method

[0117] Hereinafter, for the physical quantity sensor of the second embodiment, the same reference numerals are used for the same structural elements as in the first embodiment, and the contents that are repeated in the first embodiment are omitted or simplified. The description mainly focuses on the contents that are different from the first embodiment.

[0118] 1-2-1. Structure of a physical quantity sensor

[0119] Figure 8 This is a functional block diagram of the physical quantity sensor according to the second embodiment. The physical quantity sensor 1 of the second embodiment is the same as that of the first embodiment, and has a physical quantity detection circuit 2, an angular velocity detection element 3, an acceleration detection element 4X, and an acceleration detection element 4Y.

[0120] Since the functions of the angular velocity detection element 3, the acceleration detection element 4X, and the acceleration detection element 4Y are the same as those in the first embodiment, their descriptions are omitted.

[0121] Similar to the first embodiment, the physical quantity detection circuit 2 may include an angular velocity signal processing circuit 10, an acceleration signal processing circuit 20, a temperature sensor 30, a reference voltage generation circuit 40, a selection circuit 50, an analog-to-digital conversion circuit 60, a digital signal processing circuit 70, a control circuit 90, a storage unit 100, an interface circuit 110, an oscillation circuit 120, and a fault diagnosis circuit 130, and may be implemented, for example, by a single-chip integrated circuit. Alternatively, the physical quantity detection circuit 2 may have a structure that omits or modifies some of these elements, or adds other elements.

[0122] The functions of the angular velocity signal processing circuit 10, acceleration signal processing circuit 20, temperature sensor 30, reference voltage generation circuit 40, selection circuit 50, analog-to-digital conversion circuit 60, digital signal processing circuit 70, control circuit 90, storage unit 100, interface circuit 110, and oscillation circuit 120 are the same as in the first embodiment, so their descriptions are omitted.

[0123] The fault diagnosis circuit 130 monitors the common voltage VCMACC, which is one of the reference voltages, performs fault diagnosis on the reference voltage generation circuit 40, and outputs a fault diagnosis signal FLG2 indicating the result of the fault diagnosis. In particular, in this embodiment, the fault diagnosis circuit 130 performs fault diagnosis on the reference voltage generation circuit 40 at a predetermined timing that differs from the timing at which the common voltage VCMACC temporarily changes with the operation of the acceleration signal processing circuit 20, which is one of the physical quantity signal processing circuits.

[0124] For example, the timing of the temporary fluctuation of the common voltage VCMACC may be the timing of at least one of the rising and falling edges of the drive signal DRVACC, and the fault diagnosis circuit 130 may perform fault diagnosis at a predetermined timing different from this timing. Alternatively, the timing of the temporary fluctuation of the common voltage VCMACC may be the timing of at least one of the rising and falling edges of the control signals CTL1 to CTLn generated by the control circuit 90, and the fault diagnosis circuit 130 may perform fault diagnosis at a predetermined timing different from this timing.

[0125] In this embodiment, the fault diagnosis circuit 130 includes an anomaly determination circuit 131 and a fault diagnosis signal output circuit 132.

[0126] The anomaly detection circuit 131 determines whether the common voltage VCMACC is abnormal and outputs an anomaly detection signal FLG1 indicating the detection result. For example, the anomaly detection signal FLG1 can be a flag signal that goes high when the common voltage VCMACC is abnormal and goes low when the common voltage VCMACC is normal.

[0127] The fault diagnosis signal output circuit 132 receives the abnormality determination signal FLG1 at a predetermined timing and outputs the fault diagnosis signal FLG2. For example, the fault diagnosis signal FLG2 can also be a flag signal that becomes high when the reference voltage generation circuit 40 malfunctions and low when the reference voltage generation circuit 40 does not malfunction. In this embodiment, the fault diagnosis signal output circuit 132 receives the abnormality determination signal FLG1 at the rising edge of the clock signal WCK provided from the control circuit 90 and outputs the fault diagnosis signal FLG2. As will be described later, the timing of the rising edge of the clock signal WCK is a predetermined timing that differs from the timing of the common voltage VCMACC, which temporarily changes with the operation of the acceleration signal processing circuit 20.

[0128] 1-2-2. Structure of Fault Diagnosis Circuit

[0129] Figure 9 This is a diagram illustrating a portion of the reference voltage generation circuit 40 and a structural example of the fault diagnosis circuit 130. Figure 9 In the example, the reference voltage generation circuit 40 includes a bandgap reference circuit 145, resistors 146 and 147, and an operational amplifier 148.

[0130] The bandgap reference circuit 145 is a circuit that uses the bandgap voltage of a semiconductor element to generate a constant power supply voltage VCC that is stable relative to variations in temperature or power supply voltage VDD. Since the structure of the bandgap reference circuit is well-known, its illustration and description are omitted.

[0131] Resistors 146 and 147 have the same resistance value R. The voltage obtained by dividing the power supply voltage VCC by 1 / 2 through resistors 146 and 147 is provided to the non-inverting input terminal of operational amplifier 148.

[0132] The inverting input terminal of operational amplifier 148 is connected to the output terminal of operational amplifier 148, which functions as a voltage follower. Therefore, the output terminal of operational amplifier 148 is half of the power supply voltage VCC, which is output from the reference voltage generation circuit 40 as a common voltage VCMACC.

[0133] The fault diagnosis circuit 130 includes comparators 231 and 232, a logic OR circuit 233, and a D-type flip-flop 234.

[0134] A common voltage VCMACC is provided to the inverting input terminal of comparator 231, and a specified threshold voltage VL is provided to the non-inverting input terminal of comparator 231. When the common voltage VCMACC is above the threshold voltage VL, the output terminal of comparator 231 is at a low level; when the common voltage VCMACC is below the threshold voltage VL, the output terminal of comparator 231 is at a high level.

[0135] A common voltage VCMACC is provided to the non-inverting input terminal of comparator 232, and a predetermined threshold voltage VH, which is higher than the threshold voltage VL, is provided to the inverting input terminal of comparator 232. When the common voltage VCMACC is lower than the threshold voltage VH, the output terminal of comparator 232 is at a low level; when the common voltage VCMACC is higher than the threshold voltage VH, the output terminal of comparator 232 is at a high level.

[0136] The logic OR circuit 233 is input with the output signals of comparator 231 and comparator 232, and outputs a logic OR signal of these signals. That is, the output signal of the logic OR circuit 233 is low when both the output signals of comparator 231 and comparator 232 are low, and is high when at least one of the output signals of comparator 231 and comparator 232 is high.

[0137] Therefore, when the common voltage VCMAD is above the threshold voltage VL and below the threshold voltage VH, the output signal of the OR circuit 233 is at a low level; when the common voltage VCMAD is below the threshold voltage VL or above the threshold voltage VH, the output signal of the OR circuit 233 is at a high level. The comparators 231 and 232, along with the OR circuit 233, constitute the anomaly determination circuit 131. The output signal of the OR circuit 233 becomes the anomaly determination signal FLG1. That is, when the common voltage VCMACC is above the threshold voltage VL and below the threshold voltage VH, the anomaly determination circuit 131 determines that the common voltage VCMACC is normal; when the common voltage VCMACC is below the threshold voltage VL or above the threshold voltage VH, it determines that the common voltage VCMACC is abnormal and outputs the anomaly determination signal FLG1 indicating the determination result.

[0138] In addition, the threshold voltages VL and VH can be fixed values ​​or can be variably set in the storage unit 100.

[0139] In the D-type flip-flop 234, the data input terminal D is input with an abnormality determination signal FLG1, and the clock input terminal is input with a clock signal WCK. At the rising edge of the clock signal WCK, the D-type flip-flop 234 receives the abnormality determination signal FLG1 and outputs the fault diagnosis signal FLG2.

[0140] exist Figure 9 In the example, the common voltage VCMACC is a voltage that is half the power supply voltage VCC through resistors 146 and 147. Therefore, if the power supply voltage VCC is always abnormal, the common voltage VCMACC will also always be abnormal, and the fault determination signal FLG1 will always be high. Therefore, whether the operational amplifier 148 fails and the common voltage VCMACC is always abnormal, or the bandgap reference circuit 145 fails and the power supply voltage VCC is always abnormal, the fault diagnosis signal FLG2 will be high, and the fault diagnosis circuit 130 can diagnose that the reference voltage generation circuit 40 has failed.

[0141] Figure 10 This is a diagram illustrating an example of the waveforms of various signals, including the common voltage VCMCC, the fault determination signal FLG1, and the fault diagnosis signal FLG2, when the reference voltage generation circuit 40 is functioning correctly. Additionally, Figure 11 This is a diagram illustrating an example of the waveforms of various signals, including the common voltage VCMCC, the fault determination signal FLG1, and the fault diagnosis signal FLG2, when the reference voltage generation circuit 40 malfunctions.

[0142] In this embodiment, to reduce the area of ​​the reference voltage generation circuit 40, it is assumed that the supply capability of the power supply voltage VCC relative to the acceleration signal processing circuit 20 may not be sufficient. Since the high level of the drive signal DRVACC is the power supply voltage VCC, the power supply voltage VCC fluctuates significantly during the timing of the rising and falling edges of the drive signal DRVACC. Accompanying this, as... Figure 10 and Figure 11 As shown, the common voltage VCC also fluctuates significantly. Similarly, since the high level of control signals CTL1 to CTLn is the power supply voltage VCC, the power supply voltage VCC fluctuates significantly during the timing of the rising and falling edges of each of the control signals CTL1 to CTLn. This is accompanied by... Figure 10 as well as Figure 11 As shown, the common voltage VCMACC also varies considerably.

[0143] exist Figure 10In the example, during the timing of the rising and falling edges of the drive signal DRVCC and the rising and falling edges of the control signals CTL1 to CTLn, the common voltage VCMACC becomes lower than the threshold voltage VL. As a result, the abnormality determination signal FLG1 periodically becomes high during one cycle of the clock signal MCK. Even if the common voltage VCMACC is temporarily lower than the threshold voltage VL during these timings, it will not affect the operation of the acceleration signal processing circuit 20, so it is not a fault of the reference voltage generation circuit 40. However, assuming that the abnormality determination signal FLG1 temporarily becomes high during the timing of the temporary change in the common voltage VCMACC, the fault diagnosis signal output circuit 132 takes in the abnormality determination signal FLG1 and outputs a high-level fault diagnosis signal FLG2. Furthermore, if an external device reads the high-level fault diagnosis signal FLG2 through the interface circuit 110, the external device will mistakenly determine that the reference voltage generation circuit 40 has failed.

[0144] In addition, Figure 11 In the example, the reference voltage generation circuit 40 malfunctions, and the common voltage VCMACC is higher than the threshold voltage VH. In fact, with... Figure 10 Similarly, during the timing of the rising and falling edges of the drive signal DRVCC and the rising and falling edges of the control signals CTL1 to CTLn, the common voltage VCMACC fluctuates significantly. Therefore, the common voltage VCMACC will temporarily fall within the range above the threshold voltage VL and below the threshold voltage VH. Thus, in Figure 11 In the example, with Figure 10 Conversely, at these timing edges, the fault determination signal FLG1 temporarily goes low. Therefore, assuming the fault determination signal FLG1 is input into the fault diagnosis signal output circuit 132 at the timing point when it temporarily goes low, a low-level fault diagnosis signal FLG2 is output. Furthermore, if an external device reads the low-level fault diagnosis signal FLG2 via the interface circuit 110, the external device will mistakenly determine that the reference voltage generation circuit 40 has not malfunctioned.

[0145] In contrast, in this embodiment, the timing of the fault diagnosis signal output circuit 132 acquiring the abnormal judgment signal FLG1, i.e., the rising edge of the clock signal WCK, does not overlap with the timing of the temporary fluctuation of the common voltage VCMACC. In this embodiment, the control circuit 90 has a counter (not shown), and generates control signals CTL1 to CTLn for the acceleration signal processing circuit 20 based on the counter's count value CNT. Furthermore, the acceleration signal processing circuit 20 generates a drive signal DRVACC based on at least a portion of the control signals CTL1 to CTLn. Figure 10 and Figure 11 In the example, the count value CNT is initialized to 0 during each period when the drive signal DRVACC is low and during each period when the drive signal DRVACC is high, and then increments from 0 to N sequentially. The operation of the acceleration signal processing circuit 20 is controlled based on the count value CNT. Furthermore, the timing of the count value CNT changing from 2 to 3 is set as the rising edge of the clock signal WCK, which is a timing that does not overlap with the timing of the rising or falling edge of the drive signal DRVACC and the rising or falling edge of the control signals CTL1 to CTLn, i.e., the timing of the temporary change of the common voltage VCMACC.

[0146] Therefore, in Figure 10 In this example, the fault diagnosis signal output circuit 132 does not pick up the fault diagnosis signal FLG1 at the timing point when the fault diagnosis signal FLG1 temporarily becomes high, and the fault diagnosis signal FLG2 remains at a low level. Therefore, even if the external device reads the fault diagnosis signal FLG2 through the interface circuit 110 at any timing, it can correctly determine that the reference voltage generation circuit 40 is not faulty.

[0147] In addition, Figure 11 In this example, the fault diagnosis signal output circuit 132 does not pick up the fault diagnosis signal FLG1 at the timing point when the fault diagnosis signal FLG1 temporarily goes low, and the fault diagnosis signal FLG2 remains at a high level. Therefore, even if the external device reads the fault diagnosis signal FLG2 through the interface circuit 110 at any timing, it can correctly determine that the reference voltage generation circuit 40 has failed.

[0148] 1-2-3. Steps in Fault Diagnosis Methods

[0149] The fault diagnosis method of the physical quantity sensor 1 in the second embodiment includes a fault diagnosis step of monitoring the common voltage VCMACC, which is one of the reference voltages, performing fault diagnosis of the reference voltage generation circuit 40, and outputting a fault diagnosis signal FLG2 indicating the result of the fault diagnosis. In the fault diagnosis step, the fault diagnosis is performed at a predetermined timing that is different from the timing at which the common voltage VCMACC temporarily changes with the operation of the acceleration signal processing circuit 20.

[0150] Figure 12 This is a flowchart illustrating an example of the steps in the fault diagnosis method for the physical quantity sensor 1 according to the second embodiment. Additionally, in Figure 12 In the flowchart, the processing of each step can also be changed appropriately.

[0151] like Figure 12As shown, when the common voltage VCMACC is within the specified voltage range ("Yes" in step S11), that is, when the common voltage VCMACC is above the threshold voltage VL and below the threshold voltage VH, the anomaly determination circuit 131 of the physical quantity sensor 1 sets the anomaly determination signal FLG1 to no anomaly (step S12). Specifically, the anomaly determination circuit 131 sets the anomaly determination signal FLG1 to a low level.

[0152] On the other hand, when the common voltage VCMACC is not within the specified voltage range (No in step S11), that is, when the common voltage VCMACC is lower than the threshold voltage VL or higher than the threshold voltage VH, the abnormality determination circuit 131 of the physical quantity sensor 1 sets the abnormality determination signal FLG1 to be abnormal (step S13). Specifically, the abnormality determination circuit 131 sets the abnormality determination signal FLG1 to a high level.

[0153] Before the fault diagnosis timing, which is a predetermined time, arrives (No in step S14), the anomaly determination circuit 131 repeats the processing of steps S11, S12, and S13. Then, when the fault diagnosis timing arrives (Yes in step S14), the fault diagnosis signal output circuit 132 of the physical quantity sensor 1 takes in the anomaly determination signal FLG1 and outputs the fault diagnosis signal FLG2 (step S15), and the anomaly determination circuit 131 repeats the processing of steps S11, S12, and S13 again.

[0154] in addition, Figure 12 Steps S11 to S15 are equivalent to fault diagnosis steps. Steps S11, S12, and S13 are fault determination steps in which the fault determination circuit 131 determines whether the common voltage VCMACC, which is one of the reference voltages, is abnormal, and outputs an fault determination signal FLG1 indicating the determination result. In addition, steps S14 and S15 are fault diagnosis signal output steps in which the fault diagnosis signal output circuit 132 takes the abnormal determination signal FLG1 at a predetermined timing and outputs a fault diagnosis signal FLG2.

[0155] In the second embodiment described above, the physical quantity detection circuit 2 includes a fault diagnosis circuit 130. This fault diagnosis circuit 130 monitors the common voltage VCMACC generated by the reference voltage generation circuit 40 and supplied to the acceleration signal processing circuit 20, performs fault diagnosis on the reference voltage generation circuit 40, and outputs a fault diagnosis signal FLG2 indicating the result of the fault diagnosis. The fault diagnosis circuit 130 performs fault diagnosis at a predetermined timing that differs from the timing at which the common voltage VCMACC temporarily changes with the operation of the acceleration signal processing circuit 20. According to this embodiment, since the fault diagnosis circuit 130 performs fault diagnosis at a predetermined timing that differs from the timing at which the common voltage VCMACC temporarily changes with the operation of the acceleration signal processing circuit 20, the possibility of erroneously judging that the reference voltage generation circuit 40 has failed can be reduced even if the common voltage VCMACC temporarily changes. For example, even if the provision capability of the common voltage VCMACC of the reference voltage generation circuit 40 is low, the possibility of erroneous judgment by the fault diagnosis circuit 130 can be reduced, thus allowing for a reduction in the size of the reference voltage generation circuit 40 and improving cost.

[0156] In particular, in this embodiment, the fault diagnosis circuit 130 performs fault diagnosis at a predetermined timing that differs from the rising and falling edges of the driving signals DRVACC of the acceleration detection elements 4X and 4Y, which are different from the rising and falling edges of the control signals CTL1 to CTLn of the acceleration signal processing circuit 20, which are different from the rising and falling edges of the control signals CTL1 to CTLn of the acceleration signal processing circuit 20. Therefore, even if the common voltage VCMACC changes temporarily, the possibility of mistakenly judging that the reference voltage generation circuit 40 has failed can be reduced.

[0157] Furthermore, in this embodiment, the fault diagnosis circuit 130 includes: an anomaly determination circuit 131, which determines whether the common voltage VCMACC is abnormal and outputs an anomaly determination signal FLG1 indicating the determination result; and a fault diagnosis signal output circuit 132, which takes in the anomaly determination signal FLG1 at a predetermined timing different from the timing at which the common voltage VCMACC temporarily changes with the operation of the acceleration signal processing circuit 20, and outputs a fault diagnosis signal FLG2. Therefore, according to this embodiment, even if the anomaly determination circuit 131 temporarily outputs the anomaly determination signal FLG1 indicating that the common voltage VCMACC is abnormal when the common voltage VCMACC temporarily changes, the fault diagnosis signal output circuit 132 can reduce the possibility of mistakenly outputting the fault diagnosis signal FLG2 indicating that the reference voltage generation circuit 40 has malfunctioned, instead of taking in the anomaly determination signal FLG1 indicating that the common voltage VCMACC is abnormal.

[0158] Thus, according to this embodiment, the possibility of erroneously judging that the reference voltage generation circuit 40 has failed can be reduced, thereby improving the reliability of fault diagnosis of the physical quantity detection circuit 2 and the physical quantity sensor 1.

[0159] 1-3. Variations

[0160] For example, in the first embodiment described above, the fault diagnosis circuit 80 monitors the common voltage VCMAD, and in the second embodiment described above, the fault diagnosis circuit 130 monitors the common voltage VCMAC. However, the fault diagnosis circuit may also monitor both the common voltage VCMAD and the common voltage VCMAC. That is, the physical quantity sensor 1 may also be a combination of the structures of the first and second embodiments.

[0161] Furthermore, in the first embodiment described above, the fault diagnosis circuit 80 monitors the common voltage VCMAD, but it can also monitor the full-scale voltage VFSAD, and can also monitor any voltage that varies with the full-scale voltage VFSAD. In the second embodiment described above, the fault diagnosis circuit 130 monitors the common voltage VCMAD, but it can also monitor the power supply voltage VCC, and can also monitor any voltage that varies with the power supply voltage VCC. Alternatively, the fault diagnosis circuit can monitor any voltage that varies with the power supply voltage VGR, such as the common voltage VCMGR, and can also monitor the power supply voltage VGR.

[0162] Furthermore, in the above embodiments, the physical quantity sensor 1 detects both angular velocity and acceleration as physical quantities, but it can also detect either angular velocity or acceleration. Additionally, the physical quantity sensor 1 can also detect physical quantities other than angular velocity and acceleration as physical quantities.

[0163] In addition, in the above embodiments, the analog-to-digital converter 60 is input with a differential signal and converts the differential signal into a digital signal ADO, but it can also be input with a single-ended signal and convert the single-ended signal into a digital signal ADO.

[0164] Furthermore, in the above embodiments, the physical quantity sensor 1 includes an angular velocity detection element 3, an acceleration detection element 4X, and an acceleration detection element 4Y, but it may also be a sensor that only has a portion of these physical quantity detection elements. Additionally, the physical quantity sensor 1 may also include physical quantity detection elements that detect physical quantities other than angular velocity or acceleration, such as physical quantity detection elements that detect angular acceleration, velocity, force, etc.

[0165] Furthermore, in the above embodiments, the example given is a double-T type quartz oscillator for the angular velocity sensing element 3. However, the oscillator of a physical quantity sensing element that detects various physical quantities can be, for example, a tuning fork type or a comb type, or a tone plate type with shapes such as triangular prism, square prism, or cylinder. Additionally, the material of the oscillator for the physical quantity sensing element can be different from quartz (SiO2). For example, piezoelectric single crystals such as lithium tantalate (LiTaO3) and lithium niobate (LiNbO3) or piezoelectric ceramics such as lead zirconate titanate (PZT) can be used, or silicon semiconductors can be used. Furthermore, the oscillator of the physical quantity sensing element can also be constructed by distributing a piezoelectric thin film such as zinc oxide (ZnO) or aluminum nitride (AlN) sandwiched between driving electrodes on a portion of the surface of the silicon semiconductor.

[0166] Furthermore, in the above embodiments, piezoelectric angular velocity sensing element 3 and electrostatic capacitive acceleration sensing elements 4X and 4Y are exemplified. However, physical quantity sensing elements that detect various physical quantities are not limited to piezoelectric or electrostatic capacitive elements; they can also be electrodynamic, eddy current, optical, strain gauge, or other types of elements. Additionally, the detection method of the physical quantity sensing element is not limited to vibration-based methods; for example, it can also be optical, rotational, or fluid-based methods.

[0167] The above-described embodiments and modifications are examples only and are not limited thereto. For example, various embodiments and modifications can be appropriately combined.

[0168] This invention includes structures that are substantially the same as those described in the embodiments (e.g., structures with the same function, method, and result, or structures with the same purpose and effect). Furthermore, this invention includes structures obtained by replacing non-essential parts of the structures described in the embodiments. Furthermore, this invention includes structures capable of achieving the same function or effect as the structures described in the embodiments, or achieving the same purpose. Furthermore, this invention includes structures obtained by adding known techniques to the structures described in the embodiments.

[0169] The following content is derived from the above implementation methods and variations.

[0170] One embodiment of a physical quantity detection circuit includes: a detection signal generation circuit that generates a detection signal corresponding to the physical quantity based on the output signal of a physical quantity detection element; an analog-to-digital conversion circuit that converts the detection signal into a digital signal; a reference voltage generation circuit that generates a reference voltage supplied to the analog-to-digital conversion circuit; and a fault diagnosis circuit that monitors the reference voltage, performs fault diagnosis on the reference voltage generation circuit, and outputs a fault diagnosis signal indicating the result of the fault diagnosis, wherein the fault diagnosis circuit performs the fault diagnosis at a predetermined timing different from the timing at which the reference voltage temporarily changes with the operation of the analog-to-digital conversion circuit.

[0171] According to this physical quantity detection circuit, the fault diagnosis circuit performs fault diagnosis at a predetermined timing, different from the timing at which the reference voltage temporarily changes due to the operation of the analog / digital conversion circuit. Therefore, even if the reference voltage changes temporarily, the possibility of misjudging that the reference voltage generation circuit has failed can be reduced. For example, even if the reference voltage generation circuit has a low reference voltage supply capability, the possibility of the fault diagnosis circuit making an incorrect judgment can be reduced. Therefore, the size of the reference voltage generation circuit can be reduced, which helps to reduce the cost of the physical quantity detection circuit.

[0172] In one embodiment of the physical quantity detection circuit, the timing of the temporary change in the reference voltage may be the timing at which the analog-to-digital conversion circuit begins sampling the detection signal.

[0173] According to this physical quantity detection circuit, the fault diagnosis circuit performs fault diagnosis at a predetermined timing that differs from the timing at which the analog / digital conversion circuit begins to detect the signal when the reference voltage temporarily changes. Therefore, even if the reference voltage changes temporarily, the possibility of mistakenly judging that the reference voltage generation circuit has failed can be reduced.

[0174] In one embodiment of the physical quantity detection circuit, the timing of the temporary change in the reference voltage may be the timing at which the analog-to-digital conversion circuit ends the sampling of the detection signal.

[0175] According to this physical quantity detection circuit, the fault diagnosis circuit performs fault diagnosis at a predetermined timing that differs from the timing at which the analog / digital conversion circuit ends sampling of the detection signal when the reference voltage temporarily changes. Therefore, even if the reference voltage temporarily changes, the possibility of mistakenly judging that the reference voltage generation circuit has failed can be reduced.

[0176] One embodiment of a physical quantity detection circuit includes: a physical quantity signal processing circuit that outputs a drive signal to drive a physical quantity detection element that detects the physical quantity, and generates a detection signal corresponding to the physical quantity based on the output signal of the physical quantity detection element; a reference voltage generation circuit that generates a reference voltage supplied to the physical quantity signal processing circuit; and a fault diagnosis circuit that monitors the reference voltage, performs fault diagnosis on the reference voltage generation circuit, and outputs a fault diagnosis signal indicating the result of the fault diagnosis, wherein the fault diagnosis circuit performs the fault diagnosis at a predetermined timing that differs from the timing at which the reference voltage temporarily changes with the operation of the physical quantity signal processing circuit.

[0177] According to this physical quantity detection circuit, the fault diagnosis circuit performs fault diagnosis at a predetermined timing that differs from the timing at which the reference voltage temporarily changes due to the operation of the physical quantity signal processing circuit. Therefore, even if the reference voltage changes temporarily, the possibility of mistakenly identifying a fault in the reference voltage generation circuit can be reduced. For example, even if the reference voltage generation circuit has a low reference voltage supply capability, the possibility of the fault diagnosis circuit making an incorrect judgment can be reduced. Therefore, the size of the reference voltage generation circuit can be reduced, which helps to reduce the cost of the physical quantity detection circuit.

[0178] In one embodiment of the physical quantity detection circuit, the timing of the temporary variation of the reference voltage may be the timing of at least one of the rising edge and falling edge of the drive signal.

[0179] According to the physical quantity detection circuit, the fault diagnosis circuit performs fault diagnosis at a predetermined timing that differs from the timing of at least one of the rising and falling edges of the drive signal when the reference voltage temporarily changes. Therefore, even if the reference voltage changes temporarily, the possibility of mistakenly judging that the reference voltage generation circuit has failed can be reduced.

[0180] Alternatively, one embodiment of the physical quantity detection circuit may include a control circuit that generates a control signal to control the physical quantity signal processing circuit, wherein the timing of the temporary variation of the reference voltage is the timing of at least one of the rising and falling edges of the control signal.

[0181] According to the physical quantity detection circuit, the fault diagnosis circuit performs fault diagnosis at a predetermined timing that differs from the timing of at least one of the rising and falling edges of the control signal when the reference voltage temporarily changes. Therefore, even if the reference voltage changes temporarily, the possibility of mistakenly judging that the reference voltage generation circuit has failed can be reduced.

[0182] In one embodiment of the physical quantity detection circuit, the fault diagnosis circuit may include: an anomaly determination circuit that determines whether the reference voltage is abnormal and outputs an anomaly determination signal indicating the determination result; and a fault diagnosis signal output circuit that takes in the anomaly determination signal at the predetermined timing and outputs the fault diagnosis signal.

[0183] According to this physical quantity detection circuit, even if the abnormality determination circuit temporarily outputs an abnormality determination signal indicating an abnormality in the reference voltage when the reference voltage changes temporarily, it can reduce the possibility that the fault diagnosis signal output circuit will take the abnormality determination signal indicating an abnormality in the reference voltage and erroneously output a fault diagnosis signal indicating a fault in the reference voltage generation circuit.

[0184] One type of physical quantity sensor includes a physical quantity detection circuit and a physical quantity detection element.

[0185] This physical quantity sensor achieves high reliability because it has a physical quantity detection circuit that reduces the possibility of misjudging a fault in the reference voltage generation circuit even if the reference voltage changes temporarily.

[0186] In one embodiment of a fault diagnosis method for a physical quantity sensor, the physical quantity sensor includes a physical quantity detection element for detecting a physical quantity, a detection circuit for generating a detection signal corresponding to the physical quantity based on the output signal of the physical quantity detection element, an analog-to-digital converter circuit for converting the detection signal into a digital signal, and a reference voltage generation circuit for generating a reference voltage supplied to the analog-to-digital converter circuit. The fault diagnosis method for the physical quantity sensor includes a fault diagnosis step in which the reference voltage is monitored, a fault diagnosis is performed on the reference voltage generation circuit, and a fault diagnosis signal representing the result of the fault diagnosis is output. In this fault diagnosis step, the fault diagnosis is performed at a predetermined timing different from the timing at which the reference voltage temporarily changes with the operation of the analog-to-digital converter circuit.

[0187] According to the fault diagnosis method of this physical quantity sensor, in the fault diagnosis step, fault diagnosis is performed at a predetermined timing that is different from the timing at which the reference voltage temporarily changes with the operation of the analog / digital conversion circuit. Therefore, even if the reference voltage changes temporarily, the possibility of mistakenly judging that the reference voltage generation circuit has failed can be reduced.

[0188] In one embodiment of a fault diagnosis method for a physical quantity sensor, the physical quantity sensor includes a physical quantity detection element for detecting a physical quantity, a physical quantity signal processing circuit for outputting a drive signal to drive the physical quantity detection element and generating a detection signal corresponding to the physical quantity based on the output signal of the physical quantity detection element, and a reference voltage generation circuit for generating a reference voltage provided to the physical quantity signal processing circuit, wherein...

[0189] The fault diagnosis method for the physical quantity sensor includes a fault diagnosis step in which the reference voltage is monitored, a fault diagnosis of the reference voltage generation circuit is performed, and a fault diagnosis signal representing the result of the fault diagnosis is output. In the fault diagnosis step, the fault diagnosis is performed at a predetermined timing that is different from the timing at which the reference voltage temporarily changes with the operation of the physical quantity signal processing circuit.

[0190] According to the fault diagnosis method of the physical quantity sensor, in the fault diagnosis step, the fault diagnosis is performed at a predetermined timing that is different from the timing at which the reference voltage temporarily changes with the operation of the physical quantity signal processing circuit. Therefore, even if the reference voltage changes temporarily, the possibility of mistakenly judging that the reference voltage generation circuit has failed can be reduced.

Claims

1. A fault diagnosis circuit, wherein, The fault diagnosis circuit includes: An anomaly detection circuit determines whether the reference voltage supplied to the analog-to-digital converter is abnormal and outputs an anomaly detection signal indicating the detection result. as well as The fault diagnosis signal output circuit, at a predetermined timing different from the timing of the temporary fluctuation of the reference voltage due to the operation of the analog-to-digital conversion circuit, takes in the abnormality determination signal and outputs a fault diagnosis signal. The fault diagnosis circuit performs fault diagnosis on the reference voltage generation circuit that provides the reference voltage. The timing for the fault diagnosis is different from the timing for the temporary change. The temporarily changed timing is the timing at which the analog-to-digital conversion circuit starts sampling or the timing at which the sampling ends. The fault diagnosis signal output circuit outputs the fault diagnosis signal at the rising edge of the clock signal provided by the control circuit that controls the analog-to-digital conversion circuit.

2. The fault diagnosis circuit according to claim 1, wherein, The anomaly detection circuit includes: The first comparator has the reference voltage input to its inverting input terminal; The second comparator has the reference voltage input to its non-inverting input terminal; as well as A logic OR circuit that outputs a logic OR signal based on the output signals of the first comparator and the second comparator.

3. An electronic circuit, wherein, This electronic circuit includes: The fault diagnosis circuit according to claim 1 or 2; Analog-to-digital conversion circuits; and Reference voltage generation circuit.

4. The electronic circuit according to claim 3, wherein, The electronic circuit includes a control circuit.

5. A fault diagnosis circuit, wherein, The fault diagnosis circuit includes: An anomaly detection circuit determines whether the reference voltage supplied to the physical quantity signal processing circuit is abnormal and outputs an anomaly detection signal indicating the detection result. The physical quantity signal processing circuit generates a detection signal based on the output signal of the physical quantity detection element. as well as The fault diagnosis signal output circuit, at a predetermined timing different from the timing of the temporary fluctuation of the reference voltage due to the operation of the physical quantity signal processing circuit, takes in the abnormality determination signal and outputs a fault diagnosis signal. The fault diagnosis circuit performs fault diagnosis on the reference voltage generation circuit that provides the reference voltage. The timing for the fault diagnosis is different from the timing for the temporary change. The timing of the temporary variation is the timing of at least one of the rising and falling edges of the drive signal that drives the physical quantity detection element. The fault diagnosis signal output circuit outputs the fault diagnosis signal at the rising edge of the clock signal provided by the control circuit that controls the physical quantity signal processing circuit.

6. The fault diagnosis circuit according to claim 5, wherein, The anomaly detection circuit includes: The first comparator has the reference voltage input to its inverting input terminal; The second comparator has the reference voltage input to its non-inverting input terminal; as well as A logic OR circuit that outputs a logic OR signal based on the output signals of the first comparator and the second comparator.

7. A fault diagnosis circuit, wherein, The fault diagnosis circuit includes: An anomaly detection circuit determines whether the reference voltage supplied to the physical quantity signal processing circuit is abnormal and outputs an anomaly detection signal indicating the detection result. The physical quantity signal processing circuit generates a detection signal based on the output signal of the physical quantity detection element. as well as The fault diagnosis signal output circuit, at a predetermined timing different from the timing of the temporary fluctuation of the reference voltage due to the operation of the physical quantity signal processing circuit, takes in the abnormality determination signal and outputs a fault diagnosis signal. The fault diagnosis circuit performs fault diagnosis on the reference voltage generation circuit that provides the reference voltage. The timing for the fault diagnosis is different from the timing for the temporary change. The timing of the temporary variation is the timing of at least one of the rising and falling edges of the control signal of the control circuit controlling the physical quantity signal processing circuit. The fault diagnosis signal output circuit outputs the fault diagnosis signal at the rising edge of the clock signal provided by the control circuit.

8. The fault diagnosis circuit according to claim 7, wherein, The anomaly detection circuit includes: The first comparator has the reference voltage input to its inverting input terminal; The second comparator has the reference voltage input to its non-inverting input terminal; as well as A logic OR circuit that outputs a logic OR signal based on the output signals of the first comparator and the second comparator.

9. A physical quantity detection circuit, wherein, The physical quantity detection circuit includes: The fault diagnosis circuit according to any one of claims 5 to 8; Physical quantity signal processing circuit; Reference voltage generation circuit; and Control circuit.

10. A physical quantity sensor, wherein, This physical quantity sensor includes: The physical quantity detection circuit according to claim 9; and Physical quantity detection element.

Images