Signal transmission method and electronic equipment

Abstract

The present application provides a signal transmission method and electronic device, which belong to the field of communication technology, wherein the electronic device is a foldable electronic device, and the electronic device includes: a processor located on the main board side; at least one peripheral chip and an extension chip located on the sub-board side. The processor output interface and the bus interface are both coupled to the processor; at least one peripheral input and output interface is respectively coupled to at least one peripheral chip. The extension chip is used to receive a first control signal sent by the peripheral chip through the peripheral input and output interface, and send the first control signal to the processor through the processor output interface; and / or, to receive a second control signal sent by the processor through the bus interface, and control the peripheral chip based on the second control signal. In this way, the multiple through-axis lines between the processor and the peripheral chip in the existing solution are transferred to the extension chip, and only two through-axis lines are required between the extension chip and the processor to achieve communication, thereby reducing the through-axis lines.

Description

Technical Field

[0001] The present application belongs to the field of communication technology, and in particular relates to a signal transmission method and electronic equipment. Background Art

[0002] With the rapid development of electronic device technology, foldable electronic devices have emerged to address the issues of traditional tablet computers being bulky and inconvenient to carry, as well as the small screens of mobile phones. Foldable electronic devices can unfold their screens when in use to provide a larger display area. When not in use, they can be folded back to the unfolded state, making them easier to carry.

[0003] A foldable electronic device consists of a mainboard, a sub-board, and a hinge. The mainboard and sub-boards are connected by a hinge and are located on either side of the hinge. The mainboard is the core component of a foldable electronic device, responsible for controlling the entire system's functions and data processing, including processing applications, managing power, and connecting to the network. Sub-boards are additional components within a foldable electronic device that connect to the mainboard to provide additional functionality and interaction. For example, sub-boards may include external devices such as audio components, displays, charging devices, sensors, and power supplies.

[0004] The main and secondary boards communicate and transmit data via electrically connected circuits, enabling the coordinated operation of the entire system. Because the main and secondary boards are located on either side of the hinge, all wiring between them must be routed through the hinge. However, with the development of foldable electronic devices, the number of wiring that needs to be routed through the hinge is increasing, and the limited width of foldable electronic devices has hindered the development of foldable electronic devices. Summary of the Invention

[0005] A signal transmission method and electronic device provided in the embodiments of the present application can save on axis-through lines and improve the bottleneck problem of circuit layout in foldable electronic devices.

[0006] In a first aspect, the present application provides an electronic device, which is a foldable electronic device, and the electronic device includes: a processor, the processor is located on the main board side of the electronic device; at least one peripheral chip, the at least one peripheral chip is located on the sub-board side of the electronic device, the main board and the sub-board are connected by a hinge and are arranged on both sides of the hinge; an expansion chip, the expansion chip is located on the sub-board side, the expansion chip includes a processor output interface, a bus interface and at least one peripheral input and output interface; the processor output interface and the bus interface are both coupled to the processor; the at least one peripheral input and output interface is respectively coupled to the at least one peripheral chip; the expansion chip is used to receive a first control signal sent by the peripheral chip through the peripheral input and output interface, and send the first control signal to the processor through the processor output interface; and / or, to receive a second control signal sent by the processor through the bus interface, and control the peripheral chip based on the second control signal.

[0007] In this way, the present application transfers multiple through-axis lines between the processor and the peripheral chip in the existing solution to the expansion chip. Then, only two through-axis lines corresponding to the processor output interface and the bus interface are needed between the expansion chip and the processor to achieve communication, thereby reducing the through-axis lines.

[0008] In one implementable manner, the processor includes a first sub-processor and a second sub-processor, the extension chip is coupled to the first sub-processor through the processor output interface, and the extension chip is coupled to the second sub-processor through the bus interface; the first sub-processor is coupled to the second sub-processor; the extension chip is specifically used to send the first control signal to the first sub-processor through the processor output interface; and / or, to receive the second control signal sent by the second sub-processor through the bus interface, and control the peripheral chip based on the second control signal.

[0009] In this way, when each peripheral chip is controlled by a different processor, the through-axis line can also be saved.

[0010] In one implementable manner, the processor includes a first sub-processor and a second sub-processor, the extension chip is coupled to the second sub-processor through the processor output interface, and the extension chip is coupled to the second sub-processor through the bus interface; the first sub-processor is coupled to the second sub-processor; the extension chip is specifically used to send the first control signal to the second sub-processor through the processor output interface; and / or, to receive the second control signal sent by the second sub-processor through the bus interface, and control the peripheral chip based on the second control signal.

[0011] In this way, when each peripheral chip is controlled by a different processor, the through-axis line can also be saved.

[0012] In one achievable manner, the power consumption of the second sub-processor is less than the power consumption of the first sub-processor.

[0013] In one achievable manner, the second sub-processor is configured to include a driver for the extension chip in the second sub-processor, and upon receiving the first control signal, obtain first status information of the extension chip through the bus interface, and determine, based on the first status information, the peripheral chip that inputs the first control signal.

[0014] Because the first control signal is sent to the second sub-processor by the expansion chip, after receiving the first control signal, the second sub-processor only knows that the first control signal originates from the expansion chip, but is unaware of which peripheral chip the first control signal originates from. Therefore, in response to receiving the first control signal, the second sub-processor obtains first status information of the expansion chip to determine which peripheral chip generated the first control signal. For example, the processor can read a register of the expansion chip via the bus interface I2C-1 to obtain the first status information. The first status information is information used to determine the peripheral chip that inputs the first control signal. For example, the first status information may include information about the interface that generates the first control signal and the correspondence between each interface and the peripheral chip.

[0015] In one achievable manner, the second sub-processor is further configured to wake up the driver of the peripheral chip and obtain second status information of the peripheral chip when the second sub-processor includes the driver of the peripheral chip.

[0016] In this way, when the peripheral chip is the peripheral chip controlled by the second sub-processor, the second state information of the peripheral chip is obtained by the awakened second sub-processor without waking up the first sub-processor. This can reduce the operating power consumption of the entire system.

[0017] In one implementable manner, the second sub-processor is further used to wake up the first processor and send indication information to the first processor when the second sub-processor does not include the driver of the peripheral chip, wherein the indication information is used to indicate the peripheral chip that inputs the first control signal; the first sub-processor is used to wake up the driver of the peripheral chip based on the indication information and obtain second status information of the peripheral chip when the first sub-processor includes the driver of the peripheral chip and receives the indication information.

[0018] In this way, when the peripheral chip is the peripheral chip controlled by the first sub-processor, the second sub-processor needs to wake up the first sub-processor first, and then the first sub-processor in the awakened state obtains the second state information of the peripheral chip.

[0019] In one achievable manner, the first sub-processor is configured to send a second control signal to the second processor when the first sub-processor includes a driver for a target peripheral chip; wherein the second control signal is used to instruct execution of a first target control on the target peripheral chip; and the second sub-processor is configured to control the extension chip through the bus interface to execute the first target control on the target peripheral chip when the second sub-processor includes a driver for the extension chip and receives the second control signal.

[0020] In this way, when the first sub-processor wants to control the corresponding peripheral chip, the first sub-processor first notifies the second sub-processor, and then the second sub-processor communicates with the expansion chip to achieve control of the target peripheral chip.

[0021] In one achievable manner, the second sub-processor is further configured to, when the second sub-processor includes a driver for a target peripheral chip, control the extension chip through the bus interface to perform a second target control on the target peripheral chip.

[0022] In this way, when the second sub-processor wants to control the corresponding peripheral chip, the second sub-processor can directly communicate with the expansion chip to achieve control of the target peripheral chip.

[0023] In one implementable manner, the processor includes a first sub-processor and a second sub-processor, the expansion chip includes a first sub-expansion chip and a second sub-expansion chip, and the at least one peripheral chip includes at least one first peripheral chip and at least one second peripheral chip; wherein the first sub-processor includes a driver for the at least one first peripheral chip, and the second sub-processor includes a driver for the at least one second peripheral chip;

[0024] The first sub-expansion chip includes a first processor output interface, a first bus interface, and at least one first peripheral input and output interface; the first processor output interface and the first bus interface are both coupled to the first sub-processor; the at least one first peripheral input and output interface is respectively coupled to the at least one first peripheral chip;

[0025] The second sub-expansion chip includes a second processor output interface, a second bus interface and at least one second peripheral input and output interface; the second processor output interface and the second bus interface are both coupled to the second sub-processor; the at least one second peripheral input and output interface is coupled to the at least one second peripheral chip;

[0026] The first sub-expansion chip is configured to receive a third control signal sent by the first peripheral chip through the first peripheral input / output interface, and send the third control signal to the first sub-processor through the first processor output interface; and / or to receive a fourth control signal sent by the first sub-processor through the first bus interface, and control the first peripheral chip based on the fourth control signal;

[0027] The second sub-extension chip is used to receive the fifth control signal sent by the second peripheral chip through the second peripheral input and output interface, and send the fifth control signal to the second sub-processor through the second processor output interface; and / or, to receive the sixth control signal sent by the second sub-processor through the second bus interface, and control the second peripheral chip based on the sixth control signal.

[0028] Thus, compared to a solution where multiple sub-processors share one expansion chip, each sub-processor in this solution can communicate directly with its corresponding sub-expansion chip, eliminating the need for coordination with other sub-processors. This simplifies the signal transmission method.

[0029] In one implementable manner, the first sub-processor is configured to include a driver for the first sub-expansion chip in the first sub-processor, and upon receiving the third control signal, obtain third state information of the first sub-expansion chip through the first bus interface, and determine, based on the third state information, the first peripheral chip to which the third control signal is input;

[0030] The second sub-processor is configured to include a driver for the second sub-expansion chip in the second sub-processor, and upon receiving the fifth control signal, obtain fourth status information of the second sub-expansion chip through the second bus interface, and determine, based on the fourth status information, the second peripheral chip to which the fifth control signal is input.

[0031] In one achievable manner, the at least one peripheral input / output interface includes one or more of a reset interface, an enable interface, an interrupt interface, and a GPIO interface; the processor output interface includes an interrupt interface, and the bus interface is an inter-integrated circuit serial bus I2C interface, an inter-integrated circuit serial bus I3C interface, or a serial peripheral device SPI interface.

[0032] In this way, the solution provided by this application is suitable for peripheral chips that transmit one or more control signals.

[0033] In a second aspect, the present application provides a signal transmission method, which is applied to an electronic device, wherein the electronic device is a foldable electronic device, and the electronic device includes a processor located on the main board side of the electronic device, and at least one peripheral chip and an expansion chip located on the sub-board side of the electronic device, and the processor is coupled to the at least one peripheral chip through the expansion chip; the method includes: the expansion chip receives a first control signal sent by the peripheral chip, and sends the first control signal to the processor; the processor obtains first status information of the expansion chip in response to receiving the first control signal, and determines the peripheral chip that inputs the first control signal based on the first status information; the processor wakes up the driver of the peripheral chip and obtains second status information of the peripheral chip.

[0034] The electronic device may be any electronic device described in the first aspect.

[0035] In this way, communication between the processor and various peripheral chips can still be achieved while saving the through-axis wiring.

[0036] In one achievable manner, the processor includes a first sub-processor and a second sub-processor, and the power consumption of the second sub-processor is less than that of the first sub-processor; the method includes: including a driver for the extension chip in the second sub-processor, and upon receiving the first control signal, the second sub-processor obtains first status information of the extension chip, and determines, based on the first status information, the peripheral chip that inputs the first control signal.

[0037] Because the first control signal is sent to the second sub-processor by the expansion chip, after receiving the first control signal, the second sub-processor only knows that the first control signal originates from the expansion chip, but is unaware of which peripheral chip the first control signal originates from. Therefore, in response to receiving the first control signal, the second sub-processor obtains first status information of the expansion chip to determine which peripheral chip generated the first control signal. For example, the processor can read a register of the expansion chip via the bus interface I2C-1 to obtain the first status information. The first status information is information used to determine the peripheral chip that inputs the first control signal. For example, the first status information may include information about the interface that generates the first control signal and the correspondence between each interface and the peripheral chip.

[0038] In one achievable manner, the processor includes a first sub-processor and a second sub-processor, and the power consumption of the second sub-processor is less than that of the first sub-processor; the method includes: when the first sub-processor includes a driver for the extension chip and receives the first control signal, the first sub-processor obtains first status information of the extension chip, and based on the first status information, determines the peripheral chip that inputs the first control signal.

[0039] In one achievable manner, when the second sub-processor includes a driver for the peripheral chip, the driver for the peripheral chip is awakened, and second status information of the peripheral chip is acquired.

[0040] In this way, when the peripheral chip is the peripheral chip controlled by the second sub-processor, the second state information of the peripheral chip is obtained by the awakened second sub-processor without waking up the first sub-processor. This can reduce the operating power consumption of the entire system.

[0041] In one feasible manner, when the second sub-processor does not include the driver of the peripheral chip, the second sub-processor wakes up the first sub-processor and sends indication information to the first sub-processor, wherein the indication information is used to indicate the peripheral chip that inputs the first control signal; when the first sub-processor includes the driver of the peripheral chip, in response to receiving the indication information, the first sub-processor wakes up the driver of the peripheral chip based on the indication information and obtains the second status information of the peripheral chip.

[0042] In this way, when the peripheral chip is the peripheral chip controlled by the first sub-processor, the second sub-processor needs to wake up the first sub-processor first, and then the first sub-processor in the awakened state obtains the second state information of the peripheral chip.

[0043] In one achievable manner, the method further includes: the processor sending a second control signal to the expansion chip, the second control signal being used to instruct execution of target control on the target peripheral chip; and the expansion chip executing the target control on the target peripheral in response to receiving the second control signal.

[0044] In one implementable manner, the method further includes: when the first sub-processor includes a driver for the target peripheral chip, the first sub-processor sends a second control signal to the second processor; wherein the second control signal is used to indicate execution of a first target control on the target peripheral chip; in response to receiving the second control signal, the second sub-processor controls the expansion chip to execute the first target control on the target peripheral chip.

[0045] In this way, when the first sub-processor wants to control the corresponding peripheral chip, the first sub-processor first notifies the second sub-processor, and then the second sub-processor communicates with the expansion chip to achieve control of the target peripheral chip.

[0046] In one achievable manner, the method further includes: in a case where the second sub-processor includes a driver for a target peripheral chip, the second sub-processor controls the extension chip to perform a second target control on the target peripheral chip.

[0047] In this way, when the second sub-processor wants to control the corresponding peripheral chip, the second sub-processor can directly communicate with the expansion chip to achieve control of the target peripheral chip.

[0048] In one implementable manner, the processor includes a first sub-processor and a second sub-processor, the expansion chip includes a first sub-expansion chip and a second sub-expansion chip, and the at least one peripheral chip includes at least one first peripheral chip and at least one second peripheral chip; the first sub-processor is coupled to the at least one first peripheral chip via the first sub-expansion chip, and the second sub-processor is coupled to the at least two first peripheral chips via the second sub-expansion chip; the method includes:

[0049] The first sub-expansion chip receives a third control signal sent by the first peripheral chip, and sends the third control signal to the first sub-processor;

[0050] In response to receiving the third control signal, the first sub-processor obtains third status information of the first sub-expansion chip, and determines the first peripheral chip to which the third control signal is input based on the third status information; and / or,

[0051] The second sub-expansion chip receives the fifth control signal sent by the second peripheral chip, and sends the fifth control signal to the second sub-processor;

[0052] In response to receiving the fifth control signal, the second sub-processor obtains fourth status information of the second sub-expansion chip, and determines the second peripheral chip that inputs the fifth control signal based on the fourth status information.

[0053] Thus, compared to a solution where multiple sub-processors share one expansion chip, each sub-processor in this solution can communicate directly with its corresponding sub-expansion chip, eliminating the need for coordination with other sub-processors. This simplifies the signal transmission method.

[0054] In one implementable manner, the first control signal, the third control signal, and the fifth control signal are interrupt signals, and the second control signal, the fourth control signal, and the sixth control signal are reset interfaces, enable signals, or GPIO control signals.

[0055] In a third aspect, the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program or instructions. When the computer program or instructions are executed on a computer, the computer executes the method as described in any one of the second aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0057] Figure 1A A schematic diagram of a foldable electronic device provided in an embodiment of the present application;

[0058] Figure 1B A schematic diagram of the internal circuit of a foldable electronic device provided in an embodiment of the present application;

[0059] Figure 2 A schematic diagram of a circuit configuration of a foldable electronic device provided in an embodiment of the present application;

[0060] Figure 3 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application;

[0061] Figure 4 A software framework diagram of an electronic device provided in an embodiment of the present application;

[0062] Figure 5 A schematic diagram of the internal circuit of an electronic device provided in an embodiment of the present application;

[0063] Figure 6A A flowchart of a secondary board transmitting a signal to a main board provided in an embodiment of the present application;

[0064] Figure 6B A flow chart of a signal transmission from a main board to a secondary board provided in an embodiment of the present application;

[0065] Figure 7 A schematic diagram of the internal circuit of another electronic device provided in an embodiment of the present application;

[0066] Figure 8A schematic diagram of the internal circuit of another electronic device provided in an embodiment of the present application;

[0067] Figure 9A A flowchart of another embodiment of the present application providing a method for transmitting signals from a secondary board to a primary board;

[0068] Figure 9B A flowchart of another embodiment of the present application providing a method for transmitting signals from a secondary board to a primary board;

[0069] Figure 9C A flow chart of a signal transmission from a main board to a secondary board provided in an embodiment of the present application;

[0070] Figure 10 This is a schematic diagram of the internal circuit of another electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0071] With the rapid development of electronic device technology, foldable electronic devices have emerged to address the issues of traditional tablet computers being bulky and inconvenient to carry, as well as the small screens of mobile phones. Foldable electronic devices can unfold their screens when in use to provide a larger display area. When not in use, they can be folded back to the unfolded state, making them easier to carry.

[0072] like Figure 1A As shown, the foldable electronic device includes a main board 10, a sub-board 20, and a hinge 30. The main board 10 and the sub-board 20 are typically connected by the hinge 30 and are located on both sides of the hinge 30. The main board 10 is the core component of the foldable electronic device. The main board 10 is responsible for controlling the functions and data processing of the entire system, including processing applications, managing power, connecting to the network, etc. The sub-board 20 is an additional board in the foldable electronic device that is connected to the main board 10 to provide more functions and interaction methods. For example, the sub-board 20 may include external devices such as audio devices, display devices, charging devices, sensors, and power supplies.

[0073] For example, Figure 1B As shown, the mainboard 10 carries a system on chip (SOC), a power clock control chip PMK, a power management unit (PMU), and a power chip PM8010. The sub-board 20 carries peripheral chips corresponding to multiple external devices, such as audio driver chips such as SmartPA, display driver chips such as OLED / TP, charging (SC) driver chips, sensor / RF / camera driver chips, and power driver chips.

[0074] Each peripheral chip may include multiple general-purpose input / output (GPIO) interfaces, and the GPIO interfaces may be configured as control signals. For example, the GPIO interface may be configured to input and output various control signals such as a reset (Rst) signal, an interrupt (Int) signal, an enable (Enable) signal, and a power signal. An interface configured to input and output an Rst signal may be referred to as an Rst interface, an interface configured to input and output an Int signal may be referred to as an Int interface, and an interface configured to input and output an Enable signal may be referred to as an Enable interface.

[0075] In this way, each peripheral chip can be coupled to the system on chip (SOC), PMK, PMU and PM8010 on the mainboard 10 through multiple GPIO interfaces to achieve communication connection with the mainboard 10, and then the mainboard 10 can send control signals (such as Rst signals, Enable signals and other control signals) to each peripheral chip, and each peripheral chip can also report control signals (such as Int signals) to the mainboard 10.

[0076] In the embodiment of the present application, the circuit for transmitting control signals between the main board 10 and the sub-board 20 is called a GPIO circuit. Figure 1B and Figure 2 As shown, seven GPIO lines are connected between the audio driver chip and the SOC for controlling audio components, such as interrupting audio playback and resetting audio ports. Four GPIO lines are connected between the display driver chip and the SOC for controlling the display, such as initializing brightness and contrast. Five GPIO lines are connected between the charging driver chip and the SOC for controlling the charging component, such as interrupting or enabling charging. Five GPIO lines are connected between the sensor / RF / camera driver chip and the SOC for controlling sensors / RF / camera components, such as interrupting or enabling them. Seven GPIO lines are connected between the power driver chip and the PM8010 power supply chip for controlling the power supply, such as controlling the power supply to sensors / RF / camera components, and display components.

[0077] Thus, there are at least 28 GPIO lines between the main board 10 and the sub-board 20. For details, see Figure 2 , which will not be described here. In the embodiment of the present application, the line that needs to pass through the rotating shaft 30 horizontally is called a through-shaft line. For example, Figure 1B It includes 28 through-axis GPIO lines.

[0078] The above description is based on the example of 28 through-hole GPIO lines between the main board 10 and the slave board 20, and does not limit the through-hole lines between the main board 10 and the slave board 20. For example, in some electronic devices, the main board 10 and the slave board 20 may have more than 100 through-hole lines, including GPIO lines and some buses.

[0079] However, with the development of foldable electronic devices, the number of peripheral chips or GPIO interfaces on the sub-board 20 may increase, resulting in more through-axis GPIO lines. However, the width W of a foldable electronic device is limited. Therefore, it is difficult to layout more GPIO lines within the limited width W of the foldable electronic device. Therefore, this through-axis GPIO line design solution will limit the development of foldable electronic devices.

[0080] In order to solve the above-mentioned technical problems, an embodiment of the present application provides an electronic device and a signal transmission method, in which an extension chip is added to the sub-board, wherein the interface for inputting and outputting control signals in the peripheral chip is coupled to the extension chip, and the extension chip is then coupled to the SOC on the main board through a bus and a GPIO interface. In this way, the original 28-way through-axis GPIO lines are replaced by one through-axis bus and one through-axis GPIO line between the main board and the sub-board, thereby reducing the through-axis lines. The original 28-way through-axis GPIO lines are improved to between the extension chip and each peripheral chip on the same sub-board, so these 28-way GPIO lines do not need a through-axis design. In this way, the electronic device provided by the present application embodiment can solve the problem that it is difficult to layout more GPIO lines within the limited width range of foldable electronic devices.

[0081] The implementation methods provided in this application are described in detail below.

[0082] The electronic device in the embodiments of the present application may be a foldable electronic device, for example, a foldable mobile phone, a handheld computer, a laptop computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), an augmented reality (AR) or virtual reality (VR) device, etc. The embodiments of the present application do not impose any particular restrictions on the specific form of the electronic device. For example, the electronic device is a foldable mobile phone as an example for illustration.

[0083] like Figure 3As shown, the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0084] It should be understood that the structure illustrated in the embodiments of the present invention does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0085] The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), an audio digital signal processor (ADSP), a baseband processor, and / or a neural-network processing unit (NPU). The different processing units may be independent devices or integrated into one or more processors.

[0086] The controller can generate operation control signals according to the instruction operation code and timing signal to complete the control of instruction fetching and execution.

[0087] Processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in processor 110 is a cache memory. This memory can store instructions or data that have just been used or are being recycled by processor 110. If processor 110 needs to use the same instruction or data again, it can directly access the memory. This avoids duplicate accesses, reduces processor 110 latency, and thus improves system efficiency.

[0088] In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface.

[0089] The I2C interface is a bidirectional synchronous serial bus that includes a serial data line (SDA) and a serial clock line (SCL). In some embodiments, the processor 110 may include multiple I2C bus lines. The processor 110 may be coupled to the touch sensor 180K, the charger, the flash, the camera 193, and the like via different I2C bus interfaces. For example, the processor 110 may be coupled to the touch sensor 180K via the I2C interface, enabling communication between the processor 110 and the touch sensor 180K via the I2C bus interface, thereby implementing the touch function of the electronic device 100.

[0090] The I2S interface can be used for audio communication. In some embodiments, the processor 110 can include multiple I2S buses. The processor 110 can be coupled to the audio module 170 via the I2S bus to enable communication between the processor 110 and the audio module 170. In some embodiments, the audio module 170 can transmit audio signals to the wireless communication module 160 via the I2S interface, enabling the function of answering calls through a Bluetooth headset.

[0091] The PCM interface can also be used for audio communication, sampling, quantizing, and encoding analog signals. In some embodiments, the audio module 170 and the wireless communication module 160 can be coupled via a PCM bus interface. In some embodiments, the audio module 170 can also transmit audio signals to the wireless communication module 160 via the PCM interface, enabling the function of answering calls via a Bluetooth headset. Both the I2S interface and the PCM interface can be used for audio communication.

[0092] The UART interface is a universal serial data bus used for asynchronous communication. This bus can be a bidirectional communication bus. It converts the data to be transmitted between serial communication and parallel communication. In some embodiments, the UART interface is typically used to connect the processor 110 and the wireless communication module 160. For example, the processor 110 communicates with the Bluetooth module in the wireless communication module 160 via the UART interface to implement Bluetooth functionality. In some embodiments, the audio module 170 can transmit audio signals to the wireless communication module 160 via the UART interface, enabling the function of playing music through Bluetooth headphones.

[0093] The MIPI interface can be used to connect the processor 110 to peripheral devices such as the display 194 and the camera 193. MIPI interfaces include the camera serial interface (CSI) and the display serial interface (DSI). In some embodiments, the processor 110 and the camera 193 communicate via the CSI interface to implement the camera function of the electronic device 100. The processor 110 and the display 194 communicate via the DSI interface to implement the display function of the electronic device 100.

[0094] The GPIO interface can be configured through software. The GPIO interface can be configured as a control signal or as a data signal. In some embodiments, the GPIO interface can be used to connect the processor 110 with the camera 193, the display 194, the wireless communication module 160, the audio module 170, the sensor module 180, etc. The GPIO interface can also be configured as an I2C interface, an I2S interface, a UART interface, a MIPI interface, etc. For example, in an embodiment of the present application, the GPIO interface can be used to connect the processor 110 with the camera 193, the display 194, the wireless communication module 160, the audio module 170, the sensor module 180, etc. through an expansion chip.

[0095] The USB interface 130 is an interface that complies with USB standards and may be a Mini USB interface, a Micro USB interface, a USB Type-C interface, or the like. The USB interface 130 can be used to connect a charger to charge the electronic device 100, or to transfer data between the electronic device 100 and peripheral devices. It can also be used to connect headphones to play audio. This interface can also be used to connect other electronic devices, such as augmented reality devices.

[0096] It is understood that the interface connection relationship between the modules illustrated in the embodiment of the present invention is merely an illustrative illustration and does not constitute a structural limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may also adopt different interface connection methods from the above embodiments, or a combination of multiple interface connection methods.

[0097] The charging management module 140 is configured to receive charging input from a charger. The charger can be either a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 can receive charging input from the wired charger via the USB interface 130. In some wireless charging embodiments, the charging management module 140 can receive wireless charging input via the wireless charging coil of the electronic device 100. While charging the battery 142, the charging management module 140 can also provide power to the electronic device via the power management module 141.

[0098] The power management module 141 is used to connect the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and provides power to the processor 110, the internal memory 121, the display 194, the camera 193, and the wireless communication module 160. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage, impedance). In some other embodiments, the power management module 141 can also be set in the processor 110. In other embodiments, the power management module 141 and the charging management module 140 can also be set in the same device.

[0099] The wireless communication function of the electronic device 100 can be implemented through the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modem processor and the baseband processor.

[0100] Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 100 can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In other embodiments, the antennas can be used in conjunction with a tuning switch.

[0101] The mobile communication module 150 can provide solutions for wireless communications including 2G / 3G / 4G / 5G applied to the electronic device 100. The mobile communication module 150 may include at least one filter, a switch, a power amplifier, a low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves from the antenna 1, and filter, amplify, and process the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves for radiation through the antenna 1. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the same device as at least some of the modules of the processor 110.

[0102] The modem processor may include a modulator and a demodulator. The modulator is used to modulate the low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After being processed by the baseband processor, the low-frequency baseband signal is passed to the application processor. The application processor outputs a sound signal through an audio device (not limited to the speaker 170A, the receiver 170B, etc.) or displays an image or video through the display screen 194. In some embodiments, the modem processor may be an independent device. In other embodiments, the modem processor may be independent of the processor 110 and be set in the same device as the mobile communication module 150 or other functional modules.

[0103] The wireless communication module 160 can provide wireless communication solutions including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc., which are applied to the electronic device 100. The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, frequency modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 110. The wireless communication module 160 can also receive the signal to be sent from the processor 110, frequency modulate it, amplify it, and convert it into electromagnetic waves for radiation through the antenna 2.

[0104] In some embodiments, the antenna 1 of the electronic device 100 is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the electronic device 100 can communicate with the network and other devices through wireless communication technology. The wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technology. The GNSS may include a global positioning system (GPS), a global navigation satellite system (GLONASS), a Beidou navigation satellite system (BDS), a quasi-zenith satellite system (QZSS) and / or a satellite based augmentation system (SBAS).

[0105] Electronic device 100 implements display functionality through a GPU, display screen 194, and an application processor. A GPU is a microprocessor for image processing that connects display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs that execute program instructions to generate or modify display information.

[0106] Display screen 194 is used to display images, videos, and the like. Display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a MiniLED, a MicroLED, a Micro-oLed, or a quantum dot light-emitting diode (QLED). In some embodiments, electronic device 100 may include one or N display screens 194, where N is a positive integer greater than one.

[0107] The electronic device 100 can implement a shooting function through an ISP, a camera 193, a video codec, a GPU, a display screen 194, and an application processor.

[0108] The ISP processes data fed back by camera 193. For example, when taking a photo, the shutter is opened, and light is transmitted through the lens to the camera's photosensitive element. The light signal is converted into an electrical signal, which is then passed to the ISP for processing and converted into a visible image. The ISP can also perform algorithmic optimization on image noise, brightness, and skin tone. It can also optimize parameters such as exposure and color temperature of the captured scene. In some embodiments, the ISP can be located within camera 193.

[0109] The camera 193 is used to capture still images or videos. The object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, and then passes the electrical signal to the ISP for conversion into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV or other format. In some embodiments, the electronic device 100 may include 1 or N cameras 193, where N is a positive integer greater than 1.

[0110] The digital signal processor is used to process digital signals. In addition to processing digital image signals, it can also process other digital signals. For example, when the electronic device 100 selects a frequency point, the digital signal processor is used to perform Fourier transform on the frequency point energy.

[0111] Video codecs are used to compress or decompress digital video. Electronic device 100 may support one or more video codecs. This allows electronic device 100 to play or record videos in various encoding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, and MPEG4.

[0112] The NPU is a neural network (NN) computing processor. Drawing on the structure of biological neural networks, such as the transmission patterns between neurons in the human brain, it rapidly processes input information and can continuously self-learn. The NPU can enable intelligent cognitive applications in electronic device 100, such as image recognition, face recognition, speech recognition, and text comprehension.

[0113] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 via the external memory interface 120 to implement data storage functions. For example, files such as music and videos can be stored on the external memory card.

[0114] The internal memory 121 can be used to store computer executable program codes, which include instructions. The internal memory 121 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area may store data created during the use of the electronic device 100 (such as audio data, a phone book, etc.), etc. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The processor 110 executes various functional applications and data processing of the electronic device 100 by running instructions stored in the internal memory 121 and / or instructions stored in a memory provided in the processor.

[0115] The electronic device 100 can implement audio functions such as music playback and recording through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone jack 170D, and the application processor.

[0116] The audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals. The audio module 170 can also be used to encode and decode audio signals. In some embodiments, the audio module 170 can be provided in the processor 110, or some functional modules of the audio module 170 can be provided in the processor 110.

[0117] Speaker 170A, also known as a "horn," is used to convert audio electrical signals into sound signals. Electronic device 100 can use speaker 170A to listen to music or make hands-free calls. Multiple speakers 170A can be provided in electronic device 100. For example, one speaker 170A can be provided on the top of electronic device 100, another speaker 170A can be provided on the bottom, and so on.

[0118] Receiver 170B, also known as an "earpiece," is used to convert audio signals into sound signals. When electronic device 100 receives a call or voice message, the user can hold receiver 170B close to their ear to listen to the voice. In some embodiments, speaker 170A and receiver 170B may be integrated into one component, although this is not a limitation of the present invention.

[0119] Microphone 170C, also known as "microphone" or "microphone", is used to convert sound signals into electrical signals. When making a call or sending a voice message, the user can speak by putting their mouth close to the microphone 170C to input the sound signal into the microphone 170C. The electronic device 100 can be provided with at least one microphone 170C. In other embodiments, the electronic device 100 can be provided with two microphones 170C, which can not only collect sound signals but also realize noise reduction function. In other embodiments, the electronic device 100 can also be provided with three, four or more microphones 170C to collect sound signals, reduce noise, identify the source of sound, realize directional recording function, etc.

[0120] The headphone jack 170D is used to connect a wired headphone and can be the USB interface 130 or a 3.5mm open mobile terminal platform (OMTP) standard interface or a cellular telecommunications industry association of the USA (CTIA) standard interface.

[0121] Pressure sensor 180A is used to sense pressure signals and convert them into electrical signals. In some embodiments, pressure sensor 180A can be located on display screen 194. There are many types of pressure sensors 180A, such as resistive, inductive, and capacitive. A capacitive pressure sensor can include at least two parallel plates made of conductive material. When force acts on pressure sensor 180A, the capacitance between the electrodes changes. Electronic device 100 determines the intensity of the pressure based on this change in capacitance. When a touch operation is applied to display screen 194, electronic device 100 detects the touch intensity based on pressure sensor 180A. Electronic device 100 can also calculate the touch location based on the detection signal from pressure sensor 180A. In some embodiments, touch operations applied to the same touch location but with different touch intensities can correspond to different operation instructions. For example, when a touch operation with an intensity less than a first pressure threshold is applied to a short message application icon, a command to view short messages is executed. When a touch operation with an intensity greater than or equal to the first pressure threshold is applied to a short message application icon, a command to create a new short message is executed.

[0122] The gyroscope sensor 180B can be used to determine the motion posture of the electronic device 100. In some embodiments, the angular velocity of the electronic device 100 around three axes (i.e., x, y, and z axes) can be determined by the gyroscope sensor 180B. The gyroscope sensor 180B can be used for anti-shake shooting. For example, when the shutter is pressed, the gyroscope sensor 180B detects the angle of the electronic device 100 shaking, calculates the distance that the lens module needs to compensate based on the angle, and allows the lens to offset the shaking of the electronic device 100 through reverse movement to achieve anti-shake. The gyroscope sensor 180B can also be used for navigation and somatosensory game scenes.

[0123] The air pressure sensor 180C is used to measure air pressure. In some embodiments, the electronic device 100 calculates the altitude using the air pressure value measured by the air pressure sensor 180C to assist in positioning and navigation.

[0124] The magnetic sensor 180D includes a Hall sensor. The electronic device 100 can use the magnetic sensor 180D to detect the opening and closing of the flip case. In some embodiments, when the electronic device 100 is a flip phone, the electronic device 100 can detect the opening and closing of the flip cover based on the magnetic sensor 180D. Based on the detected opening and closing status of the case or flip cover, features such as automatic unlocking of the flip cover can be configured.

[0125] Accelerometer 180E can detect the magnitude of acceleration of electronic device 100 in all directions (generally three axes). It can also detect the magnitude and direction of gravity when electronic device 100 is stationary. It can also be used to identify the electronic device's posture, enabling applications such as switching between landscape and portrait modes and pedometers.

[0126] The distance sensor 180F is used to measure distance. The electronic device 100 can measure distance using infrared or laser. In some embodiments, when shooting a scene, the electronic device 100 can use the distance sensor 180F to measure distance to achieve fast focusing.

[0127] The proximity light sensor 180G may include, for example, a light emitting diode (LED) and a light detector, such as a photodiode. The light emitting diode may be an infrared light emitting diode. The electronic device 100 emits infrared light outward through the light emitting diode. The electronic device 100 uses a photodiode to detect infrared reflected light from nearby objects. When sufficient reflected light is detected, it can be determined that there is an object near the electronic device 100. When insufficient reflected light is detected, the electronic device 100 can determine that there is no object near the electronic device 100. The electronic device 100 can use the proximity light sensor 180G to detect that the user is holding the electronic device 100 close to the ear to talk, so as to automatically turn off the screen to save power. The proximity light sensor 180G can also be used in leather case mode and pocket mode to automatically unlock and lock the screen.

[0128] Ambient light sensor 180L is used to sense ambient light brightness. Electronic device 100 can adaptively adjust the brightness of display screen 194 based on the perceived ambient light. Ambient light sensor 180L can also be used to automatically adjust white balance when taking photos. Ambient light sensor 180L can also work with proximity light sensor 180G to detect whether electronic device 100 is in a pocket to prevent accidental touches.

[0129] The fingerprint sensor 180H is used to collect fingerprints. The electronic device 100 can use the collected fingerprint characteristics to implement fingerprint unlocking, access application locks, fingerprint photography, fingerprint call answering, etc.

[0130] The temperature sensor 180J is used to detect temperature. In some embodiments, the electronic device 100 uses the temperature detected by the temperature sensor 180J to execute a temperature processing strategy. For example, when the temperature reported by the temperature sensor 180J exceeds a threshold, the electronic device 100 reduces the performance of the processor located near the temperature sensor 180J to reduce power consumption and implement thermal protection. In other embodiments, when the temperature is lower than another threshold, the electronic device 100 heats the battery 142 to prevent the electronic device 100 from shutting down abnormally due to low temperature. In other embodiments, when the temperature is lower than another threshold, the electronic device 100 boosts the output voltage of the battery 142 to prevent abnormal shutdown due to low temperature.

[0131] The touch sensor 180K is also called a "touch-sensitive device." The touch sensor 180K can be disposed on the display screen 194. The touch sensor 180K and the display screen 194 form a touch screen, also called a "touch screen." The touch sensor 180K is used to detect touch operations applied thereto or in the vicinity thereof. The touch sensor can transmit the detected touch operations to the application processor to determine the type of touch event. Visual output related to the touch operations can be provided via the display screen 194. In other embodiments, the touch sensor 180K can also be disposed on the surface of the electronic device 100, at a location different from that of the display screen 194.

[0132] The bone conduction sensor 180M can obtain vibration signals. In some embodiments, the bone conduction sensor 180M can obtain vibration signals from the vibrating bones of the human body. The bone conduction sensor 180M can also contact the human pulse to receive blood pressure pulse signals. In some embodiments, the bone conduction sensor 180M can also be set in headphones to form bone conduction headphones. The audio module 170 can parse out voice signals based on the vibration signals of the vibrating bones of the human body obtained by the bone conduction sensor 180M to implement voice functions. The application processor can parse heart rate information based on the blood pressure pulse signals obtained by the bone conduction sensor 180M to implement heart rate detection functions.

[0133] The buttons 190 include a power button, a volume button, and the like. The buttons 190 may be mechanical buttons or touch buttons. The electronic device 100 may receive key inputs and generate key signal inputs related to user settings and function control of the electronic device 100.

[0134] Motor 191 can generate vibration prompts. Motor 191 can be used for incoming call vibration prompts, and can also be used for touch vibration feedback. For example, touch operations acting on different applications (such as taking pictures, audio playback, etc.) can correspond to different vibration feedback effects. For touch operations acting on different areas of the display screen 194, motor 191 can also correspond to different vibration feedback effects. Different application scenarios (for example: time reminders, receiving messages, alarm clocks, games, etc.) can also correspond to different vibration feedback effects. The touch vibration feedback effect can also support customization.

[0135] The indicator 192 may be an indicator light, which may be used to indicate the charging status, power level changes, messages, missed calls, notifications, etc.

[0136] The SIM card interface 195 is used to connect a SIM card. The SIM card can be connected to or disconnected from the electronic device 100 by inserting it into or removing it from the SIM card interface 195. The electronic device 100 can support 1 or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 195 can support Nano SIM cards, Micro SIM cards, SIM cards, and the like. Multiple cards can be inserted into the same SIM card interface 195 at the same time. The types of the multiple cards can be the same or different. The SIM card interface 195 can also be compatible with different types of SIM cards. The SIM card interface 195 can also be compatible with external memory cards. The electronic device 100 interacts with the network through the SIM card to implement functions such as calls and data communications. In some embodiments, the electronic device 100 uses an eSIM, i.e., an embedded SIM card. The eSIM card can be embedded in the electronic device 100 and cannot be separated from the electronic device 100.

[0137] The software system of the electronic device 100 can adopt a layered architecture, an event-driven architecture, a micro-kernel architecture, a micro-service architecture, or a cloud architecture. In the embodiment of the present invention, the Android system with a layered architecture is used as an example to illustrate the software structure of the electronic device 100.

[0138] Figure 4 It is a software structure block diagram of the electronic device 100 according to an embodiment of the present application.

[0139] A layered architecture divides software into several layers, each with distinct roles and responsibilities. Layers communicate with each other through software interfaces. In some embodiments, the Android system is divided into four layers: the application layer, the application framework layer, the Android runtime and system libraries, and the kernel layer.

[0140] The application layer can include a series of application packages.

[0141] like Figure 4 As shown, the application package may include applications such as camera, gallery, calendar, call, map, navigation, WLAN, Bluetooth, music, video, short message, etc.

[0142] The application framework layer provides an application programming interface (API) and programming framework for the applications in the application layer. The application framework layer includes some predefined functions.

[0143] like Figure 4 As shown, the application framework layer may include a window manager, a content provider, a view system, a phone manager, a resource manager, a notification manager, and the like.

[0144] The window manager is used to manage window programs. The window manager can obtain the display size, determine whether there is a status bar, lock the screen, take screenshots, etc.

[0145] Content providers are used to store and retrieve data and make it accessible to applications. The data may include videos, images, audio, calls made and received, browsing history and bookmarks, phone books, etc.

[0146] The view system includes visual controls, such as those for displaying text and images. The view system is used to build applications. A display interface can consist of one or more views. For example, a display interface containing a text notification icon might include a view for displaying text and a view for displaying images.

[0147] The phone manager is used to provide communication functions of the electronic device 100, such as management of call status (including answering, hanging up, etc.).

[0148] The resource manager provides various resources for applications, such as localized strings, icons, images, layout files, video files, and so on.

[0149] The Notification Manager allows applications to display notifications in the status bar. These messages can be displayed briefly and then disappear automatically without user interaction. For example, the Notification Manager is used to notify users of completed downloads and message reminders. The Notification Manager can also display notifications in the top status bar of the system as icons or scrolling text, such as notifications from background applications, or as dialog windows on the screen. Examples include text messages in the status bar, beeps, vibrations on electronic devices, and flashing indicator lights.

[0150] Android Runtime includes core libraries and a virtual machine. Android runtime is responsible for scheduling and management of the Android system.

[0151] The core library consists of two parts: one is the function that needs to be called by the Java language, and the other is the Android core library.

[0152] The application layer and application framework layer run in a virtual machine. The virtual machine executes Java files in the application layer and application framework layer as binary files. The virtual machine manages object lifecycles, stack management, thread management, security and exception management, and garbage collection.

[0153] The system library can include multiple functional modules, such as surface manager, media library, 3D graphics processing library (such as OpenGL ES), 2D graphics engine (such as SGL), etc.

[0154] The surface manager is used to manage the display subsystem and provide fusion of 2D and 3D layers for multiple applications.

[0155] The media library supports playback and recording of a variety of common audio and video formats, as well as static image files. The media library can support a variety of audio and video encoding formats, such as: MPEG4, H.264, MP3, AAC, AMR, JPG, PNG, etc.

[0156] The 3D graphics processing library is used to implement 3D graphics drawing, image rendering, compositing, and layer processing.

[0157] A 2D graphics engine is a drawing engine for 2D drawings.

[0158] The kernel layer is the layer between hardware and software. The kernel layer includes at least display driver, camera driver, audio driver, sensor driver, charging driver, etc. The embodiment of the present application also includes an expansion chip driver.

[0159] Figure 5 This is a schematic diagram of an electronic device provided in an embodiment of the present application. Figure 5 As shown, the electronic device provided in the embodiment of the present application may include a processor, at least one peripheral chip and an expansion chip. The processor is located on the main board side, and the at least one peripheral chip and the expansion chip are both located on the sub-board side. The expansion chip includes a processor output interface Int, a bus interface I2C-1 and at least one peripheral input and output interface (Int1...Intn, Rst1...Rstn, etc.). The processor output interface Int and the bus interface I2C-1 are both coupled to the processor; at least one peripheral input and output interface is respectively coupled to at least one peripheral chip. The expansion chip is used to receive a first control signal sent by the peripheral chip through the peripheral input and output interface, and send the first control signal to the processor through the processor output interface; and / or, to receive a second control signal sent by the processor through the bus interface I2C-1, and control the peripheral chip based on the second control signal.

[0160] Among them, the peripheral input and output interface refers to the interface used to realize communication between the expansion chip and the peripheral chip. For example, the peripheral input and output interface may include an Rst interface, an Enable interface, an Int interface, and a GPIO interface for transmitting control signals. In this way, the peripheral chip can input a first control signal, such as an interrupt signal, to the expansion chip through the Rst interface. The expansion chip can also output control signals such as enable and reset to the corresponding peripheral chip through the Enable interface, Rst interface, and GPIO interface respectively to reset or enable the corresponding interface of the peripheral chip.

[0161] For example, the peripheral chips include an audio driver chip, a display driver chip, a charging driver chip, and a sensor driver chip. Figure 5 As shown, the peripheral input and output interfaces Int1 and Rst1 on the expansion chip are coupled to the corresponding pins on the audio driver chip. In this way, the audio driver chip can input an interrupt signal to the expansion chip through Rst1, and the expansion chip can output a reset signal to the audio driver chip through Rst1. Similarly, the peripheral input and output interfaces Int2 and Rst2 on the expansion chip are coupled to the corresponding pins on the display driver chip, the peripheral input and output interfaces Int3 and Rst3 on the expansion chip are coupled to the corresponding pins on the charging driver chip, and the peripheral input and output interfaces Int4 and Rst4 on the expansion chip are coupled to the corresponding pins on the sensor driver chip. Similarly, each peripheral chip can input an interrupt signal to the expansion chip through its own peripheral input and output interface (Int2, Int3, Int4...Intn), and the expansion chip can output a reset signal to the corresponding peripheral chip through the peripheral input and output interface (Rst2, Rst3, Rst4...Rstn).

[0162] like Figure 5 As shown, the lines for transmitting control signals between the expansion chip and each peripheral chip are all located on the daughterboard side, eliminating the need for a through-pin design, thereby reducing through-pin GPIO lines. This way, even if more peripheral chips are added or the number of pins on the peripheral chips used for transmitting control signals increases, no additional through-pin GPIO lines will be added.

[0163] For the motherboard side, the motherboard can carry a processor, and the processor can be integrated into the SOC. The expansion chip is coupled to the processor through the processor output interface Int, so that the expansion chip can output the received first control signal (such as an interrupt signal) to the processor through the processor output interface Int. The expansion chip is coupled to the processor through the bus interface I2C-1, so that the processor can communicate with the expansion chip through the bus interface I2C-1. For example, the processor can send a second control signal to the expansion chip through the bus interface I2C-1. Correspondingly, the expansion chip can receive the second control signal sent by the processor through the bus interface I2C-1 and control the peripheral chip based on the second control signal. For another example, the processor can also obtain the first status information of the expansion chip through the bus interface I2C-1. For example, the processor can read the register of the expansion chip through the bus interface I2C-1 to obtain the first status information.

[0164] In this way, compared to Figure 1B The solution of using 28 through-axis GPIO lines is adopted, such as Figure 5 As shown, the embodiment of the present application only requires two through-axis lines to realize the communication connection between each peripheral chip and the processor, which greatly saves the through-axis lines and can solve the problem of circuit layout bottleneck in foldable electronic devices.

[0165] It should be noted that the embodiments of the present application do not limit the number and type of peripheral chips, and the solutions provided by the embodiments of the present application can be applied to any peripheral chip that needs to transmit control signals. The above is only an example of an example in which peripheral chips include audio driver chips, display driver chips, charging driver chips, and sensor driver chips, and does not represent a limitation on peripheral chips. More or fewer peripheral chips can be included on the sub-board. For example, other peripheral chips such as power driver chips, RF driver chips, camera driver chips, etc. can also be included on the sub-board.

[0166] It should also be noted that the above embodiment is merely an example of an I2C bus interface, and does not limit the bus interface type. For example, the bus interface may also be an I3C bus or an SPI bus.

[0167] The following is an exemplary description of a signal transmission method provided in an embodiment of the present application. The signal transmission method includes a method for transmitting a signal from a main board to a secondary board, and a method for transmitting a signal from a secondary board to a main board. The method can be applied to Figure 5 Electronic devices shown.

[0168] Figure 6A A flowchart of a method for transmitting signals from a main board to a sub-board provided in an embodiment of the present application. Figure 6BThis is a flow chart of a method for transmitting signals from a secondary board to a main board provided in an embodiment of the present application. Figure 6A and Figure 6B As shown, a signal transmission method provided in an embodiment of the present application may include the following steps:

[0169] Step 101: The expansion chip receives a first control signal sent by the peripheral chip, and sends the first control signal to the processor.

[0170] In some embodiments, the first control signal may be an interrupt signal, and the corresponding peripheral chip may provide an interrupt interface. When the peripheral chip needs to notify the processor of an important event, the peripheral chip may set the interrupt interface to a high level or trigger a level / edge signal, which may be referred to as the first control signal.

[0171] For example, in Figure 6A In the electronic device shown, if a speaker malfunctions, the audio driver chip can generate an interrupt signal to request interrupt processing from the processor. The audio driver chip can then send the interrupt signal to the expansion chip via the Int1 interface. After receiving the interrupt signal from the audio driver chip, the expansion chip then sends the interrupt signal to the processor via the Int interface.

[0172] That is to say, in the embodiment of the present application, the first control signal generated by the peripheral chip is first input into the expansion chip and then transferred to the processor by the expansion chip.

[0173] However, since the first control signal is sent to the processor by the expansion chip, after receiving the first control signal, the processor only knows that the first control signal originates from the expansion chip and is unclear about which peripheral chip the first control signal originates from. Therefore, in response to receiving the first control signal, the processor executes step 102 to determine which peripheral chip generated the first control signal.

[0174] Step 102: In response to receiving the first control signal, the processor obtains first status information of the extension chip, and determines the peripheral chip that inputs the first control signal based on the first status information.

[0175] In the embodiment of the present application, the processor includes a driver for the extension chip, ie, the extension chip driver. In this way, the processor can communicate with the extension chip through the extension chip driver.

[0176] For example, Figure 6A As shown, the expansion chip driver in the processor can obtain the first state information of the expansion chip through the bus interface I2C-1. The first state information can be used to determine the peripheral chip that inputs the first control signal.

[0177] Specifically, the processor can read the register of the expansion chip through the bus interface I2C-1 to obtain the first status information. The register of the expansion chip can record the interface that generates the first control signal, and each interface of the expansion chip corresponds to each peripheral chip. Therefore, the processor can determine the peripheral chip that inputs the first control signal based on the information of the interface that generates the first control signal and the correspondence between each interface and the peripheral chip.

[0178] For example, combined Figure 5 and Figure 6A As shown, interface Int1 on the expansion chip corresponds to the audio driver chip, interface Int2 corresponds to the display driver chip, interface Int3 corresponds to the charging driver chip, and interface Int4 corresponds to the sensor driver chip. Assuming that the first control signal is a control signal generated by the audio driver chip, the processor can determine that the first control signal is generated by interface Int1 by reading the register of the expansion chip. Furthermore, based on the correspondence between interface Int1 and the peripheral chip, it can be determined that the first control signal is generated by the audio driver chip corresponding to interface Int1.

[0179] Step 103: The processor wakes up the driver of the peripheral chip and obtains second state information of the peripheral chip.

[0180] The processor may include a driver corresponding to each peripheral chip. For example, Figure 5 As shown, the processor may include an audio driver corresponding to the audio driver chip, a display driver corresponding to the display driver chip, a charging driver corresponding to the charging driver chip, and a sensor driver corresponding to the sensor driver chip. In this way, the processor can communicate with the corresponding peripheral chip through the driver of the peripheral chip. For example, the processor obtains the second state information of the peripheral chip by waking up the driver corresponding to the peripheral chip.

[0181] In some embodiments, the processor can communicate with each peripheral chip through its own bus interface. Figure 5 As shown, the audio driver chip and the processor can communicate through the bus interface I2C-2, the display driver chip and the processor can communicate through the bus interface I2C-3, the charging driver chip and the processor can communicate through the bus interface I2C-4, and the sensor driver chip and the processor can communicate through the bus interface I2C-5.

[0182] It should be noted that the driver for waking up the processor in step 103 is the driver for the peripheral chip that inputs the first control signal. Figure 6A As shown, when the first control signal is input to the audio driver chip, the processor wakes up the audio driver of the audio driver chip and obtains the second state information of the audio driver chip through the bus interface I2C-2.

[0183] The second state information may include information indicating the reason why the peripheral chip generated the first control signal. For example, the second state information indicates that the first control signal generated by the audio driver chip is an overcurrent protection (OCP) interrupt. Thus, the processor may, based on the second state information, execute an active control process on the audio driver chip. For example, the processor may, based on the second state information, execute a reset operation on the Rst1 interface of the audio driver chip.

[0184] The following is an example of a method for transmitting signals from the secondary board to the main board (also known as an active control process). This method can be applied to Figure 5 Electronic devices shown.

[0185] Figure 6B This is a flow chart of a method for transmitting signals from a secondary board to a main board provided in an embodiment of the present application. Figure 6B As shown, the signal transmission method provided in the embodiment of the present application may include the following steps:

[0186] Step 104: The processor sends a second control signal to the expansion chip, where the second control signal is used to instruct to perform target control on the target peripheral chip.

[0187] The method for transmitting signals from a secondary board to a main board provided in the embodiment of the present application can be applied to the scenario of initializing a peripheral chip or actively controlling a peripheral chip.

[0188] For example, Figure 6B As shown, in the scenario of initializing the peripheral chip, the processor can actively send a second control signal to the expansion chip through the bus interface I2C-1. The second control signal can be used to instruct the audio driver chip to initialize processing. For example, the second control signal is a reset signal, which is used to reset the peripheral chip to an initial state.

[0189] For example, in the scenario of actively controlling a peripheral chip, it is assumed that the processor receives a play request sent by a user. In this way, the processor can respond to the received play request by actively sending a second control signal to the expansion chip through the bus interface I2C-1. For example, the second control signal is used to instruct the audio driver chip to play the corresponding audio.

[0190] It should be noted that the target peripheral chip in the embodiment of the present application can be any one or more peripheral chips. The embodiment of the present application does not specifically limit the target control, and can be different according to the specific application scenario. For example, the target control can be initialization, enable, start, pause, etc.

[0191] Step 105 : The expansion chip performs target control on the target peripheral chip in response to receiving the second control signal.

[0192] In the embodiment of the present application, different controls can be implemented between each peripheral chip and the expansion chip through multiple peripheral input and output interfaces. In this way, the expansion chip can perform target control on the target interface of the target peripheral chip based on the second control signal.

[0193] For example, assuming that the second control signal is used to instruct the audio driver chip to initialize, the expansion chip can process the Rst1 interface corresponding to the audio driver chip based on the second control signal to initialize the audio driver chip. For example, the expansion chip can set the Rst1 interface to a specific level or trigger a specific level / edge signal to control the reset operation.

[0194] In some embodiments, the target peripheral chip can communicate with the processor via its own bus interface to confirm whether the reset is successful. For example, the audio driver chip can communicate with the processor via the bus interface I2C-2 to confirm whether the Rst1 interface is reset successfully.

[0195] In the above embodiment, each peripheral chip can be controlled by the same processor or by different processors.

[0196] For example, in some embodiments, a processor may include one or more sub-processors, which may be an AP, a GPU, an ISP, a DSP, an ADSP, a baseband processor, a smart sensor hub, etc. Different sub-processors may be independent devices or integrated into one or more processors.

[0197] In some embodiments, each sub-processor can be used to control one or more peripheral chips. For example, a processor includes a first sub-processor and a second sub-processor, the first sub-processor is an AP, and the second sub-processor is an ADSP. The AP can be used to control an audio driver chip and a display driver chip, and the ADSP can be used to control a charging driver chip and a sensor driver chip. Based on this, the embodiment of the present application can refer to the peripheral chip controlled by the first sub-processor as a first peripheral chip (for example, an audio driver chip and a display driver chip), and the peripheral chip controlled by the second sub-processor as a second peripheral chip (for example, a charging driver chip and a sensor driver chip).

[0198] Thus, in some embodiments, when the processor includes a first sub-processor and a second sub-processor, the processor output interface and the bus interface of the expansion chip can be coupled to different sub-processors. Figure 7As shown, the expansion chip can be coupled to the first sub-processor via the processor output interface, and the expansion chip can be coupled to the second sub-processor via the bus interface; wherein the first sub-processor is coupled to the second sub-processor. In this way, the expansion chip can be used to receive a first control signal sent by the peripheral chip via the peripheral input / output interface, and send the first control signal to the first sub-processor via the processor output interface; and / or to receive a second control signal sent by the second sub-processor via the bus interface, and control the peripheral chip based on the second control signal.

[0199] For example, Figure 7 As shown, taking the example of a processor including an AP and an ADSP, the processor output interface Int of the expansion chip can be coupled to the AP, and the bus interface I2C-1 of the expansion chip can be coupled to the ADSP. The AP and ADSP can be coupled via a GPIO interface. In this way, the expansion chip can output a first control signal to the AP via the processor output interface Int, and the AP can output the first control signal to the ADSP via the GPIO interface, thereby waking up the ADSP. In this way, the ADSP can read the registers of the expansion chip via the bus interface I2C-1.

[0200] In some embodiments, when the processor includes a first sub-processor and a second sub-processor, the processor output interface and the bus interface of the expansion chip can be coupled to the same sub-processor. Figure 8 As shown, the expansion chip can also be coupled to the second sub-processor via the processor output interface, and the expansion chip can be coupled to the second sub-processor via the bus interface; wherein the first sub-processor is coupled to the second sub-processor. In this way, the expansion chip can be used to receive a first control signal sent by the peripheral chip via the peripheral input / output interface, and send the first control signal to the second sub-processor via the processor output interface; and / or to receive a second control signal sent by the second sub-processor via the bus interface, and control the peripheral chip based on the second control signal.

[0201] It should be understood that the above embodiment is only exemplified by the second sub-processor to which both the processor output interface and the bus interface are coupled. The processor output interface and the bus interface may also be coupled to the first sub-processor.

[0202] The following is a detailed description of another signal transmission method provided in the embodiment of the present application. This method can be applied to Figure 7 and Figure 8 The electronic device shown in FIG. Figure 7 The signal transmission method of the electronic device shown is exemplarily described.

[0203] Figure 9A and Figure 9BA flowchart of a method for transmitting signals from a main board to a sub-board provided in an embodiment of the present application. Figure 9C This is a flow chart of another method for transmitting signals from a main board to a sub-board provided in an embodiment of the present application. Figure 9A 、 9B and Figure 9C As shown, another signal transmission method provided in an embodiment of the present application may include the following steps:

[0204] Step 201: The expansion chip receives a first control signal sent by the peripheral chip, and sends the first control signal to the first sub-processor.

[0205] In some embodiments, the first sub-processor may include an always-on processor (AOP). The AOP may be used to receive a first control signal and is responsible for transmitting the first control signal to each sub-processor so that each sub-processor can receive the same first control signal. In this way, regardless of whether the processor output interface Int of the extension chip is coupled to the first sub-processor or to the second sub-processor, each sub-processor can ultimately receive the same first control signal. Therefore, in an embodiment of the present application, the processor output interface Int of the extension chip can be coupled to the first sub-processor (e.g., Figure 7 Alternatively, the processor output interface Int of the expansion chip can be coupled to the second sub-processor (as shown in FIG. Figure 8 shown).

[0206] In addition, because the AOP acts as a relay station for the first control signal, there is no need to wake up the first processor to receive the first control signal, thereby reducing power consumption. For example, the AOP can receive the first control signal and forward it to the AP and ADSP. In this way, both the AP and ADSP can receive the first control signal without waking up the AP and ADSP.

[0207] In some embodiments, a feedback mechanism can be established between the AP and the ADSP to prevent the ADSP from freezing while the AP is unaware of whether the ADSP has received the first control signal. For example, after the AP sends the first control signal to the ADSP, it can receive feedback information indicating whether the ADSP has received the first control signal.

[0208] Because the first control signal comes from the expansion chip, after the first sub-processor and the second sub-processor receive the first control signal, they only know that the first control signal comes from the expansion chip and are unaware of the peripheral chip from which the first control signal originates. Therefore, the expansion chip driver can be configured in the first sub-processor or the second sub-processor to communicate with the expansion chip through the first sub-processor or the second sub-processor, determine the peripheral chip that received the first control signal, and then wake up the driver corresponding to the peripheral chip.

[0209] In addition, since the first sub-processor and the second sub-processor can control different peripheral chips respectively, the driver of the first peripheral chip controlled by the first sub-processor can be configured in the first sub-processor, and the driver of the second peripheral chip controlled by the second sub-processor can be configured in the second sub-processor.

[0210] For example, Figure 7 and Figure 8 As shown, the audio driver and display driver can both be configured in the AP, and the charging driver and sensor driver can both be configured in the ADSP. In this way, the AP can communicate with the audio driver chip and the display driver chip by waking up the audio driver and the display driver. For example, the AP can read the status of the audio driver chip through the bus interface I2C-2, and read the status of the display driver chip through the bus interface I2C-3. Similarly, the ADSP can communicate with the charging driver chip and the sensor driver chip by waking up the charging driver and the sensor driver. For example, the ADSP can read the status of the charging driver chip through the bus interface I2C-4, and read the status of the sensor driver chip through the bus interface I2C-5.

[0211] In the case where the processor includes a first sub-processor and a second sub-processor, the extension chip driver can be configured in the first sub-processor or the second sub-processor. Thus, when the first sub-processor or the second sub-processor receives the first control signal, the sub-processor configured with the extension chip driver can be awakened. The awakened sub-processor can then read the status of the extension chip or send control information to the extension chip.

[0212] If the expansion chip driver is configured on the first sub-processor, the bus interface I2C-1 of the expansion chip is coupled to the first sub-processor to enable communication between the first sub-processor and the expansion chip. If the expansion chip driver is configured on the second sub-processor, the bus interface I2C-1 of the expansion chip is coupled to the second sub-processor to enable communication between the second sub-processor and the expansion chip.

[0213] Typically, processors in electronic devices are divided into low-power processors and high-power processors. For example, the AP in an electronic device is a high-power processor, primarily responsible for executing the operating system, user interface, and application programs. ADSPs and smart sensor hubs in electronic devices are low-power processors.

[0214] In order to reduce operating power consumption, the embodiment of the present application can configure the extended chip driver in a low-power processor. For example, when the power consumption of the second sub-processor is lower than that of the first sub-processor, the extended chip driver can be configured in the second sub-processor.

[0215] For example, Figure 7 and Figure 8 As shown, when the first sub-processor is an AP and the second sub-processor is an ADSP, the extension chip driver can be configured in the ADSP. In this way, after the ADSP receives the first control signal, the ADSP will be awakened and then the ADSP will execute the step of obtaining the first status information of the extension chip.

[0216] Furthermore, if, based on the first state information, it is determined that the peripheral chip inputting the first control signal is a second peripheral chip controlled by the ADSP, the driver corresponding to the second peripheral chip is awakened. Correspondingly, if, based on the first state information, it is determined that the peripheral chip inputting the first control signal is a first peripheral chip controlled by the AP, the driver corresponding to the first peripheral chip is awakened (i.e., the AP is awakened).

[0217] As can be seen from this, by configuring the expansion chip driver in the low-power ADSP processor, when the peripheral chip receiving the first control signal is the second peripheral chip, the low-power ADSP performs the entire process, eliminating the need to wake up the high-power AP. Instead, when the peripheral chip receiving the first control signal is the first peripheral chip, the high-power AP is woken up. This reduces the overall system power consumption.

[0218] It should be noted that in the above embodiment, when the electronic device includes a first peripheral chip and a second peripheral chip, the extended chip driver can be configured in the low-power processor ADSP to reduce operating power consumption. However, if the electronic device only includes the first peripheral chip, the extended chip driver can be configured in the AP. If the electronic device only includes the second peripheral chip, the extended chip driver can also be configured in the ADSP.

[0219] The following is an exemplary description using an example in which the extended chip driver is configured on a low-power second sub-processor (eg, ADSP).

[0220] In step 202 , when the second sub-processor includes a driver for the extension chip and receives a first control signal, the second sub-processor obtains first status information of the extension chip and determines the peripheral chip that inputs the first control signal based on the first status information.

[0221] like Figure 9A As shown, the bus interface I2C-1 of the expansion chip is coupled to the ADSP. In this way, the second sub-processor can obtain the first status information of the expansion chip through the bus interface I2C-1 and determine the peripheral chip that inputs the first control signal based on the first status information.

[0222] The peripheral chip that inputs the first control signal may belong to the first peripheral chip or the second peripheral chip.

[0223] It should be noted that the specific method of obtaining the first state information and determining the peripheral chip that inputs the first control signal based on the first state information can be found in the description of step 102 and will not be repeated here.

[0224] Step 203 : When the peripheral chip receiving the first control signal is the second peripheral chip, wake up the driver of the peripheral chip receiving the first control signal and obtain second state information of the peripheral chip.

[0225] That is, in a case where the second sub-processor includes a driver of a peripheral chip that inputs the first control signal, the driver of the peripheral chip is awakened.

[0226] For example, Figure 9A As shown, if the peripheral chip that inputs the first control signal is a charging driver chip, the charging driver on the second sub-processor is awakened; then, the second sub-processor can obtain the second state information of the charging driver chip through the bus interface I2C-4. If the peripheral chip that inputs the first control signal is a sensor driver chip, the sensor driver on the second sub-processor is awakened; then, the second sub-processor can obtain the second state information of the charging driver chip through the bus interface I2C-5.

[0227] It can be seen that if the extended driver is configured in the low-power second sub-processor, when the peripheral chip that inputs the first control signal is the second chip, there is no need to wake up the high-power first sub-processor, which can reduce power consumption.

[0228] It should be noted that the specific method of waking up the driver of the peripheral chip and obtaining the second state information of the peripheral chip can be found in the description of step 103 and will not be repeated here.

[0229] Step 204 : When the peripheral chip that inputs the first control signal is the first peripheral chip, the second sub-processor wakes up the first sub-processor and sends indication information to the first sub-processor, where the indication information is used to indicate the peripheral chip that inputs the first control signal.

[0230] That is, when the second sub-processor does not include a driver for the peripheral chip that inputs the first control signal, steps 204 to 205 are executed.

[0231] For example, Figure 9B As shown, in the case where the peripheral chip that inputs the first control signal is an audio driver chip, since the second sub-processor does not include an audio driver, the second sub-processor wakes up the first sub-processor that includes the audio driver and sends an indication message to the first sub-processor to inform the first sub-processor that the peripheral chip that inputs the first control signal is an audio driver chip. Similarly, in the case where the peripheral chip that inputs the first control signal is a display driver chip, the second sub-processor wakes up the first sub-processor that includes the display driver and sends an indication message to the first sub-processor to inform the first sub-processor that the peripheral chip that inputs the first control signal is a display driver chip.

[0232] Step 205 : When the first sub-processor includes a driver for a peripheral chip, in response to receiving the indication information, the first sub-processor wakes up the driver for the peripheral chip based on the indication information and obtains second state information of the peripheral chip.

[0233] For example, Figure 9B As shown, if the peripheral chip that inputs the first control signal is an audio driver chip, the audio driver on the first sub-processor is awakened; then, the first sub-processor can obtain the second status information of the audio driver chip through the bus interface I2C-2. Similarly, if the peripheral chip that inputs the first control signal is a display driver chip, the display driver on the first sub-processor is awakened; then, the first sub-processor can obtain the second status information of the display driver chip through the bus interface I2C-3.

[0234] It should be noted that the above embodiment only illustrates the corresponding signal transmission method when the extended chip driver is configured in the second sub-processor, and does not limit the signal transmission method. The signal transmission method is also applicable to the case where the extended chip driver is configured in the first sub-processor. Among them, when the extended chip driver is configured in the first sub-processor, the corresponding signal transmission method can refer to the description of steps 201 to 205 above, which will not be repeated here. For example, when the extended chip driver is configured in the first sub-processor, the bus interface I2C-1 of the extended chip is coupled to the AP. In this way, if the first control signal is received, the first sub-processor obtains the first status information of the extended chip, and based on the first status information, determines the peripheral chip that inputs the first control signal.

[0235] It should also be noted that the above embodiment is merely an example of configuring the extended chip driver in a low-power ADSP, and does not limit the configuration of the extended chip driver. For example, the extended chip driver can also be configured in other low-power sub-processors, such as a sensor hub.

[0236] The following describes in detail the signal transmission method from the secondary board to the main board provided in the embodiment of the present application.

[0237] Since the first sub-processor is used to control the first peripheral chip and the second sub-processor is used to control the second peripheral chip, under the main control process, the first sub-processor can be used to send the corresponding second control signal to the first peripheral chip, and the second sub-processor can be used to send the corresponding second control signal to the second peripheral chip.

[0238] For example, an expansion chip is coupled to a second sub-processor via the I2C-1 bus interface. Since the first sub-processor cannot communicate directly with the expansion chip, if the first sub-processor wants to send a second control signal to a target peripheral chip (i.e., the first peripheral chip), the first sub-processor first sends the second control signal to the second processor; the second control signal is used to instruct the execution of the first target control on the target peripheral chip. Then, in response to receiving the second control signal, the second sub-processor controls the expansion chip to execute the first target control on the target peripheral chip.

[0239] For example, Figure 9C As shown, the AP can control the audio driver chip and the display driver chip. Since the AP cannot transmit the second control signal to the extension chip, the AP can transfer the second control signal to the extension chip through the ADSP, so as to implement the first target control of the audio driver chip or the display driver chip through the extension chip, such as initialization, enabling, starting, pausing and other controls.

[0240] The AP and the ADSP can access each other through the glink channel. In this way, the AP can send a second control signal to the ADSP through the glink channel. It should be understood that different channels can be used for access between different processors, and this embodiment of the application does not limit this.

[0241] Continuing with the example of the expansion chip being coupled to the second sub-processor via the bus interface I2C-1, if the second sub-processor is to send a second control signal to the target peripheral chip (i.e., the second peripheral chip), in this case, the second control signal is used to instruct the execution of the second target control on the target peripheral chip. Since the second sub-processor is coupled to the expansion chip via the bus interface I2C-1, the second sub-processor can directly control the expansion chip to execute the second target control on the target peripheral chip.

[0242] For example, Figure 9C As shown, ADSP can control the charging driver chip and the sensor driver chip. Since ADSP can transmit control signals to the extension chip, ADSP can directly output the second control signal to the extension chip to implement the second target control of the charging driver chip or the sensor driver chip through the extension chip, such as initialization, enabling, starting, pausing and other controls.

[0243] In the above embodiment, when the processor includes a first sub-processor and a second sub-processor, communication between the first sub-processor, the second sub-processor and the peripheral chip can be achieved through an expansion chip.

[0244] In some embodiments, when the processor includes a first sub-processor and a second sub-processor, communication between the first sub-processor, the second sub-processor and the peripheral chip can also be achieved through two expansion chips.

[0245] For example, Figure 10 As shown, two expansion chips can be set on the sub-board, a first sub-expansion chip and a second sub-expansion chip. The first sub-expansion chip is used to couple the first sub-processor and the first peripheral chip, and the second sub-expansion chip is used to couple the second sub-processor and the second peripheral chip.

[0246] Specifically, such as Figure 10As shown, the first sub-expansion chip may include a first processor output interface Int-1, a first bus interface I2C-1-1, and at least one first peripheral input / output interface. The first processor output interface Int-1 and the first bus interface I2C-1-1 are both coupled to the first sub-processor, and the at least one first peripheral input / output interface is respectively coupled to at least one first peripheral chip. In this way, the first sub-expansion chip can be used to receive a third control signal sent by the first peripheral chip through the first peripheral input / output interface, and send the third control signal to the first sub-processor through the first processor output interface Int-1; and / or, to receive a fourth control signal sent by the first sub-processor through the first bus interface I2C-1-1, and control the first peripheral chip based on the fourth control signal.

[0247] Similarly, the second sub-expansion chip includes a second processor output interface Int-2, a second bus interface I2C-1-2, and at least one second peripheral input / output interface; the second processor output interface Int-2 and the second bus interface I2C-1-2 are both coupled to the second sub-processor; and the at least one second peripheral input / output interface is coupled to at least one second peripheral chip. Thus, the second sub-expansion chip can be configured to receive a fifth control signal sent by the second peripheral chip via the second peripheral input / output interface, and to send the fifth control signal to the second sub-processor via the second processor output interface Int-2; and / or to receive a sixth control signal sent by the second sub-processor via the second bus interface I2C-1-2, and to control the second peripheral chip based on the sixth control signal.

[0248] It should be noted that when the first sub-processor and the second sub-processor are each configured with an expansion chip, the driver for the first sub-expansion chip is configured in the first sub-processor, and the driver for the second sub-expansion chip is configured in the second sub-processor. Thus, when the first sub-processor receives the third control signal, the first sub-processor can obtain third status information of the first sub-expansion chip via the first bus interface I2C-1-1 and, based on the third status information, determine the first peripheral chip to input the third control signal.

[0249] Similarly, when the second sub-processor receives the fifth control signal, the second sub-processor can obtain the fourth status information of the second sub-expansion chip through the second bus interface I2C-1-2, and determine the second peripheral chip that inputs the fifth control signal based on the fourth status information.

[0250] In this way, compared with the solution of multiple sub-processors sharing one expansion chip, Figure 10 In the provided solution, each sub-processor can communicate directly with its corresponding sub-expansion chip, eliminating the need for coordination with other sub-processors, thus simplifying the signal transmission method.

[0251] It should be noted that the signal transmission method between the first sub-processor and the first peripheral chip, and the signal transmission method between the second sub-processor and the second peripheral chip can refer to the description of steps 101 to 105 and will not be repeated here.

[0252] It should be noted that the above embodiment is only illustrative of the example of implementing communication between the first sub-processor, the second sub-processor and the peripheral chip through the extension chip, and does not limit this. The embodiment of the present application can also implement communication between more sub-processors and more peripheral chips through the extension chip. For example, a third sub-processor can also be included, and the third sub-processor can communicate with the power driver chip through the extension chip. Among them, the principle of multiple sub-processors communicating with the peripheral chip through the extension chip is basically the same as the principle of the first sub-processor and the second sub-processor communicating with the peripheral chip through the extension chip. For details, please refer to the description of the above embodiment, which will not be repeated here.

[0253] It should also be noted that the above embodiments illustrate the coupling between the expansion chip and the peripheral chip via the interrupt interface and the reset interface, and do not limit the peripheral input and output interfaces on the expansion chip. For example, the expansion chip and the peripheral chip may also be coupled via an enable interface, a GPIO interface, etc.

[0254] The various method embodiments described herein may be independent solutions or may be combined according to internal logic, and all of these solutions fall within the scope of protection of this application.

[0255] It is understandable that, in the above-mentioned various method embodiments, the methods and operations implemented by the electronic device may also be implemented by components (such as chips, modules or circuits) that can be used in the electronic device.

[0256] The above embodiments introduce the signal transmission method provided by the present application. It is understandable that, in order to implement the above functions, the electronic device includes a hardware structure and / or software module corresponding to each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in a hardware or computer software driven hardware manner depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0257] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above signal transmission method embodiment, and for the sake of brevity, it will not be repeated here.

[0258] It should be understood that the processor in the embodiment of the present application can be a chip. For example, the chip can be a general-purpose processor or a dedicated processor. The chip can include at least one processor. The at least one processor can be used to support Figure 5 、 Figure 7 、 Figure 8 and Figure 10 The electronic device shown implements the technical solution of a method embodiment.

[0259] It should be noted that the processor in the embodiments of the present application can be implemented using the following circuits or devices: one or more field programmable gate arrays (FPGA), programmable logic devices (PLD), application specific integrated circuits (ASIC), system on chip (SoC), central processor unit (CPU), network processor (NP), digital signal processor (DSP), microcontroller unit (MCU), controller, state machine, gate logic, discrete hardware components, any other suitable circuit, or any combination of circuits that can perform the various functions described throughout this application.

[0260] During implementation, each step of the above method can be completed by an integrated logic circuit of the hardware in the processor or by instructions in the form of software. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it will not be described in detail here.

[0261] It is understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0262] According to the method provided in the embodiment of the present application, the embodiment of the present application also provides a computer program product, which includes: a computer program or instruction, which, when the computer program or instruction is run on a computer, causes the computer to execute Figures 1A to 10 A method according to any one of the embodiments shown.

[0263] According to the method provided in the embodiment of the present application, the embodiment of the present application also provides a computer storage medium, which stores a computer program or instruction, and when the computer program or instruction is run on a computer, the computer executes Figures 1A to 10 A method according to any one of the embodiments shown.

[0264] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the electronic device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0265] In the several embodiments provided in this application, it should be understood that the disclosed electronic devices and methods can be implemented in other ways. For example, the electronic device embodiments described above are merely illustrative, and for example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not implemented. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0266] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed across multiple network elements. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0267] In addition, the functional modules in the various embodiments of the present application may be integrated into one processing unit, or each module may exist physically separately, or two or more modules may be integrated into one unit.

[0268] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0269] The chips, computer storage media, computer program products, and electronic devices provided in the above-mentioned embodiments of the present application are all used to execute the methods provided above. Therefore, the beneficial effects that can be achieved can refer to the corresponding beneficial effects of the methods provided above, and will not be repeated here.

[0270] It should be understood that in each embodiment of the present application, the execution order of each step should be determined by its function and internal logic. The size of the sequence number of each step does not mean the order of execution and does not limit the implementation process of the embodiment.

[0271] The various sections of this specification are described in a progressive manner. Similar portions between embodiments can be referenced to each other. Each embodiment focuses on the differences between the other embodiments. In particular, the chip, computer storage medium, and computer program product embodiments are generally similar to the method embodiments, so their descriptions are simplified. For relevant details, refer to the descriptions in the method embodiments.

[0272] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0273] The above-described embodiments of the present application do not constitute a limitation on the scope of protection of the present application.

Claims

1. An electronic device, characterized in that: The electronic device is a foldable electronic device, and the electronic device includes: A processor, the processor being located on a mainboard side of the electronic device; At least one peripheral chip, wherein the at least one peripheral chip is located on the secondary board side of the electronic device, and the main board and the secondary board are connected by a rotating shaft and are respectively located on both sides of the rotating shaft; an expansion chip, the expansion chip being located on the secondary board side, the expansion chip comprising a processor output interface, a bus interface, and at least one peripheral input / output interface; the processor output interface and the bus interface being coupled to the processor; the at least one peripheral input / output interface being coupled to the at least one peripheral chip; The expansion chip is configured to receive a first control signal sent by the peripheral chip through the peripheral input / output interface, and send the first control signal to the processor through the processor output interface; and / or to receive a second control signal sent by the processor through the bus interface, and control the peripheral chip based on the second control signal; The processor is coupled to the at least one peripheral chip through at least one peripheral bus interface; the processor is further configured to wake up a driver of the peripheral chip upon receiving the first control signal, and obtain second status information of the peripheral chip through the peripheral bus interface; the second status information includes information indicating a reason why the peripheral chip generates the first control signal; The processor is further configured to execute an active control process on the peripheral chip based on the second state information; the active control process includes: sending a second control signal to the extension chip, so that the extension chip controls the peripheral chip based on the second control signal.

2. The electronic device according to claim 1, wherein The processor includes a first sub-processor and a second sub-processor, the extension chip is coupled to the first sub-processor through the processor output interface, and the extension chip is coupled to the second sub-processor through the bus interface; the first sub-processor is coupled to the second sub-processor; the extension chip is specifically used to send the first control signal to the first sub-processor through the processor output interface; and / or, to receive the second control signal sent by the second sub-processor through the bus interface, and control the peripheral chip based on the second control signal.

3. The electronic device according to claim 1, wherein The processor includes a first sub-processor and a second sub-processor, the extension chip is coupled to the second sub-processor through the processor output interface, and the extension chip is coupled to the second sub-processor through the bus interface; the first sub-processor is coupled to the second sub-processor; the extension chip is specifically used to send the first control signal to the second sub-processor through the processor output interface; and / or, to receive the second control signal sent by the second sub-processor through the bus interface, and control the peripheral chip based on the second control signal.

4. The electronic device according to claim 2 or 3, characterized in that: The power consumption of the second sub-processor is less than the power consumption of the first sub-processor.

5. The electronic device according to claim 4, characterized in that The second sub-processor is configured to include a driver for the extension chip in the second sub-processor, and upon receiving the first control signal, obtain first status information of the extension chip through the bus interface, and determine, based on the first status information, the peripheral chip that inputs the first control signal.

6. The electronic device according to claim 5, characterized in that The second sub-processor is further configured to wake up the driver of the peripheral chip and obtain second status information of the peripheral chip when the second sub-processor includes the driver of the peripheral chip.

7. The electronic device according to claim 5, wherein: The second sub-processor is further configured to wake up the first sub-processor and send indication information to the first sub-processor when the second sub-processor does not include a driver for the peripheral chip, where the indication information is used to indicate the peripheral chip that inputs the first control signal; The first sub-processor is configured to wake up the driver of the peripheral chip based on the indication information and obtain second status information of the peripheral chip when the first sub-processor includes the driver of the peripheral chip and receives the indication information.

8. The electronic device according to claim 2 or 3, characterized in that: The first sub-processor is configured to send a second control signal to the second sub-processor when the first sub-processor includes a driver for a target peripheral chip; wherein the second control signal is used to instruct execution of a first target control on the target peripheral chip; The second sub-processor is configured to control the extension chip to perform first target control on the target peripheral chip through the bus interface when the second sub-processor includes a driver for the extension chip and receives the second control signal.

9. The electronic device according to claim 8, wherein: The second sub-processor is further configured to control the expansion chip to perform second target control on the target peripheral chip through the bus interface when the second sub-processor includes a driver for the target peripheral chip.

10. The electronic device according to claim 1, wherein The processor includes a first sub-processor and a second sub-processor, the extension chip includes a first sub-extension chip and a second sub-extension chip, and the at least one peripheral chip includes at least one first peripheral chip and at least one second peripheral chip; wherein the first sub-processor includes a driver for the at least one first peripheral chip, and the second sub-processor includes a driver for the at least one second peripheral chip; The first sub-expansion chip includes a first processor output interface, a first bus interface, and at least one first peripheral input and output interface; the first processor output interface and the first bus interface are both coupled to the first sub-processor; the at least one first peripheral input and output interface is respectively coupled to the at least one first peripheral chip; The second sub-expansion chip includes a second processor output interface, a second bus interface and at least one second peripheral input and output interface; the second processor output interface and the second bus interface are both coupled to the second sub-processor; the at least one second peripheral input and output interface is coupled to the at least one second peripheral chip; The first sub-expansion chip is configured to receive a third control signal sent by the first peripheral chip through the first peripheral input / output interface, and send the third control signal to the first sub-processor through the first processor output interface; and / or to receive a fourth control signal sent by the first sub-processor through the first bus interface, and control the first peripheral chip based on the fourth control signal; The second sub-extension chip is used to receive the fifth control signal sent by the second peripheral chip through the second peripheral input and output interface, and send the fifth control signal to the second sub-processor through the second processor output interface; and / or, to receive the sixth control signal sent by the second sub-processor through the second bus interface, and control the second peripheral chip based on the sixth control signal.

11. The electronic device according to claim 10, characterized in that the first sub-processor being configured to include a driver for the first sub-expansion chip in the first sub-processor, and upon receiving the third control signal, obtain third status information of the first sub-expansion chip through the first bus interface, and determine, based on the third status information, the first peripheral chip to which the third control signal is input; The second sub-processor is configured to include a driver for the second sub-expansion chip in the second sub-processor, and upon receiving the fifth control signal, obtain fourth status information of the second sub-expansion chip through the second bus interface, and determine, based on the fourth status information, the second peripheral chip to which the fifth control signal is input.

12. The electronic device according to claim 1, wherein The at least one peripheral input and output interface includes one or more of a reset interface, an enable interface, an interrupt interface, and a GPIO interface; the processor output interface includes an interrupt interface, and the bus interface is an inter-integrated circuit serial bus I2C interface, an inter-integrated circuit serial bus I3C interface, or a serial peripheral device SPI interface.

13. A signal transmission method, characterized in that: The method is applied to an electronic device, wherein the electronic device is a foldable electronic device, the electronic device includes a processor located on a main board side of the electronic device, and at least one peripheral chip and an expansion chip located on a sub-board side of the electronic device, the processor being coupled to the at least one peripheral chip via the expansion chip; the method includes: The expansion chip receives a first control signal sent by the peripheral chip, and sends the first control signal to the processor; In response to receiving the first control signal, the processor acquires first status information of the extension chip, and determines the peripheral chip that inputs the first control signal based on the first status information; The processor is coupled to the at least one peripheral chip through at least one peripheral bus interface; the processor wakes up the driver of the peripheral chip and obtains the second state information of the peripheral chip through the peripheral bus interface; The processor performs an active control process on the peripheral chip based on the second state information; the active control process includes: sending a second control signal to the extension chip, so that the extension chip controls the peripheral chip based on the second control signal.

14. The method according to claim 13, characterized in that The processor includes a first sub-processor and a second sub-processor, wherein the power consumption of the second sub-processor is less than the power consumption of the first sub-processor; and the method includes: When the second sub-processor includes a driver for the extension chip and receives the first control signal, the second sub-processor obtains first status information of the extension chip and determines the peripheral chip that inputs the first control signal based on the first status information.

15. The method according to claim 13, characterized in that The processor includes a first sub-processor and a second sub-processor, wherein the power consumption of the second sub-processor is less than the power consumption of the first sub-processor; and the method includes: When the first sub-processor includes a driver for the extension chip and receives the first control signal, the first sub-processor obtains first status information of the extension chip and determines the peripheral chip that inputs the first control signal based on the first status information.

16. The method according to claim 14, characterized in that In a case where the second sub-processor includes a driver for the peripheral chip, the driver for the peripheral chip is awakened, and second status information of the peripheral chip is acquired.

17. The method according to claim 14, characterized in that In a case where the second sub-processor does not include a driver for the peripheral chip, the second sub-processor wakes up the first sub-processor and sends indication information to the first sub-processor, where the indication information is used to indicate the peripheral chip that inputs the first control signal; In a case where the first sub-processor includes a driver for the peripheral chip, in response to receiving the indication information, the first sub-processor wakes up the driver for the peripheral chip based on the indication information and obtains second status information of the peripheral chip.

18. The method according to claim 13, characterized in that The method further comprises: The processor sends a second control signal to the expansion chip, where the second control signal is used to instruct to perform target control on the target peripheral chip; In response to receiving the second control signal, the expansion chip performs the target control on the target peripheral device.

19. The method according to claim 14, wherein The method further comprises: In a case where the first sub-processor includes a driver for a target peripheral chip, the first sub-processor sends a second control signal to the second sub-processor; wherein the second control signal is used to instruct execution of a first target control on the target peripheral chip; In response to receiving the second control signal, the second sub-processor controls the expansion chip to perform a first target control on the target peripheral chip.

20. The method according to claim 14, wherein The method further comprises: In a case where the second sub-processor includes a driver of a target peripheral chip, the second sub-processor controls the expansion chip to perform a second target control on the target peripheral chip.

21. The method according to claim 13, wherein The processor includes a first sub-processor and a second sub-processor, the extension chip includes a first sub-extension chip and a second sub-extension chip, and the at least one peripheral chip includes at least one first peripheral chip and at least one second peripheral chip; the first sub-processor is coupled to the at least one first peripheral chip via the first sub-extension chip, and the second sub-processor is coupled to the at least two first peripheral chips via the second sub-extension chip; the method includes: The first sub-expansion chip receives a third control signal sent by the first peripheral chip, and sends the third control signal to the first sub-processor; In response to receiving the third control signal, the first sub-processor obtains third status information of the first sub-expansion chip, and determines the first peripheral chip to which the third control signal is input based on the third status information; and / or, The second sub-expansion chip receives the fifth control signal sent by the second peripheral chip, and sends the fifth control signal to the second sub-processor; In response to receiving the fifth control signal, the second sub-processor obtains fourth status information of the second sub-expansion chip, and determines the second peripheral chip that inputs the fifth control signal based on the fourth status information.

22. The method according to claim 21, characterized in that The first control signal, the third control signal, and the fifth control signal are interrupt signals.

23. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program or instructions, and when the computer program or instructions are executed on a computer, the computer is caused to execute the method according to any one of claims 13 to 22.

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