Communication method for reliable transmission between multiple FPGA chips

Abstract

The present invention discloses a communication method for reliable transmission between multiple FPGA chips, the method comprising the following steps: S1. selecting a segmentation point, segmenting a target design into multiple FPGA chips, wherein the modules after segmentation are respectively from the N-1th module to the N-th module, wherein N is greater than or equal to 2; S2. when the N-1th module transmits data to the N-th module, in the F N‑1 In the chip, the N-1th module transfers data to a FIFO buffer, and the FIFO transfers data to the F N‑1 TX transmission module, F N‑1 The TX transmission module sends N The RX receiving module in the chip transmits data, F N The RX receiving module in the chip transmits the data to the Nth module. The present invention can realize reliable data transmission and communication among multiple FPGA chips.

Description

Technical Field

[0001] The present invention belongs to the field of communication technology, and more specifically, relates to a communication method for reliable transmission between multiple FPGA chips. Background Art

[0002] Due to the time limitation of EDA (Electronic Design Automation) tool simulation verification, large-scale digital chip verification is generally carried out in conjunction with FPGA (Field-Programmable Gate Array) chips for prototype verification. FPGA prototype verification is to implement the equivalent implementation of ASIC (Application Specific Integrated Circuit) logic design in FPGA chips for verification. Compared with EDA simulation, FPGA can achieve gate-level parallel processing, thereby obtaining great time benefits. In addition, large-scale digital chip verification usually requires a combination of software and hardware. The use of FPGA can provide software with a development platform with real-time feedback capabilities, further improving the reliability of circuit verification. Large-scale digital chips are becoming more and more complex and their scale is increasing, which requires FPGA chips with larger resources. However, FPGA chips with rich resources are not easy to obtain due to technical blockades. Therefore, splitting a complete project into multiple FPGA chips for verification has become an indispensable and important means in the current large-scale design verification. In order to give full play to the advantages of multi-FPGA chip verification, we must first find a method to solve the problem of reliable communication of cross-chip data. Summary of the invention

[0003] The present invention aims to provide a communication method for reliable transmission between multiple FPGA chips, comprising the following steps:

[0004] S1. Select a split point and split the target design into multiple FPGA chips. The split modules are from the N-1th module to the Nth module, where N is greater than or equal to 2.

[0005] S2. When the N-1th module transmits data to the Nth module, N-1 In the chip, the N-1th module transfers data to a FIFO buffer, and the FIFO transfers data to F N-1 TX transmission module, F N-1 The TX transmission module sends N The RX receiving module in the chip transmits data, F N The RX receiving module in the chip transmits the data to the Nth module;

[0006] When the Nth module transmits data to the N-1th module,N In the chip, the Nth module transfers data to a FIFO buffer, and the FIFO transfers data to the F N TX transmission module, F N The TX transmission module sends N-1 The RX receiving module in the chip transmits data, F N-1 The RX receiving module in the chip transmits the data to the N-1th module.

[0007] Furthermore, in S1, the principles for selecting the split points are as follows:

[0008] Located outside the target design;

[0009] The data to be transmitted are close and valid at the same time;

[0010] The signals belong to the same clock domain;

[0011] The bit width of the data to be transmitted is moderate.

[0012] Furthermore, the industry-wide handshake communication protocol is used between the sender and the receiver in 2.

[0013] The signal Link_rx_ready is a ready signal provided by the receiver of the communication device, indicating that the receiver can receive the receipt;

[0014] The signal Link_tx_valid is a valid signal provided by the sender of the communication device, indicating that the data of the sender is valid;

[0015] The signal Link_tx_data is the data transmitted from the transmitter of the communication device to the receiver;

[0016] When assert_on_txvalid and Link_rx_ready are both high, a Link_tx_data data is transmitted.

[0017] Further, in the sender of S2, the signal read is a read request sent by the communication device to the fifo;

[0018] The signal empty is the status of whether the fifo is empty;

[0019] Signal user_data is the fifo data signal;

[0020] The signal touser_valid indicates that the data transmitted by the communication device receiving side to the destination module is valid;

[0021] The signal touser_data is the data transmitted from the receiving side of the communication device to the destination module;

[0022] The initial state of the timer is 0. Each time the handshake is successful, Link_rx_ready and Link_rx_valid are both high. After a transmission is completed, the counter is incremented by 1. The value of the counter at this time is concatenated with the transmission data to obtain the data Link_tx_data, where Link_rx_data comes from the transmission counter and is passed to the receiver to determine which beat of the data it is. Link_rx_data is the data that needs to be transmitted. This forms the top-level interface of the sending module.

[0023] Furthermore, in the receiver of S2, the received signal is firstly subjected to three-level synchronization processing, and the signal link_tx_valid_asyn_r0 is the output of the first level r0 of Link_rx_valid synchronization;

[0024] The signal link_tx_valid_asyn_r1 is the output of the second stage r1 of Link_rx_valid synchronization;

[0025] The signal link_tx_valid_asyn_r2 is the output of the Link_rx_valid synchronization third stage r2.

[0026] The judgment splicing means that {link_tx_valid_asyn_r0, link_tx_valid_asyn_r1, link_tx_valid_asyn_r2} are spliced. When it is 3'b011, the signal assert_on_txvalid is valid, indicating that the data in the receiver's clock domain is valid; when it is 3'b110, the signal dis_assert_on_txvalid indicates that the data in the receiver's clock domain is invalid; with assert_on_txvalid as the starting point and dis_assert_on_txvalid as the end point, the signal rev_valid can be obtained. When the signal is valid, the input Link_tx_data can be saved to obtain rev_data. rev_valid is the valid signal corresponding to the data, and the reception of a Link_tx_data is completed.

[0027] Then rev_data is decomposed, and according to the data sequence information expressed by the high-order rev_data, the original data touser_data is recovered by reorganization after storage, and the valid signal corresponding to the data is touser_valid.

[0028] According to another aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, the steps of the communication method for reliable transmission between multiple FPGA chips of the present invention are implemented.

[0029] According to another aspect of the present invention, there is provided a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the communication method for reliable transmission between multiple FPGA chips of the present invention when executing the program.

[0030] Compared with the prior art, the present invention has at least the following beneficial effects:

[0031] The present invention solves the problem of realizing mutual communication between chips in multiple FPGAs. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0033] Figure 1 It is a schematic diagram of the modules before segmentation of the present invention;

[0034] Figure 2 It is a schematic diagram of the modules after segmentation of the present invention;

[0035] Figure 3 It is a schematic diagram of top-level interface signals of the communication device of the present invention;

[0036] Figure 4 It is a schematic diagram of a receiving module of a communication device of the present invention generating a key interface signal;

[0037] Figure 5 It is a schematic diagram of the top-level signal of the sending module of the communication device of the present invention;

[0038] Figure 6 It is a schematic diagram of the top-level signal of the receiving module of the communication device of the present invention;

[0039] Figure 7 It is a schematic diagram of a method for a communication device sending module to generate a data identifier according to the present invention;

[0040] Figure 8 It is a schematic diagram of a method for parsing data identifiers by a receiving module of a communication device of the present invention. DETAILED DESCRIPTION

[0041] To make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the embodiments of the present invention will be described clearly and completely in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them.

[0042] Unless otherwise defined, technical or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs.

[0043] The following is combined with Figure 1-8 The specific embodiments of the present invention are described in detail with examples.

[0044] Embodiment 1: The present invention provides the following technical solution, a communication method for reliable transmission between multiple FPGA chips, including the following contents:

[0045] The present invention is mainly used for data transmission between FPGA chips when the target design is divided and placed in different FPGA chips during FPGA prototype verification.

[0046] like Figure 1 As shown in the figure, the modules before project segmentation; the target design is segmented into two FPGA chips, F1 and F2, and a suitable segmentation point is selected for segmentation. The two modules segmented are A and B.

[0047] When A transmits data to B, in the F1 chip, the A module transfers the data to a FIFO buffer, the FIFO transfers the data to the TX sending module of this implementation, the TX sending module transfers the data to the RX receiving module in the F2 chip, and the RX receiving module transfers the data to module B;

[0048] When B transmits data to A, in the F2 chip, the B module transfers the data to a FIFO buffer, and the FIFO transfers the data to the TX sending module of this implementation. The TX sending module transfers the data to the RX receiving module in the F1 chip, and the RX receiving module transfers the data to module A. The module diagram after the project segmentation is as follows Figure 2 shown.

[0049] In S1, the principles for selecting the split points are as follows:

[0050] It is better to be close to the periphery of the design. FPGA implementation belongs to hardware implementation and has a layout concept. If the target A module is located in the middle of the FPGA chip, then the transmission module from the A module to the edge of the FPGA will inevitably require a long routing, which will limit the implementation frequency of the overall solution.

[0051] It is better that the data to be transmitted is as close as possible and valid at the same time. The data to be transmitted in module A can be the result of bit-by-bit splicing of different signals. However, if the signal sources are too dispersed in the FPGA chip, some signals will have too long routing lines and different effective timings. The first valid signal needs to wait for the subsequent signals to be valid, which will bring certain resource overhead and efficiency overhead caused by waiting time. It is typically recommended to use the complete on-chip bus data part as the transmission object, so that the data can be basically close and valid at the same time bit by bit.

[0052] It is best if the signals belong to the same clock domain. If the transmitted data comes from different clock domains, then the signals from multiple clock domains need to be synchronized to a single clock domain before transmission. However, synchronization will lead to resource overhead and loss of transmission efficiency.

[0053] The data bit width to be transmitted is preferably moderate. The FPGA chip pin resources are limited compared to the transmission requirements of hundreds of bits on the chip. Figure 7 The method shown in the figure splits the transmitted data and then transmits it in time-division multiplexing using limited FPGA chip pin resources. However, too wide a data bit width will inevitably lead to a long splitting and splicing restoration process, affecting the transmission efficiency.

[0054] It should be emphasized that the split point can be selected arbitrarily as long as the FPGA chip resources are sufficient, but choosing the split point according to the above principles will result in a better cost-effectiveness.

[0055] In S2, the industry-standard handshake communication protocol is used between the sender and the receiver.

[0056] The signal Link_rx_ready is a ready signal provided by the receiver of the communication device, indicating that the receiver can receive the receipt;

[0057] The signal Link_tx_valid is a valid signal provided by the sender of the communication device, indicating that the data of the sender is valid;

[0058] The signal Link_tx_data is the data transmitted from the transmitter of the communication device to the receiver;

[0059] When assert_on_txvalid and Link_rx_ready are both high, a Link_tx_data data is transmitted.

[0060] Furthermore, in the sender of S2, the data bit width from module A may vary. From the perspective of saving IO (Input / Output) port resources, the data can be dynamically segmented. For example, the FIFO input (module A data) data bit width is 128 bits, which can be segmented into four beats for transmission using a 32-bit wide data channel. During the transmission process, a counter is used to mark which beat the data belongs to. In this way, the receiver can restore the data as it is based on the counter to maintain data consistency before and after segmentation, thereby ensuring transmission correctness while saving bus bit width / FPGA pin resources. Figure 7 As shown,

[0061] The signal read is a read request sent by the communication device to the fifo;

[0062] The signal empty is the status of whether the fifo is empty;

[0063] Signal user_data[127:0] is the fifo data signal;

[0064] The signal touser_valid indicates that the data transmitted by the communication device receiving side to the destination module is valid;

[0065] The signal touser_data[127:0] is the data transmitted from the receiving side of the communication device to the destination module;

[0066] The initial state of the timer is 0. Each time the handshake is successful, Link_rx_ready and Link_rx_valid are both high. After a transmission is completed, the counter is incremented by 1. The value of the counter at this time is concatenated with the transmission data to obtain the data Link_tx_data[33:0] (34 bits for example). The two bits Link_rx_data[33:32] (2 bits for example) come from the transmission counter and are passed to the receiver to determine which beat of the data. Link_rx_data[31:0] (32 bits for example) is the data to be transmitted. The top-level interface of the sending module formed in this way is as follows: Figure 5 shown.

[0067] Furthermore, in the receiver of S2, the received signal is first subjected to three-level synchronization processing, such as Figure 4 As shown,

[0068] The signal link_tx_valid_asyn_r0 is the output of the Link_rx_valid synchronization first stage r0;

[0069] The signal link_tx_valid_asyn_r1 is the output of the second stage r1 of Link_rx_valid synchronization;

[0070] The signal link_tx_valid_asyn_r2 is the output of the Link_rx_valid synchronization third stage r2.

[0071] The judgment splicing means that {link_tx_valid_asyn_r0, link_tx_valid_asyn_r1, link_tx_valid_asyn_r2} are spliced. When it is 3'b011, the signal assert_on_txvalid is valid, indicating that the data in the receiver's clock domain is valid; when it is 3'b110, the signal dis_assert_on_txvalid indicates that the data in the receiver's clock domain is invalid; with assert_on_txvalid as the starting point and dis_assert_on_txvalid as the end point, the signal rev_valid can be obtained. When the signal is valid, the input Link_tx_data can be saved to obtain rev_data. rev_valid is the valid signal corresponding to the data, and the reception of a Link_tx_data is completed.

[0072] Then decompose rev_data, and according to the data sequence information expressed by its high-order rev_data[33:32], recover the original data touser_data[127:0] by reorganizing after storage (assuming that the original data is 128 bits, the sender of this process decomposes and sends the reverse process), and the corresponding valid signal of the data is touser_valid, corresponding Figure 8 As shown; thus forming the top layer of the receiving module as Figure 6 shown.

[0073] Embodiment 2:

[0074] The computer-readable storage medium of this embodiment stores a computer program thereon, and when the program is executed by a processor, the steps of the communication method for reliable transmission between multiple FPGA chips in embodiment 1 are implemented.

[0075] The computer-readable storage medium of this embodiment may be an internal storage unit of the terminal, such as a hard disk or memory of the terminal; the computer-readable storage medium of this embodiment may also be an external storage device of the terminal, such as a plug-in hard disk, a smart memory card, a secure digital card, a flash memory card, etc. equipped on the terminal; further, the computer-readable storage medium may also include both an internal storage unit of the terminal and an external storage device.

[0076] The computer-readable storage medium of this embodiment is used to store computer programs and other programs and data required by the terminal. The computer-readable storage medium can also be used to temporarily store data that has been output or is to be output.

[0077] Embodiment 3:

[0078] The computer device of this embodiment includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the steps of the communication method for reliable transmission between multiple FPGA chips of embodiment 1 are implemented.

[0079] In this embodiment, the processor may be a central processing unit, or other general-purpose processors, digital signal processors, application-specific integrated circuits, readily available programmable gate arrays or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. A portion of the memory may also include a non-volatile random access memory. For example, the memory may also store information about the device type.

[0080] Those skilled in the art will appreciate that the disclosed content of the embodiments may be provided as methods, systems, or computer program products. Therefore, the present solution may adopt the form of hardware embodiments, software embodiments, or embodiments combining software and hardware. Moreover, the present solution may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program codes.

[0081] The present solution is described with reference to the method according to the embodiment of the present solution and the flowchart and / or block diagram of the computer program product. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions; these computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 one or more processes and / or methods Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0082] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 one or more processes and / or methods Figure 1 A function specified in one or more boxes.

[0083] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 one or more processes and / or methods Figure 1 The steps for the functions specified in one or more boxes.

[0084] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0085] The examples described in the present invention are merely descriptions of the preferred implementation modes of the present invention, and are not intended to limit the concept and scope of the present invention. Without departing from the design concept of the present invention, various modifications and improvements made to the technical solutions of the present invention by engineers and technicians in this field should all fall within the protection scope of the present invention.

Claims

1. A communication method for reliable transmission between multiple FPGA chips, characterized in that: The following steps are involved: S1. Select a split point and split the target design into multiple FPGA chips. The split modules are from the N-1th module to the Nth module, where N is greater than or equal to 2. S2. When the N-1th module transmits data to the Nth module, N-1 In the chip, the N-1th module transfers data to a FIFO buffer, and the FIFO transfers data to F N-1 TX transmission module, F N-1 The TX transmission module sends N The RX receiving module in the chip transmits data, F N The RX receiving module in the chip transmits the data to the Nth module; When the Nth module transmits data to the N-1th module, N In the chip, the Nth module transfers data to a FIFO buffer, and the FIFO transfers data to the F N TX transmission module, F N The TX transmission module sends N-1 The RX receiving module in the chip transmits data, F N-1 The RX receiving module in the chip transmits data to the N-1th module; Among them, in S1, the principles for selecting the split point are as follows: located at the periphery of the target design; the data to be transmitted are similar and valid at the same time; the signals belong to the same clock domain; the bit width of the data to be transmitted is moderate; In S2, the industry-wide handshake communication protocol is used between the sender and the receiver. The signal Link_rx_ready is a ready signal provided by the receiver of the communication device, indicating that the receiver can receive the receipt; the signal Link_tx_valid is a valid signal provided by the sender of the communication device, indicating that the data of the sender is valid; the signal Link_tx_data is the data transmitted from the sender of the communication device to the receiver; when assert_on_txvalid and Link_rx_ready are both high, a Link_tx_data data is transmitted; In the receiver of S2, the received signal is firstly processed by three-level synchronization. The signal link_tx_valid_asyn_r0 is the output of the first level r0 of Link_rx_valid synchronization; The signal link_tx_valid_asyn_r1 is the output of the second stage r1 of Link_rx_valid synchronization; Signal link_tx_valid_asyn_r2 is the output of Link_rx_valid synchronization third stage r2; The judgment splicing means that {link_tx_valid_asyn_r0, link_tx_valid_asyn_r1, link_tx_valid_asyn_r2} are spliced. When it is 3'b011, the signal assert_on_txvalid is valid, indicating that the data in the receiver's clock domain is valid; when it is 3'b110, the signal dis_assert_on_txvalid indicates that the data in the receiver's clock domain is invalid; with assert_on_txvalid as the starting point and dis_assert_on_txvalid as the end point, the signal rev_valid can be obtained. When the signal is valid, the input Link_tx_data can be saved to obtain rev_data. rev_valid is the valid signal corresponding to the data, and the reception of a Link_tx_data is completed. Then rev_data is decomposed, and according to the data sequence information expressed by the high-order rev_data, the original data touser_data is recovered by reorganization after storage, and the valid signal corresponding to the data is touser_valid.

2. The method according to claim 1, characterized in that: In the sender of S2, the signal read is a read request sent by the communication device to the fifo; The signal empty is the status of whether the fifo is empty; Signal user_data is the fifo data signal; The signal touser_valid indicates that the data transmitted by the communication device receiving side to the destination module is valid; The signal touser_data is the data transmitted from the receiving side of the communication device to the destination module; The initial state of the timer is 0. Each time the handshake is successful, Link_rx_ready and Link_rx_valid are both high. After a transmission is completed, the counter is incremented by 1. The value of the counter at this time is concatenated with the transmission data to obtain the data Link_tx_data, where Link_rx_data comes from the transmission counter and is passed to the receiver to determine which beat of the data it is. Link_rx_data is the data that needs to be transmitted. This forms the top-level interface of the sending module.

3. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps in the communication method for reliable transmission between multiple FPGA chips as described in any one of claims 1 to 2 are implemented.

4. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps in the communication method for reliable transmission between multiple FPGA chips as described in any one of claims 1 to 2 are implemented.

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