Semiconductor structure and method of forming the same
By alternating the deposition of interlayer insulating layers and sacrificial layers in semiconductor structures such as DRAM, independent transistor structures and word lines are formed, solving the problems of complexity and stress defects in epitaxial growth processes, and achieving cost reduction and performance improvement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-09-05
- Publication Date
- 2026-05-12
AI Technical Summary
Existing technologies for fabricating three-dimensional semiconductor structures such as DRAM involve complex epitaxial growth processes that are prone to stress defects, leading to increased manufacturing costs and decreased performance.
By alternately depositing interlayer insulating layers and sacrificial layers on the substrate to form stacked layers, and forming transistor structures and word lines in the storage region, the process is simplified, avoiding complex epitaxial processes. Selective etching and filling processes are used to form independent gate layers and word lines.
It simplifies the manufacturing process of semiconductor structures, reduces manufacturing costs, improves manufacturing yield and electrical performance, and reduces internal stress defects.
Smart Images
Figure CN117712027B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.
[0003] To meet the demands of continuously shrinking semiconductor structures and increasing data storage capabilities, three-dimensional semiconductor structures such as DRAM have emerged. The primary method for fabricating three-dimensional semiconductor structures like DRAM involves forming stacked layers through epitaxial growth, followed by processing these layers to create the three-dimensional stacked structure. However, epitaxial growth is a complex process and prone to generating defects such as stress within the stacked layers. This not only increases the manufacturing cost of the semiconductor structure but also reduces its performance and manufacturing yield.
[0004] Therefore, how to simplify the manufacturing process of semiconductor structures, reduce the manufacturing cost of semiconductor structures, and at the same time improve the performance and manufacturing yield of semiconductor structures are technical problems that urgently need to be solved. Summary of the Invention
[0005] The semiconductor structures and methods for forming the semiconductor structures provided in some embodiments of this disclosure are used to simplify the manufacturing process of semiconductor structures, reduce the manufacturing cost of semiconductor structures, and improve the performance and manufacturing yield of semiconductor structures.
[0006] According to some embodiments, this disclosure provides a method for forming a semiconductor structure, including the following steps:
[0007] A stacked layer is formed on a substrate, the stacked layer including an interlayer insulating layer and a sacrificial layer alternately stacked along a first direction, the stacked layer including a plurality of storage regions spaced apart along a second direction, the first direction being perpendicular to the top surface of the substrate, and the second direction being parallel to the top surface of the substrate;
[0008] A portion of the sacrificial layer in the storage region is removed to form a first trench located between adjacent interlayer insulating layers;
[0009] A transistor structure is formed in the first trench, the transistor structure including a gate layer covering the inner wall of the first trench and an active structure located in the gate layer;
[0010] A word line is formed extending along the second direction, the word line covering the gate layer in a plurality of memory regions spaced apart along the second direction.
[0011] In some embodiments, the step of forming a stacked layer on a substrate includes:
[0012] Provide substrate;
[0013] The interlayer insulating layer and the sacrificial layer are alternately deposited on the top surface of the substrate along the first direction, wherein the sacrificial layer includes a first sacrificial layer, a second sacrificial layer and a third sacrificial layer stacked sequentially along the first direction.
[0014] In some embodiments, the materials of the first sacrificial layer and the third sacrificial layer are both oxide materials, and the material of the second sacrificial layer is polycrystalline silicon.
[0015] In some embodiments, before forming the first trench located between adjacent interlayer insulating layers, the following steps are further included:
[0016] The stacked layers are etched to form isolation trenches located between adjacent storage regions along the second direction;
[0017] An isolation layer is formed that fills the isolation groove.
[0018] In some embodiments, the storage region includes a transistor region and a bit line region located on one side of the transistor region along a third direction, wherein the third direction is parallel to the top surface of the substrate, and the second direction intersects the third direction; the step of forming a first trench located between adjacent interlayer insulating layers includes:
[0019] Remove the stacked layer in the bit line region to form a bit line slot;
[0020] The second sacrificial layer in the transistor region is removed along the bit line groove, and the first trench is formed in the transistor region between the first sacrificial layer and the third sacrificial layer.
[0021] In some embodiments, the active structure is a hollow structure; the step of forming a transistor structure within the first trench includes:
[0022] The gate layer is formed to cover the inner wall of the first trench;
[0023] A gate dielectric layer is formed covering the inner wall of the gate layer;
[0024] An active structure is formed in the first trench to cover the inner wall of the gate dielectric layer. The active structure includes a channel layer and a first active layer and a second active layer distributed on opposite sides of the channel layer along a third direction.
[0025] An insulating filler layer is formed that covers the inner wall of the active structure and fills the first trench.
[0026] In some embodiments, the active structure is a solid structure; the step of forming a transistor structure within the first trench includes:
[0027] The gate layer is formed to cover the inner wall of the first trench;
[0028] A gate dielectric layer is formed covering the inner wall of the gate layer;
[0029] An active structure is formed that covers the inner wall of the gate dielectric layer and fills the first trench. The active structure includes a channel layer and a first active layer and a second active layer distributed on opposite sides of the channel layer along a third direction.
[0030] In some embodiments, the storage region further includes a capacitor region, the capacitor region and the bit line region being distributed along the third direction on opposite sides of the transistor region; the gate layer covers the entire inner wall of the first trench; before forming the word line extending along the second direction, the method further includes the following steps:
[0031] Remove the isolation layer between the capacitor region and the second active layer to expose part of the isolation trench, and expose the first sacrificial layer and the third sacrificial layer on the sidewall of the isolation trench;
[0032] Remove the first sacrificial layer and the third sacrificial layer on the capacitor region and the second active layer, and remove the gate layer on the second active layer to form a second trench located below the capacitor region and the second active layer along the first direction and a third trench located above the capacitor region and the second active layer along the first direction in the storage region.
[0033] A first isolation layer is formed that fills the isolation trench between the second trench, the third trench, the capacitor region, and the second active layer.
[0034] In some embodiments, after forming a first isolation layer that fills the isolation trench between the second trench, the third trench, the capacitor region, and the second active layer, the method further includes:
[0035] Remove the second sacrificial layer from the capacitor region to form a capacitor trench located between interlayer insulating layers;
[0036] Remove the gate layer exposed to the capacitor trench to expose the second active layer;
[0037] A capacitor structure electrically connected to the second active layer is formed within the capacitor groove.
[0038] In some embodiments, the specific steps of forming the word line extending along the second direction include:
[0039] Remove the isolation layer between the channel layer and the first active layer to expose part of the isolation trench, and expose the first sacrificial layer and the third sacrificial layer on the sidewall of the isolation trench;
[0040] Remove the first sacrificial layer and the third sacrificial layer on the channel layer and the first active layer, and form a fourth trench along the first direction below the channel layer and the first active layer and a fifth trench along the first direction above the channel layer and the first active layer in the storage area.
[0041] Remove the gate layer located on the first active layer along the fourth trench and the fifth trench;
[0042] Word line material is deposited along the fourth trench and the fifth trench to form word lines that extend along the second direction and cover a plurality of gate layers spaced apart along the second direction.
[0043] In some embodiments, the step of depositing word line material along the fourth trench and the fifth trench includes:
[0044] Word line material is deposited along the fourth and fifth trenches using a selective atomic layer deposition process. The deposition rate of the word line material on the gate layer surface is greater than the deposition rate on the interlayer insulating layer. The word line material at least fills the fourth trench above the channel layer and the fifth trench below the channel layer.
[0045] In some embodiments, the gate layer is made of titanium nitride, the word line is made of molybdenum metal, the interlayer insulating layer is made of nitride, and the process for depositing the word line material includes: using molybdenum dioxide (MoO2Cl2) or molybdenum pentachloride (MoCl5) as a precursor material, using ammonia or hydrogen as an auxiliary reaction gas, and the reaction temperature is 450℃-600℃.
[0046] In some embodiments, after forming the word lines extending along the second direction, the following steps are further included:
[0047] A second isolation layer is formed, which is located in the fourth trench below the first active layer, the fifth trench above the second active layer, and the isolation trench between the trench layer and the first active layer;
[0048] A bit line extending along the first direction is formed within the bit line groove, and the bit line is electrically connected to the first active layer of the transistor structure.
[0049] In some embodiments, the active structure is made of an oxide semiconductor material.
[0050] According to other embodiments, this disclosure also provides a semiconductor structure, including:
[0051] Substrate;
[0052] A stacked structure is located on the substrate. The stacked structure includes a plurality of memory cells spaced apart along a first direction and a second direction, and an interlayer insulating layer located between adjacent memory cells along the first direction. The memory cells include transistor structures, the transistor structures include active structures, and gate layers distributed around the outer periphery of the active structures. The first direction is perpendicular to the top surface of the substrate, and the second direction is parallel to the top surface of the substrate.
[0053] Word lines extend along the second direction and cover the gate layers within a plurality of memory cells spaced apart along the second direction.
[0054] In some embodiments, the active structure is a solid structure; or,
[0055] The active structure is a hollow structure.
[0056] In some embodiments, the active structure is a hollow structure; the active structure includes a channel layer, and a first active layer and a second active layer located on opposite sides of the channel layer along a third direction, wherein the third direction is parallel to the top surface of the substrate; the transistor structure further includes:
[0057] An insulating filler layer, wherein the active structure is distributed around the outer periphery of the insulating filler layer.
[0058] In some embodiments, along the first direction, the thickness of the insulating fill layer is greater than or equal to the thickness of the channel layer.
[0059] In some embodiments, the gate layer is made of titanium nitride, the word line is made of molybdenum, and the interlayer insulating layer is made of a nitride material.
[0060] In some embodiments, the memory cell further includes a capacitor structure located outside the transistor structure along the third direction; the capacitor structure includes:
[0061] The lower electrode layer includes a main body and an extension connected to the main body along the third direction. The extension covers the top surface and the bottom surface of the second active layer. The main body covers the side surface of the second active layer. The top surface and the bottom surface of the second active layer are distributed at opposite ends of the second active layer along the first direction.
[0062] A dielectric layer covers the surface of the lower electrode layer;
[0063] An upper electrode layer covers the surface of the dielectric layer.
[0064] In some embodiments, along the first direction, the thickness of the word line located on the top surface of the gate layer or on the bottom surface of the gate layer is greater than or equal to the thickness of the gate layer.
[0065] In some embodiments, the active structure is made of an oxide semiconductor material.
[0066] The semiconductor structure and its formation method provided in some embodiments of this disclosure first form a transistor structure in a first trench of a memory region, with the gate layer of the transistor structure distributed around the periphery of the active structure to form a gate-surround structure, and the gate layers in each memory region are independent of each other. Then, word lines are formed to cover the gate layers in multiple memory regions spaced apart along a second direction. This eliminates the need for complex processes to form horizontal word lines simultaneously with the gate layer, simplifying the horizontal word line formation process and reducing the manufacturing cost of the semiconductor structure. Furthermore, some embodiments of this disclosure form a stacked layer by depositing a sacrificial layer and an interlayer insulating layer. Subsequently, by removing part of the sacrificial layer and filling the sacrificial layer location, an active structure is formed. This eliminates the need for complex epitaxial processes in forming the active structure, further simplifying the semiconductor structure manufacturing process and reducing internal defects such as stress, thereby improving the manufacturing yield and electrical performance of the semiconductor structure. Additionally, some embodiments of this disclosure feature a hollow active structure filled with an insulating filler layer, enabling the transistor structure to operate in full depletion mode, further improving the semiconductor structure yield and electrical performance. Attached Figure Description
[0067] Appendix Figure 1 This is a flowchart of a method for forming a semiconductor structure according to a specific embodiment of this disclosure;
[0068] Appendix Figure 2 -Appendix Figure 22 This is a schematic diagram of the main process structure of the semiconductor structure in the formation process of the specific embodiments of this disclosure. Detailed Implementation
[0069] The specific embodiments of the semiconductor structure and its formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.
[0070] This specific embodiment provides a semiconductor structure, with appended... Figure 1 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of this disclosure, with appended... Figure 2 -Appendix Figure 22 This is a schematic diagram of the main process structure of the semiconductor structure in the formation process of a specific embodiment of this disclosure, wherein, Figure 2 This is a top view schematic diagram of the semiconductor structure formed in this specific embodiment. Figures 3-22 yes Figure 2 The diagram shows the main process cross-sections of the aa, bb, cc, and dd positions during semiconductor structure formation, clearly illustrating the semiconductor structure formation method. Figures 1-22 As shown, the method for forming a semiconductor structure includes the following steps:
[0071] Step S11: A stacked layer is formed on the substrate 30. The stacked layer includes interlayer insulating layers 34 and sacrificial layers alternately stacked along a first direction D1. The stacked layer also includes a plurality of storage regions PM spaced apart along a second direction D2. The first direction D1 is perpendicular to the top surface of the substrate 30, and the second direction D2 is parallel to the top surface of the substrate 30. Figure 2 and Figure 3 As shown.
[0072] The semiconductor structure formed in this specific embodiment can be, but is not limited to, DRAM. The following description uses DRAM as an example. For example, substrate 30 can be, but is not limited to, a silicon substrate. This specific embodiment uses silicon as an example. In other embodiments, substrate 30 can also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. Substrate 30 is used to support the device structure thereon. A sacrificial layer and an interlayer insulating layer 34 are alternately stacked on the top surface of substrate 30 along a first direction D1 to form a stacked layer. The stacked layer includes a plurality of memory regions PM arranged at intervals along a second direction D2, and the memory regions PM are used to form memory cells. The top surface of substrate 30 refers to the surface of substrate 30 facing the stacked layer. In this specific embodiment, "a plurality" refers to two or more.
[0073] In some embodiments, the step of forming a stacked layer on the substrate 30 includes:
[0074] Substrate 30 is provided;
[0075] An interlayer insulating layer 34 and a sacrificial layer are alternately deposited on the top surface of the substrate 30 along the first direction D1. The sacrificial layer includes a first sacrificial layer 31, a second sacrificial layer 32 and a third sacrificial layer 33 stacked sequentially along the first direction D1.
[0076] Specifically, a sacrificial layer and an interlayer insulating layer 34 can be alternately deposited on the top surface of the substrate 30 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition. A high etch selectivity ratio should be maintained between the sacrificial layer and the interlayer insulating layer 34 to facilitate subsequent selective etching. The sacrificial layer can be a single-layer or multi-layer structure. To simplify the subsequent etching process of the sacrificial layer and reduce the manufacturing complexity of the semiconductor structure, in one example, the sacrificial layer includes a first sacrificial layer 31, a second sacrificial layer 32, and a third sacrificial layer 33 arranged sequentially along a first direction D1. The first sacrificial layer 31 and the third sacrificial layer 33 can be made of the same material, while the material of the second sacrificial layer 32 is different from both the first and third sacrificial layers 31 and 33, to facilitate subsequent selective etching of the first sacrificial layer 31, the second sacrificial layer 32, and the third sacrificial layer 33.
[0077] In some embodiments, the materials of the first sacrificial layer 31 and the third sacrificial layer 33 are both oxide materials (e.g., silicon dioxide), and the material of the second sacrificial layer 32 is polycrystalline silicon, so as to reduce the manufacturing cost of the semiconductor structure while improving the etching selectivity between the first sacrificial layer 31 (or the third sacrificial layer 33) and the second sacrificial layer 32.
[0078] Step S12: Remove part of the sacrificial layer of the storage region PM to form a first trench 80 located between adjacent interlayer insulating layers 34, such as... Figure 8 As shown.
[0079] In some embodiments, before forming the first trench 80 located between adjacent interlayer insulating layers 34, the following steps are further included:
[0080] The stacked layers are etched to form isolation trenches 50 located between adjacent memory regions PM along the second direction D2, such as... Figure 5 As shown;
[0081] Forming an isolation layer 60 that fills the isolation groove 50, such as Figure 6 As shown.
[0082] Specifically, after the stacked layers are formed, a first photoresist layer 40 is formed on top of the stacked layers, and the first photoresist layer 40 has a first etched window 401 that exposes the stacked layers, such as... Figure 4As shown. The position of the first etching window 401 is aligned with the gap region between adjacent memory regions PM along the second direction D2. Next, the stacked layer is etched downwards along the first etching window 401 to form an isolation trench 50 penetrating the stacked layer along the first direction D1. After removing the first photoresist layer 40, the result is as shown. Figure 5 The structure is shown. Subsequently, an insulating dielectric material such as an oxide (e.g., silicon dioxide or TEOS (tetraethoxysilane)) is deposited within the isolation trench 50 to form an isolation layer 60 filling the isolation trench 50, as shown. Figure 6 As shown. Isolation layer 60 is used for electrical isolation of adjacent storage regions PM along the second direction D2.
[0083] In some embodiments, the storage region PM includes a transistor region PT and a bit line region PB located on one side of the transistor region PT along a third direction D3, wherein the third direction D3 is parallel to the top surface of the substrate 30, and the second direction D2 intersects the third direction D3; the step of forming a first trench 80 located between adjacent interlayer insulating layers 34 includes:
[0084] Remove the stacked layer of the bit line region PB to form a bit line slot 70, such as... Figure 7 As shown;
[0085] The second sacrificial layer 32 of the transistor region PT is removed along the bit line groove 70, and a first trench 80 is formed in the transistor region PT between the first sacrificial layer 31 and the third sacrificial layer 33.
[0086] Specifically, the transistor region PT and the bit line region PB are arranged along the third direction D3. The transistor region PT in the memory region PM is used to form the transistor structure, and the bit line region PT is subsequently used to form the bit lines. The stacked layer of the bit line region PB can be removed using photolithography to form the bit line trench 70 exposing the substrate 30, such as... Figure 7 As shown. Next, along the bit line trench 70, a lateral etching process is used to remove all the second sacrificial layers 32 within the transistor region PT, forming a first trench 80 within the transistor region PT located between the first sacrificial layer 31 and the third sacrificial layer 33, as shown. Figure 8 As shown. In this specific embodiment, the intersection can be perpendicular or oblique.
[0087] Step S13: A transistor structure is formed within the first trench 80. The transistor structure includes a gate layer 90 covering the inner wall of the first trench 80, and an active structure located within the gate layer 90, such as... Figure 9 As shown.
[0088] In some embodiments, the active structure 92 is a hollow structure; the step of forming a transistor structure within the first trench 80 includes:
[0089] A gate layer 90 is formed covering the inner wall of the first trench 80;
[0090] A gate dielectric layer 91 is formed covering the inner wall of the gate layer 90;
[0091] An active structure 92 is formed in the first trench 80, covering the inner wall of the gate dielectric layer 91. The active structure 92 includes a channel layer and a first active layer and a second active layer distributed on opposite sides of the channel layer along the third direction D3.
[0092] An insulating filling layer 93 is formed, covering the inner wall of the active structure 92 and filling the first trench 80, such as... Figure 9 As shown.
[0093] The active structure 92 being a hollow structure means that at least the channel layer in the active structure 92 is a hollow structure. In one example, the first active layer is used as either a source region or a drain region, and the second active layer is used as either a source region or a drain region.
[0094] Specifically, a conductive material such as TiN can be deposited in the first trench 80 using a lateral atomic layer deposition process to form a gate layer 90 covering the entire inner wall of the first trench 80. At this time, since adjacent memory regions PM along the second direction D2 are isolated from each other by an isolation layer 60, the gate layers 90 in two adjacent memory regions PM along the second direction D2 are also independent of each other (i.e., the gate layers 90 in two adjacent memory regions PM along the second direction D2 are also isolated from each other by the isolation layer 60). Next, a dielectric material such as an oxide material (e.g., silicon dioxide) can be deposited in the first trench 80 using a lateral atomic layer deposition process to form a gate dielectric layer 91 covering the entire surface of the gate layer 90. Then, an active structure 92 covering the surface of the gate dielectric layer 91 is formed in the first trench 80; at this time, the active structure 92 does not completely fill the first trench 80. Subsequently, an insulating dielectric material can be deposited in the first trench 80 using a lateral atomic layer deposition process to form an insulating filling layer 93 that covers the entire surface of the active structure 92 and fills the first trench 80, such as... Figure 9 As shown. This embodiment forms a hollow active structure 92, and fills the interior of the hollow active structure 92 with an insulating filler layer 93, enabling the transistor structure including the active structure 92 to operate in full depletion mode. This reduces parasitic BJT (Bipolar Junction Transistor) problems and improves the FBE (Floating Body Effect) problem, thereby improving the electrical performance of the semiconductor structure and increasing its yield. In one example, the electrical performance of the transistor structure can be adjusted by adjusting the thickness of the active structure 92 along the first direction D1 to meet different application requirements.
[0095] In some embodiments, the insulating filler layer 93 is made of an oxide material. Since silicon dioxide has excellent pore-filling properties, in order to ensure that the first trench 80 can be fully filled, in one example, the insulating filler layer 93 is made of silicon dioxide.
[0096] In some embodiments, the active structure 92 is made of an oxide semiconductor material.
[0097] Specifically, the active structure 92 is made of an oxide semiconductor material, which is any one or a combination of two or more of the following: In₂O₃ (indium oxide), ZnO (zinc oxide), IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), IZTO (indium tin zinc oxide), and ZnON (zinc oxynitride). Preferably, the active structure 92 is made of IGZO.
[0098] To further simplify the semiconductor structure manufacturing process and meet the application requirements of different semiconductor structures, in some embodiments, the active structure 92 is a solid structure; the step of forming the transistor structure within the first trench 80 includes:
[0099] A gate layer 90 is formed covering the inner wall of the first trench 80;
[0100] A gate dielectric layer 91 is formed covering the inner wall of the gate layer 90;
[0101] An active structure 92 is formed, covering the inner wall of the gate dielectric layer 91 and filling the first trench 80. The active structure 92 includes a channel layer and a first active layer and a second active layer distributed along a third direction D3 on opposite sides of the channel layer. Figure 10 As shown.
[0102] The active structure 92 being a solid structure means that at least the channel layer in the active structure 92 is a solid structure. In one example, the channel layer, the first active layer, and the second active layer in the active structure 92 are all solid structures. Specifically, a conductive material such as TiN can be deposited in the first trench 80 using a lateral atomic layer deposition process to form a gate layer 90 covering the entire inner wall of the first trench 80. At this time, since adjacent memory regions PM along the second direction D2 are isolated from each other by an isolation layer 60, the gate layers 90 in the two adjacent memory regions PM along the second direction D2 are also independent of each other (i.e., the gate layers 90 in the two adjacent memory regions PM along the second direction D2 are also isolated from each other by an isolation layer 60). Subsequently, a dielectric material such as an oxide material (e.g., silicon dioxide) can be deposited in the first trench 80 using a lateral atomic layer deposition process to form a gate dielectric layer 91 covering the entire surface of the gate layer 90. Next, an active structure 92 is formed within the first trench 80, covering the surface of the gate dielectric layer 91 and filling the first trench 80, such as... Figure 10 As shown.
[0103] Step S14: A word line 200 extending along the second direction D2 is formed. The word line 200 covers the gate layer 90 within a plurality of memory regions PM spaced apart along the second direction D2, such as... Figure 2 and Figure 20 As shown.
[0104] In some embodiments, the memory region PM further includes a capacitor region PC, and the capacitor region PC and the bit line region PB are distributed along a third direction D3 on opposite sides of the transistor region PB; the gate layer 90 covers the entire inner wall of the first trench 80; before forming the word line 200 extending along the second direction D2, the following steps are also included:
[0105] Remove the isolation layer 60 between the capacitor region PC and the second active layer to expose part of the isolation trench 50. The sidewalls of the isolation trench 50 expose the first sacrificial layer 31 and the third sacrificial layer 33.
[0106] The first sacrificial layer 31 and the third sacrificial layer 33 on the capacitor region PC and the second active layer are removed, and the gate layer 90 on the second active layer is removed. A second trench 121 is formed in the storage region PM along the first direction D1 below the capacitor region PC and the second active layer, and a third trench 122 is formed along the first direction D1 above the capacitor region PC and the second active layer. Figure 12 As shown;
[0107] A first isolation layer 141 is formed, filling the second trench 121, the third trench 122, the capacitor region PC, and the isolation trench 50 between the second active layer. Figure 14 As shown.
[0108] Specifically, photolithography can be used to remove the stacked layer at the end of the capacitor region PC that is far from the transistor region PB, forming an etching trench 110 that exposes the substrate 30, such as... Figure 11 As shown. Subsequently, a lateral etching process can be used to remove the first sacrificial layer 31 and the third sacrificial layer 33 on the capacitor region PC and the second active layer along the etching trench 110, forming a second trench 121 and a third trench 122 within the storage region PM, exposing a portion of the isolation trench 50. The second trench 121 and the third trench 122 are located on opposite sides of the second sacrificial layer 32 along the first direction D1, with the second trench 121 located below the third trench 122, as shown. Figure 12 As shown. The second trench 121 and the third trench 122 expose the gate layer 90 located on the second active layer. Next, the gate layer 90 on the second active layer is removed along the second trench 121 and the third trench 122, exposing the gate dielectric layer 91 on the second active layer, as shown. Figure 13As shown. Subsequently, an insulating dielectric material such as a nitride (e.g., silicon nitride) is deposited in the second trench 121 and the third trench 122 to form a first isolation layer 141 that fills the second trench 121, the third trench 122, and the isolation trench 50 between the capacitor region and the second active layer, as shown. Figure 14 As shown.
[0109] In some embodiments, after forming a first isolation layer 141 that fills the isolation trench 50 between the second trench 121, the third trench 122, the capacitor region PC, and the second active layer, the method further includes:
[0110] The second sacrificial layer 32 of the capacitor region PC is removed to form a capacitor trench 150 located between the interlayer insulating layers 34, such as Figure 15 As shown;
[0111] Remove the gate layer 90 exposed to the capacitor trench 150 to expose the second active layer, such as... Figure 16 As shown;
[0112] A capacitor structure 20 electrically connected to the second active layer is formed within the capacitor trench 150, such as... Figure 2 and Figure 17 As shown.
[0113] Specifically, capacitor structure 20 includes a lower electrode layer, a dielectric layer 172, and an upper electrode layer 173. For example, the second sacrificial layer 32 of the capacitor region PC is removed along the etching trench 110 to form a capacitor trench 150 located between the first isolation layer 141 and the second isolation layer 142. The capacitor trench 150 exposes the gate layer 90 located at the end of the active structure 92, such as... Figure 15 As shown. The gate layer 90 and gate dielectric layer 91 located at the ends of the active structure 92 are removed along the capacitor trench 150, thereby exposing the second active layer of the active structure 92, as shown. Figure 16 As shown. Next, conductive materials such as TiN are deposited along the etching trench 110 within the capacitor trench 150 to form a lower electrode layer that covers the inner wall of the capacitor trench 150 and is in direct contact with and electrically connected to the second active layer. A dielectric material with a high dielectric constant is deposited within the capacitor trench 150 to form a dielectric layer 172 covering the surface of the lower electrode layer. Conductive materials such as TiN are deposited within the capacitor trench 150 to form an upper electrode layer 173 covering the surface of the dielectric layer 172, as shown. Figure 17As shown. In order to increase the contact area between the second active layer and the lower electrode layer, thereby reducing the contact resistance between the transistor structure and the capacitor structure 20, in one example, the lower electrode layer includes a main body 170 and an extension 171 connected to the main body 170 along a third direction D3. The extension 171 covers the top surface and the bottom surface of the second active layer, the main body 170 covers the side surface of the second active layer, and the dielectric layer 172 covers the surface of the main body 170. The top surface and the bottom surface of the second active layer are distributed at opposite ends of the second active layer along the first direction D1.
[0114] In some embodiments, the specific steps for forming the word line 200 extending along the second direction D2 include:
[0115] Remove the isolation layer 60 between the channel layer and the first active layer to expose part of the isolation trench 50. The sidewall of the isolation trench 50 exposes the first sacrificial layer 31 and the third sacrificial layer 33.
[0116] The first sacrificial layer 31 and the third sacrificial layer 33 on the channel layer and the first active layer are removed, and a fourth trench 180 located below the channel layer and the first active layer along the first direction D1 and a fifth trench 181 located above the channel layer and the first active layer along the first direction D1 are formed in the storage region PM, as follows. Figure 18 As shown;
[0117] Remove the gate layer 90 located on the first active layer along the fourth trench 180 and the fifth trench 181, as follows: Figure 19 As shown;
[0118] Word line material is deposited along the fourth trench 180 and the fifth trench 181 to form a word line 200 extending along the second direction D2 and covering a plurality of gate layers 90 spaced apart along the second direction D2, such as... Figure 20 As shown.
[0119] Specifically, the first sacrificial layer 31 and the third sacrificial layer 33 remaining in the transistor region PB are removed along the bit line trench 70 (i.e., the first sacrificial layer 31 and the third sacrificial layer 33 on the channel layer and the first active layer are removed), forming the fourth trench 180 and the fifth trench 181 that expose the gate layer 90, and exposing part of the isolation trench 50, such as Figure 18 As shown. The fourth trench 180 and the fifth trench 181 are located on opposite sides of the active structure 92 along the first direction D1, with the fourth trench 180 located below the fifth trench 181. The gate layer 90 on the first active layer is removed along the fourth trench 180 and the fifth trench 181, exposing the gate dielectric layer 91 on the first active layer, as shown. Figure 19As shown. Subsequently, word line material is deposited along the fourth trench 180 and the fifth trench 181 to form word lines 200 extending along the second direction D2 and covering a plurality of gate layers 90 spaced apart along the second direction D2, as shown. Figure 2 and Figure 20 As shown. In this specific embodiment, after forming multiple independent gate layers 90, word lines 200 for connecting the multiple gate layers 90 spaced apart along the second direction D2 are formed. This not only simplifies the formation process of word lines 200 with horizontal structures, but also ensures stable and sufficient contact connection between word lines 200 and gate layers 90, thereby improving the stability of the electrical performance of the semiconductor structure.
[0120] In some embodiments, the step of depositing character line material along the fourth trench 180 and the fifth trench 181 includes:
[0121] Selective atomic layer deposition is used to deposit word line material along the fourth trench 180 and the fifth trench 181. The deposition rate of the word line material on the surface of the gate layer 90 is greater than the deposition rate on the interlayer insulating layer 34. The word line material fills at least the fourth trench 180 above the channel layer and the fifth trench 181 below the channel layer.
[0122] Specifically, by selecting a suitable word line material, the deposition rate of the word line material on the gate layer 90 surface is made greater than that on the interlayer insulating layer 34. This ensures that the formed word lines 200 connect multiple gate layers 90 spaced along the second direction D2, while avoiding the connection of gate layers 90 spaced along the first direction D1 through the word lines 200. In other words, a horizontal word line structure is formed directly through material selection, without needing to control process parameters during deposition or perform vertical etching. This simplifies the formation process of the horizontal word lines 200, improves the manufacturing yield of the semiconductor structure, and reduces the manufacturing cost. In one example, the word line material is deposited only on the gate layer 90 surface, and not on the interlayer insulating layer 34 or the gate dielectric layer 91.
[0123] In some embodiments, the gate layer 90 is made of titanium nitride, the word line material is made of molybdenum metal, the interlayer insulating layer 34 is made of nitride material (e.g., silicon nitride), and the process for depositing the word line material includes: using molybdenum dioxide (MoO2Cl2) or molybdenum pentachloride (MoCl5) as the precursor material, using ammonia or hydrogen as the auxiliary reaction gas, and the reaction temperature is 450°C-600°C.
[0124] In some embodiments, after forming the word line 200 extending along the second direction D2, the following steps are further included:
[0125] A second isolation layer 210 is formed, which is located in the fourth trench 180 below the first active layer, the fifth trench 181 above the second active layer, and the isolation trench 50 between the trench layer and the first active layer.
[0126] A bit line 220 extending along the first direction D1 is formed within the bit line groove 70. The bit line 220 is electrically connected to the first active layer of the transistor structure, such as... Figure 2 and Figure 22 As shown.
[0127] Specifically, after forming the word line 200, a second isolation layer 210 is deposited in the fourth trench 180, the fifth trench 181, and the bit line groove 70, such as... Figure 21 As shown. In one example, the second isolation layer 210 can be an oxide material (e.g., silicon dioxide). Then, the second isolation layer 210 within the bit line trench 70 is etched away, and a conductive material such as tungsten is filled into the bit line trench 70 to form a bit line 220 extending along the first direction D1. The bit line 220 is electrically connected to the first active layer contacts within a plurality of memory regions PM spaced apart along the first direction D1, such as... Figure 2 and Figure 22 As shown.
[0128] This specific embodiment also provides a semiconductor structure, which can be adopted as follows: Figures 1-22 The semiconductor structure shown is formed using the method for forming the semiconductor structure. A schematic diagram of the semiconductor structure provided in this specific embodiment can be found in [reference]. Figures 2-22 .like Figures 2-22 As shown, the semiconductor structure includes:
[0129] Substrate 30;
[0130] A stacked structure is located on a substrate 30. The stacked structure includes a plurality of memory cells arranged at intervals along a first direction D1 and a second direction D2, and an interlayer insulating layer 34 located between adjacent memory cells along the first direction D1. The memory cells include transistor structures, and the transistor structures include active structures 92 and gate layers 90 distributed around the outer periphery of the active structures 92. The first direction D1 is perpendicular to the top surface of the substrate 30, and the second direction D2 is parallel to the top surface of the substrate 30.
[0131] Word line 200 extends along the second direction D2 and covers the gate layer 90 in a plurality of memory cells spaced apart along the second direction D2.
[0132] The semiconductor structure formed in this specific embodiment can be, but is not limited to, DRAM. The following description uses DRAM as an example. In this specific embodiment, the word line 200 and the gate layer 90 are formed in different process steps; that is, the gate layer 90 is formed first, and then the word line 200 is formed. Therefore, there is a contact interface between the word line 200 and the gate layer 90. By forming the gate layer 90 and the word line 200 in steps, this specific embodiment allows the word line 200 to cover the gate layer 90 within multiple memory cells spaced along the second direction D2. This increases the contact area between the word line 200 and the gate layer 90 while forming a horizontally structured word line 200. This ensures a stable connection between the word line 200 and the gate layer 90, reduces the internal resistance of the semiconductor structure, simplifies the semiconductor manufacturing process, and reduces the manufacturing cost of the semiconductor structure.
[0133] In some embodiments, the active structure 92 is a solid structure; or...
[0134] The active structure 92 is a hollow structure.
[0135] To enable the transistor structure to operate in fully depleted mode, thereby reducing parasitic BJT problems and improving FBE problems, in some embodiments, the active structure 92 is a hollow structure. The active structure 92 includes a channel layer and a first active layer and a second active layer located on opposite sides of the channel layer along a third direction D3, wherein the third direction D3 is parallel to the top surface of the substrate 30; the transistor structure also includes:
[0136] An insulating filler layer 93 has an active structure distributed around the outer periphery of the insulating filler layer 93.
[0137] To further improve the performance of the transistor structure, in some embodiments, the thickness of the insulating fill layer 93 along the first direction D1 is greater than or equal to the thickness of the channel layer.
[0138] In some embodiments, the insulating filler layer 93 is made of an oxide material.
[0139] In some embodiments, the gate layer 90 is made of titanium nitride, the word line 200 is made of molybdenum, and the interlayer insulating layer 34 is made of nitride.
[0140] Specifically, by selecting a suitable word line material for forming the word line 200, the deposition rate of the word line material on the surface of the gate layer 90 is greater than that on the interlayer insulating layer 34. This ensures that the formed word line 200 connects multiple gate layers 90 spaced along the second direction D2, while avoiding the connection of gate layers 90 spaced along the first direction D1 through the word line 200. In other words, the horizontal word line structure is formed directly through material selection, without the need to control the process parameters during deposition or perform etching in the vertical direction. This simplifies the formation process of the horizontal word line 200, improves the manufacturing yield of the semiconductor structure, and reduces the manufacturing cost of the semiconductor structure.
[0141] In some embodiments, the memory cell further includes a capacitor structure 20 located outside the transistor structure along the third direction D3; the capacitor structure 20 includes:
[0142] The lower electrode layer includes a main body 170 and an extension 171 connected to the main body 170 along a third direction D3. The extension covers the top surface of the second active layer and the bottom surface of the second active layer. The main body 170 covers the side surface of the second active layer. The top surface of the second active layer and the bottom surface of the second active layer are distributed at opposite ends of the second active layer along the first direction D1.
[0143] Dielectric layer 172 covers the surface of the lower electrode layer;
[0144] The upper electrode layer 173 covers the surface of the dielectric layer 172.
[0145] Specifically, the extension 171 protrudes from the main body 170 along the third direction D3, such that the lower electrode layer including the extension 171 and the main body 170 covers the second active layer, thereby increasing the contact area between the lower electrode layer and the second active layer and reducing the contact resistance between the transistor structure and the capacitor structure.
[0146] To ensure that the subsequently formed word lines 200 fully cover the gate layer 900 and reduce the resistance of the word lines 200, in some embodiments, the thickness of the word lines 200 located on the top or bottom surface of the gate layer 90 along the first direction D1 is greater than or equal to the thickness of the gate layer 90. The top and bottom surfaces of the gate layer 90 are distributed opposite each other along the first direction D1, and the bottom surface of the gate layer 90 refers to the surface of the gate layer 90 facing the substrate 30.
[0147] In some embodiments, the active structure 92 is made of an oxide semiconductor material.
[0148] The semiconductor structure and its formation method provided in some embodiments of this specific implementation first form a transistor structure in a first trench of the memory region, with the gate layer of the transistor structure distributed around the outer periphery of the active structure to form a gate-surround structure, and the gate layers in each memory region are independent of each other. Then, word lines are formed to cover the gate layers in multiple memory regions spaced apart along the second direction. This eliminates the need to form horizontal word lines simultaneously with the gate layer through complex processes, simplifying the horizontal word line formation process and reducing the manufacturing cost of the semiconductor structure. Moreover, some embodiments of this specific implementation form a stacked layer by depositing a sacrificial layer and an interlayer insulating layer. Subsequently, by removing part of the sacrificial layer and forming the active structure at the location of the sacrificial layer through a filling process, the formation of the active structure does not require complex epitaxial processes. This not only further simplifies the semiconductor structure manufacturing process but also reduces internal defects such as stress in the semiconductor structure, thereby improving the manufacturing yield and electrical performance of the semiconductor structure. In addition, the active structure in some embodiments of this specific implementation is a hollow structure, and the interior of the active structure is filled with an insulating filler layer, enabling the transistor structure to operate in full depletion mode, thereby further improving the semiconductor structure yield and electrical performance.
[0149] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.
Claims
1. A method for forming a semiconductor structure, characterized in that, Includes the following steps: Provide substrate; A stacked layer is formed on the substrate, the stacked layer including an interlayer insulating layer and a sacrificial layer alternately stacked along a first direction, the sacrificial layer including a first sacrificial layer, a second sacrificial layer and a third sacrificial layer stacked sequentially along the first direction, the stacked layer including a plurality of memory regions spaced apart along a second direction, the memory regions including transistor regions and bit line regions located on one side of the transistor regions along a third direction, wherein the first direction is perpendicular to the top surface of the substrate, the second direction is parallel to the top surface of the substrate, the third direction is parallel to the top surface of the substrate, and the second direction intersects the third direction; The stacked layers are etched to form isolation trenches located between adjacent storage regions along the second direction; An isolation layer is formed that fills the isolation groove; Remove the stacked layer in the bit line region to form a bit line slot; The second sacrificial layer in the transistor region is removed along the bit line groove, and a first trench is formed in the transistor region between the first sacrificial layer and the third sacrificial layer; A transistor structure is formed in the first trench, the transistor structure including a gate layer covering the inner wall of the first trench and an active structure located in the gate layer; A word line is formed extending along the second direction, the word line covering the gate layer in a plurality of memory regions spaced apart along the second direction.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, The materials of the first sacrificial layer and the third sacrificial layer are both oxide materials, and the material of the second sacrificial layer is polycrystalline silicon.
3. The method for forming a semiconductor structure according to claim 1, characterized in that, The active structure is a hollow structure; The step of forming a transistor structure within the first trench includes: The gate layer is formed to cover the inner wall of the first trench; A gate dielectric layer is formed covering the inner wall of the gate layer; An active structure is formed in the first trench to cover the inner wall of the gate dielectric layer. The active structure includes a channel layer and a first active layer and a second active layer distributed on opposite sides of the channel layer along a third direction. An insulating filler layer is formed that covers the inner wall of the active structure and fills the first trench.
4. The method for forming a semiconductor structure according to claim 1, characterized in that, The active structure is a solid structure; the step of forming a transistor structure within the first trench includes: The gate layer is formed to cover the inner wall of the first trench; A gate dielectric layer is formed covering the inner wall of the gate layer; An active structure is formed that covers the inner wall of the gate dielectric layer and fills the first trench. The active structure includes a channel layer and a first active layer and a second active layer distributed on opposite sides of the channel layer along a third direction.
5. The method for forming a semiconductor structure according to claim 3 or 4, characterized in that, The storage region further includes a capacitor region, and the capacitor region and the bit line region are distributed along the third direction on opposite sides of the transistor region; the gate layer covers the entire inner wall of the first trench; before forming the word line extending along the second direction, the following steps are also included: Remove the isolation layer between the capacitor region and the second active layer to expose part of the isolation trench, and expose the first sacrificial layer and the third sacrificial layer on the sidewall of the isolation trench; Remove the first sacrificial layer and the third sacrificial layer on the capacitor region and the second active layer, and remove the gate layer on the second active layer to form a second trench located below the capacitor region and the second active layer along the first direction and a third trench located above the capacitor region and the second active layer along the first direction in the storage region. A first isolation layer is formed that fills the isolation trench between the second trench, the third trench, the capacitor region, and the second active layer.
6. The method for forming a semiconductor structure according to claim 5, characterized in that, After forming a first isolation layer that fills the isolation trench between the second trench, the third trench, the capacitor region, and the second active layer, the method further includes: Remove the second sacrificial layer from the capacitor region to form a capacitor trench located between interlayer insulating layers; Remove the gate layer exposed to the capacitor trench to expose the second active layer; A capacitor structure electrically connected to the second active layer is formed within the capacitor groove.
7. The method for forming a semiconductor structure according to claim 3 or 4, characterized in that, The specific steps for forming the character lines extending along the second direction include: Remove the isolation layer between the channel layer and the first active layer to expose part of the isolation trench, and expose the first sacrificial layer and the third sacrificial layer on the sidewall of the isolation trench; Remove the first sacrificial layer and the third sacrificial layer on the channel layer and the first active layer, and form a fourth trench along the first direction below the channel layer and the first active layer and a fifth trench along the first direction above the channel layer and the first active layer in the storage area. Remove the gate layer located on the first active layer along the fourth trench and the fifth trench; Word line material is deposited along the fourth trench and the fifth trench to form word lines that extend along the second direction and cover a plurality of gate layers spaced apart along the second direction.
8. The method for forming a semiconductor structure according to claim 7, characterized in that, The step of depositing letter line material along the fourth and fifth trenches includes: Word line material is deposited along the fourth and fifth trenches using a selective atomic layer deposition process. The deposition rate of the word line material on the gate layer surface is greater than the deposition rate on the interlayer insulating layer. The word line material at least fills the fourth trench above the channel layer and the fifth trench below the channel layer.
9. The method for forming a semiconductor structure according to claim 8, characterized in that, The gate layer is made of titanium nitride, the word line is made of molybdenum metal, the interlayer insulating layer is made of nitride, and the deposition process for the word line material includes: using molybdenum dioxide (MoO2Cl2) or molybdenum pentachloride (MoCl5) as the precursor material, using ammonia or hydrogen as the auxiliary reaction gas, and the reaction temperature is 450℃-600℃.
10. The method for forming a semiconductor structure according to claim 8, characterized in that, After forming the character lines extending along the second direction, the following steps are also included: A second isolation layer is formed, which is located in the fourth trench below the first active layer, the fifth trench above the second active layer, and the isolation trench between the trench layer and the first active layer; A bit line extending along the first direction is formed within the bit line groove, and the bit line is electrically connected to the first active layer of the transistor structure.
11. The method for forming a semiconductor structure according to claim 1, characterized in that, The active structure is made of oxide semiconductor material.
12. A semiconductor structure, characterized in that, include: Substrate; A stacked structure is located on the substrate. The stacked structure includes a plurality of memory cells spaced apart along a first direction and a second direction, and an interlayer insulating layer located between adjacent memory cells along the first direction. Each memory cell includes a transistor structure, and the transistor structure includes an active structure and a gate layer distributed around the outer periphery of the active structure. The active structure is a hollow structure. The active structure includes a channel layer and a first active layer and a second active layer located on opposite sides of the channel layer along a third direction. The first direction is perpendicular to the top surface of the substrate, the second direction is parallel to the top surface of the substrate, and the third direction is parallel to the top surface of the substrate. Word lines extend along the second direction and cover the gate layers within a plurality of memory cells spaced apart along the second direction.
13. The semiconductor structure according to claim 12, characterized in that, The transistor structure also includes: An insulating filler layer, wherein the active structure is distributed around the outer periphery of the insulating filler layer.
14. The semiconductor structure according to claim 13, characterized in that, Along the first direction, the thickness of the insulating fill layer is greater than or equal to the thickness of the channel layer.
15. The semiconductor structure according to claim 12, characterized in that, The gate layer is made of titanium nitride, the word line is made of molybdenum, and the interlayer insulating layer is made of nitride.
16. The semiconductor structure according to claim 13, characterized in that, The memory cell further includes a capacitor structure located outside the transistor structure along the third direction; the capacitor structure includes: The lower electrode layer includes a main body and an extension connected to the main body along the third direction. The extension covers the top surface and the bottom surface of the second active layer. The main body covers the side surface of the second active layer. The top surface and the bottom surface of the second active layer are distributed at opposite ends of the second active layer along the first direction. A dielectric layer covers the surface of the lower electrode layer; The upper electrode layer covers the surface of the dielectric layer.
17. The semiconductor structure according to claim 12, characterized in that, Along the first direction, the thickness of the word line located on the top or bottom surface of the gate layer is greater than or equal to the thickness of the gate layer.
18. The semiconductor structure according to claim 12, characterized in that, The active structure is made of oxide semiconductor material.