Current biasing circuit and power amplifier system
By adaptively adjusting the transistor bias current through a current bias circuit, the problem of gain reduction in the process of improving the linearity of the power amplifier is solved, resulting in more efficient signal transmission and a lower bit error rate.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI INTEGRATED CIRCUIT MFG INNOVATION CENT CO LTD
- Filing Date
- 2023-12-26
- Publication Date
- 2026-06-26
AI Technical Summary
Existing linearity improvement techniques for power amplifiers suffer from problems such as reduced gain and low efficiency. In particular, transistor nonlinearity is a serious issue under high power supply voltages, which is difficult to effectively resolve with existing technologies.
A current bias circuit is adopted, including a detection unit, a conversion unit, and a detection current injection unit, to adaptively adjust the bias current of the transistors in the power amplifier. By detecting the gate differential input voltage of the transistors and converting it into a current differential injection amplifier, the linear operating range is expanded.
It improves the linear operating range of the power amplifier, enhances the accuracy and reliability of signal transmission, reduces the bit error rate, and increases the data transmission rate and network capacity.
Smart Images
Figure CN117713714B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power amplifier technology, and more particularly to a current bias circuit and a power amplifier system. Background Technology
[0002] A power amplifier is a device that extracts energy from a DC power supply and converts that energy according to the input electrical signal. Its basic principle is to use a component called a transistor to control the current in the power supply, causing the current to change in response to variations in the input signal, thereby amplifying the signal power. Its function is to allow signals to be transmitted further and more clearly.
[0003] Linearity is a crucial performance indicator for power amplifiers, playing a decisive role in the performance of the circuit system. In mobile communication systems, power amplifiers amplify radio frequency (RF) signals between base stations and terminal devices. Linearity is paramount in these systems because it ensures high-quality signal transmission, reducing bit error rates, increasing data transmission rates and network capacity, while also ensuring signal accuracy and reliability. This is critical for measuring target distance, speed, and direction, as well as accurately analyzing the spectrum. In RF front-end modules, power amplifiers are typically a key component of the signal chain, amplifying weak RF signals from receiving antennas or converting digital signals into suitable RF signals. High linearity means minimizing distortion to ensure high sensitivity and a high signal-to-noise ratio.
[0004] The primary source of nonlinearity in power amplifiers is the nonlinear current-voltage characteristics of transistors. As the drain-side output voltage swing of a transistor continuously increases, the transistor partially enters the linear region within a signal cycle. At this point, the transistor's voltage-to-current conversion capability weakens, its equivalent transconductance decreases, and it exhibits gain compression. This is especially true for amplifiers designed using advanced silicon-based processes, where the supply voltage is limited by the device's breakdown voltage, leading to even more severe nonlinearity issues.
[0005] Existing techniques for improving the linearity of power amplifiers include negative feedback and dynamic biasing. Negative feedback, by introducing resistive negative feedback, reduces the amplifier's gain dependence on transistor transconductance, thereby improving linearity. However, this technique suffers from the drawback that the negative feedback resistor reduces gain, consequently decreasing the power amplifier's output power and efficiency. Existing dynamic biasing techniques detect the power amplifier's input voltage swing and directly adjust the gate differential input voltage. However, directly controlling gain through voltage has limitations, including difficulty in adjusting gain and sensitivity to process variations, temperature fluctuations, and voltage deviations.
[0006] Therefore, it is necessary to provide a novel current bias circuit and power amplifier system to solve the above-mentioned problems existing in the prior art. Summary of the Invention
[0007] The purpose of this invention is to provide a current bias circuit and a power amplifier system that can adaptively adjust the bias current of the transistors in the power amplifier, thereby expanding the linear operating range of the power amplifier.
[0008] To achieve the above objectives, the current biasing circuit of the present invention is applied to a power amplifier, comprising a detection unit, a conversion unit, and a detection current injection unit. The detection unit is used to detect the gate differential input voltage of the transistor in the power amplifier to output a first voltage and a second voltage. The first voltage includes a static operating voltage and a detection voltage, and the detection voltage increases as the differential input voltage increases. The second voltage includes the static operating voltage. The conversion unit is used to convert the first voltage and the second voltage into a first current and a second current, and to calculate the difference between the first current and the second current to obtain the detection current. The detection current injection unit is used to inject the detection current into the power amplifier.
[0009] Optionally, the detection unit includes a first detection unit and a second detection unit. The input terminal of the first detection unit is connected to the power amplifier and is used to detect the gate differential input voltage of the transistor in the power amplifier to output a first voltage. The input terminal of the second detection subunit is left floating and is used to output a second voltage.
[0010] Optionally, the first detection unit includes a DC blocking capacitor unit, a first detector, and a first filter unit. The input terminal of the first detector is connected to the power amplifier through the DC blocking capacitor unit, and the output terminal of the first detector is connected to the first filter unit. The first filter unit is used to filter the output of the first detector to obtain the first voltage.
[0011] Optionally, the first detector includes a third NMOS transistor, a fourth NMOS transistor, and a third resistor. The drains of the third and fourth NMOS transistors are both connected to a power supply voltage. The sources of the third and fourth NMOS transistors are connected to each other, serving as the output terminal of the first detector. The gate of the third NMOS transistor is connected to one end of the third resistor, serving as the first input terminal of the first detector. The gate of the fourth NMOS transistor is connected to the other end of the third resistor, serving as the second input terminal of the first detector.
[0012] Optionally, the first filter unit includes a first resistor and a first capacitor, one end of the first resistor and one end of the first capacitor are both connected to the source of the third NMOS transistor, and the other end of the first resistor and the other end of the first capacitor are both grounded.
[0013] Optionally, the DC blocking capacitor unit includes a third capacitor and a fourth capacitor. One end of the third capacitor and one end of the fourth capacitor are both connected to the power amplifier. The other end of the third capacitor is connected to the gate of the third NMOS transistor, and the other end of the fourth capacitor is connected to the gate of the fourth NMOS transistor.
[0014] Optionally, the second detection unit includes a second detector and a second filtering unit. The input terminal of the second detector is left floating, and the second filtering unit is used to filter the output of the second detector to obtain the second voltage.
[0015] Optionally, the second detector includes a fifth NMOS transistor, a sixth NMOS transistor, and a fourth resistor. The drains of the fifth and sixth NMOS transistors are both connected to the power supply voltage. The sources of the fifth and sixth NMOS transistors are connected to each other, serving as the output terminal of the second detector. The gate of the fifth NMOS transistor is connected to one end of the fourth resistor, serving as the first input terminal of the second detector. The gate of the sixth NMOS transistor is connected to the other end of the fourth resistor, serving as the second input terminal of the second detector.
[0016] Optionally, the second filter unit includes a second resistor and a second capacitor. One end of the second resistor and one end of the second capacitor are both connected to the source of the fifth NMOS transistor, and the other end of the second resistor and the other end of the second capacitor are both grounded.
[0017] Optionally, the conversion unit includes a first common-source cascode current mirror, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor. The sources of the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor are all grounded. The gate of the tenth NMOS transistor is connected to the second voltage. The drain of the tenth NMOS transistor is connected to the first output terminal of the first common-source cascode current mirror. The gate of the seventh NMOS transistor is connected to the first voltage. The drain of the first NMOS transistor is connected to the drain of the eighth NMOS transistor, the gate of the eighth NMOS transistor, the gate of the ninth NMOS transistor, and the second output terminal of the first common-source cascode current mirror.
[0018] Optionally, the first common-source cascode current mirror includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are both connected to the power supply voltage. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, the drain of the second PMOS transistor, and the source of the fourth PMOS transistor. The drain of the first PMOS transistor is connected to the source of the third PMOS transistor. The drain of the third PMOS transistor serves as the second output terminal of the first common-source cascode current mirror. The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor and the drain of the fourth PMOS transistor, serving as the first output terminal of the first common-source cascode current mirror.
[0019] Optionally, the detection current injection unit includes a second common-source common-gate current mirror, an eleventh NMOS transistor, and a current source. The first output terminal of the second common-source common-gate current mirror is connected to the detection current, and the second output terminal of the second common-source common-gate current mirror is connected to the drain of the eleventh NMOS transistor, the gate of the eleventh NMOS transistor, and the positive terminal of the current source. This serves as the output terminal of the detection current injection unit and is connected to the power amplifier. The negative terminal of the current source is connected to the power supply voltage, and the source of the eleventh NMOS transistor is grounded.
[0020] Optionally, the second common-source cascode current mirror includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor. The sources of the fifth and sixth PMOS transistors are both connected to the power supply voltage. The gate of the fifth PMOS transistor is connected to the gate of the sixth PMOS transistor, the drain of the sixth PMOS transistor, and the source of the eighth PMOS transistor. The drain of the fifth PMOS transistor is connected to the source of the seventh PMOS transistor. The gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor and the drain of the eighth PMOS transistor, serving as the first output terminal of the second common-source cascode current mirror. The drain of the seventh PMOS transistor is connected to the drain of the eleventh NMOS transistor.
[0021] The present invention also provides a power amplifier system, including a power amplifier and the current bias circuit.
[0022] Optionally, the power amplifier includes a first NMOS transistor, a second NMOS transistor, a first transformer, and a second transformer. The sources of both the first and second NMOS transistors are grounded. The first transformer includes a first main coil and a first secondary coil. One end of the first main coil serves as the input terminal of the power amplifier, and the other end is grounded. One end of the first secondary coil is connected to the gate of the first NMOS transistor and the detection unit, and the other end is connected to the gate of the second NMOS transistor and the detection unit. The center tap of the first secondary coil is connected to the output terminal of the detection current injection unit to receive the detection current. The second transformer includes a second main coil and a second secondary coil. One end of the second main coil is connected to the drain of the first NMOS transistor, and the other end is connected to the drain of the second NMOS transistor. The center tap of the second main coil is connected to the power supply voltage. One end of the second secondary coil serves as the output terminal of the power amplifier, and the other end is grounded.
[0023] The beneficial effects of this invention are as follows: the current bias circuit includes a detection unit, a conversion unit, and a detection current injection unit. The detection unit is used to detect the gate differential input voltage of the transistor in the power amplifier to output a first voltage and a second voltage. The first voltage includes a static operating voltage and a detection voltage. The detection voltage increases as the differential input voltage increases. The second voltage includes the static operating voltage. The conversion unit is used to convert the first voltage and the second voltage into a first current and a second current, and calculate the difference between the first current and the second current to obtain the detection current. The detection current injection unit is used to inject the detection current into the power amplifier, which can adaptively adjust the bias current of the transistor in the power amplifier, thereby expanding the linear operating range of the power amplifier. Attached Figure Description
[0024] Figure 1 This is a circuit diagram of a power amplifier system in some embodiments of the present invention. Detailed Implementation
[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, but do not exclude other elements or objects.
[0026] To address the problems existing in the prior art, embodiments of the present invention provide a power amplifier system. (Refer to...) Figure 1 The power amplifier system includes a power amplifier 100 and a current bias circuit 110.
[0027] Reference Figure 1 The power amplifier 100 includes a first NMOS transistor N1, a second NMOS transistor N2, a first transformer TF1, and a second transformer TF2. The sources of the first NMOS transistor N1 and the second NMOS transistor N2 are both grounded. The first transformer TF1 includes a first main coil and a first secondary coil. One end of the first main coil serves as the input terminal Pin of the power amplifier 100, and the other end of the first main coil is grounded. One end of the first secondary coil is connected to the gate of the first NMOS transistor N1 and the detection unit, and the other end of the first secondary coil is connected to the gate of the second NMOS transistor N2 and the detection unit. The center tap of the first secondary coil is connected to the output terminal of the detection current injection unit to receive the detection current. The second transformer TF2 includes a second main coil and a second secondary coil. One end of the second main coil is connected to the drain of the first NMOS transistor N1, and the other end of the second main coil is connected to the drain of the second NMOS transistor N2. The center tap of the second main coil is connected to the power supply voltage VDD. One end of the second secondary coil serves as the output terminal Pout of the power amplifier 100, and the other end of the second secondary coil is grounded.
[0028] In some embodiments, the current biasing circuit includes a detection unit, a conversion unit, and a detection current injection unit. The detection unit is used to detect the gate differential input voltage of the transistor in the power amplifier to output a first voltage and a second voltage. The first voltage includes a static operating voltage and a detection voltage, and the detection voltage increases as the differential input voltage increases. The second voltage includes the static operating voltage. The conversion unit is used to convert the first voltage and the second voltage into a first current and a second current, and calculate the difference between the first current and the second current to obtain the detection current. The detection current injection unit is used to inject the detection current into the power amplifier.
[0029] In some embodiments, the detection unit includes a first detection unit and a second detection unit. The input terminal of the first detection unit is connected to a power amplifier and is used to detect the gate differential input voltage of the transistor in the power amplifier to output a first voltage. The input terminal of the second detection subunit is left floating and is used to output a second voltage.
[0030] In some embodiments, the first detection unit includes a DC blocking capacitor unit, a first detector, and a first filter unit. The input terminal of the first detector is connected to the power amplifier through the DC blocking capacitor unit, and the output terminal of the first detector is connected to the first filter unit. The first filter unit is used to filter the output of the first detector to obtain the first voltage.
[0031] Reference Figure 1 The first detector includes a third NMOS transistor N3, a fourth NMOS transistor N4, and a third resistor R3. The drains of the third NMOS transistor N3 and the fourth NMOS transistor N4 are both connected to the power supply voltage VDD. The sources of the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected to each other, serving as the output terminal of the first detector. The gate of the third NMOS transistor N3 is connected to one end of the third resistor R3, serving as the first input terminal of the first detector. The gate of the fourth NMOS transistor N4 is connected to the other end of the third resistor R3, serving as the second input terminal of the first detector.
[0032] Reference Figure 1 The first filter unit includes a first resistor R1 and a first capacitor C1. One end of the first resistor R1 and one end of the first capacitor C1 are both connected to the source of the third NMOS transistor N3, and the other ends of the first resistor R1 and the first capacitor C1 are both grounded.
[0033] In some embodiments, the DC blocking capacitor unit includes a third capacitor and a fourth capacitor. One end of the third capacitor and one end of the fourth capacitor are both connected to the power amplifier. The other end of the third capacitor is connected to the gate of the third NMOS transistor, and the other end of the fourth capacitor is connected to the gate of the fourth NMOS transistor. Herein, the third capacitor and the fourth capacitor are DC blocking capacitors.
[0034] Reference Figure 1 One end of the third capacitor C3 is connected to the gate of the first NMOS transistor N1, one end of the fourth capacitor C4 is connected to the gate of the second NMOS transistor N2, the other end of the third capacitor C3 is connected to the gate of the third NMOS transistor N3, and the other end of the fourth capacitor C4 is connected to the gate of the fourth NMOS transistor N4.
[0035] In some embodiments, the second detection unit includes a second detector and a second filtering unit, the input terminal of the second detector is left floating, and the second filtering unit is used to filter the output of the second detector to obtain the second voltage.
[0036] Reference Figure 1 The second detector includes a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a fourth resistor R4. The drains of the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are both connected to the power supply voltage VDD. The sources of the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are connected to each other, serving as the output terminal of the second detector. The gate of the fifth NMOS transistor N5 is connected to one end of the fourth resistor R4, serving as the first input terminal of the second detector. The gate of the sixth NMOS transistor N6 is connected to the other end of the fourth resistor R4, serving as the second input terminal of the second detector.
[0037] Reference Figure 1 The second filter unit includes a second resistor R2 and a second capacitor C2. One end of the second resistor R2 and one end of the second capacitor C2 are both connected to the source of the fifth NMOS transistor N5, and the other end of the second resistor R2 and the other end of the second capacitor C2 are both grounded.
[0038] Reference Figure 1 The third resistor R3 and the fourth resistor R4 act as bias resistors and are configured by a digital to analog converter (DAC) to achieve multi-bit adjustment, the purpose of which is to adjust the detection threshold of the detection unit.
[0039] Reference Figure 1The conversion unit includes a first common-source cascode current mirror, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, and a tenth NMOS transistor N10. The sources of the seventh NMOS transistor N7, the eighth NMOS transistor N8, the ninth NMOS transistor N9, and the tenth NMOS transistor N10 are all grounded. The gate of the tenth NMOS transistor N10 is connected to the second voltage. The drain of the tenth NMOS transistor N10 is connected to the first output terminal of the first common-source cascode current mirror. The gate of the seventh NMOS transistor N7 is connected to the first voltage. The drain of the first NMOS transistor N10 is connected to the drain of the eighth NMOS transistor N8, the gate of the eighth NMOS transistor N8, the gate of the ninth NMOS transistor N9, and the second output terminal of the first common-source cascode current mirror.
[0040] Reference Figure 1 The first common-source cascode current mirror includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, and a fourth PMOS transistor P4. The source of the first PMOS transistor P1 and the source of the second PMOS transistor P2 are both connected to the power supply voltage VDD. The gate of the first PMOS transistor P1 is connected to the gate of the second PMOS transistor P2, the drain of the second PMOS transistor P2, and the source of the fourth PMOS transistor P4. The drain of the first PMOS transistor P1 is connected to the source of the third PMOS transistor P3. The drain of the third PMOS transistor P3 serves as the second output terminal of the first common-source cascode current mirror. The gate of the third PMOS transistor P3 is connected to the gate of the fourth PMOS transistor P4 and the drain of the fourth PMOS transistor P4, serving as the first output terminal of the first common-source cascode current mirror.
[0041] Reference Figure 1 The detection current injection unit includes a second common-source common-gate current mirror, an eleventh NMOS transistor N11, and a current source. The first output terminal of the second common-source common-gate current mirror is connected to the drain of the ninth NMOS transistor N9 to receive the detection current. The second output terminal of the second common-source common-gate current mirror is connected to the drain of the eleventh NMOS transistor N11, the gate of the eleventh NMOS transistor N11, and the positive terminal of the current source. As the output terminal of the detection current injection unit, it is connected to the center tap of the first sub-coil. The negative terminal of the current source is connected to the power supply voltage VDD, and the source of the eleventh NMOS transistor N11 is grounded.
[0042] Reference Figure 1The second common-source common-gate current mirror includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, and an eighth PMOS transistor P8. The sources of the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are both connected to the power supply voltage VDD. The gate of the fifth PMOS transistor P5 is connected to the gate of the sixth PMOS transistor P6, the drain of the sixth PMOS transistor P6, and the source of the eighth PMOS transistor P8. The drain of the fifth PMOS transistor P5 is connected to the source of the seventh PMOS transistor P7. The gate of the seventh PMOS transistor P7 is connected to the gate of the eighth PMOS transistor P8 and the drain of the eighth PMOS transistor P8, serving as the first output terminal of the second common-source common-gate current mirror. The drain of the seventh PMOS transistor P7 is connected to the drain of the eleventh NMOS transistor N11.
[0043] Reference Figure 1 The fifth PMOS transistor P5 and the seventh PMOS transistor P7 form an array whose actual effective size is configured by control bits, the purpose of which is to adjust the intensity of the detection current injected into the power amplifier 100.
[0044] Reference Figure 1The output voltage of the first detector is filtered by the first filter unit to obtain a first voltage that is approximately DC. This first voltage increases with the gate voltages of the first NMOS transistor N1 and the second NMOS transistor N2, and includes both a static operating voltage and a detection voltage. The second detector, serving as a reference for the first detector, can extract the second voltage, i.e., the static operating voltage. The tenth NMOS transistor N10 and the seventh NMOS transistor N7 convert the first voltage and the second voltage into a first current and a second current, respectively. These currents are then subtracted using the current mirror subtractor function of the conversion unit to obtain a detection current that is positively correlated with the gate voltages of the first NMOS transistor N1 and the second NMOS transistor N2, and does not include the static operating current. The detection current and the reference current of the current source are injected together into the eleventh NMOS transistor N11. A channel bias current, which is adjusted in real time according to the gate voltages of the first NMOS transistor N1 and the second NMOS transistor N2 in the power amplifier 100, is mirrored in these transistors, thereby achieving linear enhancement of the power amplifier 100. The fifth PMOS transistor P5 and the seventh PMOS transistor P7 can adjust the injection intensity of the detection current. The third resistor R3 and the fourth resistor R4 act as bias resistors and can be configured via a digital-to-analog converter to adjust the detection threshold, thus achieving linear enhancement effects with different intensities and starting points. The first and second common-source cascode current mirrors are limited by their own voltage margins, preventing transistor reliability issues caused by the uncontrolled rise of the output voltage and current of the current bias circuit 110.
[0045] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.
Claims
1. A current biasing circuit, applied to a power amplifier, characterized in that, It includes a detection unit, a conversion unit, and a detection current injection unit. The detection unit is used to detect the gate differential input voltage of the transistor in the power amplifier to output a first voltage and a second voltage. The first voltage includes a static operating voltage and a detection voltage. The detection voltage increases as the differential input voltage increases. The second voltage includes the static operating voltage. The conversion unit is used to convert the first voltage into a first current, convert the second voltage into a second current, and calculate the difference between the first current and the second current to obtain the detection current; the detection current injection unit is used to inject the detection current into the power amplifier; The detection unit includes a first detection unit and a second detection unit. The input terminal of the first detection unit is connected to the power amplifier and is used to detect the gate differential input voltage of the transistor in the power amplifier to output a first voltage. The first detection unit includes a DC blocking capacitor unit, a first detector, and a first filter unit. The input terminal of the first detector is connected to the power amplifier through the DC blocking capacitor unit, and the output terminal of the first detector is connected to the first filter unit. The first filter unit is used to filter the output of the first detector to obtain the first voltage. The first detector includes a third NMOS transistor, a fourth NMOS transistor, and a third resistor. The drains of the third and fourth NMOS transistors are both connected to the power supply voltage. The sources of the third and fourth NMOS transistors are connected to each other, serving as the output terminal of the first detector. The gate of the third NMOS transistor is connected to one end of the third resistor, serving as the first input terminal of the first detector. The gate of the fourth NMOS transistor is connected to the other end of the third resistor, serving as the second input terminal of the first detector.
2. The current biasing circuit according to claim 1, characterized in that, The first filter unit includes a first resistor and a first capacitor. One end of the first resistor and one end of the first capacitor are both connected to the source of the third NMOS transistor, and the other ends of the first resistor and the first capacitor are both grounded.
3. The current biasing circuit according to claim 1, characterized in that, The DC blocking capacitor unit includes a third capacitor and a fourth capacitor. One end of the third capacitor and one end of the fourth capacitor are both connected to the power amplifier. The other end of the third capacitor is connected to the gate of the third NMOS transistor, and the other end of the fourth capacitor is connected to the gate of the fourth NMOS transistor.
4. The current biasing circuit according to claim 1, characterized in that, The second detection unit includes a second detector and a second filtering unit. The input terminal of the second detector is left AC floating, and the second filtering unit is used to filter the output of the second detector to obtain the second voltage.
5. The current biasing circuit according to claim 4, characterized in that, The second detector includes a fifth NMOS transistor, a sixth NMOS transistor, and a fourth resistor. The drains of the fifth and sixth NMOS transistors are both connected to the power supply voltage. The sources of the fifth and sixth NMOS transistors are connected to each other, serving as the output terminal of the second detector. The gate of the fifth NMOS transistor is connected to one end of the fourth resistor, serving as the first input terminal of the second detector. The gate of the sixth NMOS transistor is connected to the other end of the fourth resistor, serving as the second input terminal of the second detector.
6. The current biasing circuit according to claim 5, characterized in that, The second filter unit includes a second resistor and a second capacitor. One end of the second resistor and one end of the second capacitor are both connected to the source of the fifth NMOS transistor, and the other end of the second resistor and the other end of the second capacitor are both grounded.
7. The current biasing circuit according to claim 1, characterized in that, The detection current injection unit includes a second common-source common-gate current mirror, an eleventh NMOS transistor, and a current source. The first output terminal of the second common-source common-gate current mirror is connected to the detection current, and the second output terminal of the second common-source common-gate current mirror is connected to the drain of the eleventh NMOS transistor, the gate of the eleventh NMOS transistor, and the positive terminal of the current source. As the output terminal of the detection current injection unit, it is connected to the power amplifier. The negative terminal of the current source is connected to the power supply voltage, and the source of the eleventh NMOS transistor is grounded. The second common-source common-gate current mirror includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor. The sources of the fifth PMOS transistor and the sixth PMOS transistor are both connected to the power supply voltage. The gate of the fifth PMOS transistor is connected to the gate of the sixth PMOS transistor, the drain of the sixth PMOS transistor, and the source of the eighth PMOS transistor. The drain of the fifth PMOS transistor is connected to the source of the seventh PMOS transistor. The gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor and the drain of the eighth PMOS transistor, serving as the first output terminal of the second common-source common-gate current mirror. The drain of the seventh PMOS transistor is connected to the drain of the eleventh NMOS transistor. The conversion unit includes a first common-source cascode current mirror, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor. The sources of the seventh, eighth, ninth, and tenth NMOS transistors are all grounded. The gate of the tenth NMOS transistor is connected to the second voltage. The drain of the tenth NMOS transistor is connected to the first output terminal of the first common-source cascode current mirror. The gate of the seventh NMOS transistor is connected to the first voltage. The drain of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor, the gate of the eighth NMOS transistor, the gate of the ninth NMOS transistor, and the second output terminal of the first common-source cascode current mirror. The drain of the ninth NMOS transistor is connected to the gate of the seventh PMOS transistor, the gate of the eighth PMOS transistor, and the drain of the eighth PMOS transistor.
8. The current biasing circuit according to claim 7, characterized in that, The first common-source common-gate current mirror includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are both connected to the power supply voltage. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, the drain of the second PMOS transistor, and the source of the fourth PMOS transistor. The drain of the first PMOS transistor is connected to the source of the third PMOS transistor. The drain of the third PMOS transistor serves as the second output terminal of the first common-source common-gate current mirror. The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor and the drain of the fourth PMOS transistor, serving as the first output terminal of the first common-source common-gate current mirror.
9. A power amplifier system, characterized in that, It includes a power amplifier and a current biasing circuit as described in any one of claims 1 to 8.
10. The power amplifier system according to claim 9, characterized in that, The power amplifier includes a first NMOS transistor, a second NMOS transistor, a first transformer, and a second transformer. The sources of both the first and second NMOS transistors are grounded. The first transformer includes a first main coil and a first secondary coil. One end of the first main coil serves as the input terminal of the power amplifier, and the other end is grounded. One end of the first secondary coil is connected to the gate of the first NMOS transistor and the detection unit, and the other end is connected to the gate of the second NMOS transistor and the detection unit. The center tap of the first secondary coil is connected to the output terminal of the detection current injection unit to receive the detection current. The second transformer includes a second main coil and a second secondary coil. One end of the second main coil is connected to the drain of the first NMOS transistor, and the other end is connected to the drain of the second NMOS transistor. The center tap of the second main coil is connected to the power supply voltage. One end of the second secondary coil serves as the output terminal of the power amplifier, and the other end is grounded.