A module and method for burst light reception detection and indication
By combining voltage divider circuits, comparator selection circuits, and D flip-flops, the problem of inconsistent RESET timing of OLT receivers in PON networks is solved, enabling flexible RxSD signal control to meet the needs of different equipment manufacturers and ensure normal ONU registration and service continuity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ACCELINK TECHNOLOGIES CO LTD
- Filing Date
- 2022-09-07
- Publication Date
- 2026-06-30
AI Technical Summary
Existing technologies cannot simultaneously meet the RESET timing requirements of different equipment manufacturers for OLT receivers in PON networks, resulting in complex circuit designs and inflexible configuration of RxSD trigger thresholds.
A combination of a voltage divider circuit, a comparator selection circuit, and a D flip-flop is used. The voltage divider circuit generates a probe signal, the comparator selection circuit combines with the RESET signal, and the D flip-flop flips to output the RxSD signal according to the RESET signal, thus achieving adaptation to different RESET timings.
It meets the normal operating timing requirements of both protection time and preamble time RESET signals, eliminating the need for customized circuit design and ensuring normal ONU registration and service operation.
Smart Images
Figure CN117713947B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communication technology, and in particular to a module and method for burst light reception detection and indication. Background Technology
[0002] PON (Passive Optical Network) is a point-to-multipoint fiber optic access technology. It uses Broadcast mode for downlink and TDM mode for uplink, supporting single-fiber bidirectional transmission. An Optical Line Terminal (OLT) is a terminal device used to connect to the fiber optic trunk. The OLT and multiple Optical Network Units (ONUs) are connected via an Optical Distribution Network (ODN).
[0003] In PON networks, ONUs operate in burst transmission mode, transmitting optical signals only within authorized time slots. The corresponding OLT receivers operate in burst reception mode. Detecting and monitoring the power of burst optical signals of varying power from different ONUs has always been a technical challenge in the PON field. Received Signal Detection (RxSD) is a crucial technical indicator that affects ONU registration and service delivery. Currently, most major equipment manufacturers require RxSD response times to be below 50ns. However, due to the lack of a unified protocol standard, different manufacturers use different protocols, leading to varying timing requirements for the receiver's reset signal. Some reset signals occur within the guard time of two ONU time slots, while others occur within the ONU preamble time. Circuit design must simultaneously meet the requirements of different manufacturers, posing a significant challenge. Traditional solutions integrate this function through ICs, but these typically only satisfy a specific reset timing scenario, and the RxSD trigger threshold cannot be flexibly configured.
[0004] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention
[0005] The technical problem to be solved by the embodiments of the present invention is that the existing technology cannot simultaneously meet the two RESET timing scenarios.
[0006] In a first aspect, embodiments of the present invention provide a module for burst light reception detection and indication, including a voltage divider circuit, a comparison selection circuit, and a D flip-flop;
[0007] The voltage divider circuit is used to generate a detection signal based on the burst received optical signal;
[0008] The detection signal is input to the first input terminal of the comparison selection circuit, and the second input terminal of the comparison selection circuit is used to receive the RESET signal. When the RESET signal is low and the detection voltage is higher than the decision threshold level, the comparison selection circuit outputs the detection signal; otherwise, it outputs a low level.
[0009] The output of the comparison selection circuit is connected to the clock input of the D flip-flop to trigger the RxSD signal;
[0010] The RESET signal is also toggled to the reset input of the D flip-flop, so that when the RESET signal is high, it controls the D flip-flop to reset, causing the RxSD signal output by the D flip-flop to be low. Simultaneously, when the RESET signal is high, it controls the comparator selection circuit to make the input of the D flip-flop low, and after the RESET signal returns to low, the input of the D flip-flop becomes a rising edge in the presence of light, causing the RxSD signal output by the D flip-flop to become high.
[0011] Preferably, the voltage divider circuit includes a photodiode, a current mirror circuit, and a voltage divider resistor;
[0012] The photodiode detects the intensity of the burst received optical signal and generates a received photocurrent. The received photocurrent generates a mirror current through the mirror current source circuit, and the mirror current generates the detection signal through the voltage divider resistor.
[0013] Preferably, the comparison selection circuit includes an analog selection switch and a comparator;
[0014] The detection signal is input to the first input terminal of the analog selection switch, and the RESET signal is input to the selection terminal of the analog selection switch;
[0015] The output of the analog selection switch is connected to the non-inverting input of the comparator, and the decision threshold level is input from the inverting input of the comparator.
[0016] When the RESET signal is low, the analog selection switch outputs a probe signal, which is compared with a decision threshold level by a comparator. If the probe signal is higher than the decision threshold level, the comparator outputs the probe signal; otherwise, the comparator outputs a low level.
[0017] When the RESET signal is high, the analog selection switch outputs a low level, and the comparator outputs a low level.
[0018] Preferably, the comparator is a hysteresis comparator to prevent the RxSD signal from unstable flipping when the detection signal fluctuates at the decision threshold level.
[0019] Preferably, the module further includes a NOR gate;
[0020] The RESET signal is input to the first input terminal of the NOR gate;
[0021] The RxSD_CLR signal is input to the second input terminal of the NOR gate. The RxSD_CLR signal is used to initialize the D flip-flop. After initialization, the RxSD_CLR signal is low, causing the RESET signal to be toggled through the NOR gate and input to the clear terminal of the D flip-flop.
[0022] Preferably, the delay of the D flip-flop is less than or equal to 10 ns.
[0023] Preferably, when the RESET signal goes high within the protection time, the D flip-flop is cleared, the RxSD signal goes low, and the RxSD signal remains low until the next time the light is present, at which point the RxSD signal goes high.
[0024] Preferably, when the RESET signal is high during the preamble time, the D flip-flop is cleared, the RxSD signal is converted to low, and after the RESET signal returns to low, the RxSD signal is converted to high due to the presence of light.
[0025] Preferably, the module further includes a controller, wherein the decision threshold level is provided by the controller and output from the DA output terminal of the controller.
[0026] In a second aspect, the present invention also provides a method for burst light reception detection and indication, the method being applied to the module described in the first aspect, the method comprising:
[0027] The voltage divider circuit generates a detection signal based on the burst received optical signal and inputs the detection signal to the comparison and selection circuit;
[0028] The comparison selection circuit receives the probe signal and the RESET signal, and selectively outputs the probe signal or a low level according to the probe signal and the RESET signal; wherein, when the RESET signal is low and the probe voltage is higher than the decision threshold level, the comparison selection circuit outputs the probe signal; otherwise, the comparison selection circuit outputs a low level.
[0029] The D flip-flop receives the output signal of the comparator selection circuit and the RESET signal after inversion, and outputs the RxSD signal according to the output signal of the comparator selection circuit; wherein, when the RESET signal is high, the RxSD signal output by the D flip-flop is low, and when the RESET signal returns to low and the output signal of the comparator selection circuit has a rising edge, the RxSD signal output by the D flip-flop is converted to high.
[0030] Compared with the prior art, the beneficial effects of the embodiments of the present invention are as follows: the present invention can meet the timing requirements of the two RESET signals, namely protection time and preamble time, to ensure the normal registration of ONU and the normal operation of services, so that equipment manufacturers with different timing requirements do not need to customize the circuit design, saving manpower and resources. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 This is a schematic diagram of the architecture of a burst light receiving detection and indication module provided in an embodiment of the present invention;
[0033] Figure 2 This is a circuit diagram of a voltage divider circuit in a burst light receiving detection and indication module provided in an embodiment of the present invention;
[0034] Figure 3 This is a circuit diagram of the comparison selection circuit in a burst light reception detection and indication module provided in an embodiment of the present invention;
[0035] Figure 4 This is a schematic diagram of the architecture of a burst light receiving detection and indication module provided in an embodiment of the present invention;
[0036] Figure 5 This is a circuit diagram of a burst light receiving detection and indication module provided in an embodiment of the present invention;
[0037] Figure 6 This is a schematic diagram of the signals in a burst light reception detection and indication module provided in an embodiment of the present invention;
[0038] Figure 7 This is a schematic diagram of the signals in a burst light reception detection and indication module provided in an embodiment of the present invention;
[0039] Figure 8 This is a table of requirements for various delay parameters in a burst light reception detection and indication module provided in an embodiment of the present invention;
[0040] Figure 9 This is a schematic diagram of the architecture of a burst light receiving detection and indication module provided in an embodiment of the present invention;
[0041] Figure 10 This is a schematic diagram of the comparison selection circuit architecture in a burst light reception detection and indication module provided in an embodiment of the present invention;
[0042] Figure 11 This is a circuit diagram of a burst light receiving detection and indication module provided in an embodiment of the present invention;
[0043] Figure 12 This is a flowchart illustrating a method for burst light reception detection and indication provided in an embodiment of the present invention. Detailed Implementation
[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0045] In the description of this invention, the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and do not require that this invention must be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.
[0046] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0047] To make the objectives of this invention clearer, the operational requirements under two timing conditions in the prior art are explained, specifically including: Since multiple ONU devices are typically connected to an OLT device, and different ONU devices emit light in different time slots, there is a Tg protection time to prevent collisions between different time slots. Simultaneously, because the power of the light received by the OLT device from different ONU devices is different, the decision level of the optical signal from different ONU devices at the optical module receiver of the OLT device is different. Therefore, a RESET signal is needed between the receiving intervals of two ONUs to quickly discharge the decision level and establish a new decision level. The high level of the RESET signal may arrive during the protection time or the preamble time. The function of the RxSD signal is for the OLT optical module to indicate the received signal status of the ONU to the receiver. When the RxSD signal is high, it indicates that the optical signal from this ONU device has been received. After the reception of an optical packet is completed, RxSD needs to remain high until the next high level of RESET to clear it and switch it to a low level.
[0048] Example 1:
[0049] Embodiment 1 of the present invention provides a module for burst light reception detection and indication, such as... Figure 1 As shown, it includes a voltage divider circuit, a comparator selection circuit, and a D flip-flop.
[0050] The voltage divider circuit is used to generate a detection signal based on the burst received optical signal.
[0051] The detection signal is input to the first input terminal of the comparison selection circuit, and the second input terminal of the comparison selection circuit is used to receive the RESET signal. When the RESET signal is low and the detection voltage is higher than the decision threshold level, the comparison selection circuit outputs the detection signal; otherwise, it outputs a low level.
[0052] The output of the comparison selection circuit is connected to the clock input of the D flip-flop to trigger the RxSD signal.
[0053] The RESET signal is also toggled to the reset input of the D flip-flop, so that when the RESET signal is high, it controls the D flip-flop to reset, causing the RxSD signal output by the D flip-flop to be low. Simultaneously, when the RESET signal is high, it controls the comparator selection circuit to make the input of the D flip-flop low, and after the RESET signal returns to low, the input of the D flip-flop becomes a rising edge in the presence of light, causing the RxSD signal output by the D flip-flop to become high.
[0054] Specifically, when the reset input of the D flip-flop is low, the D flip-flop is reset to zero, restoring the output signal (RxSD signal) to a low level. When a rising edge occurs at the clock input of the D flip-flop, the D flip-flop converts the output signal to a high level.
[0055] The flip-flop input is specifically defined as follows: when the RESET signal is low, the reset input of the D flip-flop is high; conversely, when the RESET signal is high, the reset input of the D flip-flop is low. This can be achieved using an NOT gate, or by inputting the RESET signal to the first input of a NOR gate and inputting a continuous low level to the second input of the NOR gate.
[0056] The decision threshold level is obtained by those skilled in the art based on the analysis of the intensity of the detection signal.
[0057] The arrival position of the high level of the RESET signal is set by the equipment manufacturer. Its arrival position may be within the protection time of the arrival time slot of two optical packets, or within the lead time of the arrival of one optical packet.
[0058] When the RESET signal goes high within the protection time, the D flip-flop is cleared, the RxSD signal goes low, and the RxSD signal remains low until the next time the light is present, at which point the RxSD signal goes high.
[0059] When the RESET signal is high during the preamble time, the D flip-flop is cleared, the RxSD signal is converted to low, and after the RESET signal returns to low, the RxSD signal is converted to high due to the presence of light.
[0060] This embodiment, on the one hand, inputs the RESET signal to the reset input of the D flip-flop, enabling the RxSD signal to be reset to zero according to the RESET signal. Simultaneously, by inputting the RESET signal to the comparator selection circuit, the clock input of the D flip-flop is switched to a low level when the RxSD signal is reset. This ensures that after the RESET signal returns to a low level, the D flip-flop can output the RxSD signal as high based on the presence of light, thus meeting operational requirements. This embodiment requires no special control over the RESET signal or circuitry. It can switch the RxSD signal to a low level at any time when the RESET signal is high, and after the RESET signal returns to a low level, it receives optical packets and switches the RxSD signal back to high based on the presence of light. This satisfies the timing requirements for both protection time and preamble time RESET signals to operate normally, ensuring normal ONU registration and service operation.
[0061] As a specific implementation method of the voltage divider circuit in the above embodiments, such as Figure 2 As shown, the voltage divider circuit includes a photodiode, a current mirror circuit, and a voltage divider resistor.
[0062] The photodiode detects the intensity of the burst received optical signal and generates a received photocurrent. The received photocurrent generates a mirror current through the mirror current source circuit, and the mirror current generates the detection signal through the voltage divider resistor.
[0063] The photodiode is an avalanche photodiode. Figure 2 The diagram also illustrates a impedance-transfer amplifier for signal detection of the received photocurrent of an avalanche photodiode. The received photocurrent generated by the photodiode is used to generate a mirror current with a preset ratio via a mirror current source. This preset ratio is derived by those skilled in the art based on the requirements of burst light reception and is implemented through the design of the mirror current source circuit. Figure 2 As shown, the received photocurrent generated by the photodiode is Iapd, and the mirror current generated by the mirror current source is Iapd / 10. This mirror current flows through the voltage divider resistor, so that a voltage signal is output from the high voltage end of the voltage divider resistor as a detection signal.
[0064] This embodiment also provides a specific implementation method for a comparison selection circuit, such as... Figure 3 As shown, the comparison selection circuit includes an analog selection switch and a comparator.
[0065] The detection signal is input to the first input terminal of the analog selection switch, and the RESET signal is input to the selection terminal of the analog selection switch.
[0066] The output of the analog selection switch is connected to the non-inverting input of the comparator, and the decision threshold level is input from the inverting input of the comparator.
[0067] When the RESET signal is low, the analog selection switch outputs a probe signal, which is compared with a decision threshold level by a comparator. If the probe signal is higher than the decision threshold level, the comparator outputs the probe signal; otherwise, the comparator outputs a low level.
[0068] When the RESET signal is high, the analog selection switch outputs a low level, and the comparator outputs a low level.
[0069] Among them, as the most direct implementation method, the analog selection switch is a two-to-one analog selection switch.
[0070] The most common method for inputting a low level to the second input terminal of the two-to-one analog selector switch is to ground the second input terminal of the two-to-one analog selector switch.
[0071] In practical applications, during system startup, the RxSD signal needs to be set to a low level to prevent it from being initialized high, which could affect the normal reception of burst light. Based on the above embodiments, the following preferred implementation methods also exist, specifically, such as... Figure 4 As shown:
[0072] The module also includes a NOR gate; the RESET signal is input to the first input terminal of the NOR gate.
[0073] The RxSD_CLR signal is input to the second input terminal of the NOR gate. The RxSD_CLR signal is used to initialize the D flip-flop. After initialization, the RxSD_CLR signal is low, causing the RESET signal to be toggled through the NOR gate and input to the clear terminal of the D flip-flop.
[0074] In conjunction with the above preferred embodiments, this embodiment provides the following: Figure 5 The complete device circuit diagram shown below will be explained in detail below. Figure 5 As an example, the working principle of this solution will be explained in detail.
[0075] like Figure 6 As shown, when the current timing is within the protection time Tg and the RESET signal is low, the analog selection switch outputs a detection signal. Since there is no light during the current protection time, the detection signal is lower than the decision threshold level, and the comparator outputs a low level, that is, the clock input of the D flip-flop is low. At the same time, the reset input of the D flip-flop is high, and the output RxSD signal of the D flip-flop remains unchanged.
[0076] When the RESET signal goes high within the protection time Tg, the reset input of the D flip-flop goes low, resetting the D flip-flop and causing the RxSD signal to go low. Simultaneously, when the RESET signal is high, the analog selection switch outputs a low level, which, after passing through a comparator, is input to the clock input of the D flip-flop, meaning the clock input of the D flip-flop is low.
[0077] When the RESET signal returns to a low level, the analog selection switch outputs a detection signal. Since the current state is still without light, the detection signal is lower than the decision threshold level, and the comparator outputs a low level, that is, the clock input of the D flip-flop is low. At the same time, the reset input of the D flip-flop is high, and the output RxSD signal of the D flip-flop remains low.
[0078] Until the preamble time is reached, the RESET signal is low, and the analog selection switch outputs a probe signal. Since the preamble time is in a light-enabled state, the probe signal is higher than the decision threshold level, and the comparator outputs a high level. That is, the clock input of the D flip-flop changes from low to high, resulting in a rising edge. This causes the D flip-flop output RxSD signal to change to high, so that when the high level of the RESET signal arrives during the protection time, the RxSD signal responds quickly.
[0079] The above describes a scenario where the high level of the RESET signal arrives within the protection time. Figure 7 The image shows the scenario where the high level of the RESET signal arrives during the preamble time.
[0080] During the protection period, the RESET signal is low, and the analog selection switch outputs a detection signal. Since there is no light during the protection period, the detection signal is lower than the decision threshold level, and the comparator outputs a low level, that is, the clock input of the D flip-flop is low. At the same time, the reset input of the D flip-flop is high, and the output RxSD signal of the D flip-flop remains unchanged.
[0081] When the preamble time begins and the RESET signal has not yet transitioned to a high level, the analog selection switch outputs a probe signal. Since the preamble time is in a light-enabled state, the probe signal is higher than the decision threshold level. The comparator outputs a probe signal, that is, the clock input of the D flip-flop transitions from a low level to a high level, resulting in a rising edge. At the same time, the reset input of the D flip-flop is high, and the output RxSD signal of the D flip-flop transitions from a low level to a high level.
[0082] When the high level of the RESET signal arrives during the lead time, the reset input of the D flip-flop becomes low, resetting the D flip-flop and causing the RxSD signal to go low. Simultaneously, the analog selection switch outputs a low level, which, after passing through a comparator, is input to the clock input of the D flip-flop, making the clock input of the D flip-flop low as well.
[0083] When the RESET signal returns to a low level, the analog selection switch outputs a probe signal. Since the preamble time is in an illuminated state, the probe signal is higher than the decision threshold level. The comparator outputs a probe signal, meaning the clock input of the D flip-flop changes from low to high, resulting in a rising edge. Simultaneously, the reset input of the D flip-flop is high, and the D flip-flop output RxSD signal changes from low to high. This ensures that the RxSD signal responds quickly when the high level of the RESET signal arrives during the preamble time.
[0084] in, Figure 6 and Figure 7The Electrical output shown is the output electrical signal of the burst reception optical module. When the RESET signal goes high, the output electrical signal is cleared, and after the RESET signal returns to low, it responds to changes in the probe signal. Tg is the protection time, which is the time slot between two ONU optical packets when the probe signal is low. Ta is the response time of the RxSD signal, Tsettle is the burst reception setup time, and Tr is the reset time (active high). After Tg ends, a preamble time occurs, which is when the next ONU optical packet begins to be received.
[0085] Burst reception of light is typically used in PON networks. Because PON networks use a TDM uplink architecture, guard time and preamble time consume additional network bandwidth. Therefore, the protocol requires these times to be extremely short. Figure 6 and Figure 7 The time requirements for Tr, Ta, and Tsettle shown are all extremely short, generally on the order of nanoseconds. Figure 8 The diagram shows the requirements of an OLT system equipment manufacturer for the above three parameters. Therefore, to meet such stringent timing requirements, in conjunction with the above embodiments, a preferred implementation method is also provided, specifically including:
[0086] The delay of the D flip-flop is less than or equal to 10 ns.
[0087] Furthermore, the devices used in the module are low-latency devices, with each device having a latency of less than or equal to 10ns.
[0088] To prevent the RxSD signal from repeatedly flipping due to its proximity to the decision threshold level, the comparator is a hysteresis comparator, which avoids unstable flipping of the RxSD signal when the detection signal fluctuates between high and low levels of the decision threshold.
[0089] The hysteresis range of the hysteresis comparator is set by those skilled in the art based on the needs of burst light reception.
[0090] In the above embodiments, in order to enable more flexible configuration of the decision threshold level, the following preferred implementation methods also exist, such as... Figure 9 As shown:
[0091] The module also includes a controller, the decision threshold level is provided by the controller and output from the DA output terminal of the controller.
[0092] The RxSD_CLR signal can also be provided by the controller, so that it outputs a high level during system initialization and then continuously outputs a low level thereafter.
[0093] It should be noted that each device in this embodiment should have a corresponding power supply, which is the basis for the operation of the device and is well known to those skilled in the art. For the sake of clearly illustrating the technical solution of the present invention, it has been omitted in the drawings and text description. Furthermore, the corresponding devices are referred to as logic circuits in the drawings, and their internal structure and functional implementation are all prior art and should not be used as a reason for not understanding the solution of the present invention.
[0094] In this embodiment, the limiting terms such as "first input terminal" and "second input terminal" do not refer to specific ports of a single device, but are determined according to the device to which they belong. For example, a first device may have two input ports, which are respectively called the first input terminal and the second input terminal of the first device. When a second device has two input ports, they are respectively called the first input terminal and the second input terminal of the second device. The terminology is based on the common terminology of those skilled in the art and is not ambiguous. Furthermore, the first input terminal and the second input terminal in the same device do not refer to a specific order. They are merely used to separate the corresponding limited objects from the same category and to facilitate the description of two or more different objects in the same category. They should not be interpreted as having a further limiting meaning.
[0095] Example 2:
[0096] Based on the same concept as Embodiment 1, this embodiment also provides another specific implementation of the comparison selection circuit in Embodiment 1, such as... Figure 10 As shown, it specifically includes:
[0097] The comparison selection circuit includes an analog selection switch and a comparator.
[0098] The detection signal is input to the non-inverting input of the comparator, and the decision threshold level is input from the inverting input of the comparator.
[0099] The output of the comparator is connected to the first input terminal of the analog selection switch, and the RESET signal is input to the selection terminal of the analog selection switch.
[0100] The detection signal is compared with the decision threshold level by a comparator. When the detection signal is higher than the decision threshold level, the comparator outputs the detection signal; otherwise, the comparator outputs a low level. The signal is then passed through the analog selection switch. When the RESET signal is low, the analog selection switch outputs the input signal at the first input terminal, i.e., the detection signal or a low level; otherwise, the analog selection switch outputs a low level.
[0101] The overall circuit diagram consisting of the above comparison and selection circuit and the preferred embodiments in Example 1 is as follows: Figure 11As shown. Its specific workflow is based on the same concept as that of Example 1, and will not be repeated here.
[0102] Example 3:
[0103] After providing the burst light reception detection and indication modules described in Embodiments 1 and 2, this invention will further provide a burst light reception detection and indication method. This is to elaborate on the implementation methods of the corresponding structural functions in Embodiments 1 and 2, and to further analyze their design principles in detail. It should be noted that the module structures in Embodiments 1 and 2 are applicable to this Embodiment 3, and their structures will not be described again in this embodiment.
[0104] The method is applied to the module of Embodiment 1 or Embodiment 2, and the method is as follows: Figure 12 As shown, it includes:
[0105] In step 201, the voltage divider circuit generates a detection signal based on the burst received optical signal and inputs the detection signal to the comparison selection circuit;
[0106] In step 202, the comparison selection circuit receives the probe signal and the RESET signal, and selectively outputs the probe signal or a low level according to the probe signal and the RESET signal; wherein, when the RESET signal is low and the probe voltage is higher than the decision threshold level, the comparison selection circuit outputs the probe signal; otherwise, the comparison selection circuit outputs a low level.
[0107] In step 203, the D flip-flop receives the output signal of the comparator selection circuit and the RESET signal with the inverted input, and outputs the RxSD signal according to the output signal of the comparator selection circuit; wherein, when the RESET signal is high, the RxSD signal output by the D flip-flop is low, and when the RESET signal returns to low and the output signal of the comparator selection circuit has a rising edge, the RxSD signal output by the D flip-flop is converted to high.
[0108] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A module for burst light reception detection and indication, characterized by This includes a voltage divider circuit, a comparator selection circuit, and a D flip-flop; The voltage divider circuit is used to generate a detection signal based on the burst received optical signal; The detection signal is input to the first input terminal of the comparison selection circuit, and the second input terminal of the comparison selection circuit is used to receive the RESET signal. When the RESET signal is low and the detection signal is higher than the decision threshold level, the comparison selection circuit outputs the detection signal; otherwise, it outputs a low level. The output of the comparison selection circuit is connected to the clock input of the D flip-flop to trigger the RxSD signal; The RESET signal is also toggled to the reset input of the D flip-flop. When the RESET signal is high, it controls the D flip-flop to reset, so that the RxSD signal output by the D flip-flop is low. Simultaneously, when the RESET signal is high, it controls the comparator selection circuit to make the input of the D flip-flop low. After the RESET signal returns to low, the input of the D flip-flop is converted to a rising edge in the presence of light, so that the RxSD signal output by the D flip-flop is converted to a high level.
2. The module for burst light reception detection and indication according to claim 1, wherein, The voltage divider circuit includes a photodiode, a current mirror circuit, and a voltage divider resistor; The photodiode detects the intensity of the burst received optical signal and generates a received photocurrent. The received photocurrent generates a mirror current through the mirror current source circuit, and the mirror current generates the detection signal through the voltage divider resistor.
3. The burst light reception detection and indication module of claim 1, wherein, The comparison selection circuit includes an analog selection switch and a comparator; The detection signal is input to the first input terminal of the analog selection switch, and the RESET signal is input to the selection terminal of the analog selection switch; The output of the analog selection switch is connected to the non-inverting input of the comparator, and the decision threshold level is input from the inverting input of the comparator. When the RESET signal is low, the analog selection switch outputs a probe signal, which is compared with a decision threshold level by a comparator. If the probe signal is higher than the decision threshold level, the comparator outputs the probe signal; otherwise, the comparator outputs a low level. When the RESET signal is high, the analog selection switch outputs a low level, and the comparator outputs a low level.
4. The module for burst light reception detection and indication according to claim 3, wherein, The comparator is a hysteresis comparator to prevent the RxSD signal from fluctuating unstablely when the detection signal fluctuates at the decision threshold level.
5. The burst light reception detection and indication module of claim 1, wherein, The module also includes NOR gates; The RESET signal is input to the first input terminal of the NOR gate; The RxSD_CLR signal is input to the second input terminal of the NOR gate. The RxSD_CLR signal is used to initialize the D flip-flop. After initialization, the RxSD_CLR signal is low, causing the RESET signal to be toggled through the NOR gate and input to the clear terminal of the D flip-flop.
6. The burst optical reception detection and indication module of claim 1, wherein, The delay of the D flip-flop is less than or equal to 10 ns.
7. The burst optical reception detection and indication module of claim 1, wherein, When the RESET signal goes high within the protection time, the D flip-flop is cleared, the RxSD signal goes low, and the RxSD signal remains low until the next time the light is present, at which point the RxSD signal goes high.
8. The burst optical reception detection and indication module of claim 1, wherein, When the RESET signal is high during the preamble time, the D flip-flop is cleared, the RxSD signal is converted to low, and after the RESET signal returns to low, the RxSD signal is converted to high due to the presence of light.
9. The burst optical reception detection and indication module of claim 1, wherein, The module also includes a controller, the decision threshold level is provided by the controller and output from the DA output terminal of the controller.
10. A method for burst light reception detection and indication, characterized in that, The method is applied to the module as described in any one of claims 1 to 9, and the method includes: The voltage divider circuit generates a detection signal based on the burst received optical signal and inputs the detection signal to the comparison and selection circuit; The comparison selection circuit receives the probe signal and the RESET signal, and selectively outputs the probe signal or a low level according to the probe signal and the RESET signal; wherein, when the RESET signal is low and the probe signal is higher than the decision threshold level, the comparison selection circuit outputs the probe signal; otherwise, the comparison selection circuit outputs a low level. The D flip-flop receives the output signal of the comparator selection circuit and the RESET signal after inversion, and outputs the RxSD signal according to the output signal of the comparator selection circuit; wherein, when the RESET signal is high, the RxSD signal output by the D flip-flop is low, and when the RESET signal returns to low and the output signal of the comparator selection circuit has a rising edge, the RxSD signal output by the D flip-flop is converted to high.