ILV fault test circuit and test method based on row and column scanning

Abstract

An ILV fault test circuit and test method based on row and column scanning relates to the field of integrated circuit testing and testability design. The present invention is intended to solve the problem that most existing fault test methods for ILVs have large circuit area occupation, while methods with small circuit area occupation cannot locate the fault. In the present invention, the test signal input end of the input shift register serves as the test signal input end of the ILV fault test circuit, and the test signal output ends of the input shift register correspond one-to-one with the daisy chain, and each test signal output end of the input shift register is connected to the test signal input end of its corresponding daisy chain; the test signal output end of the output shift register serves as the test signal output end of the ILV fault test circuit, and the test signal input ends of the output shift register correspond one-to-one with the daisy chain, and each test signal input end of the output shift register is connected to the test signal output end of its corresponding daisy chain.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit testing and testability design. Background Art

[0002] With the advancement of integrated circuit technology, transistor feature sizes have continued to shrink, approaching their physical limits. To continue Moore's Law, monolithic 3-D integrated circuits (M3D ICs) are becoming the future trend in integrated circuits by fabricating multiple, vertically isolated active layers. This allows for circuit integration and functional diversity far exceeding traditional planar ICs, making them a key development trend. In M3D ICs, nanoscale inter-layer vias (ILVs) serve as vertical signal pathways between different active layers. Ensuring their effectiveness and reliability is crucial for ensuring the optimal performance of M3D ICs. However, the high-density integration design and oxide isolation layer thinning process make ILVs highly susceptible to failure. Therefore, it is necessary to perform real-time fault detection and localization of newly added ILVs during the M3D IC production process. ILV fault detection can identify defects in newly added ILVs, thereby ensuring the yield of M3D ICs. ILV fault localization can provide manufacturers with the location of defective ILVs for design optimization.

[0003] Currently, there are three main fault testing methods for ILVs:

[0004] One approach is to use boundary scan circuits based on the IEEE P1838 standard to test ILVs for faults. Although this method is mature, it incurs significant circuit area overhead due to the high density and large number of ILVs (up to 100 million per mm2).

[0005] The second approach is to add a dedicated test layer to test ILVs for faults. Although this method reduces testing costs to a certain extent, the dedicated test layer can only cover fault testing of the upper and lower layers of ILVs, resulting in a huge circuit area overhead and difficulty in scaling to multiple layers.

[0006] The third method involves fault testing of ILVs using built-in self-test circuits. This method significantly reduces the test circuit footprint through specialized circuitry and effectively covers common ILV faults. However, its main drawback is that it can only determine the presence of a fault, but cannot pinpoint its location. Summary of the Invention

[0007] The present invention aims to solve the problem that most of the existing fault testing methods for ILVs occupy a large circuit area, while methods with a small circuit area cannot locate the fault. An ILV fault testing circuit and testing method based on row and column scanning are now provided.

[0008] The ILV fault test circuit based on row and column scanning, in an M×N ILV array under test, the ILVs in each row are connected end to end through row tri-state drivers to form a row daisy chain, and the ILVs in each column are connected end to end through column tri-state drivers to form a column daisy chain, with a total of M+N daisy chains;

[0009] The ILV fault test circuit includes: an input shift register and an output shift register;

[0010] The test signal input end of the input shift register serves as the test signal input end of the ILV fault test circuit. The input shift register includes M+N test signal output ends, and the M+N test signal output ends correspond one-to-one to M+N daisy chains respectively. Each test signal output end of the input shift register is connected to the test signal input end of its corresponding daisy chain.

[0011] The test signal output end of the output shift register serves as the test signal output end of the ILV fault test circuit. The output shift register includes M+N test signal input ends, which correspond one-to-one to M+N daisy chains respectively. Each test signal input end of the output shift register is connected to the test signal output end of its corresponding daisy chain.

[0012] Furthermore, the input shift register includes M+N number 1 D flip-flops;

[0013] All No. 1 D flip-flops are connected in sequence to form an input signal transmission chain, the No. 1 D flip-flop input terminal located at the input end of the input signal transmission chain serves as the test signal input terminal of the input shift register, and the output terminal of each No. 1 D flip-flop serves as a test signal output terminal of the input shift register.

[0014] Furthermore, the clock signal input terminals of all the aforementioned number one D flip-flops are commonly connected to form a clock signal input terminal of the input shift register.

[0015] Furthermore, the output shift register includes M+N second D flip-flops and M+N-1 dual-way selectors arranged alternately, such that there is a dual-way selector between each of two adjacent second D flip-flops;

[0016] One signal input terminal of each dual-way selector serves as a test signal input terminal of the output shift register, the other signal input terminal of each dual-way selector is connected to the output terminal of the adjacent second D flip-flop, and the signal output terminal of each dual-way selector is connected to the input terminal of the adjacent second D flip-flop;

[0017] An output terminal of the second D flip-flop located at the end and having a free output terminal serves as a test signal output terminal of the output shift register, and another input terminal of the second D flip-flop located at the end serves as a test signal input terminal of the output shift register.

[0018] Furthermore, the clock signal input terminals of all the second D flip-flops are connected together to form the clock signal input terminal of the output shift register.

[0019] Furthermore, the test signal input end of each of the daisy chains is connected to the test signal output end of its corresponding input shift register via a test ILV channel;

[0020] The test signal output end of each daisy chain is connected to the test signal input end of its corresponding output shift register through a test ILV channel.

[0021] The ILV fault test method implemented based on the above-mentioned row-column scanning-based ILV fault test circuit is as follows:

[0022] When all row tri-state drivers are turned on and all column tri-state drivers are turned off, a test signal is input to all row daisy chains, and the test signal output from each row daisy chain is collected. The difference in the test signal levels between the input and output of the same row daisy chain is compared to implement row testing of the ILV array under test.

[0023] When all row tri-state drivers are turned off and all column tri-state drivers are turned on, a test signal is input to all column daisy chains, and the test signal output from each column daisy chain is collected. The difference in the test signal levels between the input and output of the same column daisy chain is compared to implement column testing of the ILV array under test.

[0024] When there is a fault in the tested ILV array, the ILV at the intersection of the faulty row and the faulty column is the faulty ILV.

[0025] Furthermore, the test signal includes two different digital signals 1 and 0, and the test signals input into two adjacent rows or columns are different.

[0026] Furthermore, the above row test and column test are performed in the same manner, as follows:

[0027] When the test signals input and output of a daisy chain are the same, the daisy chain is fault-free;

[0028] When the input test signal of a daisy chain is 1 and the output test signal is 0, the daisy chain has an open circuit or Stack-at 0 fault;

[0029] When the input test signal of a daisy chain is 0 and the output test signal is 1, the daisy chain has a Stack-at 1 fault;

[0030] When the input test signals of two adjacent daisy chains are 10 or 01 and the output test signals are both 00, a short circuit fault exists between the two adjacent daisy chains.

[0031] Furthermore, the dual-way selector includes an output capture mode and an output shift mode;

[0032] Adjust the dual-way selector to be in output capture mode so that each daisy chain latches the test signal into the corresponding No. 2 D flip-flop;

[0033] The dual selector is adjusted to be in an output shift mode so that the test signal latched by each second D flip-flop is output from the output shift register.

[0034] The present invention has the following advantages:

[0035] 1. It can effectively detect four common ILV faults: open circuit, short circuit, Stack-at 0, and Stack-at 1, and can locate the above faults.

[0036] 2. It can be applied to the testing of newly added ILVs and can be extended to M3D ICs of any layer.

[0037] 3. It has a fast test speed. For a 4-layer M3D IC with 30,000 ILVs, it only takes 3.012ms to complete all tests.

[0038] 4. Compared with the currently known ILV fault testing methods, it has the smallest test area overhead. For 4-layer M3D ICs with 30,000 ILVs, its test circuit area overhead is 4.919μm 2 / ILV. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is the ILV test schematic;

[0040] Figure 2 To test the circuit diagram;

[0041] Figure 3 Schematic diagram of the test structure of multi-layer M3D ICs;

[0042] Figure 4This is the test flow chart of ILV;

[0043] Figure 5 This is the test result timing diagram when the test vector is 10101010;

[0044] Figure 6 This is the timing diagram of the test results when the test vector is 01010101. DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other in the absence of conflict.

[0046] Specific implementation method 1: refer to Figures 1 to 3 This embodiment will be described in detail.

[0047] like Figure 1 The diagram shows a 4×4 ILV array under test. To detect faults in all ILVs in the array, the ILVs in each row are connected end-to-end in a row daisy chain using row tri-state drivers. The ILVs in each column are connected end-to-end in a column daisy chain using column tri-state drivers, for a total of eight daisy chains. Daisy chaining is a wiring scheme that does not form a mesh topology. Only adjacent devices can communicate directly, as the last device does not connect to the first. This wiring method can be used to transmit power, digital signals, and analog signals.

[0048] The column tri-state driver is controlled by the enable signal En1. When En1 = "1", the column tri-state driver is turned on, and when En1 = "0", the column tri-state driver is turned off. The row tri-state driver is controlled by the enable signal En2. When En2 = "1", the row tri-state driver is turned on, and when En2 = "0", the row tri-state driver is turned off. By controlling En1 and En2, the circuit can be placed in three different states:

[0049] 1. Normal working state: At this time, En1 = "0" and En2 = "0", all column three-state drivers and row three-state drivers are turned off, so that the ILVs are isolated from each other. The ILVs are used as vertical signal paths between upper and lower layers.

[0050] 2. Row test state: At this time, En1 = "0" and En2 = "1", all column three-state drivers are turned off, and all row three-state drivers are turned on, so that the ILV is isolated in the column direction and connected end to end in the row direction.

[0051] 3. Column test state: At this time, En1 = "1" and En2 = "0", all column three-state drivers are turned on, and all row three-state drivers are turned off, so that the ILV is isolated in the row direction and connected end to end in the column direction.

[0052] like Figure 2 As shown, the ILV fault test circuit based on row and column scanning described in this embodiment includes: an input shift register and an output shift register.

[0053] The input shift register consists of eight D-type flip-flops (number 1). The test signal outputs and test signal inputs of the eight number 1 D-type flip-flops are connected in sequence, forming an input signal transmission chain. TDI is the input shift register's test signal input port, connected to the unused number 1 D-type flip-flop. The test signal outputs of the eight number 1 D-type flip-flops are connected to the test signal inputs of the eight daisy-chains. CLK1 is the input shift register's clock signal input port, connected to the clock signal inputs of the eight number 1 D-type flip-flops. Assuming the test vector "10101010" is input to TDI, after eight CLK1 clock cycles, the test vector will shift to the end of the input shift register, causing the four row daisy-chain inputs to lock to "1," "0," "1," "0," and the four column daisy-chain inputs to lock to "1," "0," "1," "0," respectively.

[0054] The output shift register includes eight alternating D-type flip-flops and seven dual-way selectors, so that there is a dual-way selector between two adjacent D-type flip-flops. Each dual-way selector corresponds to the D-type flip-flop adjacent to its output end, and the eight D-type flip-flops correspond one-to-one to eight daisy chains. The signal output end of the dual-way selector is connected to the test signal input end of its corresponding D-type flip-flop, one test signal input end of the dual-way selector is connected to the test signal output end of its adjacent D-type flip-flop, and the other test signal input end of the dual-way selector is connected to the daisy chain output end corresponding to the corresponding D-type flip-flop. TDO is the test signal output port of the output shift register, which is connected to the D-type flip-flop with an idle test signal output end. CLK2 is the clock signal input port of the output shift register, which is connected to the clock signal input ends of the eight D-type flip-flops.

[0055] Switch is the mode select port of the dual selector, which is connected to the mode select ports of the seven dual selectors. The dual selector has two operating modes: output capture mode and output shift mode. When Switch = "0", it is in output capture mode. In this case, the output of each daisy chain is connected to the corresponding second D flip-flop through the multiplexer. Under the action of the eight clock signals CLK2, the test signal output by each daisy chain will be latched in the corresponding second D flip-flop. When Switch = "1", it is in output shift mode. In this case, the second D flip-flops that have latched the daisy chain output test signals are connected through the multiplexer to form an output shift register. Under the action of the eight clock signals CLK2, the latched test signals are sequentially shifted out of the TDO port.

[0056] The working principle of this embodiment is as follows:

[0057] When the test signals at the input and output of a daisy chain are the same (i.e., if the input is 1, the output is also 1, or if the input is 0, the output is also 0), then the daisy chain is fault-free.

[0058] If the test signals at the input and output of a daisy chain are different, the daisy chain is faulty. The fault type is determined as follows:

[0059] When the input test signal of a daisy chain is 1 and the output test signal is 0, the daisy chain has an open circuit or Stack-at 0 fault;

[0060] When the input test signal of a daisy chain is 0 and the output test signal is 1, the daisy chain has a Stack-at 1 fault.

[0061] When determining a daisy chain fault between rows or columns, if the input test signals of two adjacent row daisy chains or two adjacent column daisy chains are 10 or 01 and the output test signals are both 00, a short circuit fault exists between the two adjacent daisy chains.

[0062] This method can be used to determine whether a fault occurs in a row, column, or between rows or columns. This allows for both fault detection and fault location. For example, when the daisy chain test input for row 2 is "1," the daisy chain test output for row 2 is "0," indicating an open circuit or Stack-at-0 fault in the ILV in row 2. Simultaneously, if the daisy chain test input for column 3 is "1" and the daisy chain test output for column 3 is "0," the fault is determined to be open circuit or Stack-at-0 in column 3. Combining the row and column test results, it can be determined that the faulty ILV is located at the junction of row 2 and column 3, thus completing fault location.

[0063] Furthermore, in this embodiment, the test signal input end of each daisy chain is connected to the test signal output end of its corresponding input shift register through a test ILV channel; the test signal output end of each daisy chain is connected to the test signal input end of its corresponding output shift register through a test ILV channel.

[0064] The above method is to detect and locate the fault of newly added ILV in multi-layer M3D ICs. Figure 3 The circuit structure shown in Figure 1 is shown in Figure 12. Among them, the input shift register, multiplexer and output shift register are always at the bottom layer. As common test resources, they can provide test vector input, test response capture and test response shift out to the newly added ILV in the top layer through the enable control signal. For example, if Figure 3 Middle layer 4 is the newly added circuit layer. After the integration of layer 4 transistors and interconnects, an ILV is added between layer 4 and layer 3 to create a vertical signal path. These newly added ILVs require fault testing to ensure their effectiveness. First, by enabling control signals, both the ILV between layer 1 and layer 2 and the ILV between layer 2 and layer 3 are isolated from the outside world. At this point, the test vectors from the input shift registers will pass directly through the test ILV channel to the newly added ILV input port between layer 4 and layer 3. The test responses from the newly added ILVs will also be captured and shifted out by the output shift registers through the test ILV channel. To ensure the reliability of the test ILV channel, a triple-module redundant structure can be designed.

[0065] Specific embodiment 2: Based on the ILV fault test circuit based on row and column scanning described in specific embodiment 1, the ILV fault test method is implemented as follows:

[0066] When all row tri-state drivers are turned on and all column tri-state drivers are turned off, a test signal is input to all row daisy chains, and the test signal output from each row daisy chain is collected. The difference in the test signal levels between the input and output of the same row daisy chain is compared to implement row testing of the ILV array under test.

[0067] When all row tri-state drivers are turned off and all column tri-state drivers are turned on, a test signal is input to all column daisy chains, and the test signal output from each column daisy chain is collected. The difference in the test signal levels between the input and output of the same column daisy chain is compared to implement column testing of the ILV array under test.

[0068] When there is a fault in the tested ILV array, the ILV at the intersection of the faulty row and the faulty column is the faulty ILV.

[0069] The test signal includes two different digital signals 1 and 0, and the test signals input into two adjacent rows or columns are different.

[0070] The row test and column test are the same, as follows:

[0071] When the test signals input and output of a daisy chain are the same, the daisy chain is fault-free;

[0072] When the input test signal of a daisy chain is 1 and the output test signal is 0, the daisy chain has an open circuit or Stack-at 0 fault;

[0073] When the input test signal of a daisy chain is 0 and the output test signal is 1, the daisy chain has a Stack-at 1 fault;

[0074] When the input test signals of two adjacent daisy chains are 10 or 01 and the output test signals are both 00, a short circuit fault exists between the two adjacent daisy chains.

[0075] The dual selector includes output capture mode and output shift mode;

[0076] Adjust the dual-way selector to be in output capture mode so that each daisy chain latches the test signal into the corresponding No. 2 D flip-flop;

[0077] The dual selector is adjusted to be in an output shift mode so that the test signal latched by each second D flip-flop is output from the output shift register.

[0078] HSPICE software was used to perform fault test simulation on the first and second embodiments. The specific parameters are as follows:

[0079] Test object: A 4x4 ILV matrix containing an open ILV, where the open ILV is located in the second row and third column.

[0080] Test circuit power supply voltage: 1.1V.

[0081] Input shift register clock frequency: CLK1 = 1GHz.

[0082] Output shift register clock frequency: CLK2 = 1GHz.

[0083] The CMOS model used in the simulation is the 45nm PTM low-power CMOS model.

[0084] Test circuit component selection: NanGate 45nm standard component library.

[0085] The test result timing diagram is as follows Figure 5 and Figure 6 As shown. Figure 5 It can be seen that according to Figure 4As shown in the test process, the first step after the test starts is to shift in the test vector "10101010". After 8 CLK1 cycles, the test vector reaches each test input port through the input shift register. The second step of the test is the ILV row test. By setting the row test enable En2 = "1" while keeping the column test enable En1 = "0", all ILVs are isolated from each other in the column direction and form a daisy chain in the row direction. At this time, the row test input is "1010", the Switch signal is "0", and the output shift register is in the signal capture state. After one CLK2 cycle, the row test response will be latched in the DFF connected to it. The third step of the test is to shift out the row test response. At this time, the Switch signal changes from "0" to "1", causing the output shift register to be in the shift state. In this state, the test response originally latched in each DFF is serially shifted out through the TDO port. According to Figure 2 In the test structure design shown, the row test response will be shifted out first, so after 4 CLK2 cycles, the test response output of "1010" can be observed on the TDO port, which corresponds to the row test input of "1010". The fourth step of the test is the ILV column test. By setting the column test enable En1 = "1" while keeping the row test enable En2 = "0", all ILVs are isolated from each other in the row direction and form a daisy chain in the column direction. At this time, the column test input is "1010", the Switch signal is "0", and the output shift register is in the signal capture state. After one CLK2 cycle, the column test response will be latched in the DFF connected to it. According to Figure 2 In the test structure shown, the column test response begins shifting out after the row test response has fully shifted out. Therefore, after eight CLK2 cycles, a test response output of "XXXX1000" is observed on the TDO port. The following four bits correspond to the column test input of "1010." Based on the above test results, when the third column test input is "1," the test output is "0," indicating an open ILV or Stack-at0 fault in the third column.

[0086] Except that the test vector is changed from "10101010" to "01010101", Figure 6 The test process shown is the same as Figure 5 Completely consistent. For a row test input of "0101," the row test response is "0001." For a column test input of "0101," the column test response is "0101." Based on the above test results, when the second row test input is "1," the test output is "0," indicating an open circuit or Stack-at 0 fault in the ILV of the second row.

[0087] Combining the row and column test results, it can be determined that the ILV with an open circuit or Stack-at 0 fault is located at the intersection of the third column and the second row. This is completely consistent with the fault setting of the experimental object, proving the effectiveness of this method in detecting and locating ILV open circuit or Stack-at 0 faults.

[0088] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the invention. It should be understood that many modifications may be made to the illustrative embodiments, and that other arrangements may be devised, without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that the various dependent claims and features described herein may be combined in ways other than those described in the original claims. It should also be understood that features described in conjunction with individual embodiments may be used in conjunction with other described embodiments.

Claims

1. ILV fault test circuit based on row and column scanning, characterized in that: In an M×N array of ILVs to be tested, the ILVs in each row are connected end-to-end via row tri-state drivers to form a row daisy chain, and the ILVs in each column are connected end-to-end via column tri-state drivers to form a column daisy chain, for a total of M+N daisy chains. The ILV fault test circuit includes: an input shift register and an output shift register; The test signal input end of the input shift register serves as the test signal input end of the ILV fault test circuit. The input shift register includes M+N test signal output ends, and the M+N test signal output ends correspond one-to-one to M+N daisy chains respectively. Each test signal output end of the input shift register is connected to the test signal input end of its corresponding daisy chain. The test signal output end of the output shift register serves as the test signal output end of the ILV fault test circuit. The output shift register includes M+N test signal input ends, which correspond one-to-one to M+N daisy chains respectively. Each test signal input end of the output shift register is connected to the test signal output end of its corresponding daisy chain.

2. The ILV fault test circuit based on row and column scanning according to claim 1, characterized in that: The input shift register includes M+N number 1 D flip-flops; All No. 1 D flip-flops are connected in sequence to form an input signal transmission chain, the No. 1 D flip-flop input terminal located at the input end of the input signal transmission chain serves as the test signal input terminal of the input shift register, and the output terminal of each No. 1 D flip-flop serves as a test signal output terminal of the input shift register.

3. The ILV fault test circuit based on row and column scanning according to claim 2, characterized in that: The clock signal input terminals of all the No. 1 D flip-flops are connected together to form the clock signal input terminal of the input shift register.

4. The ILV fault test circuit based on row and column scanning according to claim 1, 2 or 3, characterized in that: The output shift register includes M+N second D flip-flops and M+N-1 dual-way selectors arranged alternately, so that there is a dual-way selector between each of two adjacent second D flip-flops; One signal input terminal of each dual-way selector serves as a test signal input terminal of the output shift register; The other signal input terminal of each dual-way selector is connected to the output terminal of the adjacent No. 2 D flip-flop, and the signal output terminal of each dual-way selector is connected to the input terminal of the adjacent No. 2 D flip-flop; A second D flip-flop output terminal located at the end and having a free output terminal serves as a test signal output terminal of the output shift register; Another input terminal of the second D flip-flop located at the end serves as a test signal input terminal of the output shift register.

5. The ILV fault testing circuit based on row and column scanning according to claim 4, characterized in that: The clock signal input terminals of all the second D flip-flops are connected together to form the clock signal input terminal of the output shift register.

6. The ILV fault test circuit based on row and column scanning according to claim 1, 2, 3 or 5, characterized in that: The test signal input end of each daisy chain is connected to the test signal output end of its corresponding input shift register through a test ILV channel; The test signal output end of each daisy chain is connected to the test signal input end of its corresponding output shift register through a test ILV channel.

7. An ILV fault testing method implemented by the row-column scanning-based ILV fault testing circuit according to claim 5, characterized in that: The details are as follows: When all row tri-state drivers are turned on and all column tri-state drivers are turned off, a test signal is input to all row daisy chains, and the test signal output from each row daisy chain is collected. The difference in the test signal levels between the input and output of the same row daisy chain is compared to implement row testing of the ILV array under test. When all row tri-state drivers are turned off and all column tri-state drivers are turned on, a test signal is input to all column daisy chains, and the test signal output from each column daisy chain is collected. The difference in the test signal levels between the input and output of the same column daisy chain is compared to implement column testing of the ILV array under test. When there is a fault in the tested ILV array, the ILV at the intersection of the faulty row and the faulty column is the faulty ILV.

8. The ILV fault testing method implemented by the row-column scanning-based ILV fault testing circuit according to claim 7, characterized in that: The test signal includes two different digital signals 1 and 0, and the test signals input into two adjacent rows or columns are different.

9. The ILV fault testing method implemented by the row-column scanning-based ILV fault testing circuit according to claim 8, characterized in that: The row test and column test are the same, as follows: When the test signals input and output of a daisy chain are the same, the daisy chain is fault-free; When the input test signal of a daisy chain is 1 and the output test signal is 0, the daisy chain has an open circuit or Stack-at 0 fault; When the input test signal of a daisy chain is 0 and the output test signal is 1, the daisy chain has a Stack-at 1 fault; When the input test signals of two adjacent daisy chains are 10 or 01 and the output test signals are both 00, a short circuit fault exists between the two adjacent daisy chains.

10. The ILV fault testing method implemented by the ILV fault testing circuit based on row and column scanning according to claim 9, characterized in that: The dual-way selector includes an output capture mode and an output shift mode; Adjust the dual-way selector to be in output capture mode so that each daisy chain latches the test signal into the corresponding No. 2 D flip-flop; The dual selector is adjusted to be in an output shift mode so that the test signal latched by each second D flip-flop is output from the output shift register.

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