Semiconductor structure

Abstract

The disclosed embodiments relate to the field of semiconductors, and provide a semiconductor structure, wherein the semiconductor structure comprises: a substrate; functional transistors and floating transistors arranged alternately, the functional transistor comprising: a functional gate, a first source-drain doping region and a second source-drain doping region, the functional gate being located on the surface of the substrate, the first source-drain doping region and the second source-drain doping region being located on opposite sides of the functional gate, and the floating transistor comprising: a floating gate, a third source-drain doping region and a fourth source-drain doping region, the floating gate being located on the surface of the substrate, the third source-drain doping region and the fourth source-drain doping region being located on opposite sides of the floating gate, and the third source-drain doping region is electrically connected to the second source-drain doping region of the functional transistor on one side of the floating transistor, and the fourth source-drain doping region is electrically connected to the first source-drain doping region of the functional transistor on the other side of the floating transistor, and the floating transistor is a non-functional transistor. The integration of the semiconductor structure can be improved while increasing the current carrying capacity of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the semiconductor field, and in particular to a semiconductor structure. Background Art

[0002] An integrated circuit is a miniature electronic device or component. Using a certain process, the transistors, resistors, capacitors, inductors and other components and wiring required in a circuit are interconnected and made on one or several small semiconductor chips or dielectric substrates, and then packaged in a tube shell to become a miniature structure with the required circuit function; all the components have formed a whole in structure, making electronic components a big step forward in miniaturization, low power consumption, intelligence and high reliability. Summary of the invention

[0003] The embodiments of the present disclosure provide a semiconductor structure, which can at least improve the integration of the semiconductor structure and increase the current carrying capacity of the semiconductor structure.

[0004] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor structure, including: a substrate; functional transistors and floating transistors arranged alternately, the functional transistor including: a functional gate, a first source-drain doping region and a second source-drain doping region, the functional gate is located on the surface of the substrate, the first source-drain doping region and the second source-drain doping region are located on two opposite sides of the functional gate, the floating transistor includes: a floating gate, a third source-drain doping region and a fourth source-drain doping region, the floating gate is located on the surface of the substrate, the third source-drain doping region and the fourth source-drain doping region are located on two opposite sides of the floating gate, and the third source-drain doping region is electrically connected to the second source-drain doping region of the functional transistor on one side of the floating transistor, and the fourth source-drain doping region is electrically connected to the first source-drain doping region of the functional transistor on the other side of the floating transistor, and the floating transistor is a non-functional transistor.

[0005] In some embodiments, the third source-drain doping region and the second source-drain doping region electrically connected to the third source-drain doping region are the same source-drain doping region, and the third source-drain doping region is also electrically connected to the fourth source-drain doping region.

[0006] In some embodiments, the fourth source-drain doping region and the first source-drain doping region electrically connected to the fourth source-drain doping region are the same source-drain doping region, and the fourth source-drain doping region is also electrically connected to the third source-drain doping region.

[0007] In some embodiments, the third source-drain doping region and the fourth source-drain doping region are connected to the same potential, and the floating gate is not connected to a potential or is connected to a specific potential.

[0008] In some embodiments, it also includes: a first metal layer and a second metal layer arranged at intervals, the first metal layer is electrically connected to the second source and drain doping region and the third source and drain doping region, the second metal layer is electrically connected to the first source and drain doping region and the fourth source and drain doping region, and the first metal layer is electrically connected to the second metal layer.

[0009] In some embodiments, it also includes: a plurality of first intermediate layers, the plurality of first intermediate layers are respectively located on the top surfaces of the second source / drain doped region and the third source / drain doped region; a plurality of first conductive vias, the first conductive vias are located between the first intermediate layer and the first metal layer to electrically connect the first intermediate layer with the first metal layer; a plurality of second intermediate layers, the plurality of second intermediate layers are respectively located on the top surfaces of the fourth source / drain doped region and the first source / drain doped region; a plurality of second conductive vias, the second conductive vias are located between the intermediate layer and the second metal layer to electrically connect the second intermediate layer with the second metal layer.

[0010] In some embodiments, the method further includes: a metal wire, one end of the metal wire contacts the first metal layer, and the other end of the metal wire contacts the second metal layer.

[0011] In some embodiments, in the direction in which the functional transistor and the floating transistor are arranged, the width of the floating gate is less than or equal to the width of the functional gate.

[0012] In some embodiments, a plurality of floating transistors are arranged continuously between two functional transistors.

[0013] In some embodiments, only one floating transistor is disposed between a plurality of continuous functional transistors and another plurality of continuous functional transistors.

[0014] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: by arranging the functional transistors and the floating transistors alternately, and electrically connecting the second source-drain doping region of the functional transistor to the third source-drain doping region of the floating transistor, and electrically connecting the fourth source-drain doping region of the same floating transistor to the first source-drain doping region of the functional transistor on the other side, the limit current that the functional transistor can carry toward the first source-drain doping region and / or the second source-drain doping region of the floating transistor can be increased, and at the same time, the integration level of the entire semiconductor structure can be controlled. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 A schematic diagram of the structure of a first transistor provided in an embodiment of the present disclosure;

[0017] Figure 2 A schematic diagram of the structure of a second transistor provided in an embodiment of the present disclosure;

[0018] Figure 3 A schematic diagram of the structure of a third transistor provided in an embodiment of the present disclosure;

[0019] Figure 4 A schematic diagram of a layout of a first semiconductor structure provided in an embodiment of the present disclosure;

[0020] Figure 5 A cross-sectional view of a first semiconductor structure provided in accordance with an embodiment of the present disclosure;

[0021] Figure 6 A schematic diagram of a layout of a second semiconductor structure provided in an embodiment of the present disclosure;

[0022] Figure 7 A cross-sectional view of a second semiconductor structure provided in one embodiment of the present disclosure;

[0023] Figure 8 A schematic diagram of a layout of a third semiconductor structure provided in an embodiment of the present disclosure;

[0024] Fig. 9 A cross-sectional view of a third semiconductor structure provided in an embodiment of the present disclosure;

[0025] Fig.10 A schematic diagram of a layout of a fourth semiconductor structure provided in an embodiment of the present disclosure;

[0026] Fig.11 A cross-sectional view of a fourth semiconductor structure provided in an embodiment of the present disclosure;

[0027] Fig.12 A schematic diagram of a layout of a fifth semiconductor structure provided in an embodiment of the present disclosure;

[0028] Fig.13A cross-sectional view of a fifth semiconductor structure provided according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] refer to Figures 1 to 5 , Figure 1 A schematic diagram of the structure of a first transistor provided in an embodiment of the present disclosure, Figure 2 A schematic diagram of the structure of a second transistor provided in an embodiment of the present disclosure, Figure 3 A schematic diagram of the structure of a third transistor provided in an embodiment of the present disclosure, Figure 4 A schematic diagram of a layout of a semiconductor structure provided by an embodiment of the present disclosure, Figure 5 For along Figure 4 Cross-sectional view along the BB direction.

[0030] It is understandable that both functional transistors and floating transistors can be Figures 1 to 3 A stereoscopic structure of any one of at least three kinds of Figure 1 is a schematic diagram of the structure of a planar transistor. Figure 2 It is a schematic diagram of the structure of a FinFET (FinField-Effect Transistor) transistor. Figure 3 This is a schematic diagram of the structure of a GAA (Gate-All-Around) transistor. Figures 1 to 3 The figure shows a functional transistor as an example. In fact, the structure of the floating transistor may be the same. For the present disclosure, the functional transistor or floating transistor in the semiconductor structure provided by the present disclosure may be any one of the three types of transistors mentioned above. The following is an example of a planar transistor structure.

[0031] Figure 4 and Figure 5 The semiconductor structure shown is a plurality of functional transistors 101 arranged at intervals, and there are gaps between the functional transistors 101 .

[0032] In some embodiments, the semiconductor structure includes: a substrate 100, and the material of the substrate 100 may include a semiconductor material, for example, including but not limited to silicon. In some embodiments, the substrate 100 may include: silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, gallium arsenic phosphide, gallium indium phosphide, gallium in arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide, etc. In some embodiments, the semiconductor substrate 100 may also be a silicon-on-insulator structure.

[0033] In addition, the substrate 100 may be doped according to design requirements (eg, a P-type substrate or an N-type substrate). In some embodiments, the substrate 100 may be doped with P-type doping ions (eg, boron ions, aluminum ions) or N-type doping ions (eg, phosphorus ions, arsenic ions).

[0034] The functional transistor 101 includes a functional gate 111, a first source-drain doping region 121, and a second source-drain doping region 131. The functional gate 111 is used to control the on and off of the channel of the functional transistor 101. The first source-drain doping region 121 and the second source-drain doping region 131 serve as the source and drain of the functional transistor 101, respectively.

[0035] In some embodiments, the functional gate 111 may include a multi-layer structure, for example, may include: a gate dielectric layer, a gate conductive layer and a gate protection layer, wherein the gate dielectric layer is located between the gate conductive layer and the substrate 100, the gate dielectric layer is used to avoid direct contact between the gate conductive layer and the substrate 100, thereby preventing carriers from directly flowing into the gate conductive layer, and the gate protection layer is used to protect the gate conductive layer.

[0036] The semiconductor structure may further include: a first metal layer 102 and a second metal layer 103, wherein the first metal layer 102 may be electrically connected to the second source / drain doping region 131, and the second metal layer 103 may be electrically connected to the first source / drain doping region 121. Electrical signals may be provided to the second source / drain doping region 131 and the first source / drain doping region 121 through the first metal layer 102 and the second metal layer 103, or electrical signals of the second source / drain doping region 131 and the first source / drain doping region 121 may be led out through the first metal layer 102 and the second metal layer 103.

[0037] In some embodiments, the first metal layer 102 and the second metal layer 103 may be a multi-layer stack, and the metal stacks are electrically connected through conductive vias. Taking the first metal layer 102 as an example, the first metal layer 102 may be composed of a multi-layer metal stack, and the metal stacks are electrically connected through conductive vias, and the materials of the multi-layer metals may be different, that is, the first metal layer 102 may be composed of a multi-layer metal stack of different materials.

[0038] The semiconductor structure may also include: a first intermediate layer 104, a first conductive via 105, a second intermediate layer 106 and a second conductive via 107, wherein the first intermediate layer 104 is located on the top surface of the second source-drain doped region 131, the second intermediate layer 106 is located on the top surface of the first source-drain doped region 121, the first conductive via 105 is used to electrically connect the first intermediate layer 104 and the first metal layer 102, and the second conductive via 107 is used to electrically connect the second intermediate layer 106 and the second metal layer 103.

[0039] By providing the first intermediate layer 104 and the second intermediate layer 106, the first metal layer 102 and the second metal layer 103 can be prevented from directly contacting the second source-drain doping region 131 and the first source-drain doping region 121. On the one hand, it can be prevented that the metal ions in the first metal layer 102 and the second metal layer 103 diffuse into the second source-drain doping region 131 and the first source-drain doping region 121, thereby avoiding affecting the performance of the second source-drain doping region 131 and the first source-drain doping region 121. On the other hand, the lattice difference between the second source-drain doping region 131 and the first source-drain doping region 121 and the first intermediate layer 104 and the second intermediate layer 106 can be reduced, thereby reducing the contact resistance.

[0040] In some embodiments, the first metal layer 102 and the first conductive via 105 can be used as a multi-layer stack, for example, a two-layer structure, and the two-layer structure can be a stack of the first intermediate layer 104, the first conductive via 105, the first metal layer 102, the first conductive via 105 and the first metal layer 102 in sequence.

[0041] In some embodiments, the first metal layer 102 and the first conductive via 105 are used as a multi-layer stack, and the materials of different film layers can be different. For example, the materials of the first metal layer 102 of the first layer and the first metal layer 102 of the second layer are different.

[0042] In some embodiments, the materials of the first intermediate layer 104 and the second intermediate layer 106 may be the same, for example, titanium nitride (TiN), tungsten nitride (WN) or titanium silicon nitride (TiSiN), etc. The materials of the first intermediate layer 104 and the second intermediate layer 106 may also be different.

[0043] In some embodiments, the semiconductor structure may further include a pseudo polysilicon structure 108. When semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are scaled down through various technology nodes, device stacking density and device performance are challenged by device layout and isolation. In order to avoid leakage between adjacent devices (cells), a pseudo polysilicon structure 108 is usually formed.

[0044] Each functional transistor 101 corresponds to two pseudo polysilicon structures 108 , and there are gaps between different functional transistors 101 .

[0045] For a semiconductor structure, a plurality of functional transistors 101 arranged at intervals are provided. Although this can provide better electrical performance for the semiconductor structure, the functional transistors 101 arranged at intervals will occupy a larger space, resulting in the inability to improve the integration of the semiconductor structure.

[0046] refer to Figure 6 and Figure 7 , Figure 6A schematic diagram of a layout of a second semiconductor structure provided in an embodiment of the present disclosure, Figure 7 For along Figure 6 Cross-section along the BB direction.

[0047] Figure 6 and Figure 7 The semiconductor structure shown is a plurality of functional transistors 201 with a common source or a common drain.

[0048] It should be noted that the features of the substrate 200, the functional transistor 201, the functional gate 211, the first source-drain doped region 221, the second source-drain doped region 231, the first metal layer 202, the second metal layer 203, the first intermediate layer 204, the first conductive via 205, the second intermediate layer 206 and the second conductive via 207 in the figure correspond one to one with the features of the substrate 100, the functional transistor 101, the functional gate 111, the first source-drain doped region 121, the second source-drain doped region 131, the first metal layer 102, the second metal layer 103, the first intermediate layer 104, the first conductive via 105, the second intermediate layer 106 and the second conductive via 107 in the above-mentioned embodiment. For relevant descriptions, reference can be made to the descriptions in the above-mentioned embodiment. The difference between this embodiment and the above-mentioned embodiment is that the adjacent functional transistors 201 in this embodiment share the second source-drain doped region 231. It can be understood that the adjacent functional transistors in the disclosed embodiment may also share the first source-drain doped region.

[0049] It can be understood that by sharing the second source-drain doping region 231, the occupied area of ​​the semiconductor structure can be greatly reduced, thereby improving the integration of the semiconductor structure. Compared with the above embodiment, taking two functional transistors as an example, the semiconductor structure in the above embodiment includes: four pseudo-polysilicon structures, two functional gates, two first source-drain doping regions and two second source-drain doping regions, while the semiconductor structure in the embodiment of the present disclosure includes: two pseudo-polysilicon structures 207, two functional gates 211, two first source-drain doping regions 221 and one second source-drain doping region 231. It can be understood that the more the number of functional transistors 201, the more space can be saved compared with the previous embodiment.

[0050] However, in a conductor with electricity, the movement of electrons will collide with metal ions, causing the metal ions to shift, which manifests as metal deformation on a macro scale. For nano-thin wires in chips, the net (connecting wires) may be short-circuited or broken over time, causing the chip to fail. The EM (electromigration) phenomenon has a profound impact on the life of the chip, because as long as the chip is in use, the EM phenomenon will occur. The longer it is used, the more EM accumulates, and the metal becomes more and more deformed. If a large number of metal ions are lost in a certain place, the circuit may be broken here; and if a large number of metal ions from other places gather in a certain place, the net here may become wider, and a short circuit will occur when it touches the adjacent wires.

[0051] For the semiconductor structure corresponding to the shared first source-drain doping region 221 or the second source-drain doping region 231, the overcurrent size of the shared first source-drain doping region 221 or the second source-drain doping region 231 is twice the overcurrent size of the unshared first source-drain doping region 221 and the second source-drain doping region 231. Due to the existence of the EM (electromigration effect) phenomenon, in this scenario, the EM of the functional transistor 201 is limited by the size of the current flowing through the shared first source-drain doping region 221 or the second source-drain doping region 231, and the limiting current size of the shared first source-drain doping region 221 or the second source-drain doping region 231 is half of the limiting current size of the unshared first source-drain doping region 221 and the second source-drain doping region 231.

[0052] refer to Figure 8 and Fig. 9 , Figure 8 A schematic diagram of a layout of a third semiconductor structure provided in an embodiment of the present disclosure, Fig. 9 For along Figure 8 Cross-section along the BB direction.

[0053] The semiconductor structure may include: a substrate 300 .

[0054] The semiconductor structure may also include: alternatingly arranged functional transistors 301 and floating transistors 308, the functional transistor 301 including: a functional gate 311, a first source-drain doping region 321 and a second source-drain doping region 331, the functional gate 311 is located on the surface of the substrate 300, the first source-drain doping region 321 and the second source-drain doping region 331 are located on opposite sides of the functional gate 311, the floating transistor 308 includes: a floating gate 318, a third source-drain doping region 328 and a fourth source-drain doping region 338, the floating gate 318 is located on the surface of the substrate 300, the third source-drain doping region 328 and the fourth source-drain doping region 338 are located on opposite sides of the floating gate 318, and the third source-drain doping region 328 is electrically connected to the second source-drain doping region 331 of the functional transistor 301 on one side of the floating transistor 308, and the fourth source-drain doping region 338 is electrically connected to the first source-drain doping region 321 of the functional transistor 301 on the other side of the floating transistor 308, and the floating transistor 308 is a non-functional transistor.

[0055] It can be understood that, compared with the above-mentioned multiple spaced functional transistors 101, the semiconductor structure with alternatingly arranged functional transistors 301 and floating transistors 308 has a higher degree of integration. Compared with the above-mentioned functional transistors 201 with a common source or drain, the semiconductor structure with alternatingly arranged functional transistors 301 and floating transistors 308 has a stronger EM capability. In fact, the EM capability of the semiconductor structure with alternatingly arranged functional transistors 301 and floating transistors 308 can be comparable to the EM capability of the above-mentioned spaced functional transistors 101.

[0056] Specifically, taking the semiconductor structure including two functional transistors 301 as an example, the semiconductor structure in this embodiment includes: two pseudo polysilicon structures 401, two functional gates 311, a floating gate 318, two first source-drain doping regions 321, two second source-drain doping regions 331, a third source-drain doping region 328 and a fourth source-drain doping region 338. Compared with a plurality of functional transistors 101 arranged at intervals, the integration is higher, and compared with the functional transistor 201 with a shared source or drain, the EM capability is also stronger.

[0057] It should be noted that the features of the substrate 300, the functional transistor 301, the functional gate 311, the first source-drain doped region 321, the second source-drain doped region 331, the first metal layer 302, the second metal layer 303, the first intermediate layer 304, the first conductive via 305, the second intermediate layer 306 and the second conductive via 307 in the figure correspond one to one with the features of the substrate 100, the functional transistor 101, the functional gate 111, the first source-drain doped region 121, the second source-drain doped region 131, the first metal layer 102, the second metal layer 103, the first intermediate layer 104, the first conductive via 105, the second intermediate layer 106 and the second conductive via 107 in the above-mentioned embodiments. For related descriptions, please refer to the descriptions in the above-mentioned embodiments and will not be repeated below.

[0058] In some embodiments, the third source-drain doping region 328 and the fourth source-drain doping region 338 are connected to the same potential, and the floating gate is not connected to a potential or is connected to a specific potential. By controlling the third source-drain doping region 328 and the fourth source-drain doping region 338 to be connected to the same potential, it is possible to control the third source-drain doping region 328 and the fourth source-drain doping region 338 to have no current.

[0059] In some embodiments, the semiconductor structure may further include: a first metal layer 302 and a second metal layer 303 arranged at intervals, a first metal layer 302 electrically connected to a second source / drain doping region 331 and a third source / drain doping region 328, a second metal layer 303 electrically connected to a first source / drain doping region 321 and a fourth source / drain doping region 338, a first metal layer 302 electrically connected to a second metal layer 303, the second source / drain doping region 331 and the third source / drain doping region 328 are electrically connected through the first metal layer 302, the first source / drain doping region 321 and the fourth source / drain doping region 338 are electrically connected through the second metal layer 303, and the electrical potential between the second source / drain doping region 331 and the third source / drain doping region 328 can be equalized by electrically connecting the first metal layer 302 and the second metal layer 303, and the electrical potential between the first source / drain doping region 321 and the fourth source / drain doping region 338 can be equalized.

[0060] In some embodiments, a first metal layer 302 can also be electrically connected to a second source / drain doping region 331 or a third source / drain doping region 328, and then the two first metal layers 302 are electrically connected to achieve electrical connection between a second source / drain doping region 331 and a third source / drain doping region 328, and a second metal layer 303 can be electrically connected to a first source / drain doping region 321 or a fourth source / drain doping region 338, and then the two second metal layers 303 are electrically connected to achieve electrical connection between a first source / drain doping region 321 and a fourth source / drain doping region 338.

[0061] In some embodiments, the second source-drain doping region 331 and the third source-drain doping region 328 are in direct contact with each other, and the second source-drain doping region 331 and the third source-drain doping region 328 can be regarded as a common source-drain doping region, and the width of this common source-drain doping region is greater than the width of the single second source-drain doping region 331; in some embodiments, the second source-drain doping region 331 and the third source-drain doping region 328 are in direct contact with each other, and the first metal layer 302 may not be additionally provided.

[0062] In some embodiments, the second source / drain doping region 331 and the third source / drain doping region 328 may also be spaced apart from each other.

[0063] In some embodiments, the doping concentrations of the first source-drain doping region 321, the second source-drain doping region 331, the third source-drain doping region 328, and the fourth source-drain doping region 338 are the same. By setting the doping concentrations of the first source-drain doping region 321, the second source-drain doping region 331, the third source-drain doping region 328, and the fourth source-drain doping region 338 to be the same, the manufacturing process of the entire semiconductor structure can be simplified, and the doping of the first source-drain doping region 321, the second source-drain doping region 331, the third source-drain doping region 328, and the fourth source-drain doping region 338 can be completed in the same process step.

[0064] In some embodiments, it also includes: multiple first intermediate layers 304, the multiple first intermediate layers 304 are respectively located on the top surfaces of the second source and drain doping regions 331 and the third source and drain doping regions 328; multiple first conductive vias 305, the first conductive vias 305 are located between the first intermediate layer 304 and the first metal layer 302 to electrically connect the first intermediate layer 304 with the first metal layer 302; multiple second intermediate layers 306, the multiple second intermediate layers 306 are respectively located on the top surfaces of the fourth source and drain doping regions 338 and the first source and drain doping regions 321; multiple second conductive vias 307, the second conductive vias 307 are located between the second intermediate layer 306 and the second metal layer 303 to electrically connect the second intermediate layer 306 with the second metal layer 303. By providing the first intermediate layer 304 and the second intermediate layer 306, the first metal layer 302 and the second metal layer 303 can be prevented from directly contacting the second source-drain doping region 331 and the first source-drain doping region 321. The first intermediate layer 304 and the first metal layer 302 can be electrically connected through the first conductive via 305, and the second intermediate layer 306 and the second metal layer 303 can be electrically connected through the second conductive via 307.

[0065] In some embodiments, the first intermediate layer 304 and the first conductive via 305 may also be interconnections of other conductive structures. For example, by replacing the first intermediate layer 304 and the first conductive via 305 with a connecting column, it is only necessary to realize that the signals of the second source-drain doping region 331 and the third source-drain doping region 328 can be brought out. Similarly, the second intermediate layer 306 and the second conductive via 307 may also be interconnections of other conductive structures.

[0066] In some embodiments, the semiconductor structure may further include: a metal wire 309, one end of the metal wire 309 contacts the first metal layer 302, and the other end contacts the second metal layer 303. The metal wire 309 can be used to electrically connect the first metal layer 302 and the second metal layer 303, and the metal wire 309 can be used to achieve equal electric potential between the first metal layer 302 and the second metal layer 303.

[0067] In some embodiments, in the direction in which the functional transistor 301 and the floating transistor 308 are arranged, the width of the floating gate 318 is less than or equal to the width of the functional gate 311. It can be understood that the floating transistor 308 is a non-functional transistor, and therefore, setting the width of the floating gate 318 to be less than the width of the functional gate 311 can further increase the integration of the semiconductor structure, and setting the width of the floating gate 318 to be equal to the width of the functional gate 311 can form the floating gate 318 and the functional gate 311 in the same process step, which can simplify the manufacturing method of the entire semiconductor structure, improve the robustness of the process, and enhance the performance of the formed semiconductor structure.

[0068] In some embodiments, the width of the floating gate 318 may not be affected by the width of the functional gate 311 . For example, the width of the floating gate 318 may be greater than the width of the functional gate 311 .

[0069] By providing the floating gate 318 , different functional transistors 301 can be separated, thereby preventing the functional transistors 301 from influencing each other.

[0070] In some embodiments, the alternating arrangement of functional transistors 301 and floating transistors 308 may be: a plurality of continuous floating transistors 308 are arranged between two functional transistors 301. It can be understood that within the same layout area, the larger the spacing between the functional transistors 301, the more sufficient the wiring space of the functional transistors 301. Therefore, by arranging a plurality of continuous floating transistors 308 between two functional transistors 301, the wiring space of the functional transistors 301 can be increased. Secondly, the functional transistor 301 will generate heat when working, while the floating transistor 308 will not work and will not generate heat. Therefore, within the same layout area, the more floating transistors 308 there are, the stronger the heat dissipation capacity of the entire semiconductor structure will be. By arranging a plurality of continuous floating transistors 308 between two functional transistors 301, the heat dissipation capacity of the semiconductor structure can be increased.

[0071] In some embodiments, the alternating arrangement of functional transistors 301 and floating transistors 308 may also be: only one floating transistor 308 is set between a plurality of continuous functional transistors 301 and another plurality of continuous functional transistors 301. For example, the semiconductor structure includes: functional transistors 301, functional transistors 301, floating transistors 308, functional transistors 301 and functional transistors 301 arranged in sequence. By setting only one floating transistor 308 between a plurality of continuous functional transistors 301 and another plurality of continuous functional transistors 301, the integration of the semiconductor structure can be further improved.

[0072] In some embodiments, the EM capability of the first source-drain doping region 321 and the second source-drain doping region 331 in the functional transistor 301 will be affected by the direction of the current. For example, the first source-drain doping region 321 is connected to the working power supply, and the second source-drain doping region 331 is grounded. Then, for the first source-drain doping region 321, the current direction of the first source-drain doping region 321 is from the outside to the inside of the functional transistor, and the current direction of the second source-drain doping region 331 is from the functional transistor 301 to the outside. In this way, the EM capability of the second source-drain doping region 331 will be stronger than the EM capability of the first source-drain doping region 321. For such a transistor, an end with a stronger EM capability can be set to be electrically connected to an end with a stronger EM capability of another functional transistor 301, and an end with a weaker EM capability can be electrically connected to a floating transistor 308 to enhance the EM capability of the end. That is, the semiconductor structure includes: a functional transistor 301, a functional transistor 301, a floating transistor 308, a functional transistor 301 and a functional transistor 301 arranged in sequence. In this way, the EM capability of the entire semiconductor structure can be increased while increasing the integration of the semiconductor structure.

[0073] It should be noted that the above-mentioned EM capability is stronger at the end where the current flows toward the outside of the functional transistor 301 , which is an example. In fact, the EM capability may be stronger at the end where the current flows toward the inside of the functional transistor 301 .

[0074] It should be noted that, in the above description, the plurality of continuous functional transistors 301 are arranged at intervals, so as to avoid mutual influence between the functional transistors 301 .

[0075] refer to Fig.10 and Fig.11 , Fig.10 A schematic diagram of a layout of a fourth semiconductor structure provided in an embodiment of the present disclosure, Fig.11 For along Fig.10 Cross-section along the BB direction.

[0076] In some embodiments, the third source-drain doping region 328 and the second source-drain doping region 331 electrically connected to the third source-drain doping region 328 are the same source-drain doping region, and the third source-drain doping region 328 is also electrically connected to the fourth source-drain doping region 338 .

[0077] It can be understood that by setting the third source-drain doping region 328 and the second source-drain doping region 331 electrically connected to the third source-drain doping region 328 as the same source-drain doping region, that is, setting a source or a drain of the functional transistor 301 to share a source or a drain with the floating transistor, the integration of the semiconductor structure can be further improved, and by setting the third source-drain doping region 328 to be electrically connected to the fourth source-drain doping region 338, the EM capability of the semiconductor structure can be improved.

[0078] In some embodiments, the fourth source-drain doping region 338 and the first source-drain doping region 321 electrically connected to the fourth source-drain doping region 338 are the same source-drain doping region, and the fourth source-drain doping region 338 is also electrically connected to the third source-drain doping region 328, that is, a source or a drain of the functional transistor 301 is set to share a source or a drain with the floating transistor 308, thereby further improving the integration of the semiconductor structure. By setting the fourth source-drain doping region 338 to be electrically connected to the third source-drain doping region 328, the EM capability of the semiconductor structure can be improved.

[0079] It should be noted that other contents can be referred to Figure 8 and Fig. 9 The description of the content will not be repeated below.

[0080] refer to Fig.12 and Fig.13 , Fig.12 A schematic diagram of a layout of a fifth semiconductor structure provided in an embodiment of the present disclosure, Fig.13 For along Fig.12 Cross-section along the BB direction.

[0081] In some embodiments, the third source-drain doping region 328 and the second source-drain doping region 331 electrically connected to the third source-drain doping region 328 are set as the same source-drain doping region, and the fourth source-drain doping region 338 and the first source-drain doping region 321 electrically connected to the fourth source-drain doping region 338 are set as the same source-drain doping region, and the fourth source-drain doping region 338 is also electrically connected to the third source-drain doping region 328. In other words, the third source-drain doping region 328 and the fourth source-drain doping region 338 of the floating transistor 308 share the source or drain with the functional transistors 301 on both sides of the floating transistor 308, respectively, thereby further improving the integration of the semiconductor structure and, at the same time, improving the EM capability of the semiconductor structure.

[0082] In some embodiments, the third source-drain doping region 328 and the second source-drain doping region 331 electrically connected to the third source-drain doping region 328 are the same source-drain doping region, the fourth source-drain doping region 338 and the first source-drain doping region 321 electrically connected to the fourth source-drain doping region 338 are the same source-drain doping region, and only one first metal layer 302 connected to one third source-drain doping region 328 and one second metal layer 303 connected to one fourth source-drain doping region 338 can be set, thereby reducing the setting of the first metal layer 302 and the second metal layer 303.

[0083] It should be noted that other contents can be referred to Figure 8 and Fig. 9 The description of the content will not be repeated below.

[0084] The embodiment of the present disclosure arranges the functional transistors 301 and the floating transistors 308 alternately, and electrically connects the second source-drain doping region 331 of the functional transistor 301 and the third source-drain doping region 328 of the floating transistor 308, and electrically connects the fourth source-drain doping region 338 of the same floating transistor 308 to the first source-drain doping region 321 of the functional transistor 301 on the other side, thereby increasing the limit current that the functional transistor 301 can carry toward the first source-drain doping region 321 and / or the second source-drain doping region 331 of the floating transistor 308, and at the same time, controlling the integration level of the entire semiconductor structure.

[0085] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; Functional transistors and floating transistors are arranged alternately, the functional transistor comprising: a functional gate, a first source-drain doping region and a second source-drain doping region, the functional gate is located on the surface of the substrate, the first source-drain doping region and the second source-drain doping region are located on two opposite sides of the functional gate, the floating transistor comprises: a floating gate, a third source-drain doping region and a fourth source-drain doping region, the floating gate is located on the surface of the substrate, the third source-drain doping region and the fourth source-drain doping region are located on two opposite sides of the floating gate, and the third source-drain doping region is electrically connected to the second source-drain doping region of the functional transistor on one side of the floating transistor, the fourth source-drain doping region is electrically connected to the first source-drain doping region of the functional transistor on the other side of the floating transistor, and the floating transistor is a non-functional transistor; The first source-drain doping region, the second source-drain doping region, the third source-drain doping region and the fourth source-drain doping region have the same doping type; The third source-drain doping region and the fourth source-drain doping region are connected to the same potential, and the floating gate is not connected to a potential or is connected to a specific potential; The third source-drain doping region is used to improve the EM capability of the second source-drain doping region electrically connected to the third source-drain doping region, and the fourth source-drain doping region is used to improve the EM capability of the first source-drain doping region electrically connected to the fourth source-drain doping region.

2. The semiconductor structure according to claim 1, characterized in that: The third source-drain doping region and the second source-drain doping region electrically connected to the third source-drain doping region are the same source-drain doping region, and the third source-drain doping region is also electrically connected to the fourth source-drain doping region.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The fourth source-drain doping region and the first source-drain doping region electrically connected to the fourth source-drain doping region are the same source-drain doping region, and the fourth source-drain doping region is also electrically connected to the third source-drain doping region.

4. The semiconductor structure according to claim 1, characterized in that Also includes: The first metal layer and the second metal layer are arranged at intervals, the first metal layer is electrically connected to the second source-drain doping region and the third source-drain doping region, the second metal layer is electrically connected to the first source-drain doping region and the fourth source-drain doping region, and the first metal layer is electrically connected to the second metal layer.

5. The semiconductor structure according to claim 4, characterized in that: Also includes: A plurality of first intermediate layers, wherein the plurality of first intermediate layers are respectively located on top surfaces of the second source / drain doping region and the third source / drain doping region; a plurality of first conductive vias, wherein the first conductive vias are located between the first intermediate layer and the first metal layer to electrically connect the first intermediate layer to the first metal layer; A plurality of second intermediate layers, wherein the plurality of second intermediate layers are respectively located on top surfaces of the fourth source-drain doping region and the first source-drain doping region; A plurality of second conductive vias are provided, wherein the second conductive vias are located between the second intermediate layer and the second metal layer to electrically connect the second intermediate layer and the second metal layer.

6. The semiconductor structure according to claim 4, characterized in that: Also includes: A metal wire, one end of the metal wire is in contact with the first metal layer, and the other end of the metal wire is in contact with the second metal layer.

7. The semiconductor structure according to claim 1, characterized in that: In the direction in which the functional transistor and the floating transistor are arranged, the width of the floating gate is less than or equal to the width of the functional gate.

8. The semiconductor structure according to claim 1, characterized in that: A plurality of continuously arranged floating transistors are included between the two functional transistors.

9. The semiconductor structure according to claim 1, characterized in that: Only one floating transistor is arranged between a plurality of continuous functional transistors and another plurality of continuous functional transistors.

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