Package substrate structure and method of manufacturing the same

Abstract

The present application provides a packaging substrate structure and a manufacturing method thereof. The method includes forming a contact pad on a first carrier plate; attaching a conductive bump on an exposed portion of the first carrier plate; forming a substrate including a dielectric layer, a circuit layer, a first via and a second via on the first carrier plate; forming a connection member including an insulating layer and a third via on the substrate; removing the conductive bump and exposing a narrow end of the second via; and disposing a die on the second via. The narrow end of the second via is exposed by the conductive bump, and the die is connected to the narrow end of the second via, so as to reduce the pitch of the connection ends.

Description

Technical Field

[0001] This invention relates to a packaging substrate structure and its manufacturing method, and more particularly to a packaging substrate structure for stacked packaging and its manufacturing method. Background Technology

[0002] In recent years, the development of electronic devices has been rapid, and the demand for miniaturization, high input / output (I / O) density, and reliability in electronic packaging technology has continued to increase. Among these technologies, package-on-package (POP) is an effective means of saving circuit board space. For example, POP packages the memory and processor into separate integrated circuits (ICs), with solder balls or conductive pillars connected to the bottom or top of the two ICs, and then the processor is stacked on top of the memory. Summary of the Invention

[0003] One aspect of the present invention is to provide a method for manufacturing a package substrate structure, thereby simultaneously fabricating a first via and a second via.

[0004] Another aspect of the present invention is to provide a packaging substrate structure, which is obtained by the method described above.

[0005] According to one aspect of the present invention, a method for manufacturing a package substrate structure is provided. The method includes providing a first carrier plate and a metal layer, wherein the metal layer is disposed on a surface of the first carrier plate; patterning the metal layer to form pads and partially exposing the first carrier plate; attaching conductive blocks to the exposed portions of the first carrier plate; forming a substrate on the first carrier plate; removing the first carrier plate to expose the conductive blocks and pads in a dielectric layer; forming a connecting substrate on the surface of the dielectric layer; removing a portion of the insulating layer in the connecting substrate, leaving only the insulating layer around a second via, to form a plurality of connecting members and expose the conductive blocks; removing the conductive blocks to form grooves in the dielectric layer and expose the narrow ends of the second vias; and disposing at least one wafer on a conductive blind via. The substrate includes a dielectric layer laminated to the surface of the first carrier plate, and the dielectric layer covering the conductive blocks and pads; a circuit layer formed on the surface of the dielectric layer away from the pads; a plurality of first vias electrically connecting the circuit layer and the pads; and second vias electrically connecting the conductive blocks and the circuit layer. The connection substrate includes an insulating layer covering the conductive block and the pad; and a plurality of third vias penetrating the insulating layer and exposed on the top surface of the insulating layer, wherein the third vias are electrically connected to the pad.

[0006] According to one embodiment of the present invention, prior to the removal of the first carrier plate, the method further includes forming a solder resist layer on the substrate.

[0007] According to one embodiment of the present invention, after removing the first carrier plate as described above, the method further includes forming a second carrier plate on the solder resist layer relative to the conductive block.

[0008] According to one embodiment of the present invention, after applying the conductive block, the method further includes applying an adhesive layer on the conductive block, wherein the second via is formed on the adhesive layer, and the step of removing the conductive block further includes removing the adhesive layer.

[0009] According to one embodiment of the invention, after removing a portion of the insulating layer and before removing the conductive block, the dielectric layer is further thinned to form at least one protrusion on the surface of the dielectric layer away from the circuit layer.

[0010] According to one embodiment of the present invention, prior to bonding the wafer, the method further includes forming an underfill layer in the groove and on the second via.

[0011] According to one aspect of the present invention, a packaging substrate structure is provided, comprising a circuit substrate, a plurality of pads, and a plurality of connecting members disposed on the pads. The circuit substrate includes a dielectric layer, a circuit layer, a first via disposed in the dielectric layer, and a second via disposed in the dielectric layer. A first surface of the dielectric layer includes at least one protrusion. The circuit layer is disposed on a second surface of the dielectric layer, wherein the second surface is opposite to the first surface. The second via has a trapezoidal cross-sectional shape and a narrow end, the narrow end protruding from the first surface of the dielectric layer. Pads are disposed on the protrusion. Each connecting member includes at least one third via and an insulating layer covering the third via. The third via is electrically connected to the pad, and the outermost third via is exposed on the top surface of the insulating layer.

[0012] According to one embodiment of the present invention, the pad is electrically connected to the circuit layer via the first via.

[0013] According to an embodiment of the present invention, the above-described packaging substrate structure further includes a bottom filler layer disposed on the narrow end of the second via.

[0014] According to one embodiment of the present invention, the cross-sectional shape of each of the first vias is trapezoidal, and the width of the first via decreases along the direction from the second surface of the dielectric layer toward the first surface.

[0015] According to one embodiment of the present invention, each of the third through holes has a trapezoidal cross-sectional shape, and the width of the third through hole decreases along the top surface of the insulating layer toward the pad.

[0016] According to an embodiment of the present invention, the above-described packaging substrate structure further includes at least one wafer or at least one semiconductor element bonded to the second via.

[0017] By applying the packaging substrate structure and manufacturing method of the present invention, multiple connecting members are formed on the circuit substrate, and a second via with uniform height is formed by using conductive blocks. The chip is connected by the narrow end of the second via, thereby reducing the spacing between the connecting ends of the packaging substrate. Attached Figure Description

[0018] A better understanding of the present invention will be obtained by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, as is standard practice in the industry, many features are not drawn to scale. In fact, for clarity of discussion, the dimensions of many features may be arbitrarily scaled.

[0019] Figure 1 A cross-sectional view of a packaging substrate structure according to some embodiments of the present invention is shown.

[0020] Figures 2A to 2M A cross-sectional view is shown at an intermediate stage of the manufacturing process of a packaging substrate structure according to some embodiments of the present invention. Detailed Implementation

[0021] This invention provides numerous different embodiments or illustrations to implement various features of the invention. The specific examples of components and configurations described below are for the purpose of simplifying the invention. These are, of course, merely illustrative and are not intended to be limiting. For example, a description of a first feature formed on or above a second feature includes embodiments where the first and second features are in direct contact, as well as embodiments where other features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, the invention repeats element symbols and / or letters in various specific examples. This repetition is for the purpose of simplifying and clarifying the description and does not imply a relationship between the various discussed embodiments and / or configurations.

[0022] Furthermore, spatially relative terms, such as "below," "below," "lower," "above," and "upper," are used to facilitate the description of the relationship between a part or feature depicted in the accompanying drawings and other parts or features. In addition to the directions depicted in the drawings, spatially relative terms also include different orientations of the elements during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used in this invention can also be interpreted in this way.

[0023] As electronic devices become increasingly functional, the interconnect density within package structures continues to rise. In this context, increasing the number of interconnects by reducing the size of solder balls or copper pillars in a stacked package is limited by material and process constraints. Therefore, the number of interconnects restricts improvements in the performance of stacked packages.

[0024] Existing Package-on-Package (POP) technology requires solder balls to ensure the spacing between the package substrate and the chip in order to connect the upper and lower packages. However, to increase the density and number of chip connectors, the size of the solder balls must be reduced; otherwise, the aforementioned spacing cannot be met simultaneously. Another existing approach involves etching and electroplating copper pillars or filling conductive paste in dry film or sealant to connect the substrates. However, due to the process characteristics of electroplating and filling conductive paste, the chip connectors are limited by the aspect ratio, making it difficult to increase the spacing of the connectors disposed on the sealant surface.

[0025] Another existing stacked packaging technology uses through-mold vias (TMV), which uses laser drilling to create through-holes and then fills the through-holes with conductive material. However, the molding material is a composite material of organic and inorganic components, resulting in high costs for manufacturing through-holes and limitations on the aperture ratio. Therefore, this invention provides a packaging substrate structure and its manufacturing method to achieve the aforementioned high line density and to meet specific packaging stack-up heights.

[0026] Please see Figure 1This illustration depicts a cross-sectional view of a package substrate structure 100 according to some embodiments of the present invention. The package substrate structure 100 includes a circuit substrate 101, which includes a solder resist layer 110 and a dielectric layer 120 on the solder resist layer 110. In some embodiments, the top surface 120T of the dielectric layer 120 has at least one protrusion 121 extending above the top surface 120T. The circuit substrate 101 also includes a plurality of circuit layers 132 on the bottom surface 120B of the dielectric layer 120. In some embodiments, the circuit layers 132 may also be selectively disposed in the dielectric layer 120. In some embodiments, the circuit substrate 101 may be a multilayer circuit board.

[0027] The circuit board 101 also includes a plurality of first vias 131, first vias 162, and second vias 130. For example... Figure 1 As illustrated, some of the second vias 130 are stacked with the first vias 131, i.e., three vias (one second via 130 and two first vias 131) are stacked on top of each other, but the number of stacks is not limited; and some of the second vias 130 may not be stacked with the first vias 131. Some of the first vias 162 are not below the second vias 130. In some embodiments, the cross-sectional shapes of the first vias 131, the first vias 162, and the second vias 130 are all trapezoidal, and the widths of the first vias 131, the first vias 162, and the second vias 130 gradually decrease along the direction from the bottom surface 120B to the top surface 120T of the dielectric layer 120. Furthermore, the narrow end portion (i.e., the smaller width end portion) 130A of the second via 130 protrudes from the dielectric layer 120 and is exposed in the groove (not shown) of the dielectric layer 120. In some embodiments, the first via 131, the first via 162, and the second via 130 can be fabricated simultaneously using plasma etching or laser ablation.

[0028] Furthermore, in some embodiments, the solder mask layer 110 may have an opening 115 below the first via 131 to expose solder pads or solder pads (not shown) in the wiring layer 132. The solder pads would cover the first via 131.

[0029] In addition, in this embodiment, the packaging substrate structure 100 also includes a plurality of pads 161 disposed on the protrusions 121 of the dielectric layer 120. In other words, the pads 161 are above the top surface 120T of the dielectric layer 120. In some embodiments, the pads 161 are electrically connected to the circuit layer 132 via a first via 131.

[0030] The packaging substrate structure 100 also includes a plurality of connecting members 171 disposed on the pad 161. Each connecting member 171 includes at least one third via 164 and an insulating layer 170 covering the third via 164. The third via 164 is electrically connected to the pad 161. In some embodiments, the cross-sectional shape of the third via 164 is trapezoidal, and the width of the third via 164 decreases along the top surface 170T of the insulating layer 170 toward the pad 161. In other words, both the first via 162 and the third via 164 are connected to the pad 161 with their narrow ends (i.e., the smaller width end portions). It should be noted that... Figure 1 The uppermost third via 164 is illustrated to include a gasket 164A, but in other embodiments, the uppermost third via 164 may not have a gasket 164A.

[0031] The insulating layer 170 covers the third via 164 to protect it and contribute to the stability of the connection member 171. In some embodiments, the insulating layer 170 is made of the same material as the dielectric layer 120. In other embodiments, since no wiring is provided in the insulating layer 170, a lower-cost insulating material can be used.

[0032] In some embodiments, each connecting member 171 may include only one third via 164 or may include multiple stacked third vias 164. In the aforementioned embodiment with only one third via 164, the third via 164 is exposed on the top surface 170T of the insulating layer 170; in the embodiment with multiple stacked third vias 164, the outermost or furthest third via 164 from the pad 161 is exposed on the top surface 170T of the insulating layer 170. The number of stacked third vias 164 of the connecting member 171 can be adjusted according to application requirements. The connecting member 171 can replace existing solder balls or copper pillars to connect another package (e.g., another package substrate structure 100) to form a package substrate structure for stacked packaging. Therefore, using the connecting member 171 of the present invention can help improve the circuit density of the substrate.

[0033] In some embodiments, an underfill layer 140 is disposed in a recess (not shown) in the dielectric layer 120. In other words, the bottom surface of the underfill layer 140 is lower than the top surface 120T of the dielectric layer 120. The narrow end portion 130A of the second via 130 is connected to the underfill layer 140. The package substrate structure 100 includes at least one wafer (or at least one semiconductor element) 150, and the wafer 150 is disposed on the underfill layer 140 and the narrow end portion 130A of the second via 130. In some embodiments, a solder ball 142 is further included between the narrow end portion 130A of the second via 130 and the wafer 150 to electrically connect the wafer 150 and the second via 130. The present invention utilizes the narrow end portion 130A of the second via 130 as the connection end of the wafer, which is beneficial to reduce the spacing of the connection ends and thereby increase the density of the connection lines. Furthermore, the narrow end portion 130A of the second via 130 protruding from the dielectric layer 120 can effectively improve the reliability of interconnection with the chip 150.

[0034] Please see Figures 2A to 2M This illustration depicts a cross-sectional view during an intermediate stage of the manufacturing process of a package substrate structure 200 according to some embodiments of the present invention. First, please refer to... Figure 2A A first support plate 201 and a metal layer 203 on the first support plate 201 are provided. In some embodiments, the first support plate 201 comprises a resin material or other suitable material. In some embodiments, the metal layer 203 comprises copper.

[0035] Please see Figure 2B Patterned Figure 2A A metal layer 203 is formed to expose a portion of the first carrier plate 201 and to form pads 261. Furthermore, conductive blocks 205 are attached to the exposed portion of the first carrier plate 201. In some embodiments, the conductive blocks 205 may be attached between the pads 261. In some embodiments, after attaching the conductive blocks 205, an adhesive layer 207 may be formed on the conductive blocks 205.

[0036] Please see Figure 2C A substrate is formed on a first carrier plate 201 using a build-up process. The substrate includes a dielectric layer 220A, a first via 262A, a second via 230A, and a circuit layer 232. Specifically, the dielectric layer 220A and a metal layer 213 are first formed on the first carrier plate 201, a pad 261, a conductive block 205, and an adhesive layer 207, with the metal layer 213 on top of the dielectric layer 220A. In some embodiments, the metal layer 213 comprises the same material as the metal layer 203 (or the pad 261). Next, a laser drilling operation 10 is performed to form a first opening O1 and a second opening O2.

[0037] The direction shown in the laser drilling operation 10 can be the direction of laser beam travel. The first opening O1 extends downward from the top 213T of the metal layer 213 to expose the pad 261, while the second opening O2 extends downward from the top 213T of the metal layer 213 to expose the conductive block 205. Due to the direction of the laser drilling operation 10, the first opening O1 and the second opening O2 are formed with a trapezoidal cross-sectional shape, and their width decreases along the direction from the pad 261 to the first support plate 201.

[0038] Please see Figure 2D In the first opening O1 and the second opening O2 (refer to) Figure 2C A conductive material (e.g., copper) is deposited and filled on the dielectric layer 220A to form a first via 262A and a second via 230A, respectively. The first via 262A and the second via 230A, formed by conformal deposition, also have a trapezoidal cross-section with a width decreasing along the direction from the pad 261 to the first carrier plate 201. Next, a metal layer 213 (see reference 201) is patterned on the dielectric layer 220A. Figure 2C This partially removes the metal layer 213, thereby exposing the top surface 220A of the dielectric layer 220A. T Then, the circuit layer 232 is formed on the first via 262A and the top surface 220A exposed by the dielectric layer 220A. T Above. In some embodiments, the second via 230A is electrically connected to the conductive block 205 and the circuit layer 232.

[0039] Please see Figure 2E ,repeat Figure 2C and Figure 2D The steps (i.e., layer building method) are used to form a first via 262B stacked on the first via 262A, and to form a first via 230 on the second via 230A. It should be noted that the dielectric layer 220B includes the dielectric layer 220A and a portion of the dielectric layer formed on the dielectric layer 220A. Figure 2E The illustration shows only two first vias 262B formed on the second vias 230A at both ends, without forming first vias 262B on the two second vias 230A in the middle; however, the invention is not limited thereto. In other words, depending on the subsequent application or structural configuration, the first vias 262B may not be formed on the second vias 230A, or more or fewer first vias 262B may be formed on the second vias 230A. Similarly, a circuit layer 232 is formed on the top surface of the dielectric layer 220B.

[0040] Please see Figure 2F ,repeat Figure 2C and Figure 2D The step (i.e., the layering method) is used to form the first via 262C stacked on top of the first via 262B. It should be noted that, as... Figure 2FAs shown, only the first via 262C is formed, and the first via is not formed on the second via 230A. However, in some other embodiments, the first via may continue to be formed and stacked on the second via 230A (see reference). Figure 2E On. Similar to Figure 2E The dielectric layer 220 includes a dielectric layer 220B and a portion of the dielectric layer formed on the dielectric layer 220B. Similarly, a circuit layer 232 is formed on the top surface of the dielectric layer 220. In the following description, the first vias 262A, 262B, and 262C may be collectively referred to as the first via 262. It should be understood that in some embodiments, the circuit layer 232 may be formed only on the dielectric layer 220, and not within the dielectric layer 220 (i.e., not on dielectric layers 220A and 220B).

[0041] Please see Figure 2G A solder resist layer 210 is formed on the dielectric layer 220 and covers the circuit layer 232. The solder resist layer 210 is mainly used to protect the circuit layer 232 on the circuit board. In some embodiments, the solder resist layer 210 contains ink or other suitable insulating material.

[0042] It should be noted that, in order to increase output and reduce production time, Figures 2A to 2G The steps can be selectively performed simultaneously on both the upper and lower sides of the first support plate 201, thus forming a symmetrical structure on both sides. Then, the upper and lower structures are separated, and subsequent processes are performed separately for each.

[0043] Please see Figure 2H The first carrier plate 201 is removed to expose the conductive block 205 and pad 261 in the dielectric layer 220. Next, a second carrier plate 280 is formed on the solder mask layer 210 relative to the conductive block 205. In other words, the second carrier plate 280 does not cover the conductive block 205. It should be understood that... Figure 2H The structure is to Figure 2G The structure is flipped upside down, therefore... Figure 2H The lower solder mask layer 210 is Figure 2G The topmost solder mask layer 210. In some embodiments, the second carrier plate 280 contains the same material as the first carrier plate 201.

[0044] Next, a connecting substrate 271 is formed (see reference). Figure 2J On dielectric layer 220 and conductive block 205. Specifically, first, please refer to Figure 2IAn insulating layer 270 is formed on the dielectric layer 220 and the conductive block 205. In some embodiments, the insulating layer 270 and the dielectric layer 220 comprise different materials. Next, a laser drilling operation 20 is performed to form an opening O3 in the insulating layer 270, such that the opening O3 extends downward from the top of the insulating layer 270 to expose the pad 261. The direction indicated by the laser drilling operation 20 may be the direction of travel of the laser beam. Due to the direction of the laser drilling operation 20, the width of the opening O3 decreases along the direction from the insulating layer 270 to the dielectric layer 220, that is, the opening O3 has a trapezoidal cross-sectional shape.

[0045] Conductive material is filled into opening O3 to form a third via 264 on pad 261. Then, the process is repeated... Figure 2I After the steps, please refer to Figure 2J A third via 264 is formed on the pad 261, and is connected to the first via 262 through the pad 261. The third via 264 has the same shape as the opening O3, so the width of the third via 264 also decreases along the direction from the insulating layer 270 to the dielectric layer 220. Therefore, the narrow end of the third via 264 (i.e., the part with the smallest width) and the narrow end of the first via 262 are connected to the pad 261 from the top and bottom, respectively.

[0046] Please see Figure 2K A portion of the insulating layer 270 is removed, leaving only the portion of the insulating layer 270 around the third via 264, to form the connecting member 273. Simultaneously, the dielectric layer 220 is thinned so that it has a protrusion 221 on its surface relative to the solder mask layer 210, and the protrusion 221 is higher than the rest of the dielectric layer 220. In some embodiments, the side surfaces of the conductive block 205 may be exposed during the thinning of the dielectric layer 220. In other words, the top surface of the conductive block 205 is made higher than the top surface of the remaining dielectric layer 220. In some embodiments, the removal of the insulating layer 270 may be performed using plasma etching or laser etching. In some embodiments, the top portion of the third via 264 is exposed to the top surface of the remaining insulating layer 270.

[0047] It should be noted that, Figure 2K The illustrated third via 264 has a gasket, but in other embodiments, the third via may not have a gasket. In other words, the gasket of the third via 264 may be removed or retained during the removal of the insulating layer 270.

[0048] Depending on the application, the above process can be repeated. Figure 2I and Figure 2JThe layer-addition process involves fabricating different stack numbers of third vias 264 according to actual needs. If there are more than one stack of third vias 264, the removal of the insulating layer 270 and the thinning of the dielectric layer 220 can be performed after all the third vias 264 are completed.

[0049] Please see Figure 2L Remove conductive block 205 and adhesive layer 207 (see reference). Figure 2K A groove R1 is formed to expose the narrow end portion 230A1 of the second via 230A. In some embodiments, the material of the conductive block 205 is different from the material of the second via 230A to avoid damaging the narrow end portion 230A1 of the second via 230A during the etching process to remove the conductive block 205, thus affecting subsequent applications. In some embodiments, the height of each narrow end portion 230A1 of the second via 230A exposed in the groove R1 is the same.

[0050] Please see Figure 2M A bottom filler layer 240 is formed in the groove R1 (refer to...) Figure 2K It is bonded to the narrow end portion 230A1 of the second through hole 230A (refer to...) Figure 2K On the substrate 200. In some embodiments, solder balls (not shown) may be selectively disposed in the bottom filler layer 240 and electrically connected to the narrow end portion 230A1 of the second via 230A. Next, a wafer 250 is bonded onto the bottom filler layer 240 to form the package substrate structure 200. In some embodiments, the second carrier plate 280 may be selectively removed, and an opening 215 is formed at the bottom of the exposed solder resist layer 210 and directly below the first via 262 to expose the solder pads (not shown).

[0051] As described above, the present invention provides a packaging substrate structure and a method for manufacturing the same, which can simultaneously fabricate stacked first vias, second vias, and third vias to form connection components, thereby increasing the circuit density in the substrate. Furthermore, using the narrow end of the second via as a connection pad for the chip can help reduce the spacing and improve the reliability of interconnection with the chip. Additionally, covering the stacked third via with an insulating layer enhances the stability of the connection components.

[0052] Although the present invention has been disclosed above with reference to several embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0053] [Symbol Explanation]

[0054] 10,20: Laser drilling operation

[0055] 100: Packaging substrate structure

[0056] 101: Circuit board

[0057] 110: Solder mask layer

[0058] 115: Opening

[0059] 120: Dielectric layer

[0060] 120B: Bottom surface

[0061] 120T: Top surface

[0062] 121: Protrusion

[0063] 130: Second via

[0064] 130A: Narrow end section

[0065] 131: First through hole

[0066] 132: Line Layer

[0067] 140: Bottom filler layer

[0068] 142: Tin Ball

[0069] 150: Chip

[0070] 161: Connecting pad

[0071] 162: First through hole

[0072] 164: Third via

[0073] 164A: Pad

[0074] 170: Insulation layer

[0075] 170T: Top Surface

[0076] 171: Connecting components

[0077] 200: Packaging substrate structure

[0078] 201: First load-bearing plate

[0079] 203: Metal layer

[0080] 205: Conductive block

[0081] 207: Adhesive layer

[0082] 210: Solder resist layer

[0083] 213: Metal layer

[0084] 213T: Top

[0085] 215: Opening

[0086] 220, 220A, 220B: Dielectric layer

[0087] 220A T Top surface

[0088] 221: Protrusion

[0089] 230: First through hole

[0090] 230A: Second via

[0091] 230A1: Narrow end section

[0092] 232: Line Layer

[0093] 240: Bottom filler layer

[0094] 250: Chip

[0095] 261: Connecting pad

[0096] 262, 262A, 262B, 262C: First through-hole

[0097] 264: Third via

[0098] 270: Insulation layer

[0099] 271: Connecting substrate

[0100] 273: Connecting components

[0101] 280: Second bearing plate

[0102] O1: First opening

[0103] O2: Second opening

[0104] O3: Opening

[0105] R1: Groove.

Claims

1. A method for manufacturing a packaging substrate structure, characterized in that, Include: A first support plate and a metal layer are provided, wherein the metal layer is disposed on the surface of the first support plate; The metal layer is patterned to form at least one pad and partially expose the first carrier plate; The conductive block is attached to the exposed portion of the first carrier plate; A substrate is formed on the first carrier plate, wherein the substrate comprises: A dielectric layer is laminated onto the surface of the first carrier plate and covers the conductive block and the pad. Multiple circuit layers are formed on the surface of the dielectric layer away from the pad; Multiple first vias electrically connect the circuit layer and the pad; and At least one second via electrically connects the conductive block to the circuit layer; Remove the first carrier plate to expose the conductive block and the pad in the dielectric layer; A connection substrate is formed on the surface of the dielectric layer, wherein the connection substrate comprises: An insulating layer covers the conductive block and the pad; and Multiple third vias penetrate the insulating layer and are exposed on the top surface of the insulating layer, wherein the third vias are electrically connected to the pad; A portion of the insulating layer in the connecting substrate is removed, leaving only the insulating layer around the second via to form a plurality of connecting members and expose the conductive block; Remove the conductive block to form a groove on the dielectric layer and expose the narrow end of the second via; as well as At least one chip is disposed on the second via.

2. The method for manufacturing the packaging substrate structure according to claim 1, characterized in that, Also includes: Before removing the first carrier plate, a solder resist layer is formed on the substrate.

3. The method for manufacturing the packaging substrate structure according to claim 2, characterized in that, After removing the first carrier plate, it also includes: A second carrier plate is formed on the solder resist layer relative to the conductive block.

4. The method for manufacturing the packaging substrate structure according to claim 1, characterized in that, After attaching the conductive block, it further includes: The step of applying an adhesive layer to the conductive block, wherein the second via is formed on the adhesive layer, and removing the conductive block further includes: Remove the adhesive layer.

5. The method for manufacturing the packaging substrate structure according to claim 1, characterized in that, After removing part of the insulating layer and before removing the conductive block, the method further includes: The dielectric layer is thinned to form at least one protrusion on the surface of the dielectric layer away from the circuit layer.

6. The method for manufacturing the packaging substrate structure according to claim 1, characterized in that, Before bonding at least one chip, it also includes: A bottom filler layer is formed in the groove and on the second through hole.

7. A packaging substrate structure, characterized in that, Include: Circuit board, comprising: A dielectric layer, wherein a first surface of the dielectric layer includes at least one protrusion; Multiple circuit layers are disposed on a second surface of the dielectric layer, wherein the second surface is relative to the first surface; Multiple first vias are disposed in the dielectric layer; and At least one second via is disposed in the dielectric layer, wherein the cross-sectional shape of the second via is trapezoidal and has a narrow end, and the narrow end protrudes from the first surface of the dielectric layer; Multiple pads are disposed on the protrusion; and Multiple connecting members are disposed on the pad, wherein each connecting member comprises: At least one third through-hole is electrically connected to the pad; and An insulating layer covers the at least one third via, wherein the outermost of the at least one third via is exposed on the top surface of the insulating layer.

8. The packaging substrate structure according to claim 7, characterized in that, The pad is electrically connected to the circuit layer via the first through-hole.

9. The packaging substrate structure according to claim 7, characterized in that, Also includes: A bottom filler layer is disposed on the narrow end of the second through hole.

10. The packaging substrate structure according to claim 7, characterized in that, Each of the first vias has a trapezoidal cross-sectional shape, and the width of the first via decreases along the direction from the second surface of the dielectric layer toward the first surface.

11. The packaging substrate structure according to claim 7, characterized in that, Each of the third through holes has a trapezoidal cross-sectional shape, and the width of the third through hole decreases along the top surface of the insulating layer toward the pad.

12. The packaging substrate structure according to claim 7, characterized in that, Also includes: At least one wafer or at least one semiconductor element is bonded to the second via.

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