Method for forming a high-voltage transistor using thin gate polysilicon

Abstract

The present application relates to a method for forming high-voltage transistors using thin gate polysilicon. A semiconductor device and a method of manufacturing the same are disclosed. The method includes depositing a polysilicon gate layer on a gate dielectric formed on a surface of a substrate in a peripheral region, forming a dielectric layer on the polysilicon gate layer, and depositing a height-enhanced (HE) film on the dielectric layer. Then, the HE film, the dielectric layer, the polysilicon gate layer, and the gate dielectric are patterned to form a high-voltage field-effect transistor (HVFET) gate in the peripheral region. A high-energy implantation is performed to form at least one lightly doped region in a source region or a drain region in the substrate adjacent to the HVFET gate. Then, the HE film is removed, and a low-voltage (LV) logic FET is formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal gate logic FET.

Description

[0001] This application is a divisional application of the application with the filing date of July 12, 2018, application number 201880041674.2, and invention title "Method for Forming High-Voltage Transistors with Thin Gate Polysilicon".

[0002] Cross - reference to Related Applications

[0003] This application is an international application of the U.S. non - provisional patent application with serial number 15 / 848,327 filed on December 20, 2017, which claims the benefit and priority of the U.S. provisional patent application with serial number 62 / 534,463 filed on July 19, 2017, and all of these applications are incorporated herein by reference in their entirety. Technical Field

[0004] The present disclosure generally relates to semiconductor devices, and more particularly to non - volatile memory (NVM) devices and methods of manufacturing the same, the NVM devices including memory cells, high - voltage field - effect transistors (HVFETs), and advanced logic FETs embedded or integrally formed on a single substrate. Background

[0005] Flash or non - volatile memory (NVM) devices typically include a grid or array of storage elements or cells, each storage element or cell including at least one NVM transistor and multiple peripheral circuits, the peripheral circuits including a decoder, drivers, sense amplifiers, and control circuits to read from and write to the array. The NVM transistors typically include a charge - trapping or charge - storage layer and require a high voltage (HV) in the range of 4 to 10 volts for programming and erasing operations. The peripheral circuits include logic field - effect transistors (FETs) that typically operate at low voltages, and multiple HVFETs capable of supporting the high voltage required by the NVM transistors.

[0006] To provide improved efficiency, security, functionality, and reliability, it has become increasingly common to monolithically include logic FETs and HVFETs on the same substrate as the memory cells. However, including logic FETs and HVFETs with NVM transistors on the same substrate is challenging because each device or transistor typically requires different manufacturing parameters.

[0007] Accordingly, there is a need for a semiconductor or NVM device including memory cells, HVFETs, and logic FETs embedded or integrally formed on a single substrate and a method of manufacturing the same. Summary

[0008] A semiconductor device and a method of manufacturing the same are provided. Generally, the method begins with forming an ONO stack that will be formed on the surface of a substrate in a memory region for a memory gate (MG), and forming a gate dielectric that will be formed on the surface of the substrate in a peripheral region for a high-voltage field-effect transistor (HVFET) gate. Next, a polysilicon gate layer is deposited on the ONO stack and the gate dielectric, a dielectric layer is formed on the polysilicon gate layer, and a height-enhancing (HE) film is deposited on the dielectric layer. Then, the HE film, the dielectric layer, the gate layer, the gate dielectric, and the ONO stack are patterned for the MG and the HVFET gate. Source / drain (S / D) regions are implanted adjacent to the HVFET gate, and the HE polysilicon layer is removed to form the MG and the HVFET gate. The depth of the S / D regions in the substrate is generally greater than the height of the HVFET gate above the surface of the substrate. In some embodiments, the HE film comprises amorphous silicon or polysilicon and is thick enough to prevent dopants from a drain implant from reaching the channel under the HVFET gate.

[0009] According to another embodiment, the method further comprises, after removing the HE film, forming a polysilicon gate for a low-voltage (LV) logic FET in a peripheral region and replacing the polysilicon gate of the LV logic FET with a metal gate using a high-K metal gate (HKMG) process.

[0010] The present application provides the following:

[0011] 1). A method of manufacturing a semiconductor device, comprising:

[0012] Depositing a polysilicon gate layer on a gate dielectric formed on the surface of a substrate in a peripheral region;

[0013] Forming a dielectric layer on the polysilicon gate layer;

[0014] Depositing a height-enhancing (HE) film on the dielectric layer;

[0015] Patterning the HE film, the dielectric layer, the polysilicon gate layer, and the gate dielectric for a high-voltage field-effect transistor (HVFET) gate to be formed in the peripheral region;

[0016] Performing a high-energy implantation to form at least one lightly doped region in a source or drain (S / D) region in the substrate adjacent to the HVFET gate;

[0017] Removing the HE film; and

[0018] A low-voltage (LV) logic FET is formed in the peripheral region, where the LV logic FET is a high-k metal gate (HKMG) logic FET.

[0019] 2). The method according to 1), wherein the depth of the lightly doped region in the substrate is greater than the height of the HVFET gate.

[0020] 3). The method according to 1), wherein depositing the HE film includes depositing an amorphous silicon film or a polysilicon film.

[0021] 4). The method according to 3), further comprising implanting the HE film with pre-amorphization implantation.

[0022] 5). The method according to 1), wherein removing the HE film includes chemical mechanical planarization (CMP), plasma etching, or a combination thereof.

[0023] 6). The method according to 1), wherein performing the high-energy implantation includes forming a lightly doped drain (LDD).

[0024] 7). The method according to 1), wherein the HVFET gate includes a polysilicon gate formed by a patterned polysilicon gate layer, and the method further includes forming a silicide on the polysilicon gate.

[0025] 8). The method according to 1), wherein depositing the polysilicon gate layer includes depositing the polysilicon gate layer on an ONO stack formed on the surface of the substrate in a memory region; and

[0026] Patterning the HE film, the dielectric layer, the polysilicon gate layer, and the gate dielectric further includes patterning the dielectric layer, the polysilicon gate layer, and the ONO stack for a memory gate (MG) to be formed in the memory region.

[0027] 9). A method of manufacturing a semiconductor device, comprising:

[0028] Depositing a polysilicon gate layer on an ONO stack formed on the surface of a substrate in a memory region and on a gate dielectric formed on the surface of the substrate in a peripheral region;

[0029] Forming a dielectric layer on the polysilicon gate layer;

[0030] Depositing a height-enhanced (HE) film on the dielectric layer;

[0031] Pattern the HE film, the dielectric layer, the polysilicon gate layer, the gate dielectric, and the ONO stack for a memory gate (MG) to be formed in the memory region and a high-voltage field-effect transistor (HVFET) gate to be formed in the peripheral region;

[0032] Perform a high-energy implantation to form at least one lightly doped region in a source or drain (S / D) region in the substrate adjacent to the HVFET gate;

[0033] Remove the HE film; and

[0034] Form a low-voltage (LV) logic FET in the peripheral region, wherein the LV logic FET is a high-k metal gate (HKMG) logic FET.

[0035] 10). The method according to 9), wherein depositing the HE film includes depositing the HE film to a thickness sufficient to prevent dopants from the high-energy implantation from reaching a channel under the HVFET gate.

[0036] 11). The method according to 9), wherein depositing the HE film includes depositing an amorphous silicon film or a polysilicon film.

[0037] 12). The method according to 11), further including implanting the HE film with a pre-amorphization implantation.

[0038] 13). The method according to 9), wherein removing the HE film includes chemical mechanical planarization (CMP), plasma etching, or a combination thereof.

[0039] 14). The method according to 9), wherein performing the high-energy implantation includes forming a lightly doped drain (LDD).

[0040] 15). The method according to 9), wherein the HVFET gate includes a polysilicon gate formed by a patterned polysilicon gate layer, and the method further includes forming a silicide on the polysilicon gate.

[0041] 16). The method according to 9), wherein patterning the HE film, the dielectric layer, the polysilicon gate layer, the gate dielectric, and the ONO stack includes: separately patterning the HE film, the dielectric layer, the polysilicon gate layer, and the gate dielectric for the MG, and patterning the HE film, the dielectric layer, the polysilicon gate layer, and the ONO stack for the HVFET gate.

[0042] 17). A method of manufacturing a semiconductor device, comprising:

[0043] Deposit a polysilicon gate layer on a gate dielectric formed on the surface of a substrate;

[0044] Form a dielectric layer on the polysilicon gate layer;

[0045] Deposit a height enhanced (HE) film on the dielectric layer;

[0046] Pattern the HE film, the dielectric layer, the polysilicon gate layer, and the gate dielectric for a high-voltage field effect transistor (HVFET) gate to be formed on the surface of the substrate;

[0047] Perform a high-energy implantation to form at least one lightly doped region in a source or drain (S / D) region in the substrate adjacent to the HVFET gate;

[0048] Remove the HE film; and

[0049] Form a low-voltage (LV) logic FET on the surface of the substrate, wherein the LV logic FET is a high-k metal gate (HKMG) logic FET,

[0050] wherein the depth of the lightly doped region in the substrate is greater than the gate height of the HVFET gate above the surface of the substrate, and wherein depositing the HE film includes depositing the HE film to a thickness sufficient to prevent dopants from the high-energy implantation from reaching a channel under the HVFET gate.

[0051] 18). The method according to 17), wherein depositing the HE film includes depositing an amorphous silicon film or a polysilicon film.

[0052] 19). The method according to 18), further comprising implanting the HE film with a pre-amorphization implantation.

[0053] 20). The method according to 17), wherein removing the HE film includes chemical mechanical planarization (CMP), plasma etching, or a combination thereof.

[0054] 21). The method according to 17), wherein performing the high-energy implantation includes forming a lightly doped drain (LDD).

[0055] Additional features and advantages of embodiments of the present invention and the structure and operation of various embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be noted that the present invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Based on the teachings contained herein, additional embodiments will be apparent to those skilled in the relevant art. Description of the Drawings

[0056] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying schematic diagrams, in which corresponding reference numerals indicate corresponding parts. In addition, the drawings incorporated herein and forming a part of the specification illustrate embodiments of the present invention and, together with the description, further serve to explain the principles of the present invention and enable those skilled in the relevant art to develop and use the present invention.

[0057] Figure 1 is a schematic block diagram of a non-volatile memory (NVM) device including an array of memory cells and a plurality of peripheral circuits, the peripheral circuits including a decoder, a driver, a sense amplifier, and a control circuit integrally formed on a single substrate;

[0058] Figure 2 is a block diagram of a cross-section of a part of an NVM device including split-gate memory cells in a memory region and HVFETs and logic FETs in a peripheral region according to an embodiment of the present disclosure;

[0059] Figure 3 is according to an embodiment of the present disclosure Figure 2 detailed block diagram of a cross-section of an embodiment of a split-gate memory cell;

[0060] Figure 4 is according to an embodiment of the present disclosure Figure 2 detailed block diagram of a cross-section of an embodiment of a logic FET;

[0061] Figure 5 is according to an embodiment of the present disclosure Figure 2 detailed block diagram of a cross-section of an embodiment of an HVFET;

[0062] Figures 6A - 6C is a flowchart depicting a method of manufacturing an NVM device according to an embodiment of the present disclosure;

[0063] Figures 7A - 7I shows Figures 6A - 6C a cross-section of a part of an NVM device at different points during its manufacture according to the method of manufacture.

[0064] The features and advantages of embodiments of the present invention will become more apparent from the detailed description set forth below in conjunction with the accompanying drawings. In the drawings, like reference numerals generally denote identical, functionally similar, and / or structurally similar elements. Detailed Description

[0065] This specification discloses one or more embodiments including features of the present invention. The disclosed embodiments are merely examples to illustrate the present invention. The scope of the present invention is not limited to the disclosed embodiments. The present invention is defined by the claims appended hereto.

[0066] The described embodiments and the references in the specification to "one embodiment", "an embodiment", "example embodiment", etc. indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment must include the specific features, structures, or characteristics. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a specific feature, structure, or characteristic is described in connection with an embodiment, it should be understood that implementing such a feature, structure, or characteristic in connection with other embodiments is within the knowledge of those skilled in the art, whether or not explicitly described.

[0067] Before describing the various embodiments in more detail, further explanations will be given of certain terms that may be used throughout the description.

[0068] The term "etch" or "etching" is used herein to generally describe a manufacturing process for patterning a material such that at least a portion of the material remains after the etching is complete. For example, it should be understood that a process for etching silicon includes the steps of patterning a mask layer (e.g., photoresist or hard mask) on the silicon and then removing the regions of silicon that are no longer protected by the mask layer. Thus, after the etching process is complete, the regions of silicon protected by the mask will remain. However, in another example, etching may also refer to a process that may or may not use a mask and may or may not leave a portion of the material after the etching process is complete.

[0069] The above description is used to distinguish between the terms "etch" and "remove". When removing a material, all or substantially all of the material is removed in the process. However, in some embodiments, "remove" is considered a broad term that may include etching.

[0070] The term "CMP" as used herein generally describes a chemical mechanical polishing or planarization process used during semiconductor manufacturing to smooth a surface on or above a substrate. The process typically uses a combination of an abrasive and / or corrosive colloidal slurry and mechanical force, which is provided by securing the substrate to a dynamic polishing head and pressing the substrate against a rotating polishing pad. The process removes material from the substrate, thereby providing a planarized surface.

[0071] During the description herein, various regions for fabricating memory cells, logic, and high voltage transistors or devices on a substrate are mentioned. Although two different regions are described herein, it should be understood that any number of regions may exist on the substrate and regions may be designated with certain types of devices or materials. Generally, regions are used to conveniently describe areas of the substrate that include similar devices and should not limit the scope or spirit of the described embodiments.

[0072] The terms "deposition" or "processing" are used herein to describe the act of applying a layer of material to a substrate. These terms are intended to describe any possible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc. According to various embodiments, for example, deposition can be performed according to any suitable known method. For example, deposition can include growing, coating, or any process of transferring a material to a substrate. Among other things, some known techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), and plasma-enhanced CVD (PECVD).

[0073] The "substrate" used throughout the description is generally considered to be silicon. However, the substrate can also be any of a variety of semiconductor materials, such as germanium, gallium arsenide, indium phosphide, etc. In other embodiments, the substrate can be non-conductive, such as a glass or sapphire wafer.

[0074] As used herein, a "mask" can include any suitable material that allows selective removal (e.g., etching) of the unmasked portion of the material. According to some embodiments, the mask structure can include a photoresist, such as polymethyl methacrylate (PMMA), polymethylglutarimide (PMGI), phenol formaldehyde resin, a suitable epoxy resin, etc., or a hard mask including silicon nitride.

[0075] Before describing such embodiments in more detail, it is beneficial to present an example memory cell and environment in which the present embodiment can be implemented.

[0076] Figure 1 A schematic block diagram of a non-volatile memory (NVM) device 100 including a memory array 102 and a plurality of peripheral circuits is shown. The peripheral circuits include a decoder, a driver, a sense amplifier, and a control circuit integrally formed on a single substrate to read from and write to the memory array 102. See Figure 1 , the NVM device 100 also includes a command and control circuit 104, such as a microcontroller, a microprocessor, or a state machine, to issue commands or control signals to each of the memory cells in the memory array 102 (not shown in the figure) along with other peripheral circuits for reading from or writing to the memory array. Generally, the peripheral circuits also include a row decoder 106, a column decoder 108, a sense amplifier 110, and a source line driver 112.

[0077] When a data word is to be stored or written to the NVM device 100, the row decoder 106 receives and decodes the memory address and then provides it to the command and control circuit 104. The command and control circuit 104 then selects a row of memory cells in the memory array 102 by applying a signal to the word lines (WLs) of the memory cells in the selected row, provides the column address to the column decoder 108, and provides a control signal to the source line driver 112. The column decoder 108 translates the column address and applies signals to the bit lines (BLs) of each memory cell in the selected column. The source line driver 112 then couples a high voltage (typically from about 4 to about 10 volts DC) to the source lines of the memory cells to program or erase the NVM transistors in the memory cells.

[0078] Typically, when a data word is to be recalled or read out from the NVM device 100, the row decoder 106 receives, decodes the memory address and provides it to the command and control circuit 104, and then the command and control circuit 104 selects a row of memory cells in the memory array 102 by applying a signal to the WLs of the memory cells in the selected row, provides the column address to the column decoder 108, and provides a control signal to the source line driver 112. The sense amplifier 110 compares the data voltage for each memory cell in the selected row with a reference voltage to determine whether to read a logic "0" or "1" from the cell.

[0079] Each peripheral circuit may include a large number of low voltage logic field effect transistors (FETs), and the row decoder 106 and the source line driver 112 also include many high voltage field effect transistors (HVFETs) to support the voltages (e.g., 4 to 10V) required for programming and erasing operations.

[0080] Figure 2A cross-section of a portion of the NVM device 200 is shown, which portion includes a memory array 202 formed on a substrate 210 in a memory region 214. The NVM device 200 also includes an HVFET 206 and a logic FET 208 formed within or on a peripheral region 216 of the same substrate 210. In the illustrated embodiment, the memory cells are split-gate memory cells, each memory cell including a memory gate (MG) and a select gate (SG). Generally, as in the illustrated embodiment for adjacent memory cells 204, the HVFET 206 and the logic FET 208 are isolated from each other by shallow trench isolation structures (STI 212) surrounding each region or area or device. In this example, the substrate 210 includes a memory region 214 where the memory cells 204 are located and a peripheral region 216. The peripheral region 216 is further divided by the STI 212 into a logic or low voltage (LV) region where the logic FET 208 is formed and an HV region where the HVFET 206 is formed. In the illustrated embodiment, the memory array 202 includes a plurality of split-gate memory cells 204, each split-gate memory cell including a memory gate (MG) and a select gate (SG). It should be understood that Figure 2 the cross-section is merely exemplary, and the peripheral region 216 may further include additional integrated circuit components such as resistors, capacitors, inductors, etc. (not shown in this figure), as well as the logic FET 208 and the HVFET 206. It should also be understood that the memory region 214 and the peripheral region 216 may be located in any region (including non-adjacent regions) of the substrate 210 and may include multiple instances of each of the different regions 214 / 216.

[0081] According to various embodiments, the substrate 210 and the true substrate generally used throughout the specification may be silicon. However, the substrate 210 may also be any of a variety of semiconductor materials such as germanium, gallium arsenide, indium phosphide, etc. In other embodiments, the substrate 210 may be non-conductive, such as a glass or sapphire wafer.

[0082] Reference will now be made to Figures 3 to 5 describe the memory cells 204, the logic FET 208, and the HVFET 206 in more detail.

[0083] Figure 3FIG. 0 shows an example of a split-gate memory cell 300 including a memory gate (MG 302) and a select gate (SG 304) formed over a common or shared channel 306 on a substrate 308. Each memory cell includes a first source / drain (S / D) region 310 and a second source / drain (S / D) region 312. Regions 310 and 312 form the source or drain of split-gate memory cell 300 depending on the potential applied to each memory cell. In split-gate memory cell 300, for convenience, region 310 adjacent to SG 304 is generally referred to as the drain, and region 312 adjacent to MG 302 is generally referred to as the source, regardless of the relative bias. Typically, substrate 308 is a p-type silicon substrate or includes a p-type well in which memory cells 300 are formed, and regions 310 and 312 are moderately to heavily doped with n-type dopants. However, it is also possible that substrate 308 is n-type and regions 310 and 312 are doped with p-type dopants.

[0084] Both MG 302 and SG 304 include doped polysilicon conductors. The doped polysilicon conductor of SG 304 is disposed on or over a select gate dielectric 314, and the doped polysilicon conductor of MG gate 302 is disposed on or over a multi-layer charge storage or trapping stack 316 having one or more charge trapping layers between dielectric layers. In one example, charge trapping stack 316 includes a charge trapping silicon nitride layer 316b sandwiched between two silicon dioxide layers 316a and 316c to produce a three-layer structure commonly and generally referred to as an “ONO stack”. Other charge trapping stacks 316 can include a polysilicon charge storage layer 316b sandwiched between two dielectric layers 316a, 316c to produce a floating gate MOS field effect transistor (FGMOS). A vertical inter-gate dielectric 318 is also disposed between SG 304 and MG 302 to electrically isolate the doped polysilicon conductors of the gates. In some embodiments, such as the illustrated embodiment, inter-gate dielectric 318 can include one or more layers or films of dielectric materials having different dielectric properties. For example, inter-gate dielectric 318 can include an ONO dielectric similar to charge trapping dielectric 316.

[0085] Memory cell 300 also includes self-aligned silicide or self-aligned polysilicide (SALICIDE) 320 on the surfaces of the select gate 304 and the S / D regions 310 and 312, and sidewall spacers 322 surrounding the SG and MG. The sidewall spacers 322 can include one or more layers of dielectric material, such as silicon oxide or silicon nitride. The self-aligned polysilicide 320 reduces the resistance between contacts (not shown in this figure) to the active regions of the memory cell (e.g., the S / D regions 310 and 312), as well as the resistance between the contacts to the polysilicon of the SG 304 and optionally the contacts to the MG 302 in embodiments not shown in this figure. In some embodiments, for example Figure 3 In the illustrated embodiment, the self-aligned polysilicide 320 formed on top of the SG 304 is pulled back or away from the sidewalls adjacent to the inter-gate dielectric 318 to provide further isolation to prevent short-circuiting or leakage between the self-aligned polysilicide and the MG 302. It should be understood that this description is intended to provide a general overview of the split-gate configuration, and in actual practice, more detailed steps and layers are provided to form the final memory cell 300.

[0086] Figure 4 An embodiment of a logic FET 400 suitable for Figure 1 and Figure 2 is shown for an NVM device. In the illustrated embodiment, the logic FET 400 is a high-k metal gate (HKMG) logic FET that has a metal gate 402 surrounded by sidewall spacers 404 and a high-k gate dielectric 406 that covers a channel 408 that separates source and drain (S / D) regions 410 formed in a substrate 412. The logic FET 400 also includes self-aligned silicide or self-aligned polysilicide 414 on or above the surface of the S / D region 410 to reduce the resistance between contacts (not shown in this figure) and the S / D region. The metal gate 402 can be made of any suitable metal or alloy, including but not limited to aluminum, copper, titanium, tungsten, and their alloys. Suitable high-k dielectric materials for the high-k gate dielectric 406 can include but not limited to hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxynitride, hafnium zirconium oxide, and lanthanum oxide. Optionally, the high-k gate dielectric 406 can include one or more layers of suitable high-k dielectric materials. The sidewall spacers 404 can include one or more layers of dielectric material, such as silicon oxide or silicon nitride.

[0087] Compared to the gates of previous generations of logic FETs, the metal gate 402 of the HKMG logic FET 400 has a narrower width or a narrower channel length, and thus can improve the performance of the memory device and reduce the size of the wafer or chip on which the memory device is fabricated.

[0088] In the past, for gates with a lateral dimension of about 40 nanometers (nm) or greater, a thick gate polysilicon could be used to form memory cells, HVFETs, and logic transistors integrally on a single substrate. However, as the lateral dimensions of circuit elements such as gates continue to shrink, it becomes necessary to limit the height of the circuit elements. Specifically, the height of the metal gate 402 of an HKMG logic FET fabricated using a gate replacement process is limited to about 300 to about 1000 angstroms to ensure that the aspect ratio notch caused by etching or removing the sacrificial gate is completely filled with metal.

[0089] In the gate replacement process, which will be described in more detail below with reference to Figures 6A - 6C and Figures 7A - 7I a sacrificial or dummy gate is formed on the high-k gate dielectric 406, sidewall spacers 404 are formed around the sacrificial gate, and an interlayer dielectric (ILD) is formed on the sidewall spacers and the sacrificial gate. Then, the ILD is polished and planarized using CMP to expose the top of the surface of the sacrificial gate, and the sacrificial gate is removed from inside the sidewall spacers 404 using a selective etching process. Then, the metal gate 402 is deposited inside the sidewall spacers 404. Since the narrowest width of the metal gate can be about 10 to about 40 nm, the height of the metal gate 402 of the HKMG logic FET is limited to about 300 to about In addition, due to the planarization of the interlayer dielectric (not shown in this figure), the sidewall spacers 404, and the CMP process required to expose the sacrificial gate, the gate heights of memory cells and HVFETs formed before or simultaneously with the HKMG logic FET 400 and coplanar therewith are also limited to a similar height.

[0090] Figure 5 An embodiment of an HVFET 500 suitable for Figure 1 and Figure 2 is shown. The HVFET 500 fabricated according to an embodiment of the present disclosure will be described in detail below with reference to Figures 6A - 6C and Figures 7A - 7I and is capable of handling voltages up to about 20 volts. The HVFET 500 includes a doped polysilicon gate 502 surrounded by sidewall spacers 504 and disposed on or above an HVFET gate dielectric 506 that covers a channel 508 separating source and drain (S / D) regions 510 formed in a substrate 512. The sidewall spacers 504 may include one or more layers of dielectric material, such as silicon oxide or silicon nitride. The HVFET 500 also includes a self-aligned silicide or self-aligned polysilicide 514 formed on or above the surfaces of the doped polysilicon gate 502 and the S / D regions 510 to reduce the resistance between contacts (not shown in this figure), the doped polysilicon gate, and the S / D regions.

[0091] To provide the required high breakdown voltage, the HVFET 500 has a relatively thick HVFET gate dielectric 506, a relatively long channel 508, and relatively deep S / D regions 510. After forming the HVFET gate 502, the deep S / D regions 510 are formed using a high-energy, low-dose implant to form a lightly doped drain (LDD). "Deep" means extending to a depth of about 400 to about below the surface 516 of the substrate 512. High-energy, low-dose implant means implanting an appropriate ion species at an energy of about 30 to about 100 kilo electron volts (keV), and a dose of about 1e12 cm -3 to about 1e14 cm -3 .

[0092] Previous generations of HVFETs relied on a doped polysilicon gate 502 that was thick enough to prevent implanted ions from penetrating the gate stack and reaching the channel 508 during high-energy drain region implantation. However, as described above, due to the limitations imposed by the gate replacement process used to form the HKMG logic FET 400, the HVFET gate 502 needs to be equal to or less than about Using embodiments of the disclosed method, the HVFET 500 can be fabricated to have deep S / D regions 510, partially formed by LDD implants, where the HVFET gate 502 is formed of a thin polysilicon gate layer and has a gate height ranging from about 300 to about .

[0093] Reference will now be made to Figures 6A - 6C and Figures 7A to 7I for a detailed description of embodiments of a method for manufacturing an NVM device that includes memory cells, HKMG logic FETs, and HVFETs embedded or integrally formed on a single substrate. Figures 6A - 6C is a flowchart showing an embodiment of a method or process flow. Figures 7A to 7I is a block diagram showing a cross-sectional view of a portion of an NVM device 700 during the manufacture of the NVM device 700 according to the method of Figures 6A - 6C .

[0094] See Figure 6A and Figure 7A , the process begins with forming a shallow trench isolation (STI) structure 702 in the substrate 704 to electrically isolate the area in the memory region 706 where a memory array will be formed from the peripheral region 708, and to isolate the low voltage (LV) region where HKMG logic FETs will be formed from the high voltage (HV) region where HVFETs will be formed (step 602).

[0095] Next, a continuous first channel 710 for one or more memory cells is formed in the surface 712 of the substrate 704 in the memory region 706, a second channel 714 for HKMG logic FETs is formed in the LV region of the peripheral region 708, and a third channel 716 for HVFETs is formed in the HV region (step 604). The channels 710, 714, and 716 can be formed by implanting appropriate ion species using ion implantation techniques. For example, a p-type channel implant may include implanting boron B at an energy of about 5 to about 50 KeV + ions and implanting a concentration or dose of about 1e11 cm -3 to about 5e13 cm -3 . An n-type channel implant may include implanting phosphorus or arsenic ions at a similar energy and implanting to a similar dose.

[0096] See Figure 6A and Figure 7B , the process continues to form a charge trapping stack 718 covering the first channel 710 in the memory region 706, and a high voltage (HV) gate dielectric 720 covering the third channel 716 in the HV region of the peripheral region 708 of the substrate 704 (step 606). In one embodiment, the charge trapping stack 718 is formed by depositing or forming a tunnel layer 718a, a charge trapping or storage layer 718b, and a blocking layer 718c. The tunnel layer 718a may include a dielectric material such as silicon dioxide (SiO2) and may be thermally grown or deposited by CVD, PECVD, or ALD. Suitable dielectric charge trapping layers 718b may include one or more layers of silicon nitride (SiN), silicon-rich nitride, or silicon oxynitride (SiON) deposited by CVD, PECVD, or ALD. Alternatively, the charge storage layer 718b may include a conductive floating gate charge storage layer polysilicon deposited by CVD, PECVD, or ALD. The blocking layer 718c may include one or more layers of thermally grown or deposited silicon dioxide (SiO2) and / or a high-k dielectric deposited by CVD, PECVD, or ALD. Suitable high-k dielectric materials for the blocking layer 718c may include, but are not limited to, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxynitride, hafnium zirconium oxide, and lanthanum oxide.

[0097] As shown, since the surface 712 of the substrate 704 in the LV region where HKMG logic FETs will be formed is stripped before forming the HKMG logic FETs, the charge trapping stack 718 may also be allowed to extend over the LV region of the peripheral region 708.

[0098] The HV gate dielectric 720 is formed to cover the third channel 716 in the HV region of the peripheral region 708. The HV gate dielectric 720 may include one or more layers of suitable dielectric materials, such as silicon dioxide (SiO2) or silicon nitride (SiN) deposited by CVD, PECVD, or ALD. Alternatively, the HV gate dielectric 720 may include a high-k dielectric material, such as hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxynitride, zirconium oxide, or lanthanum oxide.

[0099] Next, a first polysilicon gate layer 722 is deposited on the charge trapping stack 718 and the HV gate dielectric 720 (step 608). The first polysilicon gate layer 722 may be a doped polysilicon layer and may be deposited by CVD, PECVD, or ALD to a thickness from about 300 to about . Alternatively, the first polysilicon gate layer 722 may be deposited as an undoped polysilicon layer, which is subsequently doped with appropriate ion species and appropriate doses to be used as the MG and HV gates.

[0100] A thin dielectric layer 724 is formed on the first polysilicon gate layer 722 (step 610). The dielectric layer 724 may include thermally grown or deposited by CVD, PECVD, or ALD silicon dioxide (SiO2) to a thickness from about 20 to about .

[0101] Next, a height enhanced (HE) film 726 is deposited on the dielectric layer 724 (step 612). The HE film 726 may include an amorphous silicon film or a polysilicon film deposited by CVD, PECVD, or ALD to a thickness from about 400 to about . Generally, the thickness of the HE film 726 is selected considering the thickness of the underlying dielectric layer 724 and the first polysilicon gate layer 722, as well as the energy and dose of the HVFET region implant sufficient to prevent dopants from the implant from reaching the third channel 716. For example, for a high energy, low dose region implant having an energy of about 30 to about 100 keV and a dose of about 1e12 cm -3 to about 1e14 cm -3 , the combined thickness of the first polysilicon gate layer 722, the dielectric layer 724, and the HE film 726 is about 1000 to about It has been found that the combined thickness in this range is sufficient to substantially prevent implanted ions from the deep region implant from penetrating the HVFET gate stack including the first polysilicon gate layer 722, the dielectric layer 724, and the HE film 726 and reaching the third channel 716.

[0102] See Figure 6A and Figure 7C, the HE film 726, dielectric layer 724, first polysilicon gate layer 722, HV gate dielectric 720, and charge trapping stack 718 are patterned to form a memory gate (MG 728) in the memory region 706 and an HVFET gate 730 in the peripheral region 708 (step 614). The HE film 726, dielectric layer 724, first polysilicon gate layer 722, and charge trapping stack 718 can be left in place over the LV region. The patterning can be done using standard lithography techniques to form a mask on the surface of the HE film 726, and then the HE film and underlying layers are etched anisotropically using any standard dry or wet etching technique. For example, the polysilicon layer can be dry etched in a plasma of a polysilicon etch chemistry (such as CHF3 or C2H2 or HBr / O2) at medium power (about 500 W); silicon dioxide (SiO2) can be wet etched or dry etched; and silicon nitride (SiN) can be dry etched using a low-pressure plasma of a fluorine-containing gas (such as CF4 or CHF3). After the HE film 726, dielectric layer 724, first polysilicon gate layer 722, HV gate dielectric 720, and charge trapping stack 718 have been etched or patterned to form the MG 728 and HVFET gate 730 as shown in Figure 7C , any remaining photoresist (not shown in this figure) is stripped from the mask, and a wet clean is performed. Optionally, the MG 728 and HVFET gate 730 can be patterned in separate etching steps using additional mask layers.

[0103] Optionally, a pre-amorphization implant can be performed to amorphize the HE film 726 remaining on the MG 728 and HVFET gate 730 (step 616). The pre-amorphization implant can be performed using any suitable semiconductor material or dopant. For example, the pre-amorphization implant can include implanting germanium (Ge) ions at an energy of about 5 to about 50 keV and at a dose of about 1e13 cm -3 to about 5e15 cm -3 . Amorphizing the HE film 726 before performing a high-energy, low-dose implant to form the deep, lightly doped drain (LDD) of the HVFET improves the ability of the HE film 726 to prevent the implanted ions from penetrating the HVFET gate stack and reaching the channel 716.

[0104] See Figure 6B and Figure 7D , a high-energy, low-dose implant is performed to form one or more LDDs 732 in the substrate 704 adjacent to the HVFET gate 730 (step 618). As described above, the implant can include implanting an appropriate ion species at an energy of about 30 to about 100 kiloelectron volts (keV) to a dose of about 1e12 cm -3to about 5e14 cm -3 a dose that will provide an LDD 732 extending to a depth of about 400 to about below the surface of the substrate 704.

[0105] Then an inter-gate dielectric 734 is formed on the sidewalls of the MG 728 (step 620). As described above, the inter-gate dielectric 734 may include one or more dielectric material layers or films having different dielectric properties. For example, the inter-gate dielectric 734 may include an ONO dielectric similar to the charge trapping stack 718 and may be deposited to a thickness of about 100 to about using the same CVD, PECVD or ALD techniques.

[0106] Next, any material remaining on the surface of the substrate 704 from the formation of the inter-gate dielectric 734 in the memory region 706 is removed, and an SG gate dielectric 736 is formed on the substrate surface in the memory region for forming an SG adjacent to the MG 728 (step 622). It should be understood that the material remaining on the surface can be removed using anisotropic dry etching, which uses any of the standard oxide and nitride plasma etching chemistries described above. The SG gate dielectric 736 may include one or more layers of a suitable dielectric material, such as silicon oxide or silicon nitride deposited by CVD, PECVD or ALD to a thickness of about 10 to about Alternatively, the SG gate dielectric 730 may include a suitable high-k dielectric material, such as hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxynitride, zirconium oxide and lanthanum oxide.

[0107] See Figure 6B and Figure 7E , a second polysilicon gate layer 738 is deposited on the surfaces 712 of the MG 728, the HVFET gate 730 and the substrate 704 (step 624). Like the first polysilicon gate layer 722, the second polysilicon gate layer 738 may include a doped polysilicon layer or an undoped polysilicon layer that is subsequently doped, and is deposited by CVD, PECVD or ALD to a thickness of at least about using the same CVD, PECVD or ALD techniques.

[0108] See Figure 6B and Figure 7F , a plasma etching, CMP process or a combination thereof is used to planarize or polish the layers on or above the surface of the substrate 704 to remove a portion of the second polysilicon gate layer 738 and the HE film 726 above the MG 728 and the HVFET gate 730 and to planarize the second polysilicon gate layer (step 626). The portion of the dielectric layer 724 remaining on the MG 728 and the HVFET gate 730 can be used as a stop layer for CMP or plasma etching for planarization.

[0109] See Figure 6B and Figure 7G , in the LV region of the peripheral region 708, the gate stack including the first polysilicon gate layer 722 and the dielectric layer 724 is removed, exposing the surface 712 of the substrate 704. A high-k gate dielectric 742 is deposited on the exposed surface, a doped or undoped polysilicon or amorphous silicon layer is deposited on the high-k gate dielectric, and the two layers are patterned to form a logic gate pattern 744 in the LV region (step 627). Thereafter, the second polysilicon gate layer 738 is removed from one side (e.g., the source side) of the memory cell and from the HV region, planarized and patterned to form a select gate (SG 740) on the other side (e.g., the drain side) of the memory cell drain in the memory region 706 (step 628). For example, the polysilicon layer can be dry-etched using a low-pressure etch with medium power (about 500 W) in a plasma of a standard polysilicon etch chemistry (e.g., CHF3 or C2H2 or HBr / O2); silicon dioxide can be wet-etched or dry-etched; and the nitride layer can be etched using a low-pressure nitride etch in a plasma of a fluorine-containing gas (such as CF4 or CHF3).

[0110] The high-k gate dielectric 742 can include one or more layers of high-k dielectric material, such as hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxynitride, hafnium zirconium oxide, and lanthanum oxide, deposited to a thickness of about 10 to about thickness.

[0111] The logic gate pattern 744 includes a plurality of dummy or sacrificial gates 746 formed of doped or undoped polysilicon or amorphous silicon, deposited to a thickness of about 300 to about thickness, and patterned using a patterned hard mask 748 and any of the above polysilicon or silicon dry-etching techniques. The patterned hard mask 748 is typically formed by patterning a dielectric material (e.g., silicon dioxide (SiO2) or silicon nitride (SiN)) layer using standard lithography and etching techniques.

[0112] See Figure 6C and Figure 7H , appropriate types of dopant ions are implanted to form source / drain (S / D) regions 750 in the memory region 706 adjacent to the MG 728 and SG 740, and S / D regions 752 in the LV region of the peripheral region 708 adjacent to the logic gate pattern 744 (step 630). Generally, since these S / D regions 750 / 752 are not deep, the implantation is typically performed at a relatively low energy of about 1 to about 50 kilo-electron volts (keV) up to about 1e13 cm -3to about 2e15 cm -3 for a medium heavy dose. Since the energy of these implants is low, the thin polysilicon of the HVFET gate 730 is thick enough to prevent any implanted ions from reaching the channel 716. However, in order to avoid undesirably increasing the concentration of dopants in the LDD 732, the HV region is preferably masked before performing the implant.

[0113] Next, spacers 754 are formed on the sidewalls adjacent to the MG 728, SG 740, HVFET gate 730, and logic gate pattern 744 (step 632). The spacers 754 are typically formed by sequentially depositing a conformal dielectric layer, such as silicon dioxide (SiO2) or silicon nitride (SiN), followed by a blanket etch or spacer etch to remove most of the dielectric material deposited on the horizontal surfaces of the substrate 704, thereby creating the spacer shape shown.

[0114] Then, a self-aligned silicide or self-aligned polysilicide 756 is formed on the LDD 732 and S / D regions 750 / 752 adjacent to the MG 728, SG 740, and logic gate pattern 744 (step 634). The self-aligned polysilicide can also be formed on the HVFET gate and on at least one of the MG and SG polysilicon gates. The self-aligned polysilicide 756 can include any suitable transition metal, such as titanium, cobalt, nickel, platinum, and / or tungsten, and can be formed by any silicide process commonly employed in the art, including, for example, pre-clean etch, metal deposition, annealing, and wet stripping.

[0115] See Figure 6C and Figure 7I , an interlayer dielectric (ILD 758) is formed or deposited on the substrate 704 and planarized using a CMP process to form a planarized surface through which the top surface of the sacrificial gate is exposed (step 636). Typically, the ILD 758 can include any suitable dielectric material, such as silicon dioxide (SiO2), and can be deposited or formed using suitable standard deposition techniques, including CVD.

[0116] Next, a thin patterned hard mask 760 is formed on the memory array in the memory region 706 and on the HV region in the peripheral region 708 (step 638). The patterned hard mask 760 is typically formed by patterning a dielectric material layer, such as silicon nitride, using standard lithography and etching techniques.

[0117] The sacrificial gate 746 is then removed from within the spacer 754 in the LV, and the resulting gap is filled with metal to form the metal gate 756 of the HKMG logic FET (step 640). The sacrificial gate 746 can be removed using standard polysilicon etch chemistries such as CHF3 or C2H2 or HBr / O2. Generally, the metal can include any suitable metal such as aluminum, copper, titanium, tungsten, and their alloys, and can be deposited or formed using suitable standard deposition techniques including CVD and physical vapor deposition (PVD), such as sputtering to deposit a metal layer that is again planarized in a CMP process to remove portions of the metal layer that are not in the gaps of the spacers 754. Note that since the MG 722, SG 734, and HVFET gates 724 are covered by the patterned hard mask 760, neither the gates nor the self-aligned silicides 750 are damaged during the etch or metal deposition processes.

[0118] Finally, the patterned hard mask 760 may or may not be removed, and one or more vertical contacts or vias are formed through the ILD 758 to the self-aligned silicides 750.

[0119] It should be recognized that the detailed description section (not the overview and abstract sections) is intended to explain the claims. The overview and abstract sections may set forth one or more but not all exemplary embodiments of the invention as contemplated by the inventor, and thus are not intended to limit the invention and the appended claims in any way.

[0120] Accordingly, an NVM device including memory cells, HKMG logic FETs, and HVFETs embedded or integrally formed on a single substrate and a method of forming the same have been disclosed. Embodiments of the invention have been described above by means of functional building blocks that illustrate specific functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries can be defined as long as the specified functions and their relationships are appropriately performed.

[0121] The foregoing description of the specific embodiments will fully disclose the general nature of the invention, such that others can, by applying knowledge within the art, readily modify and / or adapt such specific embodiments for various applications without undue experimentation, without departing from the general concept of the invention. Accordingly, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments. It should be understood that the language or terminology herein is for the purpose of description and not of limitation, such that the terminology or wording of this specification will be interpreted by those skilled in the art in light of the teachings and guidance.

[0122] The breadth and scope of the present invention should not be limited by any of the exemplary embodiments described above, but should be defined only in accordance with the appended claims and their equivalents.

Claims

1. A method of manufacturing a semiconductor device, comprising: Forming a charge trapping stack on a surface of a substrate in a memory region; Forming a gate dielectric on a surface of the substrate in a peripheral region; Depositing a first polysilicon layer and a height enhancing film on a surface of the substrate in the memory region and the peripheral region, wherein the height enhancing film includes an amorphous silicon film or a polysilicon film; Patterning the height enhancing film, the first polysilicon layer, and the charge trapping stack to form a memory gate in the memory region; Patterning the height enhancing film, the first polysilicon layer, and the gate dielectric in a high voltage region in the peripheral region to form a high voltage gate; Injecting ions to form a first source / drain region in the substrate adjacent to the high voltage gate; Depositing a second polysilicon layer on a surface of the substrate; and Planarizing the second polysilicon layer to remove a portion of the second polysilicon layer that extends above the memory gate and the high voltage gate; Wherein the first source / drain region includes ions injected into the substrate to a depth greater than a height of the high voltage gate above a surface of the substrate.

2. The method according to claim 1, wherein A channel under the high voltage gate does not have ions injected during formation of the first source / drain region.

3. The method according to claim 1, wherein, Patterning the first polysilicon layer to form the memory gate and patterning the first polysilicon layer to form the high voltage gate are simultaneously completed in a single patterning operation.

4. The method according to claim 1, further comprising: Patterning the second polysilicon layer to form a select gate in the memory region adjacent to the memory gate.

5. The method according to claim 4, further comprising: Forming a logic gate pattern in a low voltage region in the peripheral region before patterning the second polysilicon layer.

6. The method according to claim 5, further comprising: After patterning the second polysilicon layer, injecting ions to form a second source / drain region in the substrate adjacent to the logic gate pattern, the memory gate, and the select gate; And Forming spacers on sidewalls of the logic gate pattern, the high voltage gate, the memory gate, and the select gate.

7. The method according to claim 6, further comprising forming silicides above the first source / drain region and the second source / drain region adjacent to the logic gate pattern, the high voltage gate, the memory gate, and the select gate and on top surfaces of the high voltage gate and the select gate.

8. The method according to claim 6, further comprising: Depositing and planarizing an interlayer dielectric on a surface of the substrate, a top surface of the logic gate pattern being exposed through the interlayer dielectric; Removing the logic gate pattern; And Filling a gap generated in the interlayer dielectric with metal to form a high-k metal gate.

9. The method according to claim 8, wherein, The high voltage gate, the memory gate, the select gate, and the high-k metal gate include equal heights above a surface of the substrate.

10. A method of manufacturing a semiconductor device, comprising: Deposit a first polysilicon layer on a charge trapping stack formed on a surface of a substrate in a memory region and on a gate dielectric formed on the surface of the substrate in a peripheral region; Pattern the first polysilicon layer, the charge trapping stack, and the gate dielectric to form a memory gate in the memory region and a high voltage gate in a high voltage region of the peripheral region; Inject ions into the substrate adjacent to the high voltage gate to form a first source / drain region; Deposit a second polysilicon layer on the surface of the substrate; Planarize the second polysilicon layer to remove portions of the second polysilicon layer that extend above top surfaces of the memory gate and the high voltage gate; Form a logic gate pattern for a low voltage gate in a low voltage region of the peripheral region while using a remaining portion of the second polysilicon layer to protect the memory gate and the high voltage gate; And Pattern the remaining portion of the second polysilicon layer to form a select gate in the memory region adjacent to the memory gate, wherein the first source / drain region includes ions injected into the substrate to a depth greater than a height of the high voltage gate above the surface of the substrate, and a channel under the high voltage gate has no injected ions.

11. The method according to claim 10, wherein, The memory gate and the high voltage gate are made of the same material from the first polysilicon layer and include top surfaces having the same height from the substrate.

12. The method according to claim 10, further comprising, after patterning the remaining portion of the second polysilicon layer: Inject ions to form a second source / drain region in the substrate adjacent to the logic gate pattern, the memory gate, and the select gate; and Form spacers on sidewalls of the logic gate pattern, the high voltage gate, the memory gate, and the select gate.

13. The method according to claim 12, further comprising forming silicide above the first source / drain region and the second source / drain region adjacent to the logic gate pattern, the high voltage gate, the memory gate, and the select gate and on top surfaces of the high voltage gate and the select gate.

14. The method according to claim 12, further comprising: Deposit and planarize an interlayer dielectric on the surface of the substrate, a top surface of the logic gate pattern being exposed through the interlayer dielectric; Remove the logic gate pattern; And Fill a gap generated in the interlayer dielectric with metal to form a high-k metal gate.

15. The method according to claim 14, wherein The high voltage gate, the memory gate, the select gate, and the high-k metal gate include equal heights above the surface of the substrate.

16. A method of manufacturing a semiconductor device, comprising: Form a charge trapping stack on a surface of a substrate in a memory region; Form a gate dielectric on the surface of the substrate in a peripheral region; Deposit a first polysilicon layer on the surface of the substrate in the memory region and the peripheral region; Deposit a height-increasing film on the first polysilicon layer, wherein the height-increasing film includes an amorphous silicon film or a polysilicon film; Pattern the height-increasing film, the first polysilicon layer, and the charge trapping stack to form a memory gate in the memory region; and Pattern the height-increasing film, the first polysilicon layer, and the gate dielectric to form a high-voltage gate in a first region of the peripheral region; and Inject ions into the substrate adjacent to the high-voltage gate to form source / drain regions; Deposit a second polysilicon layer on the surface of the substrate; Planarize the second polysilicon layer to remove all of the height-increasing film and the portion of the second polysilicon layer that extends above the top surfaces of the memory gate and the high-voltage gate; and Pattern the remaining portion of the second polysilicon layer to form a select gate in the memory region adjacent to the memory gate.

17. The method according to claim 16, wherein, The source / drain regions include ions injected into the substrate to a depth greater than the height of the high-voltage gate above the surface of the substrate.

18. The method according to claim 16, wherein Patterning the height-increasing film, the first polysilicon layer, and the charge trapping stack to form the memory gate and patterning the height-increasing film, the first polysilicon layer, and the gate dielectric to form the high-voltage gate are completed simultaneously in a single patterning operation.

19. The method according to claim 16, further comprising forming a logic gate pattern in a second region in the peripheral region before patterning the remaining portion of the second polysilicon layer, wherein, The remaining portion of the second polysilicon layer protects the memory gate and the high-voltage gate during the formation of the logic gate pattern.

20. The method according to claim 19, further comprising, after patterning the second polysilicon layer: Deposit and planarize an interlayer dielectric on the surface of the substrate, with the top surface of the logic gate pattern exposed through the interlayer dielectric; Remove the logic gate pattern; And Fill the gap created in the interlayer dielectric with metal to form a high-k metal gate.

21. The method according to claim 20, wherein, The high-voltage gate, the memory gate, the select gate, and the high-k metal gate include equal heights above the surface of the substrate.

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