Memory chip and electronic device

Abstract

The application discloses a storage chip and an electronic device, and relates to the technical field of semiconductors. The storage chip comprises a buffer, and the buffer comprises a first stacked structure, a first conductive column, a first ferroelectric layer, a read transistor and a write transistor. The first stacked structure comprises at least one first plate line layer and first dielectric layers located on opposite sides of the first plate line layer. In the case where the number of the first plate line layers is multiple, the multiple first plate line layers are connected. The first conductive column penetrates through the first stacked structure. The first ferroelectric layer is located between the first plate line layer and the first conductive column and surrounds the first conductive column. The gate of the read transistor is connected with the first conductive column. One of the source and the drain of the write transistor is connected with the first conductive column. The above buffer is formed by using a ferroelectric memory, and the ferroelectric cache unit thereof is in a 2T1C structure. The buffer structure is simple, and the area occupied thereby is small, which is beneficial to reducing the area proportion of the buffer in the storage chip and improving the area efficiency of the storage chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a storage chip and an electronic device. BACKGROUND

[0002] In the past few decades, information technology has developed rapidly, and the computing power of the central processing unit (CPU) of an electronic device is still developing according to Moore's Law, but the performance of storage has not been significantly improved, resulting in a mismatch between the development of the performance of storage and the computing power. To improve this problem, a cache technology is introduced. In this way, when the CPU needs to read data, the required data will be first searched in the cache (or buffer), and if the data is found, it will be directly returned, and if the data is not found, it will be searched in the memory.

[0003] At present, the buffer is basically composed of static random access memory (SRAM). However, the structure of SRAM is relatively complex, for example, the storage unit thereof includes six transistors (6T), which leads to a relatively large area occupied by SRAM, thereby affecting the cell efficiency of the chip in which the SRAM is located. SUMMARY

[0004] Embodiments of the present application provide a storage chip and an electronic device, which are used to reduce the area occupied by the buffer and improve the cell efficiency of the storage chip.

[0005] To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a storage chip is provided, which includes a buffer. The buffer includes a first stacked structure, a first conductive column, a first ferroelectric layer, a read transistor and a write transistor. The first stacked structure includes at least one first plate line layer and first dielectric layers located on opposite sides of the first plate line layer. In the case where the number of first plate line layers is multiple, the multiple first plate line layers are connected. The first conductive column penetrates the first stacked structure. The first ferroelectric layer is located between the first plate line layer and the first conductive column and surrounds the first conductive column. The read transistor is located below the first stacked structure, and the gate of the read transistor is connected to the first conductive column. The write transistor is located below or above the first stacked structure, and one of the source and the drain of the write transistor is connected to the first conductive column.

[0007] The cache in the storage chip provided by the embodiments of the present application is formed by a ferroelectric memory. In the cache, the first conductive column can serve as one electrode, and the portions of each first plate line layer included in the first stack structure that surround the first conductive column can serve as another electrode, so that the first conductive column, the first ferroelectric layer surrounding the first conductive column, and the portions of each first plate line layer that surround the first conductive column, constitute a first ferroelectric capacitor. The first ferroelectric capacitor has a three-dimensional structure, which can effectively reduce the area occupied by the first ferroelectric capacitor in the plane of the first plate line layer.

[0008] Moreover, the first ferroelectric capacitor corresponding to each first conductive column, and the read transistor and the write transistor connected to the first conductive column, can constitute a ferroelectric cache unit of a 2T1C structure. The ferroelectric cache unit has a simple structure, and occupies an area smaller than the area occupied by a storage unit including 6T in an SRAM. In this way, the structure of the cache can be simplified, the area occupied by the cache can be effectively reduced, and the area ratio of the cache in the storage chip can be reduced, thereby improving the area efficiency of the storage chip.

[0009] In a possible implementation of the first aspect, the cache further includes a first wire above the first stack structure, and a first contact column extending in a first direction. The at least one first plate line layer is connected to the first wire through the first contact column. The first direction is a direction perpendicular to the plane in which the first plate line layer is located. The first wire is used to transmit an electrical signal (such as a reference voltage). By providing the first contact column and the first wire, the electrical signal transmitted by the first wire can be simultaneously (or substantially simultaneously) transmitted to the at least one first plate line layer included in the first stack structure through the first contact column, that is, to one electrode of each first ferroelectric capacitor, so as to store data in cooperation with the first ferroelectric capacitor.

[0010] In a possible implementation of the first aspect, when the number of first plate line layers is multiple, the multiple first plate line layers form multiple steps. At least one first contact column is arranged on each step, and the step is in contact with the bottom end of the at least one first contact column. The top end of the first contact column arranged on each step is in contact with the first wire. The embodiments of the present application utilize the multiple first plate line layers to form multiple steps, and arrange the first contact column on each step. By electrically connecting each layer of first plate line layer through the first wire and the first contact column, deep hole etching of the first stack structure can be avoided, and the preparation process of the cache can be simplified.

[0011] In a possible implementation of the first aspect, the buffer further includes a second contact pillar extending in a first direction. One end of the second contact pillar is in contact with the first wire, and the other end of the second contact pillar is configured to receive a reference voltage. The first direction is perpendicular to a plane in which the first plate line layer is located. The reference voltage received by the second contact pillar can be transmitted to the first plate line layer in sequence through the first wire and the first contact pillar, and cooperates with the data write to the first ferroelectric capacitor.

[0012] In a possible implementation of the first aspect, the memory chip further includes a ferroelectric internal memory. The memory chip has a storage area and a redundant area located at least one side of the storage area, the ferroelectric internal memory is located in the storage area, and the buffer is located in the redundant area. The ferroelectric internal memory can achieve high storage density. By integrating the buffer on the ferroelectric internal memory, the application can store commonly used data in the buffer, so that the buffer is located between the CPU and the ferroelectric internal memory and serves as a bridge between the CPU and the ferroelectric internal memory. In this way, when the CPU repeatedly reads the same data, the data can be directly read from the buffer, thereby effectively reducing the access frequency of the CPU to the ferroelectric internal memory and effectively reducing the time delay of the ferroelectric internal memory.

[0013] In a possible implementation of the first aspect, the ferroelectric internal memory includes a second stack structure, a second conductive pillar, and a second ferroelectric layer. The second stack structure includes a plurality of second plate line layers and a plurality of second dielectric layers alternately stacked. The second conductive pillar penetrates the second stack structure. The second ferroelectric layer is located between the second plate line layer and the second conductive pillar and surrounds the second conductive pillar. The first plate line layer and the second plate line layer are made of the same material and are arranged in the same layer, and the first dielectric layer and the second dielectric layer are made of the same material and are arranged in the same layer. In the application, the same film layer can be etched in the same patterning process to form the first plate line layer and the second plate line layer, or the same film layer can be etched in the same patterning process to form the first dielectric layer and the second dielectric layer. This means that the formation steps of the buffer are compatible with the formation steps of the ferroelectric internal memory, which is beneficial to simplify the preparation process.

[0014] In a possible implementation of the first aspect, the ferroelectric internal memory further includes a plurality of second wires located above the second stack structure. The plurality of second wires are respectively connected to the plurality of second plate line layers.

[0015] In a possible implementation of the first aspect, the pattern precision of the ferroelectric internal memory is higher than the pattern precision of the buffer. Compared with the buffer, the actual size value of the pattern (including but not limited to the pattern of the etched film layer, signal line, and deep hole) of the ferroelectric internal memory is closer to the theoretical size value.

[0016] In a possible implementation of the first aspect, the read transistor is formed by a front-end process. In this way, the performance of the read transistor can be improved, thereby facilitating an increase in the reading speed of data, a reduction in the time for reading data, and a reduction in latency.

[0017] In a possible implementation of the first aspect, the write transistor is located above the first stack structure. The write transistor is formed by a back-end process. In this way, not only can the area of the write transistor be reduced, but also the area of the orthographic projection of the write transistor and the read transistor on the plane where the first plate line layer is located can be reduced, thereby facilitating a reduction in the area of the ferroelectric cache unit, an increase in the density of the ferroelectric cache unit per unit area, and an increase in the capacity of the cache.

[0018] In a possible implementation of the first aspect, the write transistor and the read transistor orthographically overlap on the plane where the first plate line layer is located. In this way, the area of the orthographic projection of the write transistor and the read transistor on the plane where the first plate line layer is located can be further reduced, the density of the ferroelectric cache unit per unit area can be further increased, and the capacity of the cache can be further increased.

[0019] In a possible implementation of the first aspect, the cache further includes a first interconnection layer located between the read transistor and the first stack structure, and a second word line and a second bit line located above the first stack structure. The first interconnection layer includes a first word line and a first bit line, one of the source and the drain of the read transistor is electrically connected to the first word line, and the other of the source and the drain of the read transistor is electrically connected to the first bit line. The gate of the write transistor is electrically connected to the second word line, and the other of the source and the drain of the write transistor is electrically connected to the second bit line.

[0020] In a possible implementation of the first aspect, the write transistor is located below the first stack structure. The write transistor is formed by a front-end process. In this way, not only can the speed of writing data be improved, the time for writing data be reduced, and latency be further reduced, but also the write transistor and the read transistor can be simultaneously prepared, thereby facilitating a simplification of the preparation process of the cache and the storage chip and an improvement in the preparation efficiency.

[0021] In a possible implementation of the first aspect, the cache further includes a second interconnection layer located between the write transistor and the first stack structure and located between the read transistor and the first stack structure. The second interconnection layer includes a first word line, a first bit line, a second word line, and a second bit line. One of the source and the drain of the read transistor is electrically connected to the first word line, and the other of the source and the drain of the read transistor is electrically connected to the first bit line. The gate of the write transistor is electrically connected to the second word line, and the other of the source and the drain of the write transistor is electrically connected to the second bit line.

[0022] In a second aspect, an electronic device is provided. The electronic device includes a central processing unit and a storage chip as described in any of the embodiments of the first aspect.

[0023] The technical effects brought by any of the design manners in the second aspect can refer to the technical effects brought by different design manners in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 A structural schematic diagram of an electronic device provided by an embodiment of the present application is shown in the figure;

[0025] Figure 2 A schematic diagram of a CPU-to-memory access path provided by an embodiment of the present application is shown in the figure;

[0026] Figure 3 Another schematic diagram of a CPU-to-memory access path provided by an embodiment of the present application is shown in the figure;

[0027] Figure 4 A structural schematic diagram of a storage chip provided by an embodiment of the present application is shown in the figure;

[0028] Figure 5 A structural schematic diagram of a buffer provided by an embodiment of the present application is shown in the figure;

[0029] Figure 6a A cross-sectional view of the storage chip shown in the figure along the AA' direction is shown in the figure; Figure 4

[0030] A cross-sectional view of the storage chip shown in the figure along the BB' direction is shown in the figure; Figure 6b Figure 4 Another cross-sectional view of the storage chip shown in the figure along the AA' direction is shown in the figure;

[0031] Figure 7 Figure 4 Another cross-sectional view of the storage chip shown in the figure along the BB' direction is shown in the figure;

[0032] Figure 8 Another structural schematic diagram of a buffer provided by an embodiment of the present application is shown in the figure;

[0033] Figure 9a Another cross-sectional view of the storage chip shown in the figure along the AA' direction is shown in the figure; Figure 4

[0034] Another cross-sectional view of the storage chip shown in the figure along the BB' direction is shown in the figure; Figure 9b Figure 4 An equivalent circuit diagram of a ferroelectric buffer unit provided by an embodiment of the present application is shown in the figure;

[0035] Figure 10 An equivalent circuit diagram of a buffer provided by an embodiment of the present application is shown in the figure;

[0036] Figure 11

[0037] Figure 12 ​​​​A structure diagram of a read transistor and a first interconnection layer provided by an embodiment of the present application;

[0038] Figure 13 A structure diagram of a write transistor, a read transistor and a second interconnection layer provided by an embodiment of the present application; Figure 12 A sectional view of the structure shown in FIG. 2 along the direction of EE';

[0039] Figure 14 A structure diagram of a write transistor, a read transistor and a second interconnection layer provided by an embodiment of the present application;

[0040] Figure 15 A structure diagram of a write transistor, a read transistor and a second interconnection layer provided by an embodiment of the present application; Figure 14 A sectional view of the structure shown in FIG. 2 along the direction of FF';

[0041] Figure 16 A structure diagram of a ferroelectric memory provided by an embodiment of the present application;

[0042] Figure 17 A structure diagram of a write transistor, a read transistor and a second interconnection layer provided by an embodiment of the present application; Figure 4 A sectional view of the structure shown in FIG. 2 along the direction of DD'. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application.

[0044] In the description of the present application, "a plurality of" means two or more than two, unless otherwise specified. "At least one" or similar expressions mean any combination of the items, including any combination of single item or multiple items. For example, at least one of a, b, or c can mean: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple.

[0045] "and / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can mean: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it.

[0046] In addition, in order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the terms "first", "second", etc. are used to distinguish the same or similar items with basically the same function and role. Those skilled in the art can understand that the terms "first", "second", etc. do not limit the quantity and execution order, and the terms "first", "second", etc. also do not necessarily mean different. Meanwhile, in the embodiments of the present application, the words "exemplary" or "for example" are used to represent as an example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words "exemplary" or "for example" are intended to present the relevant concept in a specific manner, for ease of understanding.

[0047] In the embodiments of the present application, "up", "down", "left" and "right" are not limited to the relative positions of the components shown in the drawings, and it should be understood that these directional terms can be relative concepts, which are used for relative description and clarification, and can change accordingly according to the change of the position of the components shown in the drawings. In the drawings, the thickness of the layers and regions is exaggerated for clarity, and the size ratio relationship between the parts in the drawings does not reflect the actual size ratio relationship.

[0048] The present application describes exemplary embodiments with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and regions is exaggerated for clarity. Therefore, variations in the shape of the relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shape of the regions shown in the present application, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are essentially schematic and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0049] In addition, the architecture and scenarios described in the embodiments of the present application are used to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that as the architecture evolves and new scenarios appear, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0050] Embodiments of the present application provide an electronic device. The electronic device can be a mobile phone, a pad, a television, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, and a cellular phone, a personal digital assistant (PDA), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a smart wearable device (for example, a smart watch, a smart bracelet), an in-vehicle device, a smart home device, and / or a smart city device, and embodiments of the present application do not specially limit the specific type of the electronic device.

[0051] Figure 1 An architecture schematic diagram of an electronic device is exemplarily provided in embodiments of the present application. As shown in the figure, the electronic device 1000 includes a memory 100, a processor 200, an input device 300, an output device 400, and the like. Those skilled in the art can understand that the structure of the electronic device shown in the figure does not constitute a limitation on the electronic device 1000, and the electronic device 1000 can include more or fewer components than those shown in the figure, or can combine some of the components shown in the figure, or can be arranged differently from the components shown in the figure. Figure 1 Figure 1 Figure 1 Figure 1 Figure 1

[0052] The memory 100 is used to store software programs and modules. The memory 100 mainly includes a storage program area and a storage data area, wherein the storage program area can store an operating system, application programs required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; and the storage data area can store data created according to the use of the electronic device (such as audio data, image data, a phone book, etc.), and the like. In addition, the memory 100 includes an external memory 110 and an internal memory 120. The data stored in the external memory 110 and the internal memory 120 can be transmitted to each other. The external memory 110, for example, includes a hard disk, a U disk, a floppy disk, and the like.

[0053] ​​​​​The processor 200 is the control center of the electronic device 1000 described above, connects each part of the entire electronic device 1000 through various interfaces and lines, executes various functions of the electronic device 1000 and processes data by running or executing software programs and / or modules stored in the storage 100 and calling data stored in the storage 100, and thus monitors the entire electronic device 1000. Optionally, the processor 200 can include one or more processing units. For example, the processor 200 can include a CPU, and of course, the processor 200 can also include an artificial intelligence (AI) processor, a digital signal processor (DSP), and a neural network processor, and can also be other application specific integrated circuits (ASICs) and the like. In combination with Figures 1 to 3 Taking the processor 200 as an example of a CPU, the processor 200 can include one or more CPUs, and the CPU can include one or more cores, such as CPU 0, …, CPU N in Figure 2 and Figure 3 . The CPU can include an arithmetic unit 210 and a controller 220. The arithmetic unit 210 obtains data stored in the internal memory 120 and processes the data stored in the internal memory 120, and the result of the processing is usually sent back to the internal memory 120. The controller 220 can control the arithmetic unit 210 to process data, and the controller 220 can also control the external storage 110 and the internal memory 120 to store or read data.

[0054] The input device 300 receives input digital or character information and generates a key signal corresponding to a user setting or a function control of the electronic device 1000. For example, the input device 300 can include a touch screen and other input devices. The touch screen, also called a touch panel, can collect a user's touch operation (e.g., a user's operation using a finger, a stylus, or any suitable object or accessory near the touch screen) and drive a corresponding connection device according to a pre-set program. Optionally, the touch screen can include a touch detecting device and a touch controller. The touch detecting device detects a user's touch position and detects a signal generated by the touch operation and transmits the signal to the touch controller. The touch controller receives the touch information from the touch detecting device, converts the touch information into a touch coordinate, and transmits the touch coordinate to the processor 200. The touch controller can also receive a command from the processor 200 and execute the command. In addition, the touch screen can be implemented in various types such as a resistive type, a capacitive type, an infrared type, and a surface acoustic wave type. Other input devices can include, but are not limited to, one or more of a physical keyboard, a function key (e.g., a volume control key, a power on / off key, etc.), a trackball, a mouse, a joystick, etc. The controller 220 of the processor 200 can also control the input device 300 to receive or not to receive an input signal. In addition, the input digital or character information received by the input device 300 and the key signal generated in relation to a user setting or a function control of the electronic device can be stored in the internal memory 120.

[0055] The output device 400 outputs a signal corresponding to data input by the input device 300 and stored in the internal memory 120. For example, the output device 400 outputs a sound signal or a video signal. The controller 220 of the processor 200 can also control the output device 400 to output or not to output a signal.

[0056] It is noted that, Figure 1 The thick arrow in the above figure indicates data transmission, and the direction of the thick arrow indicates the direction of data transmission. For example, the one-way arrow between the input device 300 and the internal memory 120 indicates that data received by the input device 300 is transmitted to the internal memory 120. For another example, the two-way arrow between the arithmetic device 210 and the internal memory 120 indicates that data stored in the internal memory 120 can be transmitted to the arithmetic device 210, and data processed by the arithmetic device 210 can be transmitted to the internal memory 120. Figure 1 The thin arrow in the above figure indicates a component that can be controlled by the controller 220. For example, the controller 220 can control the external memory 110, the internal memory 120, the arithmetic device 210, the input device 300, and the output device 400.

[0057] Optionally, as Figure 1The electronic device 1000 shown can also include various sensors. For example, a gyroscope sensor, a hygrometer sensor, an infrared sensor, a magnetometer sensor, and the like, which are not described here again. Optionally, the electronic device 1000 can also include a wireless fidelity (WiFi) module, a Bluetooth module, and the like, which are not described here again.

[0058] It can be understood that the cache is a memory at a higher level in the storage hierarchy, and mainly acts as a bridge between the low-level memory and the CPU to reduce the latency of the CPU directly accessing data from the low-level memory (for example, the internal memory, also known as the internal memory, the main memory, etc.). The access path of the CPU to the main memory is as shown in Figure 2 and Figure 3 When the CPU reads data, it first looks for the required data in the cache, and if it is found, it is returned directly, and if it is not found, it is searched from the internal memory. Since the running speed of the cache is much faster than that of the internal memory, it can help the CPU run faster. The cache includes several independent cache modules, such as instruction cache (I-Cache), data cache (D-Cache), and translation lookaside buffer (TLB). The mainstream CPU generally integrates multiple levels of cache, such as the first-level cache (L1 Cache) and the second-level cache (L2 Cache) shown in Figure 2 and Figure 3 Among them, the first-level cache can be divided into a first-level instruction cache (L1I-Cache, L1I) and a first-level data cache (L1D-Cache, L1D).

[0059] For example, the above-mentioned multi-level cache can be integrated on the CPU to improve the execution efficiency of the CPU.

[0060] Optionally, a multi-level cache (for example, a three-level cache) can also be provided between the CPU and the internal memory 120, and the multi-level cache can be integrated in other chips (including but not limited to the CPU).

[0061] At present, the mainstream SRAM is basically used as the cache, and its capacity is increased. Since the structure of the SRAM is relatively complex and occupies a large area, if the SRAM is integrated in other chips, the area efficiency of the chip will be reduced.

[0062] Based on this, the embodiment of the application provides a storage chip. As shown in Figure 4 The storage chip 1 includes a cache 11.

[0063] In some embodiments, as shown in FIG. 1, the cache 11 includes a first stack structure 112, a first conductive pillar 113, a first ferroelectric layer 114, a read transistor (Tr) and a write transistor (Tw). Figures 5 to 9b

[0064] The first stack structure 112 includes at least one first plate layer 1121. For example, as shown in FIG. 2, the first stack structure 112 includes one first plate layer 1121. For another example, the first stack structure 112 includes multiple first plate layers 1121, which are stacked in the first direction Z. Among them, Figures 8 to 9b Figure 5 For example, as shown in FIG. 2, the first stack structure 112 includes three first plate layers 1121. The first plate layer 1121 is in a planar shape.

[0065] For example, the storage chip 1 has a first direction Z, a second direction X and a third direction Y. The first direction Z is a direction perpendicular to the plane of the first plate layer 1121, the second direction X is a direction parallel to the plane of the first plate layer, and the third direction Y is a direction parallel to the plane of the first plate layer, and the second direction X and the third direction Y are perpendicular to each other.

[0066] For example, the material of the first plate layer 1121 includes a metal material or other conductive material. For example, the material of the first plate layer 1121 includes a conductor material such as TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, Ag or any combination thereof.

[0067] The first stack structure 112 further includes a first dielectric layer 1122 located on opposite sides of the first plate layer 1121. The first dielectric layer 1122 and the first plate layer 1121 in the first stack structure 112 are alternately stacked in the first direction Z. The first dielectric layer 1122 is used for electrical isolation.

[0068] For example, the material of the first dielectric layer 1122 includes but is not limited to an insulating material such as SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4 or any combination thereof, and the structure of the first dielectric layer 1122 is a single-layer structure, a stacked structure or a stacked structure composed of a combination of materials.

[0069] The first conductive pillar 113 penetrates the first stack structure 112, the first ferroelectric layer 114 is located between the first plate layer 1121 and the first conductive pillar 113, and surrounds the first conductive pillar 113.

[0070] ​​For example, the first conductive pillar 113 is in a column shape (e.g., a cylinder shape) and extends along the first direction Z. The first ferroelectric layer 114 is in a tube shape (e.g., a cylinder shape), and the first conductive pillar 113 is inside the first ferroelectric layer 114 and is surrounded by the first ferroelectric layer 114. The first ferroelectric layer 114 is between the first plate line layer 1121 and the first conductive pillar 113 and separates the first plate line layer 1121 and the first conductive pillar 113. For example, the first ferroelectric layer 114 extends along the first direction Z, and the height of the first ferroelectric layer 114 is the same as or substantially the same as the height of the first conductive pillar 113, so that the first ferroelectric layer 114 is between the first conductive pillar 113 and each of the first plate line layers 1121 or each of the first dielectric layers 1122 in the first stack structure 112, which is conducive to simplifying the manufacturing process of the cache 11.

[0071] For example, the material of the first conductive pillar 113 includes a metal material or other conductive material. For example, the material of the first conductive pillar 113 includes a conductor material such as TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, Ag, or any combination thereof. The first ferroelectric layer 114 includes, for example, hafnium-based ferroelectric dielectric (or HfO2-based ferroelectric dielectric). The material of the first ferroelectric layer 114 includes, but is not limited to, ZrO2, HfO2, Al-doped HfO2, Si-doped HfO2, Zr-doped HfO2, La-doped HfO2, Y-doped HfO2, or other element-doped materials based on the material (e.g., HfO2) and any combination thereof.

[0072] The first ferroelectric layer 114 can act as an insulating medium, so that the part of the first plate line layer 1121 surrounding the first ferroelectric layer 114 and the first conductive pillar 113 can act as one electrode, and the part of the first conductive pillar 113 opposite to the first plate line layer 1121 can act as another electrode, together with the first ferroelectric layer 114 to form a capacitor. By using the material of the first ferroelectric layer 114, which can spontaneously polarize and the polarization state can be reoriented under the action of an external electric field, the capacitor can store data.

[0073] In the aforementioned first stacked structure 112, when the number of first board line layers 1121 is multiple, the thickness of each first board line layer 1121 can be the same or different, and the thickness of each first dielectric layer 1122 can be the same or different, which can be set according to actual needs. Furthermore, in the manufacturing process of the first stacked structure 112, different numbers of stacked layers correspond to different stacking heights. For example, the number of film layers stacked in the first stacked structure 112 can be dozens or even hundreds of layers (e.g., 32 layers, 64 layers, or 128 layers, etc.). The more film layers included in the first stacked structure 112, the higher the integration of the buffer 11; the more capacitors there are, the larger the capacity of the buffer 11. The number of stacked layers and the stacking height of the first stacked structure 112 can be designed according to actual needs or manufacturing process conditions, and this application does not impose any limitations on this.

[0074] Optionally, when the number of first plate line layers 1121 is one, the portion of the first plate line layer 1121 surrounding the first ferroelectric layer 114 and the first conductive pillar 113, the portion of the first conductive pillar 113 opposite to the first plate line layer 1121, and the capacitor formed by the first ferroelectric layer 114 can be called the first ferroelectric capacitor C1.

[0075] Optionally, when there are multiple first plate line layers 1121, the capacitor formed by the portion surrounding the first ferroelectric layer 114 and the first conductive pillar 113 in each first plate line layer 1121, the portion of the first conductive pillar 113 opposite to the first plate line layer 1121, and the portion of the first ferroelectric layer 114 opposite to the first plate line layer 1121 can be called a sub-ferroelectric capacitor C11.

[0076] like Figures 5 to 7 As shown, when there are multiple layers of the first board line layer 1121, these multiple layers of the first board line layer 1121 are connected. This allows one pole of the sub-ferroelectric capacitor C11 corresponding to each layer of the first board line layer 1121 to be electrically connected (or connected in parallel). For multiple sub-ferroelectric capacitors C11 corresponding to the same first conductive post 113, the first conductive post 113 can serve as a common electrode, allowing the other poles of the multiple sub-ferroelectric capacitors C11 to be electrically connected (or connected in parallel). This also allows the multiple sub-ferroelectric capacitors C11 corresponding to the same first conductive post 113 to be connected in parallel. The multiple sub-ferroelectric capacitors C11 connected in parallel can be equivalent to one first ferroelectric capacitor C1. The equivalent circuit of the multiple sub-ferroelectric capacitors C11 corresponding to the same first conductive post 113 is as follows: Figure 10 As shown in (a), the first ferroelectric capacitor C1 is equivalent to the plurality of sub-ferroelectric capacitors C11 as follows: Figure 10As shown in (b) of FIG. 1, the equivalent first ferroelectric capacitor C1 is in parallel connection with the plurality of sub-ferroelectric capacitors C11. At this time, the capacitance of the equivalent first ferroelectric capacitor C1 is the sum of the capacitances of the plurality of sub-ferroelectric capacitors C11 arranged in parallel. This is advantageous for increasing the capacitance of the equivalent first ferroelectric capacitor C1.

[0077] It can be understood that, since the first conductive column 113 extends along the first direction Z, the plurality of sub-ferroelectric capacitors C11 corresponding to the first conductive column 113 are arranged in sequence along the first direction Z, that is, arranged in sequence along the direction perpendicular to the plane where the first plate line layer 1121 is located. This makes the orthographic projection of the plurality of sub-ferroelectric capacitors C11 on the plane where the first plate line layer 1121 is located coincide, and further makes the area occupied by the plurality of sub-ferroelectric capacitors C11 on the plane where the first plate line layer 1121 is located the same as the area occupied by one sub-ferroelectric capacitor C11 on the plane where the first plate line layer 1121 is located.

[0078] Correspondingly, in the case where the number of the first plate line layers 1121 is one layer, the area occupied by the first ferroelectric capacitor C1 on the plane where the first plate line layer 1121 is located is basically the same as the area occupied by the first ferroelectric capacitor C1 on the plane where the number of the first plate line layers 1121 is multiple layers. That is, the area occupied by the first ferroelectric capacitor C1 on the plane where the first plate line layer 1121 is located is irrelevant to the number of the first plate line layers 1121 included in the first stack structure 112, and irrelevant to the number of the sub-ferroelectric capacitors C11 included in the first ferroelectric capacitor C1 itself.

[0079] For example, the number of the first conductive columns 113 penetrating through the first stack structure 112 is multiple, and the multiple first conductive columns 113 are arranged in an array. Correspondingly, the number of the first ferroelectric layers 114 corresponding to the first conductive columns 113 is also multiple. Since each first conductive column 113 corresponds to one first ferroelectric capacitor C1, the first stack structure 112 and the multiple first conductive columns 113 described above can constitute multiple first ferroelectric capacitors C1 arranged in an array. The multiple first ferroelectric capacitors C1 are in a three-dimensional stack structure, which is advantageous for reducing the area occupied on the plane where the first plate line layer 1121 is located.

[0080] The read transistor Tr is located below the first stack structure 112, and the write transistor Tw is located below or above the first stack structure 112. For example, Figure 7 schematically showing that the read transistor Tr and the write transistor Tw are both located below the first stack structure 112, Figure 6a and Figure 6b schematically showing that the read transistor Tr is located below the first stack structure 112, and the write transistor Tw is located above the first stack structure 112.

[0081] The gate of the read transistor Tr is connected with the first conductive column 113, and one of the source and the drain of the write transistor Tw is connected with the first conductive column 113. The write transistor Tw is used to write data into the first ferroelectric capacitor C1, the first ferroelectric capacitor C1 is used to store the written data, and the read transistor Tr is used to read the data stored in the first ferroelectric capacitor C1. For example, when the CPU reads the data stored in the cache 11, the cache 11 can keep powered on, reducing the time of the first ferroelectric capacitor C1 flipping, so that the cache 11 has a faster reading speed.

[0082] For example, the number of read transistors Tr is multiple, and the number of write transistors Tw is multiple. Each first conductive column 113 is connected with a read transistor Tr and a write transistor Tw, and constitutes a ferroelectric cache unit FCC. Since the first ferroelectric capacitor C1 has a three-dimensional structure, it is beneficial to realize the miniaturization of the ferroelectric cache unit FCC, so as to integrate more ferroelectric cache units FCC in a unit area, increase the capacity of the cache 11, and facilitate the design of a super-capacity cache.

[0083] The ferroelectric cache unit FCC described above only includes two transistors (T) and one capacitor (C), and has a 2T1C structure. Compared with the basic structure (or cache unit) of SRAM, the number of transistors is smaller, the structure is simpler, and the area occupied is smaller.

[0084] Therefore, the cache 11 in the storage chip 1 provided by the embodiments of the present application is formed by using a ferroelectric memory. In the cache 11, the first conductive column 113 can serve as one electrode, and the portions of the first plate line layers 1121 included in the first stack structure 112 and surrounding the first conductive column 113 can serve as another electrode, so that the first conductive column 113, the first ferroelectric layer 114 surrounding the first conductive column 113, and the portions of the first plate line layers 1121 surrounding the first conductive column 113 constitute a first ferroelectric capacitor C1. The first ferroelectric capacitor C1 has a three-dimensional structure, which can effectively reduce the area occupied by the first ferroelectric capacitor C1 in the plane of the first plate line layer 1121.

[0085] Moreover, the first ferroelectric capacitor C1 corresponding to each first conductive column 113, and the read transistor Tr and the write transistor Tw connected with the first conductive column 113, can constitute a 2T1C structure ferroelectric cache unit FCC. The ferroelectric cache unit FCC has a simple structure, and the area occupied by the ferroelectric cache unit FCC is smaller than the area occupied by the storage unit including 6T in the SRAM. In this way, the structure of the cache 11 can be simplified, the area occupied by the cache 11 can be effectively reduced, and the area ratio of the cache 11 in the storage chip 1 can be reduced, thereby improving the area efficiency of the storage chip 1.

[0086] In some embodiments, as shown in Figure 4 The cache 11 includes one or more cache cell sub-arrays 111.

[0087] In the case where the cache 11 includes a plurality of cache cell sub-arrays 111, the plurality of cache cell sub-arrays 111 are arranged in multiple columns along the second direction X, and each column of cache cell sub-arrays 111 includes a plurality of cache cell sub-arrays 111 arranged in sequence along the third direction Y; the plurality of cache cell sub-arrays 111 are arranged in multiple rows along the third direction Y, and each row of cache cell sub-arrays 111 includes a plurality of cache cell sub-arrays 111 arranged in sequence along the second direction X. This facilitates improving the arrangement regularity of the cache cell sub-arrays 111 and reducing the manufacturing difficulty of the cache 11.

[0088] It can be understood that the number of the first stack structures 112 described above can be one or more. In the case where the cache 11 includes a cache cell sub-array 111, one cache cell sub-array 111 includes one first stack structure 112, for example.

[0089] In some embodiments, as shown in Figure 5 and Figure 8 The cache 11 further includes a first wire DL1 and a first contact pillar 115. The first wire DL1 is located above the first stack structure 112, and the first contact pillar 115 extends along the first direction Z, and at least one layer of the first plate line layer 1121 included in the first stack structure 112 is connected to the first wire DL1 through the first contact pillar 115.

[0090] For example, the material of the first wire DL1 includes a conductor material such as TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, Ag, or any combination thereof. The material of the first contact pillar 115 includes a conductor material such as TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, Ag, or any combination thereof.

[0091] In the case where the number of the first plate line layers 1121 in the first stack structure 112 is multiple, the first wire DL1 is connected to the multiple first plate line layers 1121 through the first contact pillar 115, which can connect the multiple first plate line layers 1121 together, and further cause the multiple sub-ferroelectric capacitors C11 corresponding to the multiple first plate line layers 1121 to form a parallel connection.

[0092] The first wire DL1 is used to transmit an electrical signal (e.g. a reference voltage). By providing the first contact pillar 115 and the first wire DL1, the electrical signal transmitted by the first wire DL1 can be simultaneously (or substantially simultaneously) transmitted to at least one first plate line layer 1121 included in the first stack structure 112 (i.e. to one electrode of each first ferroelectric capacitor C1) via the first contact pillar 115, so as to store data in cooperation with the first ferroelectric capacitor C1.

[0093] In the case where the number of the first plate line layers 1121 in the first stack structure 112 is multiple, the connection between the first contact pillar 115 and the multiple first plate line layers 1121 can be in various manners.

[0094] For example, the first contact pillar 115 penetrates through the first stack structure 112 and contacts the portion of each first plate line layer 1121 surrounding the first contact pillar 115, so as to electrically connect each first plate line layer 1121 together via the first contact pillar 115.

[0095] For example, as shown in Figs. 1 and 2, the first contact pillar 115 is arranged on the first plate line layer 1121 of the first stack structure 112. Figure 6a and Figure 7 For example, as shown in Figs. 1 and 2, the first contact pillar 115 is arranged on the first plate line layer 1121 of the first stack structure 112.

[0096] For example, as shown in Figs. 1 and 2, the first contact pillar 115 is arranged on the first plate line layer 1121 of the first stack structure 112. Figure 6a and Figure 7 For example, as shown in Figs. 1 and 2, the first contact pillar 115 is arranged on the first plate line layer 1121 of the first stack structure 112.

[0097] For example, as shown in Figs. 1 and 2, the first contact pillar 115 is arranged on the first plate line layer 1121 of the first stack structure 112. Figure 6a and Figure 7 For example, as shown in Figs. 1 and 2, the first contact pillar 115 is arranged on the first plate line layer 1121 of the first stack structure 112.

[0098] The embodiment of the present application forms a plurality of steps by using the above-mentioned multi-layer first plate line layer 1121, and sets a first contact column 115 on each step, and electrically connects each layer of the first plate line layer 1121 together through the first conductive line DL1 and the first contact column 115, so that deep hole etching of the first stack structure 112 can be avoided, and the preparation process of the buffer 11 can be simplified.

[0099] In some embodiments, as shown in Figure 5 and Figure 8 The buffer 11 further comprises a second contact column 116 extending along the first direction Z. One end of the second contact column 116 is in contact with the first conductive line DL1, and the other end of the second contact column 116 is used to receive a reference voltage.

[0100] The second contact column 116 is in contact with the first conductive line DL1 to form an electrical connection, so that the electrical connection with the first plate line layer 1121 can be realized through the first conductive line DL1 and the first contact column 115, and the electrical connection with the first ferroelectric capacitor C1 can be realized. The reference voltage received by the second contact column 116 can be transmitted to the first plate line layer 1121 in turn through the first conductive line DL1 and the first contact column 115, that is, transmitted to the first ferroelectric capacitor C1, and cooperates with the data writing of the first ferroelectric capacitor C1.

[0101] For example, the above-mentioned reference voltage can be called a bias voltage, and the voltage value is, for example, 1 / 2VDD.

[0102] For example, as shown in Figure 5 and Figure 8 The above-mentioned second contact column 116 is located below the first conductive line DL1, the top end of the second contact column 116 is in contact with the first conductive line DL1, and the bottom end is used to receive the reference voltage. In this way, during the preparation of the buffer 11, the first contact column 115 and the second contact column 116 can be prepared at the same time, so as to simplify the preparation process of the buffer 11.

[0103] In some embodiments, as shown in Figure 11 The buffer 11 further comprises a first word line RWL, a first bit line RBL, a second word line WWL and a second bit line WBL. Figure 11 An equivalent circuit diagram of a buffer 11 is shown, Figure 11 in which a solid circle represents the first conductive line DL1.

[0104] For example, the gate of the read transistor Tr is electrically connected with the first pole (i.e., the first conductive pillar 113) of the first ferroelectric capacitor C1, one of the source and the drain of the read transistor Tr is electrically connected with the first word line RWL, and the other of the source and the drain of the read transistor Tr is electrically connected with the first bit line RBL. The second pole (i.e., the first plate line layer 1121) of the first ferroelectric capacitor C1 is electrically connected with the first conductive line DL1. The gate of the write transistor Tw is electrically connected with the second word line WWL, one of the source and the drain (e.g., the drain) of the write transistor Tw is electrically connected with the first pole of the first ferroelectric capacitor C1, and the other of the source and the drain (e.g., the source) of the write transistor Tw is electrically connected with the second bit line WBL. The node where the write transistor Tw, the first ferroelectric capacitor C1 and the read transistor Tr meet is referred to as a storage node (SN) for example.

[0105] Optionally, as shown in FIG. 1B, the number of the first word lines RWL is plural, and the plural first word lines RWL extend along the second direction X and are arranged in sequence along the third direction Y for example. The number of the first bit lines RBL is plural, and the plural first bit lines RBL extend along the third direction Y and are arranged in sequence along the second direction X for example. The plural read transistors Tr in a row of ferroelectric cache units FCC are electrically connected with the same first word line RWL, and the plural read transistors Tr in a column of ferroelectric cache units FCC are electrically connected with the same first bit line RBL. Figure 11 Optionally, as shown in FIG. 1B, the number of the first word lines RWL is plural, and the plural first word lines RWL extend along the second direction X and are arranged in sequence along the third direction Y for example. The number of the first bit lines RBL is plural, and the plural first bit lines RBL extend along the third direction Y and are arranged in sequence along the second direction X for example. The plural read transistors Tr in a row of ferroelectric cache units FCC are electrically connected with the same first word line RWL, and the plural read transistors Tr in a column of ferroelectric cache units FCC are electrically connected with the same first bit line RBL.

[0106] Figure 11 Optionally, as shown in FIG. 1B, the number of the second word lines WWL is plural, and the plural second word lines WWL extend along the second direction X and are arranged in sequence along the third direction Y for example. The number of the second bit lines WBL is plural, and the plural second bit lines WBL extend along the third direction Y and are arranged in sequence along the second direction X for example. The plural write transistors Tw in a row of ferroelectric cache units FCC are electrically connected with the same second word line WWL, and the plural write transistors Tw in a column of ferroelectric cache units FCC are electrically connected with the same second bit line WBL.

[0107] ​For example, the second word line WWL is used to control the turn-on or turn-off of the write transistor Tw electrically connected thereto, and the second bit line WBL is used to write data to the first ferroelectric capacitor Cl through the write transistor Tw. When writing data into the first ferroelectric capacitor Cl, the second contact column 116 receives a reference voltage and transmits the reference voltage to the second pole of the first ferroelectric capacitor Cl through the first lead line DL1; the second word line WWL controls the turn-on of the write transistor Tw, and the first pole of the first ferroelectric capacitor Cl is connected to the second bit line WBL, so that the voltage on the second bit line WBL can be transmitted to the first pole of the first ferroelectric capacitor Cl, a voltage difference is formed between the two poles of the first ferroelectric capacitor Cl, and data is written into the first ferroelectric capacitor Cl. When reading the data stored in the first ferroelectric capacitor Cl, the voltage of one of the first word line RWL and the first bit line RBL is adjusted to form a voltage difference therebetween, and the read transistor Tr is turned on, so that the data stored in the first ferroelectric capacitor Cl can be obtained by detecting the current between the source and the drain of the read transistor Tr. When the CPU accesses the cache 11, the data stored in the cache 11 can be read by the above method. Of course, the above is only an example of writing and reading data of the ferroelectric cache unit FCC, and does not limit the method of writing and reading data of the cache 11.

[0108] It can be understood that the arrangement of the write transistor Tw and the read transistor Tr in the cache 11 can include various arrangements, which can be selected according to actual needs.

[0109] In some possible embodiments, as shown in Figure 6a The read transistor Tr is formed by a front end of line (FEOL) process.

[0110] For example, the above-mentioned "read transistor Tr is formed by a front end of line (FEOL) process" means that in the process of forming the read transistor Tr, the area for preparing the read transistor Tr can be first divided on a semiconductor substrate (for example, a silicon substrate); then ion implantation is performed in the above-mentioned area by an ion implantation process to form an active region; then a gate dielectric layer and a gate electrode are formed on the active region; then ion implantation is performed on the part of the active region not covered by the gate dielectric layer and the gate electrode to form a source region (or source electrode) and a drain region (or drain electrode), thereby obtaining a metal oxide semiconductor field effect transistor (MOSFET) which can be used as the read transistor Tr. The read transistor Tr can also be referred to as a front end transistor (FEOL MOSFET).

[0111] The read transistor Tr is formed by a front-end process, which can improve the performance of the read transistor Tr, and thus improve the reading speed of data, reduce the time for reading data, and reduce the time delay.

[0112] In some possible embodiments, as shown in Figure 6a and Figure 6b the write transistor Tw is located above the first stack structure 112 and is formed by a back-end-of-line (BEOL) process.

[0113] For example, the write transistor Tw is formed by a back-end-of-line process, which means that, in the process of forming the write transistor Tw, a metal-oxide semiconductor field effect transistor is prepared on a substrate (including but not limited to a semiconductor substrate and a film layer stack structure) by using processes including but not limited to deposition, exposure, development, and etching, and the field effect transistor can be used as the write transistor Tw. The write transistor Tw can also be referred to as a back-end-of-line MOSFET (BEOL MOSFET).

[0114] Optionally, the write transistor Tw includes but is not limited to a gate-all-around field effect transistor (GAA FET), a channel-all-around field effect transistor (CAA FET), and a vertical planar channel transistor.

[0115] The write transistor Tw is formed by a back-end-of-line process, so that the write transistor Tw has a small area of a normal projection on a plane where the first plate line layer 1121 is located. This can reduce the area of a normal projection of the ferroelectric cache unit FCC on the plane where the first plate line layer 1121 is located, increase the density of the ferroelectric cache unit FCC in a unit area, and improve the capacity of the cache 11.

[0116] It can be understood that, in the case where the read transistor Tr is formed by a front-end process, the read transistor Tr is located below the first stack structure 112. This means that, as shown in Figure 6a and Figure 6b the write transistor Tw and the read transistor Tr are located on opposite sides of the first stack structure 112 along the first direction Z. The read transistor Tr is electrically connected to the bottom end of the first conductive pillar 113 (i.e., the first electrode of the first ferroelectric capacitor C1). The write transistor Tw is electrically connected to the top end of the first conductive pillar 113.

[0117] In this way, the projection area of the write transistor Tw and the read transistor Tr on the plane of the first plate line layer 1121 can be reduced, and the projection area of the ferroelectric cache unit FCC on the plane of the first plate line layer 1121 can be reduced, so that the density of the ferroelectric cache unit FCC in a unit area can be increased, and the capacity of the cache 11 can be increased.

[0118] In some examples, the projection of the write transistor Tw and the read transistor Tr on the plane of the first plate line layer 1121 overlaps. For example, the projection of the write transistor Tw and the read transistor Tr on the plane of the first plate line layer 1121 coincides or partially coincides. The area of the projection of the write transistor Tw and the read transistor Tr on the plane of the first plate line layer 1121 is only the projection area of one transistor on the plane of the first plate line layer 1121 or slightly larger than the projection area of one transistor on the plane of the first plate line layer 1121.

[0119] In this way, the projection area of the write transistor Tw and the read transistor Tr on the plane of the first plate line layer 1121 can be further reduced, and the projection area of the ferroelectric cache unit FCC on the plane of the first plate line layer 1121 can be further reduced, so that the density of the ferroelectric cache unit FCC in a unit area can be further increased, and the capacity of the cache 11 can be further increased.

[0120] In some examples, as shown in Figure 6a and Figure 6b The cache 11 further includes a first interconnection layer 117 between the read transistor Tr and the first stack structure 112. The first interconnection layer 117 includes the first word line RWL and the first bit line RBL.

[0121] Figure 12 A top view structure of the read transistor Tr and the first interconnection layer 117 is shown, Figure 13 A cross-sectional structure of the read transistor Tr and the first interconnection layer 117 along EE' direction is shown. The first word line RWL and the first bit line RBL are located in the first interconnection layer 117, and are located in different layers. The gate of the read transistor Tr is electrically connected to the first conductive column 113 through the conductive block in the first interconnection layer 117, the first electrode of the read transistor Tr is electrically connected to the first bit line RBL through the conductive block in the first interconnection layer 117, and the second electrode of the read transistor Tr is electrically connected to the first word line RWL through the conductive block in the first interconnection layer 117.

[0122] As shown in Figure 6a and Figure 6b The second word line WWL and the second bit line WBL are located above the first stack structure 112. Figure 6a and Figure 6bThe structure shown takes the write transistor Tw as an example of a ring-gate field effect transistor, a part of the second word line WWL serving as the control electrode of the write transistor Tw, and a part of the second bit line WBL serving as the other of the source electrode and the drain electrode of the write transistor Tw.

[0123] In yet some possible embodiments, as Figure 7 The write transistor Tw is located below the first stacked structure 112, and the write transistor Tw is formed by a front-end process, as shown.

[0124] It can be understood that, in the case where the read transistor Tr is formed by a front-end process, the read transistor Tr is also located below the first stacked structure 112. In this way, the write transistor Tw and the read transistor Tr can both be referred to as front-end transistors, and both are located on the same side of the first stacked structure 112, i.e., below the first stacked structure 112. The write transistor Tw and the read transistor Tr are both electrically connected to the bottom end of the first conductive column 113.

[0125] With the above arrangement, the performance of the write transistor Tw and the read transistor Tr can be improved at the same time. In this way, not only can the speed of writing data be improved and the time of writing data be reduced, but also the speed of reading data can be improved and the time of reading data can be reduced, which is further conducive to reducing the time delay.

[0126] Moreover, by arranging the write transistor Tw and the read transistor Tr on the same side of the first stacked structure 112, the write transistor Tw and the read transistor Tr can be formed synchronously in the process of manufacturing the write transistor Tw and the read transistor Tr, which is conducive to simplifying the manufacturing process of the buffer 11 and the memory chip 1 and improving the manufacturing efficiency.

[0127] In some examples, as Figure 7 The buffer 11 further includes a second interconnection layer 118 located between the write transistor Tw and the first stacked structure 112 and located between the read transistor Tr and the first stacked structure 112, as shown. The second interconnection layer 118 includes the first word line RWL, the first bit line RBL, the second word line WWL, and the second bit line WBL.

[0128] Figure 14 A top view structure of the write transistor Tw, the read transistor Tr, and the second interconnection layer 118 is shown, Figure 15A cross-sectional structure of the write transistor Tw, the read transistor Tr and the second interconnection layer 118 along the FF' direction is shown. The second word line WWL, the second bit line WBL, the first word line RWL and the first bit line RBL are located in the second interconnection layer 118, and the second bit line WBL and the first bit line RBL are located in the same layer, the second word line WWL and the first word line RWL are located in the same layer, the second bit line WBL and the first bit line RBL, and the second word line WWL and the first word line RWL, are located in different layers. The gate of the write transistor Tw is electrically connected with the second word line WWL through the conductive block located in the second interconnection layer 118, one of the source and the drain of the write transistor Tw is electrically connected with the first conductive column 113 through the conductive block in the second interconnection layer 118, and the other of the source and the drain of the write transistor Tw is electrically connected with the second bit line WBL through the conductive block in the second interconnection layer 118. The gate of the read transistor Tr is electrically connected with the first conductive column 113 through the conductive block located in the second interconnection layer 118, one of the source and the drain of the read transistor Tr is electrically connected with the first word line RWL through the conductive block in the second interconnection layer 118, and the other of the source and the drain of the read transistor Tr is electrically connected with the first bit line RBL through the conductive block in the second interconnection layer 118.

[0129] In some embodiments, as shown in FIG. 1, the storage chip 1 further includes an internal memory, which is a ferroelectric internal memory 12. That is, the internal memory is formed by ferroelectric random access memory (FRAM). The ferroelectric random access memory can be referred to as ferroelectric memory for short. Figure 4

[0130] Optionally, the storage chip 1 provided by the embodiments of the present application can include the internal memory 120 in the electronic device 1000. For example, the ferroelectric internal memory 12 in the storage chip 1 provided by the embodiments of the present application can be used as the internal memory 120 in the storage 100.

[0131] The storage chip 1 has a memory array (MA) and a redundant array (DA) located at least on one side of the memory array MA. For example, the redundant array DA can be located on one side, two sides, etc. of the memory array MA, or, as shown in FIG. 1, the redundant array DA can surround the memory array MA. Optionally, the ferroelectric internal memory 12 is located in the memory array MA, and the buffer 11 is located in the redundant array DA. That is, the ferroelectric internal memory 12 and the buffer 11 are integrated together, and the buffer 11 is located at the periphery of the ferroelectric internal memory 12, and the two together constitute the storage chip 1. Figure 4

[0132] ​​In an implementation, the above memory is usually a dynamic random access memory (DRAM). The DRAM includes a plurality of memory cells, each of which includes a transistor and a capacitor, so that each memory cell is in a 1T1C architecture. Each capacitor is used to store 1 bit of data, so that each memory cell can also store 1 bit of data.

[0133] After the feature size of the DRAM is reduced to 20 nm or less, continuous size reduction becomes more and more difficult, which makes the development of the DRAM encounter a bottleneck, resulting in a great limitation on the improvement of the storage density of the DRAM. Since the ferroelectric memory can realize a three-dimensional stacked structure, the ferroelectric memory 12 provided by the embodiments of the present application can realize a storage density much higher than that of the DRAM.

[0134] It can be understood that the working phase (or operation timing) of the above DRAM includes a charging operation, a sense operation, a column access operation, and a precharge operation, which are performed in sequence. The working phase (or operation timing) of the ferroelectric memory 12 includes a precharge operation, a swith operation, a sense operation, a column access operation, a restore operation, and a postcharge operation, which are performed in sequence. The meanings of the swith operation and the charging operation are the same, and since the flipping of the second ferroelectric capacitor (see the description below for the second ferroelectric capacitor, which will not be described here again) in the ferroelectric memory 12 is destructive, the restore operation is needed to restore the data. The postcharge operation is to reset the voltage of the floating common electrode (i.e., the second plate line layer mentioned below).

[0135] As can be seen from the above, compared with the DRAM, the ferroelectric memory 12 can realize a high storage density, but needs additional restore operation and postcharge operation in the operation timing, which will increase the overall delay of the ferroelectric memory 12.

[0136] The embodiment of the present application can store the commonly used data in the cache 11 by integrating the cache 11 on the ferroelectric memory 12, so that the cache 11 is located between the CPU and the ferroelectric memory 12 and serves as a bridge between the CPU and the ferroelectric memory 12. Although the capacity of the cache 11 is smaller than that of the ferroelectric memory 12, the reading speed of the cache 11 is fast, so that when the CPU repeatedly reads the same data, the data can be directly read from the cache 11, thereby effectively reducing the access times of the CPU to the ferroelectric memory 12 and effectively reducing the time delay of the ferroelectric memory 12.

[0137] For example, in the storage chip 1, the ferroelectric memory 12 and the cache 11 can be electrically connected. Alternatively, the ferroelectric memory 12 and the cache 11 are not electrically connected.

[0138] In some embodiments, the pattern accuracy of the ferroelectric memory 12 is higher than that of the cache 11. Here, the "pattern accuracy" refers to the closeness between the actual size value and the theoretical size value of the pattern such as the film layer, the signal line and the deep hole formed by etching in the process of manufacturing the ferroelectric memory 12 or the cache 11. Compared with the cache 11, the actual size value of the pattern of the ferroelectric memory 12 is closer to the theoretical size value.

[0139] It can be understood that in the process of manufacturing the memory 12 on the wafer (or semiconductor substrate), since the process error of the core area (for example, the storage area MA) of the wafer is smaller than that of the peripheral area (for example, the redundant area DA) of the wafer, when the ferroelectric memory 12 is formed in the storage area MA, a virtual ferroelectric memory (which does not store data, for example, is not connected to the signal line) is simultaneously formed in the redundant area DA, so as to meet the storage density requirement of the ferroelectric memory 12, ensure the manufacturability of the ferroelectric memory 12 and improve the pattern accuracy of the ferroelectric memory 12 (or the key device).

[0140] This means that the embodiment of the present application can reuse the above-mentioned virtual ferroelectric memory to form the cache 11, that is, reuse the existing structure of the storage chip 1 to form the cache 11, so as to integrate the cache 11 and the ferroelectric memory 12. In this way, on the basis of improving the pattern accuracy of the ferroelectric memory 12, ensuring the storage density requirement and the manufacturability of the ferroelectric memory 12, the manufacturing process of the cache 11 is compatible with the manufacturing process of the ferroelectric memory 12, and the cache does not need to be formed in the area other than the ferroelectric memory 12 and the virtual ferroelectric memory, which greatly improves the area utilization rate of the storage chip 1 and is beneficial to further reducing the area overhead of the cache 11.

[0141] In some embodiments, asFigure 16 and Figure 17 As shown in FIG. 12, the ferroelectric in-memory 12 includes a second stack structure 122, a second conductive pillar 123, and a second ferroelectric layer 124.

[0142] As shown in FIG. 13, the second stack structure 122 includes a plurality of second plate line layers 1221 and a plurality of second dielectric layers 1222 which are alternately stacked. Figure 17 As shown in FIG. 13, the second stack structure 122 includes a plurality of second plate line layers 1221 and a plurality of second dielectric layers 1222 which are alternately stacked.

[0143] As shown in FIG. 13, the second stack structure 122 includes a plurality of second plate line layers 1221 and a plurality of second dielectric layers 1222 which are alternately stacked. Figure 16 and Figure 17 As shown in FIG. 12, the ferroelectric in-memory 12 includes a second stack structure 122, a second conductive pillar 123, and a second ferroelectric layer 124.

[0144] For example, the second conductive pillar 123 is in a column shape (e.g., a cylinder shape) and extends along the first direction Z. The second ferroelectric layer 124 is in a tube shape (e.g., a cylinder shape), and the second conductive pillar 123 is located inside the second ferroelectric layer 124 and is surrounded by the second ferroelectric layer 124. The second ferroelectric layer 124 is located between the second plate line layer 1221 and the second conductive pillar 123 and separates the second plate line layer 1221 and the second conductive pillar 123. For example, the second ferroelectric layer 124 extends along the first direction Z, and the height of the second ferroelectric layer 124 is the same as or approximately the same as the height of the second conductive pillar 123, so that the second ferroelectric layer 124 is located between the second conductive pillar 123 and each second plate line layer 1221 or each second dielectric layer 1222 in the second stack structure 122, which is conducive to simplifying the preparation process of the ferroelectric in-memory 12.

[0145] The second ferroelectric layer 124 can act as an insulating medium, so that the part of the second plate line layer 1221 surrounding the second ferroelectric layer 124 and the second conductive pillar 123 and the part of the second conductive pillar 123 opposite to the second plate line layer 1221 can act as two electrodes and form a second ferroelectric capacitor C2 together with the second ferroelectric layer 124. By using the material of the second ferroelectric layer 124 which can spontaneously polarize and whose polarization state can be reoriented under the action of an external electric field, the second ferroelectric capacitor C2 can store data. Each second ferroelectric capacitor C2 is used to store 1 bit of data.

[0146] In the second stack structure 122, the thickness of each second plate line layer 1221 can be the same or different, and the thickness of each second dielectric layer 1222 can be the same or different, which can be set according to actual needs. In addition, in the production process of the second stack structure 122, different stack layers correspond to different stack heights. For example, the number of layers of the film layers in the second stack structure 122 can be tens of layers or even hundreds of layers (for example, 32 layers, 64 layers, or 128 layers, etc.). The more layers of film layers included in the second stack structure 122, the higher the integration of the ferroelectric memory 12, and the larger the storage density of the ferroelectric memory 12. The number of layers and the stack height of the second stack structure 122 can be designed according to actual needs or preparation process conditions, which is not limited in the present application.

[0147] For example, the second plate line layer 1221 has a large area and can be used as a common electrode. During the flipping operation and the write-back operation of the second ferroelectric capacitor C2, the voltage on the second plate line layer 1221 needs to be toggled. This results in large power consumption and operation delay of the ferroelectric memory 12. The embodiment of the present application can effectively reduce the access frequency of the CPU to the ferroelectric memory 12 by integrating the buffer 11 on the ferroelectric memory 12, thereby reducing the operation frequency of the second ferroelectric capacitor C2 (or the second plate line layer 1221) in the ferroelectric memory 12, reducing the power consumption of the ferroelectric memory 12, improving the power efficiency, and reducing the operation delay of the ferroelectric memory 12.

[0148] In some examples, the first plate line layer 1121 and the second plate line layer 1221 are made of the same material and are arranged in the same layer, and the first dielectric layer 1122 and the second dielectric layer 1222 are made of the same material and are arranged in the same layer.

[0149] Herein, in the present application, “the same layer” refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate to form by one-time patterning process. According to different specific patterns, the one-time patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous, and these specific patterns can also be at different heights or have different thicknesses.

[0150] That is, the embodiments of the present application can etch the same film layer to form the first plate line layer 1121 and the second plate line layer 1221 in the same patterning process, or the embodiments of the present application can etch the same film layer to form the first dielectric layer 1122 and the second dielectric layer 1222 in the same patterning process. Of course, the embodiments of the present application can also form the first ferroelectric layer 114 and the second ferroelectric layer 124, or form the first conductive pillar 113 and the second conductive pillar 123 in the same patterning process. This means that the formation steps of the cache 11 are compatible with the formation steps of the ferroelectric memory 12, which is conducive to simplifying the preparation process.

[0151] In some examples, as shown in Figure 4 The ferroelectric memory 12 includes one or more subarrays of memory cells 121. In the case where the ferroelectric memory 12 includes a plurality of subarrays of memory cells 121, the plurality of subarrays of memory cells 121 are arranged in a plurality of columns along the second direction X, and each column of subarrays of memory cells 121 includes a plurality of subarrays of memory cells 121 arranged in sequence along the third direction Y; the plurality of subarrays of memory cells 121 are arranged in a plurality of rows along the third direction Y, and each row of subarrays of memory cells 121 includes a plurality of subarrays of memory cells 121 arranged in sequence along the second direction X.

[0152] It can be understood that the number of the above-mentioned second stack structures 122 can be multiple. In the case where the ferroelectric memory 12 includes a subarray of memory cells 121, the subarray of memory cells 121 includes, for example, one second stack structure 122.

[0153] In some embodiments, as shown in Figure 16 and Figure 17 The ferroelectric memory 12 includes a plurality of second wires DL2 above the second stack structure 122. The plurality of second wires DL2 are respectively connected to the plurality of second plate line layers 1221.

[0154] Exemplarily, the plurality of second wires DL2 are electrically connected to the plurality of second plate line layers 1221 one by one. In this way, the second conductive pillar 123 and each layer of the second plate line layer 1221 can form a second ferroelectric capacitor C2, and thus each second conductive pillar 123 can form a plurality of second ferroelectric capacitors C2 with the plurality of second plate line layers 1221 included in the second stack structure 122.

[0155] The second wire DL2 is used to receive an electrical signal and transmit the electrical signal to the second plate line layer 1221 electrically connected thereto, and cooperate with the second conductive pillar 123 to realize independent control of flipping of the second ferroelectric capacitor C2.

[0156] Exemplarily, as shown in Figure 16 and Figure 17As shown, a plurality of selection transistors T are disposed below the second stacked structure 122. These selection transistors T are configured one-to-one with the plurality of second conductive pillars 123, and the first terminal (e.g., the drain) of one selection transistor T is in contact with the bottom end of one second conductive pillar 123. The selection transistors T and the plurality of second ferroelectric capacitors C2 corresponding to the second conductive pillars 123 electrically connected to them can constitute a ferroelectric memory cell FMC, which has a 1TnC structure. Of course, the ferroelectric memory cell FMC can also have other structures, which are not limited in this embodiment. For example, the ferroelectric memory cell FMC has a 2TnC structure.

[0157] Since the second ferroelectric capacitor C2 extends along the first direction Z, the ferroelectric memory cell FMC can also be called a vertical memory cell.

[0158] In the same ferroelectric memory cell (FMC), the orthographic projections of multiple second ferroelectric capacitors C2 onto the plane of the first board line layer 1121 are, for example, coincident. This ensures that the area occupied by the multiple second ferroelectric capacitors C2 on the plane of the first board line layer 1121 is only the area occupied by a single second ferroelectric capacitor C2 on the plane of the first board line layer 1121, effectively reducing the area ratio of the multiple second ferroelectric capacitors C2 and realizing the miniaturization of the ferroelectric memory cell (FMC), so as to integrate more ferroelectric memory cells (FMC) within a unit area.

[0159] Since a second ferroelectric capacitor C2 is used to store 1 bit of data, and each ferroelectric memory cell FMC includes multiple second ferroelectric capacitors C2, each ferroelectric memory cell FMC can store multiple bits (n-bits) of data, thereby greatly improving the storage density of the ferroelectric internal memory 11 with a three-dimensional stacked structure.

[0160] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory chip, characterized in that, The memory chip includes a cache, which comprises: The first stacked structure includes at least one first board line layer and first dielectric layers located on opposite sides of the first board line layer; when there are multiple first board line layers, the multiple first board line layers are connected to each other. The first conductive pillar penetrates the first stacked structure; The first ferroelectric layer is located between the first plate wire layer and the first conductive pillar, and surrounds the first conductive pillar; A read transistor is located below the first stacked structure; the gate of the read transistor is connected to the first conductive pillar; A write transistor is located below or above the first stacked structure; one of the source and drain of the write transistor is connected to the first conductive pillar. The memory chip further includes: ferroelectric internal memory; The memory chip has a storage area and a redundant area located on at least one side of the storage area, the ferroelectric internal memory is located in the storage area, and the cache is located in the redundant area.

2. The memory chip according to claim 1, characterized in that, The buffer also includes: The first wire located above the first stacked structure; A first contact post extending in a first direction, wherein the at least one first plate wire layer is connected to the first conductor through the first contact post; The first direction is the direction perpendicular to the plane where the first plate line layer is located.

3. The memory chip according to claim 2, characterized in that, When the number of the first board line layers is multiple. The first plate line layer is multi-layered to form multiple steps; at least one first contact post is provided on the step, and the step contacts the bottom end of at least one first contact post; The top of the first contact post installed on each step is in contact with the first conductor.

4. The memory chip according to claim 2, characterized in that, The buffer further includes: a second contact post extending along a first direction, one end of the second contact post being in contact with the first wire, and the other end of the second contact post being used to receive a reference voltage; The first direction is the direction perpendicular to the plane where the first plate line layer is located.

5. The memory chip according to claim 1, characterized in that, The ferroelectric internal memory includes: The second stacked structure includes alternating layers of multiple second board line layers and multiple layers of second dielectric layers; The second conductive pillar penetrates the second stacked structure; The second ferroelectric layer is located between the second plate wire layer and the second conductive pillar, and surrounds the second conductive pillar; The first board line layer and the second board line layer are made of the same material and are disposed in the same layer, and the first dielectric layer and the second dielectric layer are made of the same material and are disposed in the same layer.

6. The memory chip according to claim 5, characterized in that, The ferroelectric internal memory also includes: multiple second wires located above the second stacked structure; The multiple second conductors are respectively connected to the multilayer second board wire layer.

7. The memory chip according to claim 1, characterized in that, The pattern precision of the ferroelectric internal memory is higher than that of the cache.

8. The memory chip according to claim 1, characterized in that, The read transistor is fabricated using a front-end process.

9. The memory chip according to claim 1, characterized in that, The write transistor is located above the first stacked structure; The write transistor is formed using a back-end process.

10. The memory chip according to claim 9, characterized in that, The write transistor and the read transistor overlap in their orthographic projections onto the plane containing the first board line layer.

11. The memory chip according to claim 9, characterized in that, The buffer also includes: A first interconnect layer is located between the read transistor and the first stacked structure. The first interconnect layer includes a first word line and a first bit line. One of the source and drain of the read transistor is electrically connected to the first word line, and the other of the source and drain of the read transistor is electrically connected to the first bit line. The second word line and the second bit line are located above the first stacked structure. The gate of the write transistor is electrically connected to the second word line, and the other of the source and drain of the write transistor is electrically connected to the second bit line.

12. The memory chip according to claim 1, characterized in that, The write transistor is located below the first stacked structure; The write transistor is fabricated using a front-end process.

13. The memory chip according to claim 12, characterized in that, The buffer further includes a second interconnect layer located between the write transistor and the first stacked structure, and between the read transistor and the first stacked structure; The second interconnect layer includes: a first word line, a first bit line, a second word line, and a second bit line; One of the source and drain of the read transistor is electrically connected to the first word line, and the other of the source and drain of the read transistor is electrically connected to the first bit line. The gate of the write transistor is electrically connected to the second word line, and the other of the source and drain of the write transistor is electrically connected to the second bit line.

14. An electronic device, characterized in that, The electronic device includes: a central processing unit and a memory chip as described in any one of claims 1 to 13.

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