Sacrificial gate capping for gate protection

Abstract

A method includes providing a substrate including metal gate stacks and source / drain contact regions arranged alternately along a surface of the substrate, each of the source / drain contact regions recessed within a respective opening between adjacent metal gate stacks such that the source / drain contact regions provide a bottom of the opening and the adjacent metal gate stacks provide sidewalls, and the substrate including a dielectric covering the substrate such that the dielectric fills each opening. The substrate is exposed to an initial plasma etch process to remove a first portion of the dielectric downward from each opening to a first depth and form a sacrificial gate capping layer on the substrate while leaving each of the openings uncapped. The substrate is exposed to another plasma etch process to remove the sacrificial gate capping layer while removing a second portion of the dielectric downward from each opening to a second depth.

Description

[0001] Cross-references to related applications

[0002] This disclosure claims the benefits of U.S. Provisional Patent Application No. 63 / 186,665, filed May 10, 2021, and U.S. Non-Provisional Patent Application No. 17 / 721,551, filed April 15, 2022, which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates generally to the manufacture of semiconductor devices, and more specifically to a method for forming a sacrificial gate capping layer for gate protection during plasma etching. Background Technology

[0004] Advances in semiconductor technology rely on continuous improvements in manufacturing techniques. Innovations in semiconductor technology have led to the introduction of novel structures such as FinFET devices and stacked structures (e.g., 3D NAND devices). However, these new structures necessitate new manufacturing solutions to overcome challenges that would otherwise hinder manufacturing. One such challenge stems from capping layer damage and erosion of spacers on gate sidewalls caused by semiconductor plasma processing techniques. For example, dry etching processes (such as reactive ion etching (RIE)) may be used to open contacts within conventional mid-line (MOL) process flows. Dry etching processes can typically be highly aggressive for some layers within semiconductor processes. Dry etching processes often utilize plasma sources that generate massive numbers of ions, which are accelerated by bombarding sensitive device layers. Therefore, plasma etching processes can damage the underlying material, especially when opening high aspect ratio contact holes. This damage to the underlying material can then lead to uncontrollable changes in device electrical performance and reduced yield. Summary of the Invention

[0005] This disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0006] Aspect (1) provides a method comprising providing a substrate including a plurality of metal gate stacks and a plurality of source / drain contact regions alternately arranged along a surface of the substrate, wherein each of the source / drain contact regions is recessed within a corresponding opening between adjacent metal gate stacks such that the source / drain contact regions provide a bottom of the opening and the adjacent metal gate stacks provide sidewalls of the opening, and the substrate includes a dielectric covering the substrate such that the dielectric fills each opening. The substrate is exposed to an initial plasma etching process to remove a first portion of the dielectric downwards from each opening to a first depth within the opening, and a sacrificial gate capping layer is formed on the substrate while keeping each of the openings uncovered by the sacrificial gate capping layer. The substrate is exposed to another plasma etching process to remove the sacrificial gate capping layer while removing a second portion of the dielectric downwards from each opening to a second depth within the opening.

[0007] Aspect (2) includes the method of aspect (1), wherein exposing the substrate to another plasma etching process includes removing all dielectric from each of these openings to expose each of these source / drain contact regions.

[0008] Aspect (3) includes the method of aspect (1), wherein exposing the substrate to another plasma etching process includes removing the second portion to a second depth, which does not remove all dielectrics from each of these openings and does not expose each of these source / drain contact regions.

[0009] Aspect (4) includes the method of aspect (3), wherein exposing the substrate to another plasma etching process includes stopping the other plasma etching process before the sacrificial gate capping layer is completely removed.

[0010] Aspect (5) includes the method of aspect (4), further comprising repeating the formation of the sacrificial gate capping layer and exposing the substrate to another plasma etching process until all dielectrics are removed from each of these openings to expose the source / drain contact regions.

[0011] Aspect (6) includes the method of aspect (1), wherein the substrate further includes a conformal spacer layer located within each respective opening, the conformal spacer layer covering the bottom and sidewalls of the respective opening, and the dielectric covering the conformal spacer layer to fill each respective opening.

[0012] Aspect (7) includes the method of aspect (6), wherein the initial plasma etching process exposes a portion of the sidewalls of the conformal spacer layer within each respective opening.

[0013] Aspect (8) includes the method of aspect (7), wherein forming the sacrificial gate capping layer includes a portion of the sidewall covering the conformal spacer layer within each respective opening.

[0014] Aspect (9) includes the method of aspect (8), wherein forming the sacrificial gate capping layer includes forming the sacrificial gate capping layer having a first thickness on top of each metal gate stack and forming the sacrificial gate capping layer having a second thickness on the sidewalls, the first thickness being greater than the second thickness.

[0015] Aspect (10) includes the method of aspect (9), wherein forming the sacrificial gate capping layer includes forming the sacrificial gate capping layer on each sidewall such that the thickness of the sacrificial gate capping layer decreases from the upper portion of the opening to the bottom of the opening.

[0016] Aspect (11) includes the method of aspect (8), wherein exposing the substrate to another plasma etching process includes removing all dielectrics from each of the openings to expose the conformal spacer layer covering the bottom of each respective opening.

[0017] Aspect (12) includes the method of aspect (11), further comprising repeating the formation of the sacrificial gate capping layer and exposing the substrate to another plasma etching process to remove the conformal spacer layer covering the bottom of each respective opening, thereby exposing each of these source / drain contact regions.

[0018] Aspect (13) includes the method of aspect (1), further comprising forming a hard mask on the substrate, the hard mask including an exposure window located above the openings.

[0019] Aspect (14) includes the method of aspect (13), wherein forming the sacrificial gate capping layer includes covering at least a portion of the hard mask with the sacrificial gate capping layer.

[0020] On the other hand, (15) provides a method comprising providing a substrate including a source / drain contact region covered by an interlayer dielectric (ILD), a replacement metal gate adjacent to the source / drain contact region, and spacers located on the sidewalls of the replacement metal gate and the source / drain contact region. A first portion of the ILD above the source / drain contact region is removed using a first plasma etching process. A sacrificial gate capping layer is formed on the replacement metal gate and the spacers, the sacrificial gate capping layer having a first thickness on an upper portion of the spacers and a smaller second thickness on a lower portion of the spacers not covered by the ILD. A second portion of the ILD is removed using a second plasma etching process.

[0021] Aspect (16) includes the method of aspect (15), further comprising completely removing the ILD above the source / drain contact region by repeating the formation of the sacrificial gate capping layer and the removal of the second portion of the ILD at least once.

[0022] Aspect (17) includes the method of aspect (16), further comprising depositing an additional sacrificial gate capping layer on the replacement metal gate and the spacer after the ILD has been completely removed. The spacer above the source / drain contact region is removed using a third plasma etching process.

[0023] Aspect (18) includes the method of aspect (15), wherein the sacrificial gate capping layer comprises an oxide.

[0024] Aspect (19) includes the method of aspect (15), wherein the substrate further includes a patterned hard mask.

[0025] Aspect (20) includes the method of aspect (19), wherein forming the sacrificial gate capping layer includes covering at least a portion of the hard mask with the sacrificial gate capping layer.

[0026] It should be noted that the Summary of this Scope does not specify every embodiment and / or incremental novelty aspect of this disclosure or the claimed disclosure. Rather, the Summary provides only a preliminary discussion of different embodiments and corresponding novel points that outperform conventional techniques. For additional details and / or possible perspectives regarding this disclosure and its embodiments, the reader should refer to the Detailed Description of this Scope and the corresponding drawings, which are further discussed below. Attached Figure Description

[0027] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be enlarged or reduced.

[0028] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G These are schematic illustrations of substrates in various semiconductor processing steps of the method according to an example embodiment of this disclosure; and

[0029] Figures 2A and 2B are schematic illustrations of problems with conventional semiconductor processing methods. Detailed Implementation

[0030] The following disclosure provides numerous different embodiments or examples of various features for implementing the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples throughout this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Further, for ease of description, spatially related terms such as “top,” “bottom,” “below,” “under,” “lower,” “above,” “upper”, etc., may be used herein to describe the relationship of one element or feature as shown in the figures to other elements(s)(s). In addition to the orientations depicted in the figures, spatially related terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and therefore the spatially related descriptors used herein may also be interpreted accordingly.

[0031] The following sections discuss in detail various embodiments of methods and uses of semiconductor devices. However, it should be noted that the various embodiments described in detail herein are applicable to a wide range of disciplines. The specific embodiments described herein are merely illustrative of specific ways of making and using various embodiments and should not be construed as limited in scope. Embodiments of this application can be applied to various types of devices, such as FinFET transistors and stacked memory devices. Specific embodiments of the above process will be described using the following figures.

[0032] Embodiments of this application disclose a method for preventing or reducing damage to semiconductor regions during plasma etching. In one embodiment, the proposed integrated scheme addresses gate angle loss during contact-open etching processes used to manufacture advanced FinFET devices. Figures 2A and 2B illustrate this problem in semiconductor fabrication. Figure 2A shows a partial cross-sectional view of the semiconductor device during manufacturing. This semiconductor device has undergone a significant portion of front-end process (FEOL) fabrication.

[0033] In various embodiments, the substrate 201 in FIG. 2A may include silicon, silicon germanium, silicon carbide, and compound semiconductors such as gallium nitride, gallium arsenide, indium arsenide, and indium phosphide. The substrate may include a semiconductor wafer, which may include a semiconductor epitaxial layer comprising a heteroepitaxial layer. For example, in one or more embodiments, one or more heteroepitaxial layers comprising a compound semiconductor may be formed over the semiconductor substrate. In various embodiments, a portion or all of the substrate may be amorphous, polycrystalline, or monocrystalline. In various embodiments, the substrate may be doped, undoped, or may contain both doped and undoped regions.

[0034] Multiple fins (not shown) can be formed by epitaxial growth from a substrate or alternatively by using an etching-back process that leaves multiple fins. These multiple fins can be isolated from each other by shallow isolation regions (not shown). Thus, these shallow isolation regions and the multiple fins can form an alternating pattern.

[0035] The semiconductor device in Figure 2A further includes a replacement metal gate (RMG) 203, which comprises a replacement gate metal 203a (“gate”) and a gate cap 203b (e.g., SiN) on the replacement gate metal. The RMG helps to set the work function of the gate and forms the final gate electrode of the semiconductor device.

[0036] Multiple spacers 205 (e.g., SiN) are formed on the sidewalls of the RMG 203. In some examples, the spacers 205 may comprise SiN or a low-k material. The multiple spacers 205 can be formed by first depositing an insulating layer followed by an anisotropic etching process. For example, a reactive ion etching (RIE) process can be used to form the spacers. In some embodiments, the multiple spacers may comprise silicon nitride, silicon oxide, or silicon oxynitride. In various embodiments, the spacers 205 may have a thickness ranging from 0.5 nm to about 10 nm. In one embodiment, the spacers 205 may have a thickness ranging from 2 nm to about 5 nm.

[0037] Epitaxial regions 207 (“epi”) are grown on portions of multiple fins located between multiple RMGs 203 to form raised source / drain contact regions. Due to the growth pattern of the corresponding epitaxial material, the upper surface of the raised source / drain regions can form a surface with facets. Examples of materials used in the epitaxial regions 207 can include Si and SiGe. The epitaxial growth process can use any type of epitaxial process (including molecular beam epitaxy (MBE)) or various types of chemical vapor deposition (CVD).

[0038] The semiconductor device further includes an interlayer dielectric 209 (ILD) filling the recessed features between a plurality of RMG 203s. In various embodiments of the semiconductor device, the ILD 209 may include an oxide. In one example, an ILD comprising borosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), arsenic silicate glass (AsSG), or other types of glass may be deposited and heated to reflow. In one or more embodiments, the ILD 209 may also include oxides such as tetraethoxysilane (TEOS), fluorinated TEOS (FTEOS), organosilicon glass (OSG), fluorosilicate glass (FSG), or spin-coated glass (SOG).

[0039] The semiconductor device further includes a patterned hard mask 211 (HM) that defines an opening beneath the HM 211.

[0040] Figure 2B illustrates a gate angle loss 250 during a conventional contact-open etching process. This contact-open etching includes an anisotropic plasma etching process defined by an overlay patterned HM 211. The contact-open etching process removes the ILD 109 from a recessed feature 215 over the epitaxial region and further removes the spacer 205 over the epitaxial region. As schematically illustrated in Figure 2B, contact-open etching can result in an angle loss 250, where a portion of the spacer 205 and the gate cap are damaged and partially etched away during the removal of the ILD 209. In one example, the angle loss 250 is at least partly due to the low etch selectivity between the ILD 209 (e.g., oxide) and the spacer 205 (e.g., SiN). This type of angle loss can lead to electrical short circuits and ultimately semiconductor device failure. Embodiments of the present invention address the angle loss problem during contact-open etching.

[0041] Figures 1A to 1E The substrate fabrication according to an embodiment of the present invention is illustrated schematically. Figure 1A The semiconductor devices in the figure are reproduced in Figure 2A.

[0042] Figure 1B The diagram illustrates a semiconductor device following a first plasma etching process that defines an opening in a patterned HM 111. This first plasma etching process recesses the ILD 109 by removing a portion of it to form a partial opening 115a within the ILD 109. The first plasma etching process is characterized by an ion energy (Ei). iThe substrate 101 exhibits lower etch selectivity and higher etch selectivity between the ILD 109 and the spacer 105 and gate cap 103b. The spacer 105 and gate cap 103b retain at least substantially their shape during the first plasma etching process. In one example, the first plasma etching process may include alternating exposure to a plasma-excited etching gas comprising C4F6 and O2, and a plasma-excited argon (Ar) gas. High etch selectivity can be achieved by applying a low bias power to the substrate 101 and maintaining the substrate 101 at a relatively high temperature (e.g., between about 100°C and about 150°C).

[0043] Figure 1C A semiconductor device is illustrated after the deposition of a sacrificial gate cap 117 during a next manufacturing stage, according to an embodiment of the present invention. The sacrificial gate cap 117 may preferably be deposited on an upper portion of the semiconductor device, including deposition on the patterned HM 111, the gate cap 103b, and the upper portion of the spacer 105, and on the sidewalls above the partially recessed ILD 109. According to one embodiment, the thickness of the sacrificial gate cap 117 may decrease from the upper portion of the semiconductor device toward the remaining ILD 109. In one embodiment, the sacrificial gate cap is formed using a vapor deposition process (e.g., atomic layer deposition (ALD) or chemical vapor deposition (CVD) process, and others). According to one embodiment, the sacrificial gate cap may comprise an oxide (e.g., SiO2) deposited using a cyclic deposition process with alternating exposure to a silicon-containing precursor and O2 gas. For example, the SiO2 thickness of the sacrificial gate cap 117 on the top of the semiconductor device relative to its SiO2 thickness on the sidewalls of the spacer 105 can be selected using processing parameters such as O2 gas exposure time and gas pressure. These processing parameters affect the extent to which O2 gas diffuses into the recessed features and reacts with the silicon-containing precursor. In various embodiments, the sacrificial gate capping layer can have a thickness ranging from 0.5 nm to about 10 nm on top of the gate cap. In one embodiment, the sacrificial gate capping layer can have a thickness ranging from 2 nm to about 5 nm.

[0044] Figure 1DThe diagram illustrates a semiconductor device following a second plasma etching process defined by an opening in HM 111, which removes another portion of ILD 109 to form a deeper opening 115b. The second plasma etching process further removes ILD 109 in a recessed feature above the epitaxial region, but the sacrificial gate cap 117 at least substantially prevents corner loss 250 of the type depicted in FIG. 2B (where spacer 205 and a portion of gate cap 203b are etched when ILD 209 is removed). In one example, the second plasma etching process may include alternating exposure to a plasma-excited etching gas comprising C4F6 and O2, and a plasma-excited argon (Ar) gas. Unlike the first plasma etching process, the second plasma etching process may apply a high bias power to the substrate to achieve rapid directional etching of ILD 109. In one example, the second plasma etching process may be terminated when the sacrificial gate cap 117 has at least substantially been removed.

[0045] Subsequently, the step of depositing the sacrificial gate capping layer 117 and the second dry etching process can be repeated at least once until the ILD 109 is completely removed from the spacer layer 105 at the bottom of the recessed feature 115c above the epitaxial region 107. The resulting semiconductor device is Figure 1E As shown.

[0046] After removing ILD 109, it is possible to... Figure 1F The semiconductor device is further processed as shown. The step of depositing the sacrificial gate capping layer 117 as described above can be repeated, and thereafter, a third plasma etching process can be performed to etch the horizontal portion of the spacer 105 above the epitaxial region 107 at the bottom of the recessed feature, as shown. Figure 1G As shown. The third plasma etching process can, for example, include continuous etching, which comprises a plasma-excited etching gas containing C4F6, O2, and Ar. High etch selectivity can be achieved by applying a low bias power to the substrate. This also avoids damage to the epitaxial region 107 when etching through the horizontal portion of the spacer 105 above the epitaxial region 107.

[0047] According to one embodiment, the steps of first plasma etching, deposition of sacrificial gate capping layer 117, second plasma etching, and third plasma etching can be performed in a single processing chamber. This processing chamber may include a bias electrode (substrate holder), an optional top electrode above the substrate, a gas inlet system, a pumping system, and a substrate heating system.

[0048] In the foregoing description, specific details, such as the particular geometry of the processing system and the description of the various components and processes used therein, have been set forth. However, it should be understood that the techniques described herein may be practiced in other embodiments departing from these specific details, and such details are for illustrative purposes rather than limiting. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, specific figures, materials, and configurations have been set forth for illustrative purposes to provide a thorough understanding. However, embodiments may be practiced without such specific details. Components having substantially the same functional construction are indicated by similar reference numerals, and therefore any redundant descriptions may be omitted.

[0049] Various techniques have been described as multiple discontinuous operations to aid in understanding the various embodiments. However, the order in which they are described should not be construed as implying that these operations necessarily depend on that order. In fact, these operations do not need to be performed in the presented order. The described operations may be performed in an order different from the order of the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0050] As used herein, "substrate" or "wafer" generally refers to the object being processed according to the invention. A substrate may include any material portion or structure of a device (particularly a semiconductor or other electronic device) and may be, for example, a base substrate structure (e.g., a semiconductor wafer, a photomask), or a layer on or overlaid on a base substrate structure (e.g., a thin film). Therefore, a substrate is not limited to any particular base structure, underlayer, or overlay, whether patterned or unpatterned, but is contemplated to include any such layer or base structure, and any combination of layers and / or base structures. This description may refer to specific types of substrates, but this is for illustrative purposes only.

[0051] Those skilled in the art will also understand that many changes can be made to the operation of the techniques explained above while still achieving the same objectives of the invention. The scope of this disclosure is intended to cover such changes. Therefore, the foregoing description of embodiments of the invention is not intended to be limiting. Rather, any limitations on embodiments of the invention are set forth in the appended claims.

Claims

1. A manufacturing method, comprising: A substrate is provided, the substrate including a plurality of metal gate stacks and a plurality of source / drain contact regions alternately arranged along the surface of a base substrate structure, wherein each of the source / drain contact regions is recessed within a corresponding opening between adjacent metal gate stacks such that the source / drain contact regions provide the bottom of the opening and the adjacent metal gate stacks provide the sidewalls of the opening, and the substrate includes a dielectric covering the substrate such that the dielectric fills each opening; The substrate is exposed to an initial plasma etching process to remove a first portion of the dielectric down to a first depth in each opening, thereby exposing a portion of the sidewalls provided by the adjacent metal gate stack; A sacrificial gate capping layer is formed on the substrate, while ensuring that each of these openings is not covered by the sacrificial gate capping layer; and The substrate is exposed to another plasma etching process to remove the sacrificial gate capping layer, while simultaneously removing a second portion of the dielectric down to a second depth within each opening.

2. The manufacturing method as described in claim 1, wherein, Exposing the substrate to another plasma etching process involves removing all dielectric from each of these openings to expose each of these source / drain contact regions.

3. The manufacturing method as described in claim 1, wherein, Exposing the substrate to another plasma etching process involves removing the second portion to a second depth, which does not remove all the dielectric from each of these openings and does not expose each of these source / drain contact regions.

4. The manufacturing method as described in claim 3, wherein, Exposing the substrate to another plasma etching process includes stopping the other plasma etching process before the sacrificial gate capping layer is completely removed.

5. The manufacturing method of claim 4, further comprising repeatedly forming a sacrificial gate capping layer and exposing the substrate to another plasma etching process until all dielectrics are removed from each of these openings to expose the source / drain contact regions.

6. The manufacturing method as described in claim 1, wherein, The metal gate stack includes a conformal spacer layer formed as a sidewall provided by the adjacent metal gate stack.

7. The manufacturing method as described in claim 6, wherein, The initial plasma etching process exposes a portion of the conformal spacer layer corresponding to a portion of the sidewall.

8. The manufacturing method as described in claim 7, wherein, The formation of the sacrificial gate capping layer includes covering the exposed portion of the conformal spacer layer.

9. The manufacturing method as described in claim 8, wherein, Forming a sacrificial gate capping layer includes forming a sacrificial gate capping layer with a first thickness on top of each metal gate stack and forming a sacrificial gate capping layer with a second thickness on the sidewalls of the metal gate stack, wherein the first thickness is greater than the second thickness.

10. The manufacturing method as described in claim 9, wherein, Forming a sacrificial gate capping layer includes forming the sacrificial gate capping layer on each sidewall of the metal gate stack such that the thickness of the sacrificial gate capping layer decreases from the upper portion of the opening to the bottom of the opening.

11. The manufacturing method as described in claim 8, wherein, Exposing the substrate to another plasma etching process involves removing all dielectric from each of these openings to expose the conformal spacer layer covering the bottom of each respective opening.

12. The manufacturing method as described in claim 11, wherein, The conformal spacer layer is further formed at the bottom of each respective opening, and the method further includes repeatedly forming a sacrificial gate capping layer and exposing the substrate to another plasma etching process to remove the conformal spacer layer covering the bottom of each respective opening, thereby exposing each of these source / drain contact regions.

13. The manufacturing method of claim 1, further comprising forming a hard mask on the substrate, the hard mask including an exposure window located above the openings.

14. The manufacturing method as described in claim 13, wherein, Forming a sacrificial gate capping layer includes covering at least a portion of the hard mask with the sacrificial gate capping layer.

15. A manufacturing method, comprising: A substrate is provided, the substrate including a source / drain contact region, a replacement metal gate adjacent to the source / drain contact region to provide a sidewall of a recess, spacers formed on the sidewall of the replacement metal gate and the source / drain contact region, and an interlayer dielectric (ILD) disposed above the source / drain contact region to at least partially fill the recess, wherein the source / drain contact region is located at the bottom of the recess; The first portion of the ILD above the source / drain contact region is removed using a first plasma etching process, thereby exposing a portion of the spacer formed on the sidewall of the replacement metal gate; A sacrificial gate cover layer is formed on the replacement metal gate and the spacer formed on the sidewall of the recess. The sacrificial gate cover layer has a first thickness on the upper portion of the spacer formed on the sidewall and a smaller second thickness on the lower portion of the spacer formed on the sidewall that is not covered by the ILD. The second portion of the ILD is removed using a second plasma etching process to expose another portion of the spacer formed on the sidewall of the replacement metal gate; and The ILD above the source / drain contact region is completely removed by repeating the formation of the sacrificial gate capping layer and the removal of the second part of the ILD at least once.

16. The manufacturing method according to claim 15, further comprising: After the ILD is completely removed, an additional sacrificial gate capping layer is deposited on the replacement metal gate and the spacer; as well as The spacer above the source / drain contact area is removed using a third plasma etching process.

17. The manufacturing method as described in claim 15, wherein, The sacrificial gate capping layer comprises oxide.

18. The manufacturing method as described in claim 15, wherein, The substrate further includes a patterned hard mask.

19. The manufacturing method as claimed in claim 18, wherein, Forming a sacrificial gate capping layer includes covering at least a portion of the hard mask with the sacrificial gate capping layer.

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