Chip structure, packaging structure and method for manufacturing chip structure

Abstract

Embodiments of the present application provide a chip structure, a packaging structure and a preparation method of the chip structure. The chip structure comprises: a substrate; a first metal layer disposed on the substrate, the first metal layer comprising a Pad area; a second metal layer disposed on a side of the first metal layer away from the substrate and electrically connected to the Pad area; and a connecting bump structure disposed on a side of the second metal layer away from the first metal layer, the connecting bump structure being used for connecting a solder layer. The chip structure of the embodiments can ensure that the failure mode of the packaging structure after De-cap is the middle fracture of the solder layer, so that there is residual gold on both the chip and the substrate, thereby reducing the failure rate of the bump opening.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip structure, a packaging structure, and a method for fabricating the chip structure. Background Technology

[0002] With the rapid development of 4G and 5G communications, the demand for miniaturization of radio frequency devices is increasing, and CSP packaging technology is widely used in this process. (See also...) Figure 1 Currently, the CSP (Chip Scale Package) packaging method for SAW (Surface Acoustic Wave) filters is Au bump (gold ball) + GGI (Gold and Gold Interconnection).

[0003] +Mold sheet (epoxy resin), but using this encapsulation method easily results in no residual gold on the substrate after de-capping (see Figure 2A This can affect product performance. Summary of the Invention

[0004] Therefore, in order to overcome at least some of the defects and deficiencies in the prior art, embodiments of this application provide a chip structure, a packaging structure, and a method for fabricating a chip structure.

[0005] Specifically, on one hand, the chip structure provided in the embodiments of this application includes: a substrate; a first metal layer disposed on the substrate, the first metal layer including a Pad region; a second metal layer disposed on the side of the first metal layer away from the substrate and electrically connected to the Pad region; and a connecting protrusion structure disposed on the side of the second metal layer away from the first metal layer, the connecting protrusion structure being used to connect a solder layer.

[0006] On the other hand, embodiments of this application also provide a packaging structure, including: the chip structure as described above; and a solder layer, wherein the solder layer is connected to the second metal layer through the connection protrusion structure.

[0007] In another aspect, embodiments of this application also provide a method for fabricating a chip structure, the method comprising the following steps: Step 1: forming a substrate; Step 2: forming a first metal layer on the substrate, the first metal layer including a Pad region; Step 3: forming a second metal layer, wherein the second metal layer is electrically connected to the Pad region, and the end of the second metal layer opposite to the first metal layer has a connecting protrusion structure, the connecting protrusion structure being used to connect a solder layer.

[0008] As can be seen from the above, the embodiments of this application provide a connecting bump structure at one end of the second metal layer away from the substrate in the chip structure. This allows the gold balls of the solder layer to be connected through the connecting bump structure, thereby reducing the connection force between the second metal layer and the solder layer. This ensures that the fracture point of the solder layer is between the gold balls of the solder layer, thus guaranteeing that the failure mode after de-capping is the fracture in the middle of the solder layer. This results in residual gold on both the chip and the substrate, thereby reducing the failure rate of bump opening. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of a packaging structure in the prior art.

[0011] Figure 2A and Figure 2B This is a schematic diagram of the failure modes after the encapsulation structure is decapped.

[0012] Figure 3A This is a schematic diagram of a chip structure provided in the first embodiment of this application.

[0013] Figure 3B This is a schematic diagram of another chip structure provided in the first embodiment of this application.

[0014] Figure 4 This is a schematic diagram of the failure modes of the encapsulation structure after de-capping, as shown in an embodiment of this application.

[0015] Figure 5 This is a schematic diagram of the shape of the bump layer.

[0016] Figures 6 to 11 This is a schematic diagram of the packaging structure provided in the second embodiment of this application.

[0017] Figure 12A , Figures 12B to 14 This is a schematic flowchart illustrating the method for fabricating the chip structure provided in the third embodiment of this application.

[0018] Figure 15 This is a schematic diagram of a preparation method provided in the third embodiment of this application.

[0019] Figure 16 This is a schematic diagram of another preparation method provided in the third embodiment of this application.

[0020] Figure 17 This is a schematic diagram of another preparation method provided in the third embodiment of this application.

[0021] Explanation of reference numerals in the attached figures:

[0022] 100. Chip structure; 200. Packaging structure; 300. Gold ball; 10. Substrate; 20. First metal layer; 21. IDT; 22. Pad area; 30. Passivation layer; 40. Bump layer; 50. Second metal layer; 51. Connecting bump structure; 60. Solder layer; 70. Substrate; 80. Packaging layer; 90. Tin layer; 101. Deposited under-bump metal layer; 102. Wall layer; 103. Roof layer. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments described in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0024] It should be noted that all directional indicators (such as up, down, left, right, front, back, top, and bottom) in the embodiments of this application are only used to explain the relative positional relationship and movement of the components in a specific posture (as shown in the attached figure). If the specific posture changes, the directional indicator will also change accordingly. In addition, the term "vertical" used in the embodiments and claims refers to an angle of 90° between two components or a deviation of -5° to +5°, and the term "parallel" refers to an angle of 0° between two components or a deviation of -5° to +5°.

[0025] In the embodiments of this application, the descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature.

[0026] See Figure 1 In existing SAW filters, the CSP packaging method is Au bump + GGI + Mold sheet, with the chip and substrate connected by gold balls 300 in the solder layer. See [link to related documentation] Figure 2B , Figure 2BThis is a schematic diagram of the normal state of the failure mode after de-capping of a SAW filter's packaging structure. That is, after de-capping, there should be residual gold on both the chip and the substrate. However, in existing packaging methods, it is very easy for no residual gold to remain on the substrate after de-capping (see...). Figure 2A This can affect product performance.

[0027] [First Embodiment]

[0028] Based on the problems mentioned above, see Figure 3A , 3B and Figure 4 The first embodiment of this application provides a chip structure 100, which may include, for example, a substrate 10, a first metal layer 20, and a second metal layer 50. The chip structure 100 provided in this embodiment can be applied to various chip structures, such as filters, LED chips, and ARM chips. In this embodiment, a filter chip structure is used as an example for detailed description. In other embodiments, the chip structure 100 may further include, for example, a passivation layer 30.

[0029] Specifically, substrate 10 can be, for example, a piezoelectric substrate, and the material of substrate 10 can be, for example, a piezoelectric material, specifically, lithium tantalate / niobium tantalate / or a bonding sheet containing piezoelectric material. A chip can be disposed within substrate 10, for example, and the chip can be of various types, such as a filter, LED chip, ARM chip, etc., depending on actual needs. The thickness of substrate 10 can range from, for example, 150um to 250um, specifically, 150um, 200um, or 250um. The chip structure provided in this example can be applied, for example, to a filter. The thickness of a conventional Normal SAW substrate can be, for example, 200um, while the thickness of a TC SAW substrate is determined by the product's frequency band; this embodiment is not limited to this.

[0030] A first metal layer 20 is disposed on the substrate 10, and the first metal layer 20 includes a Pad region 22. The material of the first metal layer 20 can be, for example, a metallic material, specifically, Ti, Al, or Cu. When the chip structure 100 provided in this embodiment is a filter, the first metal layer 20 may also include, for example, an IDT (interdigital transducer) 21. The IDT 21 is an interdigitated metal electrode formed on the surface of the piezoelectric substrate 10. The function of the interdigital transducer is to realize acoustic-electric energy conversion. The working principle of the surface acoustic wave device is as follows: when an alternating electrical signal is applied to the input end of a set of interdigital transducers on the piezoelectric substrate, a periodically distributed electric field is generated. Due to the inverse piezoelectric effect, corresponding elastic deformation is excited near the surface of the piezoelectric medium, thereby causing the vibration of solid particles and forming a surface acoustic wave propagating along the surface of the substrate. When the surface acoustic wave reaches the other end of the piezoelectric medium, charges are generated at both ends of the metal electrode due to the direct piezoelectric effect, so that another set of interdigital transducers can be used to output an alternating electrical signal. IDT21 may be located, for example, in the middle region of substrate 10.

[0031] A passivation layer 30 is disposed on the side of the first metal layer 20 away from the substrate 10, and the passivation layer 30 may, for example, cover the first metal layer 20. Specifically, the passivation layer 30 may, for example, cover the Pad region 22 and IDT 21, and cover other regions of the substrate 10 except for IDT 21 and Pad region 22. The material of the passivation layer 30 may, for example, be silicon oxide, specifically silicon dioxide, and the thickness of the passivation layer 30 may, for example, be 10 to 60 nm. For example, the thickness of the passivation layer 30 may be, for example, 15 nm or 30 nm. The thickness of the passivation layer 30 can be set according to actual needs, and this embodiment is not limited thereto.

[0032] The second metal layer 50 is a metal wiring layer, and it is disposed on the side of the first metal layer 20 away from the substrate 10. The second metal layer 50 may, for example, be disposed on the side of the passivation layer 30 away from the substrate 10 and electrically connected to the Pad region 22. The second metal layer 50 is disposed corresponding to the Pad region 22; that is, the passivation layer 30 has an exposed area on the Pad region 22 that exposes the first metal layer 20, and the second metal layer 50 connects to the first metal layer 20 on the exposed area of ​​the Pad region 22. The material of the second metal layer 50 may be, for example, a metallic material, specifically, materials such as Ti, Al, Cu, and Au, and the thickness of the second metal layer 50 may, for example, be 1–5 μm. A connecting protrusion structure 51 is disposed on the side of the second metal layer 50 away from the first metal layer 20, and the connecting protrusion structure 51 is used to connect the solder layer 60.

[0033] In this embodiment, a connecting protrusion structure 51 is provided at the end of the second metal layer 50 in the chip structure 100 away from the substrate 10. This allows the gold balls of the solder layer 60 to be connected via the connecting protrusion structure 51, reducing the connection force between the second metal layer 50 and the solder layer 60. This ensures that the fracture point of the solder layer 60 is between the gold balls, guaranteeing that the failure mode of the package structure after de-capping is a fracture in the middle of the solder layer, leaving residual gold on both the chip and the substrate (e.g., Figure 4 (as shown), thereby reducing the failure rate of the convex point opening.

[0034] In one embodiment of this invention, referring to FIG3, the chip structure 100 may, for example, further include a bump layer 40. The bump layer 40 may be disposed between the first metal layer 20 and the second metal layer 50, or between the passivation layer 30 and the second metal layer 50. A connecting bump structure 51 corresponds to the bump layer 40 and is located on the side of the second metal layer 50 away from the bump layer 40. The bump layer 40 forms the connecting bump structure 51 on the second metal layer 50. The passivation layer 30 has an exposed area on the Pad region 22 that exposes the first metal layer 20. The bump layer 40 is disposed on the exposed area of ​​the Pad region 22. The second metal layer 50 connects to the bump layer 40 and the first metal layer 20. The second metal layer 50 may be formed, for example, by deposition, to form the connecting bump structure 51 corresponding to the bump layer 40. In this embodiment, the second metal layer 50 and the connecting protrusion structure 51 are integrally formed, that is, the second metal layer 50 and the connecting protrusion structure 51 are formed together.

[0035] In another embodiment of this example, see Figure 3B The connecting bump structure 51 is a bump layer 40 disposed on the second metal layer 50. Specifically, the chip structure 100 may, for example, further include a bump layer 40, which may be disposed on the side of the second metal layer 50 away from the first metal layer 20, i.e., the bump layer 40 forms the connecting bump structure 51. The passivation layer 30 has an exposed area on the Pad region 22 that exposes the first metal layer 20. The second metal layer 50 is disposed on the exposed area and connected to the first metal layer 20. The bump layer 40 may, for example, be disposed on the side of the second metal layer 50 away from the first metal layer 20.

[0036] In one specific embodiment of this example, the material of the bump layer 40 is silicon oxide, a metal, or polyimide (PI), wherein the silicon oxide can be, for example, silicon dioxide, and the metal can be, for example, Ti, Al, Cu, and Au. The ratio of the thickness of the bump layer 40 to the thickness of the second metal layer 50 is in the range of 1 / 4 to 1 / 3. The thickness of the second metal layer 50 can be, for example, 5 μm, and the thickness of the bump layer 40 can be, for example, 1.25 μm or 1.67 μm, depending on actual needs. The thickness refers to the dimension of each structure in the direction perpendicular to the substrate 10. When the material of the bump layer 40 is silicon dioxide, the passivation layer 30 and the bump layer 40 are integrally formed, that is, the passivation layer 30 and the bump layer 40 can be formed simultaneously, which simplifies the manufacturing process of the bump layer 40 and does not increase additional costs. When the material of the bump layer 40 is a metal, it will not affect the contact resistance of the interface. The ratio of the projected area of ​​the bump layer 40 on the substrate 10 to the area of ​​the pad region 22 ranges from 1 / 4 to 1 / 2. For example... Figure 5 As shown, the shape of the bump layer 40 can be various shapes, such as multiple spaced squares or strips, or even circles, ellipses, rings, etc. This embodiment is not limited to these.

[0037] In summary, this embodiment of the application provides a connecting protrusion structure 51 at the end of the second metal layer 50 facing away from the substrate 10 in the chip structure 100. This allows the gold balls of the solder layer 60 to be connected via the connecting protrusion structure 51, thereby reducing the connection force between the second metal layer 50 and the solder layer 60. This ensures that the breakage point of the solder layer 60 is between the gold balls of the solder layer 60, thus guaranteeing that the failure mode of the package structure 200 after de-capping is the breakage in the middle of the solder layer 60. This results in residual gold on both the chip and the substrate, thereby reducing the failure rate of bump opening.

[0038] [Second Embodiment]

[0039] A second embodiment of this application provides a packaging structure 200, which may include, for example, the chip structure 100 as described above and a solder layer 60. The solder layer 60 is connected to the second metal layer 50 via a connecting protrusion structure 51. The solder layer 60 may be, for example, a gold ball, and the material of the solder layer 60 may be, for example, Au. The thickness of the solder layer 60 may be, for example, 30–60 μm.

[0040] See Figure 6 and Figure 7 , Figure 6 and Figure 7The illustrated packaging structure is a CSP package. The packaging structure 200 may, for example, further include a substrate 70 and an encapsulation layer 80. The substrate 70 is disposed on the side of the solder layer 60 facing away from the substrate 10, and the encapsulation layer 80 covers the surface of the substrate 10 and surrounds and seals the sidewalls of the substrate 10. The material of the encapsulation layer 80 may be, for example, epoxy resin. The encapsulation layer 80 covers the surface of the substrate 10, that is, it covers the side facing away from the substrate 70 and surrounds and seals the substrate 10; specifically, it may be sealed to the substrate 70.

[0041] See Figure 8 and Figure 9 , Figure 8 and Figure 9 The package structure shown is a BDMP package. The package structure 200 may also include, for example, a tin layer 90, which is connected between the second metal layer 50 and the solder layer 60. The tin layer 90 is connected to the second metal layer 50 through a connecting protrusion structure 51.

[0042] See Figure 10 and Figure 11 , Figure 10 and Figure 11 The packaging structure shown is a wafer-level package (WLP). The packaging structure 200 may, for example, further include: a deposited under-bump metal layer 101, a wall layer 102, and a roof layer 103. The deposited under-bump metal layer is disposed between the second metal layer 50 and the solder layer 60. The wall layer 102 is disposed on both sides of the deposited under-bump metal layer 101. The roof layer 103 covers the side of the wall layer 102 away from the substrate 10. The roof layer 103 and the wall layer 102, together with the substrate 10, form a cavity, within which an IDT 21 is disposed. The deposited under-bump metal layer 101 is connected to the second metal layer 50 via a connecting bump structure 51. The deposited under-bump metal layer is a UBM (under-ball metal). The wall layer 102 and the roof layer 103 may be made of materials such as polymers (epoxy resin, polyimide, etc.), photoresist, silicon, or glass.

[0043] It should be noted that the packaging structure 200 in this embodiment is not limited to the packaging structure mentioned above.

[0044] In summary, the packaging structure 200 provided in this application embodiment has a connecting protrusion structure 51 at one end of the second metal layer 50 away from the substrate 10. The gold balls of the solder layer can be connected through the connecting protrusion structure 51, thereby reducing the connection force between the second metal layer 50 and the solder layer. This ensures that the fracture point of the solder layer is between the gold balls of the solder layer 60, thus ensuring that the failure mode of the packaging structure 200 after de-capping is the fracture in the middle of the solder layer 60. This results in residual gold on both the chip and the substrate, thereby reducing the failure rate of bump opening.

[0045] [Third Embodiment]

[0046] See Figure 12A The third embodiment of this application provides a method for fabricating the above-described chip structure, which may include, for example, the following steps:

[0047] S10, Step 1: Forming a substrate;

[0048] S30, Step 2: Form a first metal layer on the substrate, the first metal layer including a Pad region;

[0049] S70, Step 3: Form a second metal layer, and the second metal layer is electrically connected to the Pad area. The end of the second metal layer opposite to the first metal layer has a connecting protrusion structure, which is used to connect the solder layer.

[0050] See Figure 12B In one specific embodiment of this example, between step 2 and step 3, the following step is further included: S50, step 2.1: forming a passivation layer on the first metal layer.

[0051] See Figure 13 In one specific embodiment of this example, between step 2 and step 3, the method further includes: S60, step 2.5: forming a bump layer in the Pad area, wherein the bump layer causes the connecting protrusion structure to be formed on the second metal layer.

[0052] See Figure 14 In one specific embodiment of this example, after step 3, the method further includes: S80, step 4: forming a bump layer on the second metal layer.

[0053] Specifically, see Figure 15A substrate 10 is formed, which may be, for example, a piezoelectric substrate. A first metal layer 20, i.e., a metal pattern, is formed on the substrate 10. An IDT 21 and a Pad region 22 are formed on the substrate 10. Then, a passivation material layer is formed on the first metal layer 20. The passivation material layer is patterned to form a passivation layer 30 and a bump layer 40. The passivation layer 30 covers the IDT 21 and Pad region 22 on the second metal layer 50, and the bump layer 40 is disposed on the Pad region. In this embodiment, the materials of the passivation layer 30 and the bump layer 40 may be the same, for example, silicon dioxide. The passivation layer 30 and the bump layer 40 can be formed simply by adjusting the photomask according to the shape of the bump layer 40 and etching the silicon dioxide on the Pad region. In this way, there is no need for an additional deposition process of the bump layer 40, which can improve the manufacturing process and does not increase additional costs. Finally, a second metal layer 50 is formed on the Pad region and connected to the first metal layer 20. The second metal layer 50 can be formed, for example, by a deposition process. With the provision of the bump layer 40, a connecting protrusion structure 51 is formed at the end of the second metal layer 50 facing away from the passivation layer 30. The connecting protrusion structure 51 corresponds to the bump layer 40. The connecting protrusion structure 51 is used to connect the gold balls of the solder layer 60.

[0054] See Figure 16 In another embodiment of this invention, the bump layer 40 may be, for example, a metal material or a PI material. The fabrication process of the chip structure 100 is as follows: a substrate 10 is formed, which may be, for example, a piezoelectric substrate. A first metal layer 20 is formed on the substrate 10, i.e., a metal pattern is formed on the substrate 10. An IDT 21 and a Pad region 22 are formed on the substrate 10. Then, a passivation layer 30 is deposited, which covers the IDT 21 and the Pad region 22 on the second metal layer 50. After the passivation layer 30 is formed, a bump layer 40 is formed on the Pad region. Finally, a second metal layer 50 is formed on the Pad region and is connected to the first metal layer 20. The second metal layer 50 may be formed, for example, by a deposition process. By setting the bump layer 40, a connecting protrusion structure 51 is formed at the end of the second metal layer 50 away from the passivation layer 30, and the connecting protrusion structure 51 corresponds to the bump layer 40. The connecting protrusion structure 51 is used to connect the gold balls of the solder layer 60.

[0055] See Figure 17In another embodiment of this invention, the fabrication process of the chip structure 100 is as follows: a substrate 10 is formed, which may be, for example, a piezoelectric substrate. A first metal layer 20 is formed on the substrate 10, i.e., a metal pattern is formed on the substrate 10. An IDT 21 and a Pad region 22 are formed on the substrate 10. Then, a passivation layer 30 is deposited, which covers the IDT 21 and Pad region 22 on the second metal layer 50. A second metal layer 50 is formed on the Pad region and connected to the first metal layer 20. The second metal layer 50 may be formed, for example, by a deposition process, or by other processes. The surface of the second metal layer 50 facing away from the substrate 10 may be formed as a plane, for example. Finally, a bump layer 40 is formed on the second metal layer 50, i.e., the bump layer 40 is the connecting bump structure 51.

[0056] After the chip structure 100 is formed by the above preparation method, it is then packaged to form different package structures 200. The specific packaging process can be referred to the preparation process and preparation flow in the prior art, and will not be repeated here in this embodiment.

[0057] In summary, the chip structure 100 formed by the above-described fabrication process has a connecting protrusion structure 51 at the end of the second metal layer 50 away from the substrate 10. The gold balls of the solder layer can be connected through the connecting protrusion structure 51, thereby reducing the connection force between the second metal layer 50 and the solder layer. This ensures that the break point of the solder layer is between the gold balls of the solder layer 60, thus guaranteeing that the failure mode of the package structure 200 after de-capping is the breakage in the middle of the solder layer 60. This results in residual gold on both the chip and the substrate, thereby reducing the failure rate of the bump opening.

[0058] Furthermore, it is understood that the foregoing embodiments are merely illustrative examples of this application. Provided that the technical features do not conflict, the structure is not contradictory, and the inventive purpose of this application is not violated, the technical solutions of the various embodiments can be arbitrarily combined and used.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A chip structure, characterized in that, include: Substrate; A first metal layer is disposed on the substrate, the first metal layer including a Pad region; A second metal layer is disposed on the side of the first metal layer away from the substrate and is electrically connected to the Pad region; as well as A connecting protrusion structure is disposed on the side of the second metal layer away from the first metal layer. The connecting protrusion structure is used to connect the solder layer to reduce the connection force between the second metal layer and the solder layer, so that the failure mode of the chip structure after opening is the breakage of the solder layer in the middle.

2. The chip structure as described in claim 1, characterized in that, Also includes: A bump layer is disposed between the first metal layer and the second metal layer, and the connecting protrusion structure is located on the side of the second metal layer opposite to the bump layer.

3. The chip structure as described in claim 2, characterized in that, The connecting protrusion structure and the second metal layer are integrally formed.

4. The chip structure as described in claim 2, characterized in that, Also includes: A passivation layer is disposed between the first metal layer and the second metal layer.

5. The chip structure as described in claim 4, characterized in that, The passivation layer and the bump layer are integrally formed.

6. The chip structure as described in claim 2, characterized in that, The material of the bump layer is silicon dioxide, metal, or polyimide.

7. The chip structure as described in claim 1, characterized in that, The ratio of the thickness of the connecting protrusion structure to the thickness of the second metal layer is in the range of 1 / 4 to 1 / 3.

8. The chip structure as described in claim 1, characterized in that, The ratio of the projected area of ​​the connecting protrusion structure on the substrate to the area of ​​the Pad region is in the range of 1 / 4 to 1 / 2.

9. A packaging structure, characterized in that, include: The chip structure as described in any one of claims 1-8; as well as A solder layer, which is connected to the second metal layer via the connecting protrusion structure.

10. The packaging structure as described in claim 9, characterized in that, Also includes: A substrate is disposed on the side of the solder layer opposite to the substrate; as well as An encapsulation layer that covers the surface of the substrate and surrounds and seals the sidewalls of the substrate.

11. The packaging structure as described in claim 9, characterized in that, Also includes: A tin layer is connected between the second metal layer and the solder layer, and the tin layer is connected to the second metal layer through the connecting protrusion structure.

12. The packaging structure as described in claim 9, characterized in that, Also includes: A deposited under-bump metal layer is disposed between the second metal layer and the solder layer, and the deposited under-bump metal layer is connected to the second metal layer through the connecting protrusion structure; A wall layer is disposed on both sides of the metal layer below the deposition bump; as well as A roof layer that covers the side of the wall layer away from the substrate.

13. A method for fabricating a chip structure, characterized in that, The preparation method includes the following steps: Step 1: Forming a substrate; Step 2: Form a first metal layer on the substrate, the first metal layer including a Pad region; Step 3: Form a second metal layer, and the second metal layer is electrically connected to the Pad area. The end of the second metal layer away from the first metal layer has a connection protrusion structure. The connection protrusion structure is used to connect the solder layer to reduce the connection force between the second metal layer and the solder layer, so that the failure mode of the chip structure after opening is the breakage of the solder layer in the middle.

14. The preparation method according to claim 13, characterized in that, Between step 2 and step 3, the following is also included: Step 2.5: Form a bump layer in the Pad area, the bump layer causing the connecting protrusion structure to be formed on the second metal layer.

15. The preparation method according to claim 13, characterized in that, Between step 2 and step 3, the following is also included: Step 2.1: Form a passivation layer on the first metal layer.

16. The preparation method according to claim 15, characterized in that, Step 2.1 includes: A passivation material layer is formed on the first metal layer; The passivation material layer is patterned to form the passivation layer and the bump layer, wherein the bump layer is formed on the Pad region.

17. The preparation method according to claim 13, characterized in that, The process includes step 4 after step 3: forming a bump layer on the second metal layer.

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