Training method for FPGA hardware resources of low-frequency imaging system

Abstract

The present invention relates to a training method for FPGA hardware resources of a low-frequency imaging system, and belongs to the field of hardware imaging technology. The method uses a multi-phase same-frequency image acquisition clock to sequentially drive an iodelay module, splices each obtained data acquisition range into the entire bit acquisition clock cycle, and then analyzes the entire bit acquisition clock cycle, and finally determines the most stable image data acquisition point and the most stable image acquisition clock to achieve a phase training process. FPGA uses the training code of each channel to determine the bit period difference between each channel, and compensates the bit period difference to each output channel to achieve a channel training process. The present invention can achieve coverage of the entire bit acquisition clock cycle, accurately find the most stable image data acquisition point and the most stable image acquisition clock, and keep the image data collected by each channel aligned, thereby improving the stability and accuracy of image data acquisition.

Description

Technical Field

[0001] The present invention relates to the technical field of hardware imaging, and in particular to a training method for FPGA hardware resources applied to aerospace low-frequency imaging systems. Background Art

[0002] As the performance of large-array image sensors gradually improves, their applications in aerospace projects are becoming more and more extensive. Figure 1 As shown in the figure, the image signal output by the image sensor has unstable data segments t1 and t3 and stable data segment t2 in a single data cycle. If the image data acquisition point is located in the stable data segment t2, the data collected by the system is accurate and stable; if the image data acquisition point is located in the unstable data segment t1 and t3, the data collected by the system is uncertain. Affected by the complex space environment, the unstable data segment in a single data cycle of the image signal accounts for a large proportion, and it is difficult to read the image data accurately and stably. It is necessary to process the image data of each channel. This processing process is called phase training processing.

[0003] At present, the phase training process processing method recommended by domestic companies is implemented through the iodelay resources on the FPGA. The iodelay module has a 64-tap surround delay unit. By delaying the image data, it changes the image data acquisition position within the cycle and tries to collect image data at the midpoint of the stable data segment t2. The reference clock range of the iodelay module is 175-225MHz, and the maximum delay time for image data is 5.71ns. For imaging systems with lower acquisition frequencies, the iodelay module's delay time for image data is insufficient and cannot meet usage requirements. Taking an imaging system with an acquisition clock of 50MHz as an example, the simulation results are as follows: Figure 2 As shown in the figure: data_in is the input image data, data_in_delay is the delayed image data, and the maximum delay time of the iodelay module for the image data signal is 5ns, which is half of the bit acquisition clock cycle of 10ns. The delay of the iodelay module for the image data signal cannot cover the entire bit acquisition clock cycle, so it is impossible to accurately find the midpoint of the stable data segment t2, and thus it is impossible to stably and accurately acquire image data. Summary of the invention

[0004] For imaging systems with low acquisition frequency, the delay time of the iodelay module for the image data signal is not enough to cover the entire bit acquisition clock cycle, resulting in the inability to accurately find the most stable data acquisition point. To address this problem, the present invention proposes a training method for FPGA hardware resources applied to aerospace low-frequency imaging systems.

[0005] To solve the above problems, the present invention adopts the following technical solutions:

[0006] A training method for FPGA hardware resources of a low-frequency imaging system, wherein the FPGA of the low-frequency imaging system is a V5 or higher series FPGA, and the method includes a phase training process and a channel training process;

[0007] The phase training process includes:

[0008] Step I: The DCM module in the low-frequency imaging system FPGA generates a multi-phase and same-frequency image acquisition clock;

[0009] Step II: For each channel of the image sensor, use a multi-phase and same-frequency image acquisition clock to sequentially drive the iodelay module to obtain a data acquisition range corresponding to each phase of the image acquisition clock, and splice each data acquisition range into the entire bit acquisition clock cycle;

[0010] Step III: In the entire bit acquisition clock cycle, the interval between the first stable data acquisition point and the last stable data acquisition point is defined as a data stable interval, the midpoint of the data stable interval is taken as the most stable image data acquisition point of the channel, and the image acquisition clock used by the most stable image data acquisition point is taken as the most stable image acquisition clock of the channel;

[0011] The channel training process includes:

[0012] Step 1: Acquire the image data of each channel of the image sensor when the data valid signal DVAL is at a low level;

[0013] Step 2: Determine whether the image data of each channel is equal to the training code of each channel. If so, return to step 1; if not, execute step 3;

[0014] Step 3: Select a reference channel, calculate the bit period difference between other channels and the reference channel according to the training code, and increase the bitslip value of other channels through the internal state machine until other channels reach the same bit period as the reference channel;

[0015] Step 4: The iodelay module compensates the bit period difference to each output channel in the imaging state, and then returns to step 1.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] The training method for FPGA hardware resources of a low-frequency imaging system proposed in the present invention is aimed at FPGAs of V5 and above series, and fully utilizes iodelay hardware resources. By using multi-phase and same-frequency image acquisition clocks to sequentially drive the iodelay module, each phase of the image acquisition clock driving the iodelay module will obtain a data acquisition range, and then the data acquisition ranges of the image acquisition clocks of different phases are spliced ​​into the entire bit acquisition clock cycle. After analyzing the data collected by all acquisition points of the bit acquisition clock cycle, the data between the first data stable acquisition point and the last data stable acquisition point is used as the data stable interval, the midpoint of the data stable interval is taken as the most stable image data acquisition point, and the image acquisition clock used by the most stable image data acquisition point is used as the most stable image acquisition clock. Therefore, the entire bit acquisition clock cycle can be covered, the most stable image data acquisition point and the most stable image acquisition clock are accurately found, and the stability of image data acquisition is improved. At the same time, the FPGA in the present invention determines the bit period difference between each channel through the training code of each channel, and compensates the bit period difference to each output channel, so as to keep the image data collected by each channel aligned, thereby improving the accuracy of image data acquisition. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of image data collection;

[0019] Figure 2 This is the simulation diagram of the iodelay module under 50MHz acquisition clock;

[0020] Figure 3 It is a flowchart of the phase training process;

[0021] Figure 4 This is the timing diagram of the image data output by the iodelay module under the 50MHz image acquisition clock;

[0022] Figure 5 Schematic diagram of the time point for obtaining the most stable image acquisition;

[0023] Figure 6 It is a timing diagram of image data, data valid signal, row valid signal and frame valid signal;

[0024] Figure 7 Flowchart of the channel training process. DETAILED DESCRIPTION

[0025] The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0026] An embodiment of the present invention provides a method for training FPGA hardware resources of a low-frequency imaging system. The method includes a phase training process and a channel training process. Channel training is detected in real time, while phase training is only performed before imaging. Phase training is performed once for each channel.

[0027] To implement the phase training process, you need to use FPGAs of V5 and above series, which have iodelay hardware resources. The DCM module in FPGAs of V5 and above series generates image acquisition clocks with the same frequency and different phases, and uses image acquisition clocks of different phases to sequentially drive the programmable absolute delay unit, i.e., the iodelay module. The iodelay module has a 64-tap surround delay unit, so any image acquisition clock acquires image data at 64 evenly distributed acquisition points within a bit acquisition clock cycle, and these 64 evenly distributed acquisition points constitute a data acquisition range. The data acquisition ranges of image acquisition clocks of different phases are spliced ​​into the entire bit acquisition clock cycle, and the data collected by all acquisition points in the bit acquisition clock cycle are analyzed. The data stable interval is defined as the interval between the first data stable acquisition point and the last data stable acquisition point, and the midpoint of the data stable interval is taken as the most stable image data acquisition point of the corresponding channel. The image acquisition clock used by the most stable image data acquisition point is used as the most stable image acquisition clock of the corresponding channel.

[0028] like Figure 3 As shown, the phase training process specifically includes the following steps:

[0029] Step I: The DCM module in the low-frequency imaging system FPGA generates a multi-phase and same-frequency image acquisition clock. According to the ratio of the image acquisition clock of the low-frequency imaging system to the period of the 200MHz reference clock of the iodelay module, the multi-phase and same-frequency image acquisition clock required by the system is determined, and the DCM module is driven to generate these clocks. For example, for an imaging system with an acquisition mode of SDR and an image acquisition clock of 100MHz, a 100MHz clock with a 0° phase and a 100MHz clock with a 180° phase need to be generated respectively. For an imaging system with an acquisition mode of SDR and an image acquisition clock of 50MHz, 100MHz clocks with 0° phase, 90° phase, 180° phase, and 270° phase need to be generated respectively.

[0030] Step II: For one channel of the image sensor, use the multi-phase and same-frequency image acquisition clock generated by the DCM module to drive the iodelay module in sequence. Each phase of the image acquisition clock drives the iodelay module, and a data acquisition range will be obtained. After obtaining a data acquisition range corresponding to each phase of the image acquisition clock, the data acquisition ranges of different phase clocks are spliced ​​into the entire bit acquisition clock cycle, that is, the entire bit acquisition clock cycle.

[0031] Step III: In the entire bit acquisition clock cycle, find the first data stable acquisition point and the last data stable acquisition point, define the area between the two as the data stable interval, take the midpoint of the data stable interval as the most stable image data acquisition point of the channel, and use the image acquisition clock used by the most stable image data acquisition point as the most stable image acquisition clock of the channel.

[0032] Step IV: After performing phase training on the image data collected by each channel of the image sensor one by one, exit the phase training process.

[0033] Taking the imaging system with DDR acquisition mode and 50MHz image acquisition clock as an example, the phase training process is described in detail. Figure 4 As shown, clk50 and clk50_90 are 50MHz clock with 0° phase and 50MHz clock with 90° phase respectively, data is the initial image data, and data_delay is the delayed image data output by the iodelay module. When tap is equal to 0, the rising edge of clock clk50 is aligned with the starting point of the data cycle of data_delay, and the rising edge of clock clk50_90 is aligned with the midpoint of the data cycle of data_delay. When tap is equal to 63 (the maximum delay range of the iodelay module), the rising edge of clock clk50 is aligned with the midpoint of the data cycle of data_delay, and the rising edge of clock clk50_90 is aligned with the end point of the data cycle of data_delay. The data collection range of clock clk50 is the first half of the data cycle, and the data collection range of clock clk50_90 is the second half of the data cycle. The two cover the entire bit collection clock cycle. As shown Figure 5 As shown, the midpoint A3 between the first stable data acquisition point A1 and the last stable data acquisition point A2 is taken as the final image data acquisition point.

[0034] As the external environment changes, the image sensor is affected by the environmental changes, and the phase difference between the image data signals output by each channel also changes accordingly, which ultimately leads to inaccurate image data collected by the FPGA. Therefore, it is necessary to detect whether the image data collected by each channel is aligned in real time during the imaging process of the image sensor. If the image data collected by each channel is not aligned, the FPGA re-trains the image data collected by each channel, that is, the bit period difference between each channel is determined by the training code of each channel, and then the result of the algorithm processing is used for period compensation.

[0035] Figure 6 The timing diagram of image data, data valid signal (DVAL), line valid signal (LVAL) and frame valid signal (FVAL). When training each channel, first obtain the image data of each channel when the data valid signal DVAL is low (such as Figure 6 OH value in). If the image data are all equal to the training code of each channel, it is judged that the image data collected by each channel is in the "aligned" state and the imaging system works normally. Otherwise, the FPGA needs to re-train the image data collected by each channel.

[0036] like Figure 7 As shown, the channel training process specifically includes the following steps:

[0037] Step 1: In the system imaging mode, before the data collected by each channel enters the fifo, the image data collected by each channel of the image sensor when the data valid signal DVAL is at a low level is obtained;

[0038] Step 2: Determine whether the image data of each channel is equal to the training code of each channel. If the acquired image data is equal to the training code of each channel, return to step 1 and re-acquire the image data; if the acquired image data is not equal to the training code of each channel, the FPGA needs to re-train the byte of the image data collected by each channel.

[0039] Step 3: Select a channel as the reference channel, for example, the first channel is used as the reference channel, and the bit period difference between other channels and the first channel is calculated through the training code of each channel. The FPGA increases the bitslip value of other channels through the internal state machine until other channels reach the same bit period as the first channel.

[0040] Step 4: The iodelay module compensates the bit period difference to each output channel in the imaging state, and then returns to step 1 to reacquire the image data.

[0041] The training method for FPGA hardware resources of a low-frequency imaging system proposed in the present invention is targeted at FPGAs of V5 and above series, and makes full use of iodelay hardware resources. By using multi-phase and same-frequency image acquisition clocks to sequentially drive the iodelay module, each phase of the image acquisition clock driving the iodelay module will obtain a data acquisition range, and then the data acquisition ranges of image acquisition clocks of different phases are spliced ​​into the entire bit acquisition clock cycle. After analyzing the data collected by all acquisition points of the bit acquisition clock cycle, the data between the first data stable acquisition point and the last data stable acquisition point is taken as the data stable interval, and the midpoint of the data stable interval is taken as the most stable image data acquisition point. The image acquisition clock used at the acquisition point is used as the most stable image acquisition clock. Therefore, the present invention can achieve coverage of the entire bit acquisition clock cycle, accurately find the most stable image data acquisition point and the most stable image acquisition clock, and improve the stability of image data acquisition. At the same time, the FPGA in the present invention uses the training code of each channel to determine the bit period difference between each channel, and compensates the bit period difference to each output channel, so as to keep the image data collected by each channel aligned, thereby improving the accuracy of image data acquisition, and effectively solving the problem in the prior art that for imaging systems with low acquisition frequency, the delay time of the iodelay module for the image data signal is not enough to cover the entire bit acquisition clock cycle, resulting in the inability to accurately find the most stable data acquisition point.

[0042] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0043] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A training method for FPGA hardware resources of a low-frequency imaging system, characterized in that: The low-frequency imaging system FPGA is a V5 or higher series FPGA, and the method includes a phase training process and a channel training process; The phase training process includes: Step I: The DCM module in the low-frequency imaging system FPGA generates a multi-phase and same-frequency image acquisition clock; Step II: For each channel of the image sensor, use a multi-phase and same-frequency image acquisition clock to sequentially drive the iodelay module to obtain a data acquisition range corresponding to each phase of the image acquisition clock, and splice each data acquisition range into the entire bit acquisition clock cycle; Step III: In the entire bit acquisition clock cycle, the interval between the first stable data acquisition point and the last stable data acquisition point is defined as a data stable interval, the midpoint of the data stable interval is taken as the most stable image data acquisition point of the channel, and the image acquisition clock used by the most stable image data acquisition point is taken as the most stable image acquisition clock of the channel; The channel training process includes: Step 1: Acquire the image data of each channel of the image sensor when the data valid signal DVAL is at a low level; Step 2: Determine whether the image data of each channel is equal to the training code of each channel. If so, return to step 1; if not, execute step 3; Step 3: Select a reference channel, calculate the bit period difference between other channels and the reference channel according to the training code, and increase the bitslip value of other channels through the internal state machine until other channels reach the same bit period as the reference channel; Step 4: The iodelay module compensates the bit period difference to each output channel in the imaging state, and then returns to step 1.

2. A method for training FPGA hardware resources of a low-frequency imaging system according to claim 1, characterized in that: The DCM module generates a multi-phase image acquisition clock with the same frequency according to the ratio of the image acquisition clock to the period of the iodelay module reference clock.

3. The method for training FPGA hardware resources of a low-frequency imaging system according to claim 2, characterized in that: The reference clock of the iodelay module is 200MHz. When the acquisition mode of the low-frequency imaging system is SDR and the image acquisition clock is 100MHz, the DCM module generates 100MHz image acquisition clocks with 0° phase and 180° phase respectively; When the acquisition mode of the low-frequency imaging system is SDR and the image acquisition clock is 50 MHz, the DCM module generates 100 MHz image acquisition clocks with 0° phase, 90° phase, 180° phase and 270° phase respectively.

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