Capacitor and method for manufacturing same, and electronic device

Abstract

The present application discloses a capacitor and a manufacturing method thereof, and an electronic device, belonging to the technical field of electronic devices. The capacitor includes a substrate layer, a first dielectric layer, and a capacitor unit; a first groove is provided on the first dielectric layer, the number of the first dielectric layers is multiple, and the multiple first dielectric layers are arranged sequentially along the first direction on the substrate layer; the number of capacitor units is multiple, and the multiple capacitor units are arranged one by one with the multiple first grooves, at least part of the capacitor unit is located in the first groove, and each capacitor unit is electrically connected. The capacitor provided by the present application includes multiple capacitor units, each capacitor unit is respectively located in a corresponding first groove, so that the capacitance density of the capacitor is improved while the overall thickness of the capacitor is relatively small.

Description

Technical Field

[0001] The present application relates to the technical field of electronic equipment, and in particular to a capacitor and a manufacturing method thereof, and electronic equipment. Background Art

[0002] In integrated circuits, in order to obtain a stable power supply, decoupling capacitors need to be installed at the power supply end of the component. Chip-level capacitors are widely used due to their advantages such as optimizing inductive reactance and reducing capacitor thickness. With the continuous advancement of technology, the demand for the capacitance of capacitors in electronic devices continues to increase. The capacitance of chip-level capacitors can no longer meet the demand. Therefore, increasing the capacitance of chip-level capacitors has become a technical problem that needs to be solved urgently. Summary of the invention

[0003] The present application provides a capacitor and a manufacturing method thereof, and an electronic device. The capacitance of the capacitor is relatively high.

[0004] The technical solution is as follows:

[0005] In a first aspect, the present application provides a capacitor, comprising:

[0006] substrate layer;

[0007] A first dielectric layer, wherein a first groove is arranged on the first dielectric layer, there are a plurality of first dielectric layers, and the plurality of first dielectric layers are sequentially arranged along a first direction on the substrate layer;

[0008] Capacitor units, there are multiple capacitor units, the multiple capacitor units are arranged in one-to-one correspondence with the multiple first grooves, at least part of the capacitor unit is located in the first groove, and the capacitor units are electrically connected.

[0009] The capacitor provided by the present application is provided with a plurality of first dielectric layers on one side of the substrate layer, each of the first dielectric layers is provided with a first groove, and a capacitor unit is provided in the first groove. Since the number of the first dielectric layers is multiple, the number of the capacitor units is at least multiple, thus increasing the number of electrode layers per unit area of ​​the capacitor, thereby increasing the capacitance density of the capacitor, and further increasing the capacitance of the capacitor accordingly. At the same time, since the first grooves are provided on each of the first dielectric layers, at least part of the structure of the capacitor unit is located in the first grooves, thereby reducing the total thickness of the first dielectric layer and the capacitor unit, thereby increasing the capacitance density of the capacitor while reducing the overall thickness of the capacitor.

[0010] In some implementations, a plurality of first grooves are respectively disposed on each first dielectric layer, and the plurality of first grooves are distributed at intervals on the corresponding first dielectric layer.

[0011] In some implementations, in the first dielectric layer, a plurality of first grooves are spaced apart and distributed along the second direction, a length direction of each first groove is the third direction, and the first direction, the second direction and the third direction are perpendicular to each other.

[0012] In some implementations, in the first dielectric layer, a plurality of first grooves are distributed in an array.

[0013] In some implementations, a projection of the first groove on the first dielectric layer along the first direction is circular.

[0014] In some implementations, the capacitor units disposed in two adjacent first dielectric layers are disposed opposite to each other in the first direction, and the two adjacent capacitor units in the first direction are electrically connected.

[0015] In some implementations, the capacitor also includes a second dielectric layer, a second dielectric layer is arranged between every two adjacent first dielectric layers, part of the capacitor unit is located in the second dielectric layer, a first conductive region is arranged on the first dielectric layer between the two second dielectric layers, a second conductive region is arranged on each second dielectric layer, the second conductive region is connected to the first conductive region, a first conductive body is arranged in the first conductive region, a second conductive body is arranged in the second conductive region, the first conductive body is electrically connected to the capacitor unit, and the second conductive body is electrically connected to two adjacent first conductive bodies.

[0016] In some implementations, the capacitor unit includes multiple electrode layers, a third dielectric layer is arranged between adjacent electrode layers, the multiple electrode layers include at least one first electrode layer and at least one second electrode layer, the first electrode layer and the second electrode layer have opposite polarities, the first electrode layers between adjacent capacitor units in a first direction are connected, and the second electrode layers in adjacent capacitor units in the first direction are electrically connected.

[0017] In some implementations, the substrate layer is provided with a second groove, a portion of the first dielectric layer adjacent to the substrate layer is located in the second groove, and the first groove is located in the second groove.

[0018] A second aspect of the present application provides an electronic device, comprising a capacitor provided by any of the above technical solutions.

[0019] Through the above technical solution, since the electronic device includes the above capacitor, it at least has all the beneficial effects of the capacitor, which will not be repeated here.

[0020] A third aspect of the present application provides a method for manufacturing a capacitor, comprising:

[0021] providing a substrate layer;

[0022] Prepare a first dielectric layer so that the first dielectric layer has a first groove, and the first dielectric layer is located on one side of the substrate layer in a first direction;

[0023] Preparing a capacitor unit on the first dielectric layer so that at least a portion of the capacitor unit is located in the first groove;

[0024] Repeat the steps of preparing the first dielectric layer, forming the first groove on the first dielectric layer, and preparing capacitor units on the first dielectric layer until the number of first dielectric layers reaches a set value; and make two capacitor units facing each other in the first direction electrically connected.

[0025] The capacitor manufactured by the manufacturing method of the capacitor provided in the present application is manufactured by arranging multiple first dielectric layers on one side of the substrate layer, each dielectric layer is provided with a first groove, and a capacitor unit is provided in the first groove. Since the number of the first dielectric layers is multiple, the number of the capacitor units is at least multiple, thus increasing the number of electrode layers per unit area of ​​the capacitor, thereby increasing the capacitance density of the capacitor, and further increasing the capacitance of the capacitor accordingly. At the same time, since the first grooves are respectively provided on each first dielectric layer, at least part of the structure of the capacitor unit is located in the first groove, thereby reducing the total thickness of the first dielectric layer and the capacitor unit, thereby increasing the capacitance density of the capacitor while the overall thickness of the capacitor is relatively small.

[0026] In some implementations, before preparing another first dielectric layer on a side of the first dielectric layer away from the substrate layer, the method further includes:

[0027] A second dielectric layer is formed on a side of the first dielectric layer away from the substrate layer, and the second dielectric layer covers the outside of the area of ​​the capacitor unit outside the first groove;

[0028] forming a second conductive region on the second dielectric layer;

[0029] forming a second conductor in the second conductive region, the second conductor being electrically connected to the capacitor unit in the second dielectric layer;

[0030] The method for preparing the first dielectric layer located on a side of the second dielectric layer away from the substrate layer further comprises:

[0031] forming a first conductive region on the first dielectric layer, wherein the first conductive region is connected to the second conductive region;

[0032] A first conductor is formed in the first conductive region, and the first conductor is electrically connected to the second conductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic longitudinal cross-sectional view of a capacitor provided in an embodiment of the present application;

[0034] Figure 2 yes Figure 1 A partial enlarged view of the middle A;

[0035] Figure 3 is a schematic diagram of the distribution of the first grooves in the first dielectric layer of the capacitor provided in an embodiment of the present application;

[0036] Figure 4 is another schematic diagram of the distribution of the first grooves in the first dielectric layer of the capacitor provided in an embodiment of the present application;

[0037] Figure 5 is a schematic longitudinal cross-sectional view of a capacitor provided in another embodiment of the present application;

[0038] Figure 6 yes Figure 5 A partial enlarged view of point B in the middle;

[0039] Figure 7 is a flow chart of a method for preparing a capacitor provided in an embodiment of the present application;

[0040] Figure 8 The steps of the method for preparing a capacitor provided in the embodiment of the present application are Figure 1 ;

[0041] Fig. 9 The steps of the method for preparing a capacitor provided in the embodiment of the present application are Figure 2 ;

[0042] Fig.10 The steps of the method for preparing a capacitor provided in the embodiment of the present application are Figure 3 ;

[0043] Fig.11 The steps of the method for preparing a capacitor provided in the embodiment of the present application are Figure 4 ;

[0044] Fig.12 The steps of the method for preparing a capacitor provided in the embodiment of the present application are Figure 5 ;

[0045] Fig.13 The steps of the method for preparing a capacitor provided in the embodiment of the present application are Figure 6 ;

[0046] Fig.14 The steps of the method for preparing a capacitor provided in the embodiment of the present application are Figure 7 ;

[0047] Fig.15 The steps of the method for preparing a capacitor provided in the embodiment of the present application are Figure 8 ;

[0048] Fig.16 The steps of the method for preparing a capacitor provided in the embodiment of the present application are Figure 9 ;

[0049] Fig.17 The steps of the method for preparing a capacitor provided in the embodiment of the present application are Figure 10 ;

[0050] Fig.18 The steps of the method for preparing a capacitor provided in the embodiment of the present application are Figure 10 one;

[0051] Fig.19 The steps of the method for preparing a capacitor provided in the embodiment of the present application are Figure 10 two.

[0052] The meanings of the figures are as follows:

[0053] 10. Capacitor;

[0054] 100, substrate layer; 110, second groove;

[0055] 210, first dielectric layer; 211, first groove; 212, first conductive region; 220, second dielectric layer; 221, second conductive region;

[0056] 310, capacitor unit; 311, first electrode layer; 312, second electrode layer; 313, third dielectric layer;

[0057] 510, first conductor; 520, second conductor. DETAILED DESCRIPTION

[0058] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0059] It should be understood that the "multiple" mentioned in this application refers to two or more, and does not represent a specific number. For example, multiple A and multiple B, which means that the number of A is two or more, and the number of B is two or more, does not mean that the number of A is the same as the number of B. In the description of this application, unless otherwise specified, " / " means or, for example, A / B can represent A or B; "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships, for example, A and / or B, which can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, in order to facilitate the clear description of the technical solution of this application, the words "first" and "second" are used to distinguish the same or similar items with basically the same functions and effects. Those skilled in the art can understand that the words "first" and "second" do not limit the quantity and execution order, and the words "first" and "second" do not limit them to be different.

[0060] The capacitor, the method for manufacturing the capacitor, and the electronic device provided in the embodiments of the present application are explained in detail below. In each embodiment of the present application, electrical connection refers to the connection between two electrical devices through a conductor so that electrical signals can be transmitted between the two electrical devices. In each of the drawings of the present application, the leads with arrows all point to the surface of the device, and the leads with dots all point to the device itself.

[0061] In integrated circuits, in order to obtain a stable power supply, decoupling capacitors need to be installed at the power supply end of the component. Chip-level capacitors are widely used in decoupling capacitors due to their advantages such as optimizing inductive reactance and reducing capacitor thickness. With the continuous advancement of technology, the demand for the capacitance of capacitors in electronic devices continues to increase. The current chip-level capacitors are all single-layer capacitors, resulting in the current chip-level capacitors The capacitance can no longer meet the needs of most current electronic devices. Therefore, increasing the capacitance of chip-level capacitors has become a technical problem that needs to be solved urgently.

[0062] In order to solve the above technical problems, the embodiments of the present application provide a capacitor and a manufacturing method thereof, and an electronic device. The capacitor and a manufacturing method thereof, and the electronic device provided in the embodiments of the present application are explained in detail below.

[0063] like Figure 1 and Figure 2 As shown, the present embodiment provides a capacitor 10, comprising: a substrate layer 100, a first dielectric layer 210 and a capacitor unit 310. There are multiple first dielectric layers 210, and the multiple first dielectric layers 210 are arranged in sequence along the first direction on the substrate layer 100. Exemplarily, the first direction is the thickness direction of the substrate layer 100, and in the accompanying drawings, the first direction is shown as the Z direction. The multiple first dielectric layers 210 are located on the same side of the substrate layer 100. The multiple first dielectric layers 210 can be stacked or distributed at intervals on one side of the substrate layer 100. A first groove 211 is provided on the first dielectric layer 210, and the first groove 211 is used to accommodate at least a partial area of ​​the capacitor unit 310, that is, a capacitor unit 310 is respectively provided corresponding to each first groove 211, and at least a portion of the capacitor unit 310 is located in the corresponding first groove 211. The number of capacitor units 310 in the capacitor 10 is the same as the total number of first grooves 211 in the plurality of first dielectric layers 210, that is, in the capacitor 10, the number of capacitor units 310 is the same as the number of first grooves 211, and one capacitor unit 310 is provided for each first groove 211. The number of first grooves 211 provided in different first dielectric layers 210 may be the same or different. Each first dielectric layer 210 is provided with at least one first groove 211, that is, in each first dielectric layer 210, the number of first grooves 211 may be one or more.

[0064] It is worth noting that the capacitor 10 provided in this embodiment is a chip capacitor, which can be used as a decoupling capacitor at the power supply end of the component.

[0065] In some optional embodiments, the material of the substrate layer 100 may be silicon, silicon carbide, silicon germanium, gallium arsenide, or the like.

[0066] The first dielectric layer 210 is made of an insulating material. In some optional embodiments, the material of the first dielectric layer 210 may be SiO2 (silicon dioxide), SiN (silicon nitride), SiON (silicon oxynitride), SiNC (a new type of inorganic non-metallic material, representing a composite of silicon, nitrogen and carbon) or SiHNC (an inorganic polymer, representing a carbon-nitrogen-silicon-hydrogen compound), etc.

[0067] The capacitor 10 provided in this embodiment is provided with a plurality of first dielectric layers 210 on one side of the substrate layer 100, each of the first dielectric layers 210 is provided with a first groove 211, and a capacitor unit 310 is provided in the first groove 211. Since the number of the first dielectric layers 210 is multiple, the number of the capacitor units 310 provided on the first dielectric layer 210 is multiple, so that the number of electrode layers per unit area of ​​the capacitor 10 is increased, so that the capacitance density of the capacitor 10 is increased, and thus the capacitance of the capacitor 10 is also increased accordingly. At the same time, since the first groove 211 is provided on each of the first dielectric layers 210, at least part of the structure of the capacitor unit 310 is located in the first groove 211, so that the total thickness of the first dielectric layer 210 and the capacitor unit 310 is reduced, so that the capacitance density of the capacitor 10 is improved while the overall thickness of the capacitor 10 is relatively small.

[0068] In some embodiments, the capacitor unit 310 includes a plurality of electrode layers, a third dielectric layer 313 is disposed between adjacent electrode layers, the plurality of electrode layers include at least one first electrode layer 311 and at least one second electrode layer 312, and the polarity of the first electrode layer 311 is opposite to that of the second electrode layer 312. The first electrode layers 311 in each capacitor unit 310 are electrically connected, and the second electrode layers 312 in each capacitor unit 310 are electrically connected. The first electrode layers 311 between the capacitor units 310 adjacent to each other in the first direction are connected, and the second electrode layers 312 between the capacitor units 310 adjacent to each other in the first direction are connected.

[0069] A capacitor unit 310 may include only a first electrode layer 311 and a second electrode layer 312, and a third dielectric layer 313 is provided between the first electrode layer 311 and the second electrode layer 312. Alternatively, a capacitor unit 310 may include a plurality of second electrode layers 312 and a plurality of first electrode layers 311. Exemplarily, the number of the first electrode layers 311 and the second electrode layers 312 is the same. The plurality of second electrode layers 312 may be arranged adjacent to each other, and the plurality of first electrode layers 311 may be arranged adjacent to each other, or the plurality of second electrode layers 312 and the plurality of first electrode layers 311 may be staggered, that is, in the first direction, the second electrode layer 312 is adjacent to the first electrode layer 311, and the first electrode layer 311 is adjacent to the second electrode layer 312. Exemplarily, the number of the first electrode layer 311 and the second electrode layer 312 are both three, and the first electrode layer 311, the second electrode layer 312, the first electrode layer 311, the second electrode layer 312, the first electrode layer 311, the second electrode layer 312, the first electrode layer 311, the second electrode layer 312, the first electrode layer 311, the second electrode layer 312, the first electrode layer 311, the first electrode layer 311, the second electrode layer 312, the first electrode layer 312, the first electrode layer 311, the first electrode layer 311, the second electrode layer 312, the first electrode layer 312, the first electrode layer 311, the first electrode layer 311, the second electrode layer 312, the first electrode layer 312.

[0070] In some embodiments, in each capacitor unit 310, the number of the first electrode layer 311 and the second electrode layer 312 are both multiple. The multiple first electrode layers 311 and the second electrode layers 312 are stacked in sequence along the first direction. Optionally, the number of the first electrode layer 311 and the second electrode layer 312 is equal, and the multiple first electrode layers 311 and the multiple second electrode layers 312 are staggered and stacked along the first direction, and a third dielectric layer 313 is arranged between adjacent first electrode layers 311 and second electrode layers 312. Exemplarily, in each capacitor unit 310, the number of the first electrode layer 311 and the second electrode layer 312 are both two, and the two first electrode layers 311 are arranged at intervals along the first direction, wherein one of the second electrode layers 312 is located between the two first electrode layers 311, and the other second electrode layer 312 is located on the side of the two first electrode layers 311 close to the substrate layer 100, or the other second electrode layer 312 can also be located on the side of the two first electrode layers 311 away from the substrate layer 100.

[0071] When the first grooves 211 in the two first dielectric layers 210 are arranged opposite to each other in the first direction, the capacitor units 310 in the first grooves 211 in the two first dielectric layers 210 are opposite to each other and adjacent to each other in the first direction, and the first electrode layers 311 in the two adjacent capacitor units 310 in the first direction are connected to each other, and the second electrode layers 312 are connected to each other. It is worth noting that the connection between the electrode layers is specifically an electrical connection.

[0072] The polarities of the first electrode layer 311 and the second electrode layer 312 are opposite, that is, one of the first electrode layer 311 and the second electrode layer 312 is a positive electrode and the other is a negative electrode. Exemplarily, the first electrode layer 311 is a positive electrode and the second electrode layer 312 is a negative electrode. The first electrode layers 311 of each capacitor unit 310 are electrically connected to form a positive electrode connection end of the entire capacitor 10. The second electrode layers 312 of each capacitor unit 310 are electrically connected to form a negative electrode connection end of the entire capacitor 10.

[0073] In the capacitor 10 provided in the embodiment of the present application, the first dielectric layer 210 is used to insulate between adjacent capacitor units 310 and between the capacitor unit 310 closest to the substrate layer 100 and the substrate layer 100, and the third dielectric layer 313 is used to insulate between adjacent electrode layers. The third dielectric layer 313 is made of an insulating material. In some optional embodiments, the material of the third dielectric layer 313 may be SiO2, SiN, ZrO (zirconium oxide), LaO (lanthanum oxide), HfO (hafnium oxide) or AlO (aluminum oxide), etc. The third dielectric layer 313 may be a single-layer structure or a multi-layer structure, such as a three-layer structure of ZrO-AlO-ZrO.

[0074] The electrode layer is made of a conductive material, that is, the first electrode layer 311 and the second electrode layer 312 are both made of a conductive material. In some optional embodiments, the material of the electrode layer may be a metal material or polysilicon, such as TiN (titanium nitride).

[0075] In one example, the structures of the first dielectric layers 210 in the capacitor 10 are the same, that is, the number and the arrangement positions of the first grooves 211 in the first dielectric layers 210 are the same. After the multiple first dielectric layers 210 are arranged in sequence along the first direction, the first grooves 211 in two adjacent first dielectric layers 210 are arranged one by one, so that the capacitor units 310 located in the two adjacent first dielectric layers 210 are arranged one by one.

[0076] In some embodiments, a plurality of first grooves 211 are respectively disposed in each first dielectric layer 210, and the plurality of first grooves 211 are spaced apart and distributed on the corresponding first dielectric layer 210. In this way, a plurality of capacitor units 310 can be accommodated in one first dielectric layer 210, and a capacitor unit 310 including a plurality of first dielectric layers 210 can include a greater number of capacitor units 310, thereby further improving the capacitance density of the capacitor 10.

[0077] A plurality of capacitor units 310 that are arranged opposite to each other in sequence along the first direction are referred to as a capacitor unit group. In the capacitor 10, the number of the first dielectric layers 210 is a1, and each first dielectric layer 210 is provided with a2 first grooves 211. Then, there are a2 capacitor unit groups in the capacitor 10, and each capacitor unit group includes a1 capacitor units 310. Then, the total number of capacitor units 310 in the capacitor 10 is a3, and a3=a1+a2.

[0078] like Figure 3 or Figure 4 As shown, the first groove 211 is a cylindrical groove, that is, the opening and the bottom wall of the first groove 211 are of the same shape and equal size. Exemplarily, the first groove 211 can be a groove-shaped structure such as a circular column or a square column. The projection shapes of each first groove 211 on the first dielectric layer 210 along the first direction can be the same or different. The projection shape of the first groove 211 on the first dielectric layer 210 can be a circular, polygonal, racetrack, etc. Exemplarily, when the projection shape of the first groove 211 on the first dielectric layer 210 is circular, the first groove 211 is a cylindrical groove, and the opening and the bottom wall of the first groove 211 are both circular. When the projection shape of the first groove 211 on the first dielectric layer 210 is rectangular, the first groove 211 is a rectangular groove, and the opening and the bottom wall of the first groove 211 are both rectangular.

[0079] In one example, the length direction of each first groove 211 is parallel to the third direction, and the plurality of first grooves 211 are spaced apart along the second direction, and the third direction is set at an angle to the second direction. In an embodiment of the present application, the first direction, the third direction and the second direction are set at an angle in pairs. Optionally, the first direction, the third direction and the second direction are set perpendicularly in pairs. Exemplarily, the first direction is the thickness direction of the capacitor 10, the third direction is the length direction of the capacitor 10, and the second direction is the width direction of the capacitor 10. It is worth noting that the length of the capacitor 10 is not necessarily greater than the width of the capacitor 10, and the length of the capacitor 10 may be greater than, less than or equal to the width of the capacitor 10. In the drawings of the embodiments of the present application, the first direction is shown in the Z direction, the third direction is shown in the Y direction, and the second direction is shown in the X direction. It is worth noting that the X direction, the Y direction and the Z direction are not directions pointing to a single direction or a single position, and the directions parallel to the X direction are all referred to as the X direction, the directions parallel to the Y direction are all referred to as the Y direction, and the directions parallel to the Z direction are all referred to as the Z direction. Since the length direction of the first groove 211 is parallel to the third direction, distributing the multiple first grooves 211 at intervals along the second direction set at an angle to the third direction is beneficial to arranging more capacitor units 310 in the same area, which is beneficial to improving the capacitance density of the capacitor 10 and increasing the capacitance of the capacitor 10.

[0080] In some optional embodiments, such as Figure 3 As shown, the projection of the first groove 211 on the first dielectric layer 210 may be a rectangle, so that the structure of the first groove 211 is relatively simple and the production efficiency is relatively high.

[0081] In some implementations, such as Figure 4 As shown, the number of the first grooves 211 is multiple, and the multiple first grooves 211 are distributed in an array. In this arrangement, the multiple first grooves 211 are arranged more neatly, which is conducive to production and manufacturing, and is convenient for simplifying the production and manufacturing process and improving production and manufacturing efficiency. In some optional embodiments, the multiple first grooves 211 can be distributed in an array of n×m, that is, the number of columns of the multiple first grooves 211 in the third direction is n, and the number of columns of the multiple first grooves 211 in the second direction is m, and the values ​​of m and n can be equal or unequal, and are not uniquely limited here.

[0082] In some implementations, in a projection perpendicular to the first direction, such as Figure 4As shown, the projection of each first groove 211 is circular. In this arrangement, the projection of each first groove 211 perpendicular to the first direction is circular, and each first groove 211 is distributed in an array, which is conducive to reducing the distance between two adjacent first grooves 211 in the second direction, and is conducive to reducing the distance between two adjacent first grooves 211 in the third direction, thereby facilitating increasing the number of first grooves 211 set per unit area of ​​a first dielectric layer 210, thereby increasing the number of capacitor units 310 that can be accommodated in the capacitor 10 per unit area, thereby increasing the capacitance density of the capacitor 10, so as to increase the capacitance of the capacitor 10.

[0083] In some embodiments, the capacitor 10 further includes a second dielectric layer 220, a second dielectric layer 220 is disposed between every two adjacent first dielectric layers 210, a portion of the capacitor unit 310 is located in the second dielectric layer 220, and the electrode layers of the same polarity between two adjacent capacitor units 310 in the first direction are electrically connected via a conductive structure, a portion of the conductive structure is disposed in the first dielectric layer 210, and a portion of the conductive structure is disposed in the second dielectric layer 220. In some embodiments, the conductive structure includes a first conductor 510 and a second conductor 520, a structure in which the conductive structure is disposed in the first dielectric layer 210 is referred to as a first conductor 510, and a structure in which the conductive structure is disposed in the second dielectric layer 220 is referred to as a second conductor 520. A first conductive area 212 is provided on the first dielectric layer 210 between two second dielectric layers 220, a second conductive area 221 is provided on each second dielectric layer 220, the second conductive area 221 is connected to the first conductive area 212, a first conductive body 510 is provided on the first conductive area 212, a second conductive body 520 is provided on the second conductive area 221, the second conductive body 520 is electrically connected to the capacitor unit 310, and the first conductive body 510 is electrically connected to two adjacent second conductive bodies 520. In this arrangement, part of the capacitor unit 310 is located in the first dielectric layer 210, and the other part of the capacitor unit 310 is located in the second dielectric layer 220. Adjacent capacitor units 310 are electrically connected through the first conductive body 510 and the second conductive body 520. When the capacitor unit 310 includes multiple electrode layers, and the electrode layers include multiple first electrode layers 311 and multiple second electrode layers 312, two capacitor units 310 adjacent to each other in the first direction are connected by two conductive structures, one of which electrically connects the first electrode layers 311 in the two capacitor units 310, and the other electrically connects the second electrode layers 312 in the two capacitor units 310. Exemplarily, two capacitor units 310 adjacent to each other in the first direction are electrically connected by two conductive structures, and the two conductive structures are respectively located on both sides of the first groove 211 in the second direction, or the two conductive structures are respectively located on both sides of the first groove 211 in the third direction, one of which is used to electrically connect the first electrode layers 311 of the two capacitor units 310 adjacent to each other in the first direction, and the other conductive structure is used to electrically connect the second electrode layers 312 of the two capacitor units 310 adjacent to each other in the first direction.

[0084] The second dielectric layer 220 is made of an insulating material. In some optional embodiments, the material of the second dielectric layer 220 may be the same as that of the first dielectric layer 210 .

[0085] The first conductor 510 and the second conductor 520 are both made of a conductive material, such as a metal material, such as copper or aluminum.

[0086] A plurality of capacitor units 310 are stacked in sequence along the first direction on one side of the substrate layer 100, and at least one capacitor unit 310 is completely located on one side of the substrate layer 100 along the first direction, and other capacitor units 310 are arranged between the substrate layer 100. In other words, in the first direction, some capacitor units 310 may be embedded inside the substrate layer 100, but some capacitor units 310 may still be completely located outside the substrate layer 100. Of course, all capacitor units 310 may also be completely located on one side of the substrate layer 100 along the first direction.

[0087] For example, Figure 1 and Figure 2 As shown, the substrate layer 100 is a flat plate structure, and the side of the substrate layer 100 facing the first dielectric layer 210 is a plane or substantially a plane, that is, the side of the substrate layer 100 facing the first dielectric layer 210 is not provided with a groove. The first dielectric layer 210 closest to the substrate layer 100 is located on one side of the first direction of the substrate layer 100, and a first groove 211 is provided on the side of the first dielectric layer 210 away from the substrate layer 100, and a part of the structure of the capacitor unit 310 is located in the first groove 211, so that the capacitor unit 310 is completely located outside the substrate layer 100.

[0088] In other embodiments, Figure 5 and Figure 6 As shown, the substrate layer 100 may be provided with a second groove 110, and a portion of the first dielectric layer 210 adjacent to the substrate layer 100 is located in the second groove 110, and the first groove 211 is located in the second groove 110. This allows at least a portion of the structure of the capacitor unit 310 located in the first dielectric layer 210 to extend into the first groove 211 and be located in the second groove 110, while other capacitor units 310 located in a direction away from the substrate layer 100 do not have a portion extending into the second groove 110, that is, in a capacitor unit group, a portion of the capacitor unit 310 closest to the substrate layer 100 extends into the second groove 110 of the substrate layer 100 (and is located in the first groove 211 of the first dielectric layer 210 closest to the substrate layer 100), while other capacitor units 310 are completely located outside the substrate layer 100.

[0089] In a specific embodiment, the substrate layer 100 is made of silicon substrate, the first dielectric layer 210 is made of SiO2, the electrode layer is made of TiN, the third dielectric layer 313 is made of a three-layer sandwich structure of ZrO-AlO-ZrO, the first conductor 510 and the second conductor 520 are made of copper, and the second dielectric layer 220 is made of SiO2.

[0090] In a second aspect, this embodiment provides an electronic device, including the capacitor 10 provided by any of the above technical solutions. Since the electronic device includes the above capacitor 10, it at least has all the beneficial effects of the capacitor 10, which will not be described in detail here.

[0091] The electronic device may be a terminal device with a display interface such as a mobile phone, a television, a display, a tablet computer, a car computer, or a smart display wearable device such as a smart watch or a smart bracelet, or a communication device such as a server, a storage device, a base station, or a smart car, etc. The embodiments of the present application do not impose any special restrictions on the specific form of the above electronic devices.

[0092] Thirdly, Figures 1 to 7 As shown, this embodiment provides a method for manufacturing a capacitor 10, which is used to manufacture the capacitor 10 provided in the first aspect. The method for manufacturing the capacitor 10 includes:

[0093] S10, providing a substrate layer 100. The substrate layer 100 is a layered structure with uniform thickness, and the material of the substrate layer 100 can be silicon, silicon carbide, silicon germanium or gallium arsenide.

[0094] S30, prepare the first dielectric layer 210 so that the first dielectric layer 210 has a first groove 211, and the first dielectric layer 210 is located on one side of the substrate layer 100 in the first direction. The first dielectric layer 210 is made of an insulating material, such as SiO2, SiN, SiON, SiNC or SiHNC. The first dielectric layer 210 can be formed on one side of the substrate layer 100 by deposition or laying, and the projection shape and size of the first dielectric layer 210 along the first direction are the same as the projection shape and size of the substrate layer 100 along the first direction. For example, if the projection shape of the substrate layer 100 along the first direction is a rectangle, then the projection shape of the first dielectric layer 210 along the first direction is a rectangle, and the length and width of the projection of the substrate layer 100 are respectively equal to the length and width of the projection of the first dielectric layer 210. The first groove 211 on the first dielectric layer 210 can be formed by deep groove photolithography and etching steps. Exemplarily, when there are multiple first grooves 211 formed on each first dielectric layer 210 , step S30 may include: S31 , forming the first dielectric layer 210 by deposition; S32 , forming multiple first grooves 211 on the first dielectric layer 210 by photolithography and etching.

[0095] After step S30, the method further includes:

[0096] S50, prepare a capacitor unit 310 on the first dielectric layer 210, so that at least part of the capacitor unit 310 is located in the first groove 211. When the number of the first groove 211 is one, the number of the capacitor unit 310 prepared on the first dielectric layer 210 is one, and when the number of the first grooves 211 is multiple, the number of the capacitor units 310 prepared on the first dielectric layer 210 is equal to the number of the first grooves 211, that is, one capacitor unit 310 is arranged corresponding to one first groove 211. The capacitor unit 310 includes a plurality of electrode layers, the plurality of electrode layers include at least one first electrode layer 311 and at least one second electrode layer 312, and a third dielectric layer 313 is arranged between adjacent electrode layers, and the third dielectric layer 313 is used to separate two adjacent electrode layers and insulate the two adjacent electrode layers. The polarities of the first electrode layer 311 and the second electrode layer 312 are opposite. The preparation process of the capacitor unit 310 includes the deposition of the electrode layer and the deposition of the third dielectric layer 313. During the deposition of the electrode layer, the two ends of the electrode layer are located on the side of the first dielectric layer 210 away from the substrate layer 100, the middle area of ​​the electrode layer is located in the first groove 211, and the electrode layer is distributed in the first groove 211 along the inner wall of the first groove 211. For example, the first groove 211 is a rectangular groove, at least including two side walls and a bottom wall arranged opposite to each other in the second direction, the two side walls are located on both sides of the bottom wall, and the electrode layer extends from the opening of the first groove 211 along one of the side walls to the bottom wall, and extends along the bottom wall to the other side wall, and then extends to the outside of the first groove 211 through the other side wall. Similarly, the shape of the third dielectric layer 313 is similar to that of the electrode layer. After the deposition process of multiple electrode layers and the third dielectric layer 313 is completed, photolithography and etching operations are performed so that the two ends of the capacitor unit 310 located outside the first groove 211 form a step-shaped structure respectively, so that each electrode layer exposes a connection area, so as to facilitate the subsequent connection operation of the electrode layer and the second conductor 520. It is worth noting that at least the connection areas of each first electrode layer 311 in the capacitor unit 310 are located on the same side, and the connection areas of each second electrode layer 312 are located on the other side, that is, the connection areas of the first electrode layer 311 and the connection areas of the second electrode layer 312 are respectively located on both sides of the first groove 211.

[0097] S70, repeat the above steps of preparing the first dielectric layer 210, forming the first groove 211 on the first dielectric layer 210, and preparing the capacitor unit 310 on the first dielectric layer 210, until the number of the first dielectric layers 210 reaches a set value, which is the number of the first dielectric layers 210 in the capacitor 10. For example, if the capacitor 10 includes a1 first dielectric layers 210, a1 preparation operations of the first dielectric layers 210 are required, and a capacitor unit 310 is prepared on each first dielectric layer 210.

[0098] During the above-mentioned step S70, two capacitor units 310 adjacent to each other in the first direction are electrically connected. The step of electrically connecting two adjacent capacitor units 310 can be completed in several steps, for example, after preparing one capacitor unit 310, the operation of electrically connecting the capacitor unit 310 to the conductive structure is performed, after preparing another capacitor unit 310 adjacent to the capacitor unit 310 in the first direction, the operation of electrically connecting the capacitor unit 310 to the conductive structure is performed, and the conductive structure electrically connected to the capacitor unit 310 is electrically connected to the conductive structure connected to the adjacent capacitor unit 310, so that the two adjacent capacitor units 310 are electrically connected through the two conductive structures. It is worth noting that when the capacitor unit 310 includes a first electrode layer 311 and a plurality of second electrode layers 312 with opposite polarities, the electrical connection of adjacent capacitor units 310 means: the first electrode layer 311 in the same capacitor unit 310 is electrically connected and electrically connected to the first electrode layer 311 in the adjacent capacitor unit 310; the second electrode layer 312 in the same capacitor unit 310 is electrically connected and electrically connected to the second electrode layer 312 in the adjacent capacitor unit 310. Then, between two adjacent capacitor units 310, two conductive structures need to be provided, one of which is used for electrical connection of the first electrode layer 311, and the other conductive structure is used for electrical connection of the second electrode layer 312.

[0099] Taking the electrical connection of the first electrode layer 311 between two adjacent capacitor units 310 as an example, when each capacitor unit 310 includes multiple first electrode layers 311, three conductive structures can be provided for electrical connection. Exemplarily, the three conductive structures include a first conductor 510 and two second conductors 520, the second conductor 520 is used to electrically connect the multiple first electrode layers 311 in the same capacitor unit 310, and the first conductor 510 is used to electrically connect the two adjacent second conductors 520, so that the multiple first electrode layers 311 in the two capacitor units 310 are electrically connected. For the sake of convenience, the capacitor unit 310 prepared first in two adjacent capacitor units 310 in the first direction is called the previous capacitor unit 310, and the capacitor unit 310 prepared later is called the next capacitor unit 310. After the preparation of the previous capacitor unit 310 is completed, the step of preparing the second conductor 520 is performed so that the second conductor 520 is electrically connected to each first electrode layer 311 in the previous capacitor unit 310; and after the preparation of the next capacitor unit 310 is completed, the step of preparing the second conductor 520 corresponding to the next capacitor unit 310 is performed so that the second conductor 520 is electrically connected to each first electrode layer 311 in the next capacitor unit 310. The preparation step of the first conductor 510 is performed between the preparation steps of the two second conductors 520. During the preparation of the first conductor 510, the first conductor 510 is electrically connected to the second conductor 520 corresponding to the previous capacitor unit 310. During the preparation of the second conductor 520 corresponding to the subsequent capacitor unit 310, the second conductor 520 corresponding to the subsequent capacitor unit 310 is electrically connected to the first conductor 510. That is, after the preparation of the second conductor 520 corresponding to the subsequent capacitor unit 310 is completed, the electrical connection operation of the first electrode layers 311 between the two adjacent capacitor units 310 is also completed.

[0100] It is worth noting that the electrical connection operation of each second electrode layer 312 between two adjacent capacitor units 310 is the same as the electrical connection operation between each first electrode layer 311. The electrical connection operation of each first electrode layer 311 between two adjacent capacitor units 310 and the electrical connection operation of each second electrode layer 312 between two adjacent capacitor units 310 can be performed simultaneously.

[0101] To facilitate the preparation of the second conductor 520, in some embodiments, before preparing another first dielectric layer 210 on a side of the first dielectric layer 210 away from the substrate layer 100, the method for manufacturing the capacitor 10 further includes:

[0102] S71, preparing a second dielectric layer 220 on a side of the first dielectric layer 210 away from the substrate layer 100, the second dielectric layer 220 covering the outer side of the area of ​​the capacitor unit 310 located outside the first groove 211;

[0103] S72, forming a second conductive region 221 on the second dielectric layer 220;

[0104] S73, forming a second conductor 520 in the second conductive region 221, wherein the second conductor 520 is electrically connected to the capacitor unit 310 in the second dielectric layer 220;

[0105] The method for preparing the first dielectric layer 210 located on the side of the second dielectric layer 220 away from the substrate layer 100 further includes:

[0106] S74, forming a first conductive region 212 on the first dielectric layer 210, wherein the first conductive region 212 is connected to the second conductive region 221;

[0107] S75 , forming a first conductor 510 in the first conductive region 212 , and the first conductor 510 is electrically connected to the second conductor 520 .

[0108] In this manufacturing method, the second conductor 520 is disposed in the second dielectric layer 220 , and the second dielectric layer 220 facilitates the formation of the second conductive region 221 , thereby facilitating the manufacturing of the second conductor 520 .

[0109] The preparation method of the first dielectric layer 210 located on the side of the second dielectric layer 220 away from the substrate layer 100 further includes S74 and S75, that is, the preparation method of the first dielectric layer 210 closest to the substrate layer 100 does not include S74 and S75.

[0110] When the first conductive region 212 is prepared, it can be performed during the preparation of the second conductive region 221 in the second dielectric layer 220 on the side of the first dielectric layer 210 away from the substrate layer 100, that is, after the second dielectric layer 220 is prepared, a hole is punched in the second dielectric layer 220, the hole penetrates the second dielectric layer 220 and the first dielectric layer 210, and the hole is connected to the second conductive region 221 in the second dielectric layer 220 between the first dielectric layer 210 and the substrate layer 100. The portion of the hole located in the second dielectric layer 220 becomes a portion of the second conductive region 221, and is connected to other portions of the second conductive region 221 in the second dielectric layer 220, and the portion of the hole located in the first dielectric layer 210 forms the first conductive region 212.

[0111] During the process of forming the second conductive region 221 on the second dielectric layer 220 , two second conductive regions 221 are provided corresponding to each capacitor unit 310 , and the two second conductive regions 221 are respectively connected to two side regions of the capacitor unit 310 extending out of the first groove 211 .

[0112] In the process of forming the second conductor 520 in the second conductive area 221, two second conductors 520 are provided corresponding to each capacitor unit 310 in a second dielectric layer 220, wherein one second conductor 520 is electrically connected to each first electrode layer 311 in the capacitor unit 310, and the other second conductor 520 is electrically connected to each second electrode layer 312 in the capacitor unit 310.

[0113] During the process of forming the first conductive region 212 on the first dielectric layer 210 , two first conductive regions 212 are provided in the first dielectric layer 210 corresponding to one capacitor unit 310 , and the two first conductive regions 212 are respectively used to be connected to the two second conductive regions 221 corresponding to the capacitor unit 310 in a one-to-one correspondence.

[0114] In the process of forming the first conductor 510 in the first conductive area 212, in a first dielectric layer 210, two first conductors 510 are respectively provided corresponding to each capacitor unit 310, one of which is used to connect two adjacent second conductors 520 of the first electrode layer 311 for connecting the capacitor unit 310, and the other first conductor 510 is used to connect two adjacent second conductors 520 of the second electrode layer 312 for connecting the capacitor unit 310.

[0115] In a specific embodiment, a method for preparing a capacitor 10 including a1 first dielectric layers 210 includes:

[0116] like Figure 8 As shown, a substrate layer 100 is provided.

[0117] like Fig. 9 As shown, a first dielectric layer 210 is deposited on the substrate layer 100 .

[0118] like Fig.10 As shown, a plurality of first grooves 211 are formed on the first dielectric layer 210 by photolithography and etching. It is worth noting that: Fig.10 Only two first grooves 211 are taken as examples, but more first grooves 211 may be provided in practice.

[0119] like Fig.11 As shown, a capacitor unit 310 is prepared on the first dielectric layer 210 corresponding to each first groove 211 , so that at least a portion of the capacitor unit 310 is located in the corresponding first groove 211 .

[0120] like Fig.12As shown, a first second dielectric layer 220 is prepared on a side of the first dielectric layer 210 away from the substrate layer 100 , and the first second dielectric layer 220 covers the outside of the area of ​​the capacitor unit 310 of the first dielectric layer 210 outside the first groove 211 .

[0121] like Fig.13 As shown, a second conductive region 221 is formed on the first second dielectric layer 220, and a second conductor 520 is formed in the second conductive region 221. The second conductor 520 is electrically connected to the capacitor unit 310 in the second dielectric layer 220. Two second conductors 520 are respectively provided for each capacitor unit 310, wherein one second conductor 520 is electrically connected to each first electrode layer 311 in the capacitor unit 310, and the other second conductor 520 is electrically connected to each second electrode layer 312 in the capacitor unit 310. The second conductor 520 may be made of copper, and the formation of the second conductor 520 may include a copper growth process. After the copper growth is completed, the surface of the second conductor 520 exposed outside the second conductive region 221 is polished by a CMP (Chemical Mechanical Polishing) process.

[0122] like Fig.14 As shown, a second first dielectric layer 210 is deposited on a side of the first second dielectric layer 220 away from the substrate layer 100 .

[0123] like Fig.15 As shown, a capacitor unit 310 is prepared on the second first dielectric layer 210 corresponding to each first groove 211 , so that at least a portion of the capacitor unit 310 is located in the corresponding first groove 211 .

[0124] like Fig.16 As shown, a second second dielectric layer 220 is prepared on the side of the second first dielectric layer 210 away from the substrate layer 100 , and the second second dielectric layer 220 covers the outside of the area of ​​the capacitor unit 310 of the second first dielectric layer 210 outside the first groove 211 .

[0125] like Fig.17 As shown, a second conductive region 221 is formed on the second second dielectric layer 220 , and two second conductive regions 221 are respectively provided for each capacitor unit 310 , wherein one second conductive region 221 is connected to each first electrode layer 311 in the capacitor unit 310 , and the other second conductive region 221 is connected to each second electrode layer 312 in the capacitor unit 310 .

[0126] like Fig.18As shown, a hole is punched on one side of the second dielectric layer 220 , and the hole passes through the second second dielectric layer 220 and the second first dielectric layer 210 . The portion of the hole located in the second dielectric layer 220 becomes the second conductive region 221 , and the portion of the hole located in the first dielectric layer 210 becomes the first conductive region 212 .

[0127] like Fig.19 As shown, metal growth is performed in the second conductive area 221 of the second second dielectric layer 220 and the first conductive area 212 of the second first dielectric layer 210 to form a first conductor 510 in the first conductive area 212 in the second first dielectric layer 210, and a second conductor 520 is formed in the second conductive area 221 of the second dielectric layer. The first conductor 510 is connected to two second conductors 520 located on both sides of the first direction, so that the capacitor unit 310 in the first first dielectric layer 210 is electrically connected to another capacitor unit 310 directly opposite to the second dielectric layer in the first direction. Since two groups of conductors are provided for each capacitor unit 310, the first electrode layers 311 in the two capacitor units 310 directly opposite to each other in the first direction can be electrically connected, and the second electrode layers 312 can be electrically connected. The formation of the first conductor 510 and the second conductor 520 in this step may include a copper growth process. After the copper growth is completed, the surface of the second conductor 520 exposed outside the second conductive area 221 is polished by a CMP process.

[0128] Repeat the above Figures 14 to 19 The corresponding steps can realize the preparation of more capacitor units 310, and finally the capacitor 10 has a1 first dielectric layers 210 (such as Figure 1 as shown).

[0129] In the above method, the substrate layer 100 is not provided with the second groove 110, and the capacitor units 310 are all located in the first groove 211. Therefore, the operation of forming the groove body is performed on the first dielectric layer 210. Since the materials of each first dielectric layer 210 are the same, the same process flow can be used to perform the groove body preparation operation to form the first groove 211.

[0130] It is worth noting that when the capacitor 10 is Figure 5In the structure, that is, when the substrate layer 100 is provided with the second groove 110, the preparation method of the capacitor 10 further includes: preparing a plurality of second grooves 110 on the substrate layer 100 after providing the substrate layer 100 and before preparing the first first dielectric layer 210. The preparation of the second grooves 110 can be achieved by photolithography and etching operations. After the second grooves 110 are formed on the substrate layer 100, when the first dielectric layer 210 is formed by deposition, a film layer of equal thickness is deposited on the substrate layer 100, and the film layer is located in the second groove 110 at the position corresponding to the second groove 110 and adheres to the inner wall of the second groove 110, and the film layer forms the first dielectric layer 210, and the first dielectric layer 210 forms the first groove 211 at the second groove 110 during the deposition process, and there is no need to perform the first groove 211 preparation process on the first dielectric layer 210 separately again. It is worth noting that this method of forming the first groove 211 is only applicable to the first first dielectric layer 210 to be prepared. In the preparation process of other first dielectric layers 210 , the above step S32 needs to be used to form the first groove 211 . Figure 5 The other steps of the preparation process of the capacitor 10 are the same as those described above. Figures 12 to 19 The same is not repeated here.

[0131] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A capacitor, characterized in that: The capacitor is a chip capacitor, and the capacitor comprises: substrate layer; A first dielectric layer, the first dielectric layer is made of an insulating material, a first groove is provided on the first dielectric layer, there are a plurality of the first dielectric layers, and the plurality of the first dielectric layers are sequentially arranged on the substrate layer along a first direction; A capacitor unit, wherein the number of the capacitor units is plural, the plurality of the capacitor units are arranged in one-to-one correspondence with the plurality of the first grooves, at least a portion of the capacitor unit is located in the first groove, and the capacitor units are electrically connected; The capacitor units arranged in two adjacent first dielectric layers are arranged opposite to each other in the first direction, and the two adjacent capacitor units in the first direction are electrically connected; The capacitor also includes a second dielectric layer, the material of the second dielectric layer is the same as that of the first dielectric layer, one second dielectric layer is arranged between every two adjacent first dielectric layers, part of the capacitor unit is located in the second dielectric layer, a first conductive region is arranged on the first dielectric layer between two second dielectric layers, a second conductive region is arranged on each second dielectric layer, the second conductive region is connected to the first conductive region, a first conductor is arranged in the first conductive region, a second conductor is arranged in the second conductive region, the first conductor is electrically connected to the capacitor unit, and the second conductor is electrically connected to two adjacent first conductors.

2. The capacitor according to claim 1, wherein: A plurality of the first grooves are respectively arranged on each of the first dielectric layers, and the plurality of the first grooves are distributed at intervals on the corresponding first dielectric layer.

3. The capacitor according to claim 2, characterized in that In the first dielectric layer, a plurality of the first grooves are spaced apart and distributed along the second direction, a length direction of each of the first grooves is the third direction, and the first direction, the second direction and the third direction are perpendicular to each other.

4. The capacitor according to claim 2, wherein: In the first dielectric layer, a plurality of the first grooves are distributed in an array.

5. The capacitor according to claim 4, characterized in that The projection of the first groove on the first dielectric layer along the first direction is circular.

6. The capacitor according to claim 1, wherein: The capacitor unit includes multiple electrode layers, and a third dielectric layer is arranged between adjacent electrode layers. The multiple electrode layers include at least one first electrode layer and at least one second electrode layer. The polarities of the first electrode layer and the second electrode layer are opposite. The first electrode layers between adjacent capacitor units in the first direction are connected, and the second electrode layers in adjacent capacitor units in the first direction are electrically connected.

7. The capacitor according to any one of claims 1 to 6, characterized in that: The substrate layer is provided with a second groove, a portion of the first dielectric layer adjacent to the substrate layer is located in the second groove, and the first groove is located in the second groove.

8. An electronic device, characterized in that: Comprising a capacitor as described in any one of claims 1-7.

9. A method for manufacturing a capacitor, characterized in that: The capacitor is a chip capacitor, and the method comprises: providing a substrate layer; Prepare a first dielectric layer so that the first dielectric layer has a first groove, the first dielectric layer is located on one side of the substrate layer in a first direction, and the first dielectric layer is made of an insulating material; Preparing a capacitor unit on the first dielectric layer, so that at least a portion of the capacitor unit is located in the first groove; Repeat the steps of preparing the first dielectric layer, forming the first groove on the first dielectric layer, and preparing the capacitor unit on the first dielectric layer until the number of the first dielectric layers reaches a set value; and two capacitor units arranged opposite to each other in the first direction are electrically connected; Before preparing another first dielectric layer on a side of the first dielectric layer away from the substrate layer, the method further comprises: A second dielectric layer is prepared on a side of the first dielectric layer away from the substrate layer, the material of the second dielectric layer is the same as the material of the first dielectric layer, and the second dielectric layer is coated on the outside of the area of ​​the capacitor unit outside the first groove; forming a second conductive region on the second dielectric layer; forming a second conductor in the second conductive area, wherein the second conductor is electrically connected to the capacitor unit in the second dielectric layer; The method for preparing the first dielectric layer located on a side of the second dielectric layer away from the substrate layer further comprises: forming a first conductive region on the first dielectric layer, wherein the first conductive region is connected to the second conductive region; A first conductor is formed in the first conductive region, and the first conductor is electrically connected to the second conductor.

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