A pseudo-random sequence generation unit, generation system, and generation method

Abstract

The application relates to a pseudo-random sequence generation unit, a generation system and a generation method. The generation unit comprises a first generation structure, a second generation structure and a first XOR gate, and the two generation structures are identical in structure. The output of the first generation structure and the output of the second generation structure are connected through the first XOR gate, and the output of the first XOR gate is used as the output of the system to output the generated pseudo-random sequence. Wherein, the first generation structure is used for generating a first pseudo-random sequence according to a first communication protocol and a first generation polynomial, and the second generation structure is used for generating a second pseudo-random sequence according to a second communication protocol and a second generation polynomial. The first communication protocol and the second communication protocol can be the same or different, and the first generation polynomial and the second generation polynomial can be the same or different. Based on the above scheme, when the required pseudo sequence needs to be changed, a new pseudo-random sequence can be generated only by reconfiguring the logic value without redesigning the hardware, thereby saving the hardware resources.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip design technical field, in particular to a pseudo-random sequence generation unit, a generation system and a generation method. BACKGROUND

[0002] The pseudo-random sequence is a sequence that looks like a random generation, but is actually a deterministic sequence calculated by an algorithm. Unlike a truly random sequence, a pseudo-random sequence is generated from a deterministic initial value (seed) and an algorithm, and under the same seed and algorithm, the pseudo-random sequence can always reproduce the same sequence.

[0003] As a commonly used component in communication systems, the pseudo-random sequence is mainly applied in two fields. One is the spread spectrum communication application centered on CDMA technology, which uses an optimized pseudo sequence as a spread spectrum code. Among them, the pseudo-random sequence with a corresponding structure is used as a spread spectrum code according to the needs of the spread spectrum system, for example, the GPS satellite navigation uses a 10th order Golden sequence as a spread spectrum code, and the Beidou satellite navigation of China uses an 11th order Golden sequence as a spread spectrum code. The second is to scramble the data stream transmitted on the communication link by the pseudo-random sequence to prevent the occurrence of continuous high-frequency 01 sequences, which is beneficial to the receiver receiving the data stream, and also encrypts the data stream. Therefore, whether it is various satellite communication application scenarios or various communication physical layer protocol application scenarios, different pseudo-random sequences are needed

[0004] At present, the design of the pseudo-random sequence generation circuit is usually based on the requirements of the specified physical layer protocol or application scenario, so this circuit can only generate a fixed pseudo-random sequence. Once a new pseudo-random sequence requirement appears, this generation circuit will no longer be applicable, and a new generation circuit needs to be designed, which causes a large waste of hardware resources. SUMMARY

[0005] In view of the above problems of the prior art, the present application provides a pseudo-random sequence generation unit with a general structure, a generation system and a generation method, which can generate different pseudo-random sequences by only reconfiguring logic values, thereby saving a large amount of hardware resources.

[0006] To achieve the above object, the first aspect of the present application provides a pseudo-random sequence generation unit, comprising: a first generation structure, a second generation structure and a first exclusive OR gate, wherein the first generation structure and the second generation structure adopt the same components and have the same connection relationship; the output end of the first generation structure and the output end of the second generation structure are connected through the first exclusive OR gate, and the output end of the first exclusive OR gate is used as the output end of the system to output the pseudo-random sequence generated by the generation unit; wherein the first generation structure is used to generate a first pseudo-random sequence according to a first communication protocol and a first generation polynomial, and the second generation structure is used to generate a second pseudo-random sequence according to a second communication protocol and a second generation polynomial; the first communication protocol and the second communication protocol can be the same or different, and the first generation polynomial and the second generation polynomial can be the same or different.

[0007] According to the above, the first pseudo-random sequence is generated by the first generation structure, the second pseudo-random sequence is generated by the second generation structure, and the modulo-2 sum operation is performed on the first pseudo-random sequence and the second pseudo-random sequence by the first exclusive OR gate, so as to generate the final target pseudo-random sequence. Based on the generation unit provided by the present application, when a new pseudo-random sequence is needed, only the logic value of the register in the generation structure needs to be changed, and the hardware circuit does not need to be redesigned, thereby saving the hardware resources.

[0008] As an implementation manner of the first aspect, the first generation structure comprises the following components: a first register group, the first register group comprising a state register, a feedback logic register and an output logic register; a first AND gate group, the first AND gate group comprising a plurality of first AND gates, the same logic bit of the output end of the feedback logic register and the output end of the state logic register being connected through the first AND gate; a second AND gate group, the second AND gate group comprising a plurality of second AND gates, the same logic bit of the output end of the output logic register and the output end of the state logic register being connected through the second AND gate; a second exclusive OR gate, the output end of the plurality of first AND gates being connected to the input end of the second exclusive OR gate, and the output end of the second exclusive OR gate being connected to the highest logic bit of the state logic register; a third exclusive OR gate, the output end of the plurality of second AND gates being connected to the input end of the third exclusive OR gate, and the output end of the third exclusive OR gate being used as the output end of the first generation structure to output the first pseudo-random sequence.

[0009] From the above, the generating structure of the application configures initial logic values through a state register, configures logic values of feedback operations through a feedback logic register, configures output taps through an output logic register, and then generates a pseudo-random sequence through cooperation of AND gates and XOR gates, so that when the generated pseudo-random sequence needs to be changed, only the logic values configured in the three registers need to be changed, and the hardware circuit meeting the requirements does not need to be redesigned, thereby saving hardware resources.

[0010] As an implementation form of the first aspect, the state register, the feedback logic register and the output logic register are all 32-bit registers.

[0011] From the above, most of the sequence generation polynomials on the market at present are not higher than 32 bits, and 32 bits can already meet the existing demand, so the register is designed as 32 bits in this aspect, and in other ways, the number of logic bits of the register can be changed.

[0012] As an implementation form of the first aspect, the generating unit is configured to generate a pseudo sequence based on a linear feedback shift register structure.

[0013] From the above, for example, the generating unit of this aspect can generate M sequences and Golden sequences.

[0014] The second aspect of the application provides a pseudo-random sequence generating system, comprising: a first pseudo-random sequence generating unit configured to generate a pseudo-random sequence for scrambling real parts of communication data; and a second pseudo-random sequence generating unit configured to generate a pseudo-random sequence for scrambling imaginary parts of communication data; wherein the first pseudo-random sequence generating unit and the second pseudo-random sequence generating unit are the pseudo-random sequence generating unit of any one of the first aspect.

[0015] From the above, the first pseudo-random sequence generating unit can generate a pseudo-random sequence for scrambling real parts of communication data, and the second pseudo-random sequence generating unit can generate a pseudo-random sequence for scrambling imaginary parts of communication data, thereby meeting the scrambling requirements of any communication data and making the application scope of this scheme wider.

[0016] The beneficial effects of this aspect can be referred to the descriptions of the beneficial effects of each part of the first aspect.

[0017] The third aspect of the present application provides a pseudo-random sequence generation method, which is based on the generation unit of any one of the first aspect or the generation system of the second aspect, and comprises the following steps: configuring the logic values of the registers in the first generation structure and the second generation structure; generating a first pseudo-random sequence based on the first generation structure and the logic values of the registers in the first generation structure; generating a second pseudo-random sequence based on the second generation structure and the logic values of the registers in the second generation structure; and performing modulo-2 sum operation on the first pseudo-random sequence and the second pseudo-random sequence through a first exclusive OR gate to obtain a target pseudo-random sequence.

[0018] According to the above, the logic values of the registers in the first generation structure and the second generation structure are configured, so that the generation unit or the generation system normally performs relevant operations to generate the target pseudo-random sequence. Since the logic values configured in the scheme can be changed, when the target pseudo-random sequence required changes, the logic values in the registers can be changed only, and a new hardware circuit does not need to be redesigned, thereby saving hardware resources and improving the pseudo-sequence generation efficiency.

[0019] As an implementation manner of the third aspect, the configuration of the logic values of the registers in the first generation structure and the second generation structure comprises the following steps: configuring the logic values of the state registers and the output logic registers in the first generation structure according to a first communication protocol, and configuring the logic values of the feedback logic registers in the first generation structure according to a first generation polynomial; configuring the logic values of the state registers and the output logic registers in the second generation structure according to a second communication protocol, and configuring the logic values of the feedback logic registers in the second generation structure according to a second generation polynomial; wherein the first communication protocol and the second communication protocol can be the same or different, and the first generation polynomial and the second generation polynomial can be the same or different.

[0020] As an implementation manner of the third aspect, the configuration of the logic values of the registers in the first generation structure and the second generation structure comprises the following steps: when the number of logic bits of the registers is greater than a target number of logic bits, the logic bits of the registers are mapped from the highest bit to the lower bit in the order of arrangement, and the redundant logic bits are set to 0.

[0021] According to the above, when the number of logic bits of the registers is greater than the number of logic bits of the required pseudo-sequence, the configuration method of the logic values of the registers is provided, thereby improving the application range of the present scheme.

[0022] As an implementation manner of the third aspect, the target number of logic bits is determined according to the first generation polynomial or the second generation polynomial.

[0023] As an implementation manner of the third aspect, the method further comprises the following steps:

[0024] when the target pseudo-random sequence is an M-sequence: configuring the logic value of each register in the first generation structure as 0, or configuring the logic value of each register in the second generation structure as 0.

[0025] The beneficial effects of the present aspect can be seen from the description of the beneficial effects of each part of the first aspect.

[0026] The fourth aspect of the present application provides a chip comprising the pseudo-random sequence generation unit of any one of the first aspect, or the pseudo-random sequence generation system of the second aspect.

[0027] The beneficial effects of the present aspect can be seen from the description of the beneficial effects of each part of the first aspect.

[0028] The fifth aspect of the present application provides a chip comprising generating a pseudo-random sequence using the pseudo-random sequence generation method of any one of the third aspect.

[0029] The beneficial effects of the present aspect can be seen from the description of the beneficial effects of each part of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0030] The various technical features of the present application and the relationship between them will be further described below with reference to the accompanying drawings. The drawings are exemplary, some technical features are not shown in actual proportion, and some technical features in the drawings can be omitted, which are conventional in the technical field to which the present application belongs and are not essential for understanding and implementing the present application, or additional technical features are shown, which are not essential for understanding and implementing the present application, that is, the combination of various technical features shown in the drawings is not used to limit the present application. In addition, throughout the present application, the same reference signs refer to the same contents. The specific drawings are as follows:

[0031] Figure 1 A structural schematic diagram of a pseudo-random sequence generation unit provided for an embodiment of the present application;

[0032] Figure 2 A structural schematic diagram of a pseudo-random sequence generation system provided for an embodiment of the present application;

[0033] Figure 3 A flowchart of a pseudo-random sequence generation method provided for an embodiment of the present application;

[0034] Figure 4 A generation structure schematic diagram currently used for generating a WCDMA scrambling sequence in a 3GPP standard protocol;

[0035] Figure 5 A structural schematic diagram of a computing device provided for an embodiment of the present application. DETAILED DESCRIPTION

[0036] The technical solutions provided by the present application are further described below in combination with the drawings and examples. It should be understood that the system structures and service scenarios provided in the examples of the present application are mainly to illustrate possible implementation manners of the technical solutions of the present application, and should not be interpreted as the only limitation of the technical solutions of the present application. Those skilled in the art can know that the technical solutions provided by the present application are also applicable to similar technical problems as the system structure evolves and new service scenarios appear.

[0037] It should be understood that the examples of the present application provide a pseudo-random sequence generation unit, a generation system and a generation method. Since the principles of solving problems of these technical solutions are the same or similar, in the introduction of the following specific examples, some repetitions may not be described again, but should be regarded as mutual reference and mutual combination between these specific examples.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. If there is any inconsistency, the meaning explained in the specification or the meaning derived from the content described in the specification shall prevail. In addition, the terms used herein are only for the purpose of describing the examples of the present application and are not intended to limit the present application. In order to accurately describe the technical content in the present application and to accurately understand the present application, before the specific embodiments are described, the terms used in the specification are first explained as follows:

[0039] 1) M sequence: M sequence is a pseudo-random sequence generated by a linear feedback shift register (LFSR).

[0040] 2) Golden sequence: Golden sequence is a characteristic M sequence, which is generated by modulo-2 addition of two M sequences with equal code length and same code clock rate.

[0041] 3) Modulo-2 sum: a binary operation, equivalent to the "XOR" operation.

[0042] 4) Output tap: the output tap refers to selecting the bit of a particular register to do modulo-2 sum operation and output, and the selected position is the tap.

[0043] The pseudo-random sequence generation scheme provided by the present application can be applied in many fields such as cryptography and computer science. For example, it can be applied in spread spectrum applications of communication systems to generate spread spectrum codes. For another example, it can be applied on a communication link to scramble the transmitted data stream.

[0044] A pseudo-random sequence generation unit provided by the first example of the present application is described in detail below. As shown in FIG. 1, the pseudo-random sequence generation unit comprises a shift register 1, a modulo-2 adder 2 and a feedback circuit 3. Figure 1The pseudo-random sequence generating unit 10 is shown in a structural schematic diagram. The pseudo-random sequence generating unit 10 comprises a first generating structure 110, a second generating structure 120 and a first exclusive OR gate 130. The output X i of the first generating structure 110 and the output Y i of the second generating structure 120 are connected through the first exclusive OR gate 130, through which the output X i of the first generating structure 110 and the output Y i of the second generating structure 120 are subjected to a modulo-2 sum operation (essentially an exclusive OR operation), and the operation result of the modulo-2 sum is output as the pseudo-random sequence generated by the generating unit 10 (i.e. Figure 1 the output Z i of the first exclusive OR gate 130).

[0045] Next, each structure is described in detail.

[0046] The first generating structure 110 comprises a first register group 111, which comprises a state register X i_state_reg, a feedback logic register X i_feedback_mask_reg and an output logic register X i_out_mask_reg. The logic bit number of each register is the same, for example, each can be a 32-bit register, each can be a 64-bit register, each can be an 18-bit register, etc. It should be understood that the register bit number described above is only an exemplary description and does not limit the present application.

[0047] The first generating structure 110 further comprises a first AND gate group 112, which comprises a plurality of first AND gates. The number of first AND gates is the same as the logic bit number of each register in the first register group, i.e. one AND gate corresponds to one logic bit. For example, if each register in the first register group is a 32-bit register, then the first AND gate group 112 also comprises 32 first AND gates. In the present embodiment, the first AND gate group 112 is associated with the first register group 111 by being connected to the feedback logic register X i_feedback_mask_reg and the state register X i_state_reg. Specifically, the same logic bit of the output end of the feedback logic register X i_feedback_mask_reg and the output end of the state register X i_state_reg is connected through a first AND gate, i.e. in a 32-bit register, the output end of the 31st bit of the feedback logic register X i_feedback_mask_reg and the output end of the 31st bit of the state register X i_state_reg are connected through a first AND gate, and so on, until the output end of the 0th bit of the feedback logic register X i_feedback_mask_reg and the output end of the 0th bit of the state register X i_state_reg are connected through an AND gate, thereby completing the connection of the first AND gate group 112 and the first register group 111.

[0048] The first generation structure 110 further comprises a second AND gate group 113, which comprises a plurality of second AND gates, the number of which is the same as the number of logical bits of each register in the first register group. For example, if each register in the first register group is a 32-bit register, then the second AND gate group 113 also comprises 32 second AND gates. In this embodiment, the second AND gate group 113 is associated with the first register group 111 by being connected to the output logical register Xi_out_mask_reg and the state register Xi_state_reg, specifically: the same logical bit of the output end of the output logical register Xi_out_mask_reg and the output end of the state register Xi_state_reg is connected by a second AND gate, that is, in a 32-bit register, the output end of the 31st bit of the output logical register Xi_out_mask_reg and the output end of the 31st bit of the state register Xi_state_reg are connected by a second AND gate, and so on, until the output end of the 0th bit of the output logical register Xi_out_mask_reg and the output end of the 0th bit of the state register Xi_state_reg are connected by an AND gate, thereby completing the connection of the second AND gate group 113 and the first register group 111.

[0049] The first generation structure 110 further comprises a second XOR gate 114, the output end of each AND gate in the above-mentioned first AND gate group 112 is connected to the input end of the second XOR gate 114, and the output end of the second XOR gate 114 is connected to the highest logical bit of the state register Xi_state_reg. That is, the second XOR gate 114 performs a modulo-2 sum operation on the output results of all the AND gates in the first AND gate group 112, and then feeds back the result of the modulo-2 sum operation to the highest logical bit of the state register Xi_state_reg, thereby updating the sequence in the state register Xi_state_reg.

[0050] The first generation structure 110 further comprises a third XOR gate 115, the output end of each AND gate in the above-mentioned second AND gate group 113 is connected to the input end of the third XOR gate 115, that is, the third XOR gate 115 performs a modulo-2 sum operation on the output results of all the AND gates in the second AND gate group 113, and the output end of the third XOR gate 115 is used as the output end of the first generation structure 110 to output the first pseudo-random sequence (the output first pseudo-random sequence is the result obtained by the operation of the third XOR gate 115).

[0051] In some embodiments, the first pseudo-random sequence generated by the first generation structure 110 is an M-sequence.

[0052] In some embodiments, the first generation structure 110 is configured to generate the first pseudo-random sequence according to a first communication protocol or user demand and a first generation polynomial. Specifically, first, the user selects a suitable communication protocol according to the scenario in which the first pseudo-random sequence is applied. The communication protocol generally specifies a scrambling initial value, i.e., a state initial value, according to which the logic bits of the state register Xi_state_reg are configured. In some embodiments, the user can also modify the state initial value according to demand to obtain a first pseudo-random sequence that meets the target. Next, the user configures the output taps of the output logic register Xi_out_mask_reg according to the provisions of the communication protocol or the demand of the application scenario, i.e., sets the selected output logic bits of the output logic register Xi_out_mask_reg to 1 and the remaining logic bits to 0. Finally, the values of the logic bits of the feedback logic register Xi_feedback_mask_reg are configured according to the generation polynomial. After the configuration is completed, the generation unit 10 performs corresponding logical operations to generate a first pseudo-random sequence Xi that meets the target.

[0053] The second generation structure 120 uses the same components as the first generation structure 110 and has the same connection relationship, i.e., the second generation structure 120 also includes the first register group 111, the first AND gate group 112, the second AND gate group 113, the second XOR gate 114, and the third XOR gate 115, and the connection relationship between the components and among the groups is the same as that of the first generation structure 110. Therefore, the second generation structure 120 will not be described again here.

[0054] In this embodiment, the second generation structure 120 outputs the second pseudo-random sequence through the output end of the third XOR gate 115, and the second pseudo-random sequence is denoted as Yi. The second pseudo-random sequence is also an M sequence.

[0055] In some embodiments, the second generation structure 120 is configured to generate the second pseudo-random sequence according to a second communication protocol or user demand and a second generation polynomial. The specific configuration method of each register can be referred to the first generation structure 110, and will not be described again here.

[0056] In some embodiments, the first communication protocol and the second communication protocol can be the same or different, and the first generation polynomial and the second generation polynomial can be the same or different.

[0057] The first XOR gate 130 is used to connect the first generation structure 110 and the second generation structure 120. Specifically, the output end of the first generation structure 110 and the output end of the second generation structure 120 are connected with the first XOR gate 130, the first XOR gate 130 performs modulo-2 addition operation on the first pseudo-random sequence Xi output by the first generation structure 110 and the second pseudo-random sequence Yi output by the second generation structure 120, thereby obtaining the pseudo-random sequence Zi finally generated by the pseudo-random sequence generation unit 10.

[0058] It should be understood that the first generation structure 110 and the second generation structure 120 can respectively output one M sequence, and the Golden sequence is generated by performing modulo-2 addition on two M sequences. Therefore, the generation unit 10 provided in the embodiment can output both M sequence and Golden sequence. When only one pseudo-random sequence (M sequence) is needed, the enable signal of one of the modules can be turned off to make it not work, or the logic bits of the register corresponding to the signal are all configured as 0, that is, the M sequence is generated. When the Golden sequence needs to be generated, the registers of the two generation structures are normally configured according to the requirement, and the Golden sequence can be generated.

[0059] It should be noted that the order of the polynomial supported by the pseudo-random sequence generation unit 10 should be less than or equal to the bit number of the register. For example, if the register is 32 bits, the order of the supported generation polynomial should be 32 or below; if the register is 64 bits, the order of the supported generation polynomial should be 64 or below.

[0060] The pseudo-random sequence generation unit 10 provided in the embodiment of the present application is a general generation unit, which can output different pseudo-random sequences by changing the logic values of the logic bits of the state register Xi_state_reg, the feedback logic register Xi_feedback_mask_reg, and / or the output logic register Xi_out_mask_reg through software, without the need to redesign the mechanism of the generation unit after the target pseudo-random sequence changes, thereby saving hardware resources.

[0061] Next, the working principle of the pseudo-random sequence generation unit 10 will be introduced.

[0062] Step one: initial value configuration of each register through a hardware interface.

[0063] In this step, the initial values of the respective logic bits of the state register Xi_state_reg are configured according to the type of the target pseudo-random sequence and / or the communication protocol required, and the output taps of the output logic register Xi_out_mask_reg are configured according to the type of the target pseudo-random sequence and / or the communication protocol required. Then the respective logic bits of the feedback logic register Xi_feedback_mask_reg are configured according to the generation polynomial, i.e. the initial value configuration of the respective registers is completed.

[0064] Step two: apply the enable signal to the first generation structure 110 and / or the second generation structure 120 according to the requirement.

[0065] In this step, if the target pseudo-random sequence required is an M sequence, the enable signal of the first generation structure 110 or the second generation structure 120 is turned on, and the enable signal of the other generation structure is turned off.

[0066] In this step, if the target pseudo-random sequence required is a Golden sequence, the enable signals of the first generation structure 110 and the second generation structure 120 are both turned on.

[0067] Step three: the pseudo-random sequence generation unit 10 starts working: the respective corresponding bits of the feedback logic register Xi_feedback_mask_reg and the state register Xi_state_reg are subjected to phase-and operation by the first AND gate respectively, the result of the operation is output to the second XOR gate 114 for modulo-2 sum operation, and the result of the modulo-2 sum operation is fed back to the highest bit of the state register Xi_state_reg to update the logic value of the state register. It should be noted that in the figure, the leftmost side of the register represents the highest bit, and the rightmost side represents the lowest bit. The respective corresponding bits of the output logic register Xi_out_mask_reg and the state register Xi_state_reg are subjected to phase-and operation by the second AND gate respectively, the result of the operation is output to the third XOR gate 115 for modulo-2 sum operation, and the result of the modulo-2 sum operation of the third XOR gate 115 is taken as the output of the generation structure.

[0068] Step four: the pseudo-random sequences output by the two generation structures are subjected to modulo-2 sum operation by the first XOR gate 130, thereby outputting the final generated target pseudo-random sequence Zi.

[0069] It should be understood that when only one generation structure is working normally, the output of the pseudo-random sequence generation unit 10 is the pseudo-random sequence generated by the working generation structure. When both generation structures are working normally, the output of the pseudo-random sequence generation unit 10 is the modulo-2 sum of the pseudo-random sequences generated by the two generation structures.

[0070] The second embodiment of the present application provides a pseudo-random sequence generation system 20, which will be described below in combination with Figure 2 The pseudo-random sequence generation system 20 provided by the present embodiment will be described in detail. The pseudo-random sequence generation system 20 includes two groups of pseudo-random sequence generation units, i.e., a first pseudo-random sequence generation unit 210 and a second pseudo-random sequence generation unit 220. The components included in each pseudo-random sequence generation unit and the connection structure are the same as those of the first embodiment, and thus will not be described again.

[0071] In the present embodiment, the real part of the communication link data stream is scrambled by the pseudo-random sequence Zi generated by the first pseudo-random sequence generation unit 210, and the imaginary part of the communication link data stream is scrambled by the pseudo-random sequence Zq generated by the second pseudo-random sequence generation unit 220. The pseudo-random sequence generation system 20 provided by the present embodiment can basically meet the current technical requirements for generating pseudo-sequences.

[0072] In addition, the specific implementation of each component in the present embodiment, or the specific use, role or function achieved, can refer to the description in the first embodiment, and will not be described again.

[0073] The third embodiment of the present application provides a pseudo-random sequence generation method, which will be described below in combination with Figure 3 The generation method will be described in detail, which includes steps S310-S340:

[0074] S310: configuring the logic values of the registers in the first generation structure and the second generation structure.

[0075] In the present step, the logic values of the state register Xi_state_reg and the output logic register Xi_out_mask_reg in the first generation structure are configured according to the first communication protocol, and the logic value of the feedback logic register Xi_feedback_mask_reg in the first generation structure is configured according to the first generation polynomial. The logic values of the state register Xi_state_reg and the output logic register Xi_out_mask_reg in the second generation structure are configured according to the second communication protocol, and the logic value of the feedback logic register Xi_feedback_mask_reg in the second generation structure is configured according to the second generation polynomial. It should be understood that the first communication protocol and the second communication protocol herein can be the same or different, and the first generation polynomial and the second generation polynomial can be the same or different.

[0076] In some embodiments, the logic values specified in the communication protocol can also be changed according to the needs, so that the generated pseudo-random sequence is more consistent with the current application scenario.

[0077] In some embodiments, when the number of logical bits of each register is greater than the target number of logical bits, since the feedback value of the feedback register is located at the highest bit (leftmost) of the state register, the mapping can be performed from the highest bit to the lower bits in the order of the arrangement of the logical bits of each register, and the excess logical bits are set to 0. For example, the number of logical bits of each register is 32, and the target number of logical bits is 18. Then, the 18 bits from the highest bit to the left are moved as the effective logical bits in the order of the arrangement of the logical bits of the register, and the excess logical bits (14 bits from right to left) are set to 0.

[0078] It should be noted that the target number of logical bits is determined according to the generation polynomial, that is, the highest order in the generation polynomial is the target number of logical bits.

[0079] S320: generating a first pseudo-random sequence based on the first generation structure and the logical values of each register in the first generation structure.

[0080] In this step, the first pseudo-random sequence is generated by adding an enable signal to the first generation structure to perform logical operation on each component. The specific logical operation process can be referred to the description of the working principle of the first embodiment.

[0081] S330: generating a second pseudo-random sequence based on the second generation structure and the logical values of each register in the second generation structure.

[0082] In this step, the second pseudo-random sequence is generated by adding an enable signal to the second generation structure to perform logical operation on each component. The specific logical operation process can be referred to the description of the working principle of the first embodiment.

[0083] S340: performing modulo-2 sum operation on the first pseudo-random sequence and the second pseudo-random sequence through the first XOR gate to obtain a target pseudo-random sequence.

[0084] In this step, the specific calculation process can be referred to the description of the working principle of the first embodiment.

[0085] In addition, the specific implementation of each component in this embodiment, or the specific use, role or function achieved, can be referred to the description in the first embodiment or the second embodiment, and will not be described here.

[0086] In order to better understand the present application, the application will be further described in detail in combination with the fourth embodiment. In this embodiment, the application of the pseudo-random sequence generation system provided by the present application is described by taking the WCDMA scrambling sequence described in the 3GPP protocol as an example. In the WCDMA scrambling sequence described in the 3GPP protocol, the scrambling code is Golden code, and the generation polynomial is G(x1) = 1 + X 7 +X18 and G(x2)=1+X 5 +X 7 +X 10 +X 18 .

[0087] Its pseudo-sequence generation structure, designed using existing technology (i.e., the structure currently used in standard protocols), is as follows: Figure 4 As shown, based on Figure 4 It can be seen that the scrambling code consists of two sets of sequences: the first set is the I-path, and the second set is the Q-path.

[0088] First, let's analyze path I:

[0089] The I-path is obtained by modulo-2 sum of two signals, which can be equivalent to Xi and Yi in this application. Xi and Yi both come from bit 0 of their respective registers, that is, the output taps of the two output logic registers Xi_out_mask_reg and Yi_out_mask_reg are bit 0. Therefore, bit 0 of Xi_out_mask_reg and Yi_out_mask_reg is set to 1, and the other bits are set to 0.

[0090] By generating the polynomial G(x1) = 1 + X 7 +X 18 It can be seen that bits 0 and 7 of the feedback register corresponding to Xi should be set to 1, and the remaining bits should be 0; this is achieved by using the generator polynomial G(x2) = 1 + X. 5 +X 7 +X 10 +X 18 It can be seen that bits 0, 5, 7, and 10 of the feedback register corresponding to Yi should be set to 1, and the remaining bits should be 0.

[0091] According to the protocol, the status register has its 0th bit set to 1 and the rest of the bits set to 0, while all logic bits in the Yi_state_reg are set to 1.

[0092] Then analyze the Q path:

[0093] The Q-path is also obtained by modulo-2 sum of two signals, therefore these two signals can be equivalent to Xq and Yq in this application. The output of Xq comes from bits 4, 6, and 15 of the register, and the output of Yq comes from bits 5, 6, 8, 9, 10, 11, 12, 13, 14, and 15 of the register. Therefore, according to the above bit configuration, the corresponding positions of the output taps of the output logic registers Xq_out_mask_reg and Yq_out_mask_reg are set to 1, and the remaining positions are set to 0.

[0094] Since the generating polynomial is still G(x1) = 1 + X 7 +X 18 and G(x2) = 1 + X 5 +X 7 +X 10 +X 18 , the logic value of the feedback register corresponding to Xq is the same as that of the feedback register corresponding to Xi, i.e., the 0th and 7th bits are set to 1 and the rest are set to 0. The logic value of the feedback register corresponding to Yq is the same as that of the feedback register corresponding to Yi, i.e., the 0th, 5th, 7th and 10th bits are set to 1 and the rest are set to 0.

[0095] The state register is set to 0 in the 0th position and 1 in the rest positions of Xq_state_reg and all the logic bits of Yq_state_reg are set to 1 according to the protocol.

[0096] The above analysis is made under the condition of 18-bit width, while the pseudo-random sequence generation system of the present application can be 32-bit or 64-bit, etc. Hereinafter, how to map 18-bit to 32-bit is described by taking the pseudo-random sequence generation system of the present application as 32-bit as an example. It should be noted that the feedback logic register is always the highest bit fed back to the state logic register, so the highest bit of the feedback needs to be aligned, that is, the 18-bit in the above analysis corresponds to the 31st bit (the lowest bit is the 0th bit and the highest bit of the 32-bit register is the 31st bit) of the actual feedback logic register in the 32-bit actual circuit. Then the lower 14 bits of the 32-bit register are mapped in turn from the highest bit (31st bit), so the lower 14 logic bits are redundant and need to be set to 0.

[0097] The configuration values of the registers in the pseudo-random sequence generation system provided by the embodiment of the present application for the WCDMA scrambling sequence described in the 3GPP protocol are shown in Table 1 below, so that the WCDMA scrambling sequence described in the 3GPP protocol can be generated by the pseudo-random sequence generation system.

[0098] Table 1

[0099]

[0100]

[0101] If the pseudo-random sequence generation system is not 32-bit but 28-bit, the remaining lower 10 bits are all set to 0 by the same rule of alignment from the highest bit and mapping in turn.

[0102] If the pseudo-random sequence generation system is 32 bits, and the highest order of the generation polynomial is 12, the upper 12 bits of the 32 bits are configured according to the mapping rule, and the lower 20 bits are all configured as 0.

[0103] Based on the above description, the pseudo-random sequence generation system provided by the embodiment of the application is a general generation system, which can support generation of any pseudo-random sequence with an order not greater than the total number of bits of the register.

[0104] Taking a scrambling code commonly used in digital broadcast creation standards as an example, the generation polynomial is G(x) = 1 + x 14 +x 15 , the scrambling initial value is arbitrary (i.e., the initial value of the state logic register is an arbitrary value), and the pseudo-random sequence of the scrambling code is required to be an M sequence. The register values in the above formula (1) are configured according to Table 2 below, and the scrambling code sequence required by the protocol can be realized, which is output by Zi in the above formula (1). Figure 2 Figure 2

[0105] Table 2

[0106]

[0107] Taking a spreading code (C / A) code in a GPS satellite navigation system as an example, the generation polynomial is G(x1) = 1 + x 3 +x 10 , G(x2) = 1 + x 2 +x 3 +x 6 +x 8 +x 9 +x 10 , the scrambling initial value is all 1 (i.e., the initial value of the state logic register is all 1), and the pseudo-random sequence of the scrambling code is required to be a Golden code. The register values in the above formula (1) are configured according to Table 3 below, and the required GPS C / A code can be realized, which is output by Zi in the above formula (1). Figure 2 Figure 2

[0108] Table 3

[0109]

[0110]

[0111] Taking a B1 spreading code defined in a Beidou navigation system as an example, the generation polynomial is G(x1) = 1 + x + x 7 +x 8 +x 9 +x 10 +x 11 , G(x2) = 1 + G(x2) = 1 + x + x 2 +x​​​​3 +x 4 +x 5 +x 8 +x 9 +x 11 The scrambling initial value is 01010101010 (i.e. the initial value of the state logic register is 01010101010), the spread spectrum code is required to be a Golden code, and the following is required: Figure 2 The register values in the above table 4 are configured, and the required GPS C / A code is implemented, and the sequence is output by Zi in the above table 4. Figure 2

[0112] Table 4

[0113]

[0114] Based on the pseudo-random sequence generation unit or the pseudo-random sequence generation system provided in the embodiments of the present application, and the values of the registers are configured and changed according to the pseudo-random sequence generation method provided in the embodiments of the present application, so that a set of generation unit or generation system can generate multiple pseudo-random sequences, so that when the target pseudo-random sequence changes, a new pseudo-random sequence can be generated through the structure provided in the present application without re-designing the hardware structure, thereby saving hardware resources and development time.

[0115] The fifth embodiment of the present application provides a chip, which includes the pseudo-random sequence generation unit or the pseudo-random sequence generation system in the above embodiments.

[0116] The sixth embodiment of the present application provides another chip, which includes generating a pseudo-random sequence using the pseudo-random sequence generation method in the above embodiments.

[0117] Figure 5 is a structural schematic diagram of a computing device 900 provided in the embodiments of the present application. The computing device can execute the optional embodiments of the pseudo-random sequence generation method described above, and the computing device can be a terminal, a chip or a chip system inside the terminal. As shown in Figure 5 The computing device 900 includes a processor 910, a memory 920 and a communication interface 930.

[0118] It should be understood that Figure 5 The communication interface 930 in the computing device 900 shown can be used for communication between other devices, and can specifically include one or more transceiver circuits or interface circuits.

[0119] ​The processor 910 can be connected with the memory 920. The memory 920 can be used to store the program code and data. Therefore, the memory 920 can be a storage unit inside the processor 910, can be an external storage unit independent of the processor 910, or can be a component including the storage unit inside the processor 910 and the external storage unit independent of the processor 910.

[0120] Optionally, the computing device 900 can further include a bus. The memory 920 and the communication interface 930 can be connected with the processor 910 through the bus. The bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, Figure 5 In the figure, a line without an arrow is used to represent one bus, but it does not mean that there is only one bus or only one type of bus.

[0121] It should be understood that, in the embodiments of the present application, the processor 910 can be a central processing unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gates or transistor logic, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. Alternatively, the processor 910 uses one or more integrated circuits to execute related programs to implement the technical solutions provided by the embodiments of the present application.

[0122] The memory 920 can include read-only memories and random access memories, and provide instructions and data for the processor 910. A part of the processor 910 can also include a non-volatile random access memory. For example, the processor 910 can also store device type information.

[0123] When the computing device 900 is running, the processor 910 executes computer execution instructions in the memory 920 to perform any operation steps of the above method and any optional embodiments thereof.

[0124] It should be understood that the computing device 900 according to the embodiments of the present application can correspond to the respective subject performing the method according to the embodiments of the present application, and the above and other operations and / or functions of the respective modules in the computing device 900 are respectively for realizing the respective processes of the method according to the embodiments of the present application, and for brevity, will not be repeated here.

[0125] Those skilled in the art can clearly understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0126] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0127] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are merely schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed units can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0128] The units described as separate components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e. can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to realize the purposes of the embodiments of the present application.

[0129] In addition, each functional unit in the embodiments of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0130] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that make contributions to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

[0131] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program. The program is executed by a processor to perform the above method, which includes at least one of the schemes described in the above embodiments.

[0132] The computer storage medium of the embodiments of the present application can adopt any combination of one or more computer readable media. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium may, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples (non-exhaustive list) of the computer readable storage medium include: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or apparatus.

[0133] The computer readable signal medium can include a data signal propagated in a baseband or as a part of a carrier wave, in which a computer readable program code is carried. Such a propagated data signal can take various forms, including but not limited to an electromagnetic signal, an optical signal or any suitable combination of the above. The computer readable signal medium can also be any computer readable medium other than the computer readable storage medium, which can send, propagate or transmit a program for use by or in conjunction with an instruction execution system, device or apparatus.

[0134] The program code embodied on the computer readable media can be transmitted using any appropriate medium, including but not limited to wireless, wire line, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0135] Computer program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0136] In addition, the use of the terms "first", "second", "third" etc. or "module A", "module B", "module C" etc. in the description and claims herein merely denote different instances of similar objects and does not connote a specific order or sequence of execution. It is to be understood that the embodiments described herein can be carried out in any order unless otherwise specified herein.

[0137] In the description above, reference is made to steps of the method, which are represented by numerals such as S110, S120, etc. These numerals do not necessarily indicate that the steps have to be executed in the order in which they are described, but that they are executed in any order that is permitted, or even simultaneously.

[0138] The term "comprising", used in the description and in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted that the described

[0139] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but can refer to different embodiments. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0140] It is noted that the foregoing are merely preferred embodiments of, and the technical principles applied to, the present application. It can be understood by those skilled in the art that the present application is not limited to the particular embodiments described herein, and that various obvious changes, modifications and replacements can be made by those skilled in the art without departing from the scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and all of the embodiments belong to the protection scope of the present application.

Claims

1. A pseudo-random sequence generation unit, characterized in that, The first generation structure and the second generation structure adopt the same components and have the same connection relationship. The output end of the first generation structure and the output end of the second generation structure are connected through the first XOR gate, and the output end of the first XOR gate is used as the output end of the generation unit to output the pseudo-random sequence generated by the generation unit. The first generation structure is used to generate a first pseudo-random sequence according to a first communication protocol and a first generation polynomial, and the second generation structure is used to generate a second pseudo-random sequence according to a second communication protocol and a second generation polynomial; the first communication protocol and the second communication protocol can be the same or different, and the first generation polynomial and the second generation polynomial can be the same or different. The first generation structure comprises the following components: A first register group comprising a state register, a feedback logic register, and an output logic register; A first AND gate group comprising a plurality of first AND gates, and the same logic bit of the output end of the feedback logic register and the output end of the state register is connected through the first AND gate; A second AND gate group comprising a plurality of second AND gates, and the same logic bit of the output end of the output logic register and the output end of the state register is connected through the second AND gate; A second XOR gate, the output end of the plurality of first AND gates is connected with the input end of the second XOR gate, and the output end of the second XOR gate is connected to the highest logic bit of the state register; A third XOR gate, the output end of the plurality of second AND gates is connected with the input end of the third XOR gate, and the output end of the third XOR gate is used as the output end of the first generation structure to output the first pseudo-random sequence; The second generation structure adopts the same components as the first generation structure and has the same connection relationship.

2. The generating unit of claim 1, wherein, The state register, the feedback logic register, and the output logic register are all 32-bit registers.

3. The generating unit of claim 1, wherein, The generation unit is used to generate a pseudo sequence based on a linear feedback shift register structure.

4. A pseudo-random sequence generation system characterized by, It comprises: A first pseudo-random sequence generation unit for generating a pseudo-random sequence for scrambling a real part of communication data; A second pseudo-random sequence generation unit for generating a pseudo-random sequence for scrambling an imaginary part of communication data; The first pseudo-random sequence generation unit and the second pseudo-random sequence generation unit are the pseudo-random sequence generation units of any one of claims 1-3.

5. A method for generating a pseudo-random sequence, the method being implemented on the basis of a generating unit according to any one of claims 1 to 3 or on the basis of a generating system according to claim 4, characterized in that, It comprises: Configuring the logic values of the registers in the first generation structure and the second generation structure; Generating a first pseudo-random sequence based on the logic values of the registers in the first generation structure and the first generation structure; Generating a second pseudo-random sequence based on the logic values of the registers in the second generation structure and the second generation structure; Performing a modulo-2 sum operation on the first pseudo-random sequence and the second pseudo-random sequence through a first XOR gate to obtain a target pseudo-random sequence.

6. The generation method of claim 5, wherein, The configuration of the logic values of the registers in the first generation structure and the second generation structure comprises: configuring logic values of the state registers and the output logic registers in the first generation structure according to a first communication protocol, and configuring logic values of the feedback logic registers in the first generation structure according to a first generation polynomial; configuring logic values of the state registers and the output logic registers in the second generation structure according to a second communication protocol, and configuring logic values of the feedback logic registers in the second generation structure according to a second generation polynomial; wherein the first communication protocol and the second communication protocol can be the same or different, and the first generation polynomial and the second generation polynomial can be the same or different.

7. The generation method of claim 5, wherein, The configuration of the logic values of the registers in the first generation structure and the second generation structure comprises: when the number of logic bits of the registers is greater than a target number of logic bits, mapping from the highest bit to the lower bits in the order of arrangement of the logic bits of the registers, and setting the redundant logic bits to 0.

8. The generation method of claim 6, wherein, The configuration of the logic values of the registers in the first generation structure and the second generation structure comprises: when the number of logic bits of the registers is greater than a target number of logic bits, mapping from the highest bit to the lower bits in the order of arrangement of the logic bits of the registers, and setting the redundant logic bits to 0.

9. The generation method of claim 7, wherein, The target number of logic bits is determined according to the first generation polynomial or the second generation polynomial.

10. The generation method of claim 5, wherein, Further comprising: when the target pseudo-random sequence is an M sequence: configuring the logic values of the registers in the first generation structure to 0, or configuring the logic values of the registers in the second generation structure to 0.

11. A chip, characterized by The pseudo-random sequence generation unit of any one of claims 1-3, or the pseudo-random sequence generation system of claim 4.

12. A chip, characterized by The pseudo-random sequence generation method of any one of claims 5-9 is used to generate a pseudo-random sequence.

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