Non-volatile DFF for FPGA based on variable resistance resistor

Abstract

The present invention relates to a non-volatile DFF for FPGA based on a variable resistance resistor. It comprises: a DFF functional unit body, including a latch unit and a variable resistance resistor unit adaptively connected to the latch unit, the latch unit correspondingly connected to the data input port and the data output end of the non-volatile DFF; a timing signal circuit, receiving a work instruction signal, and configuring the operation state of the DFF functional unit body based on the received work instruction signal, wherein the operation state of the configured DFF functional unit body includes an electrical forming operation, a reset operation, a DFF function, a data saving operation SET and / or a data recovery operation RES; the present invention realizes a non-volatile DFF based on a variable resistance resistor, is compatible with the existing CMOS process, and reduces the writing time.

Description

Technical Field

[0001] The invention relates to a non-volatile DFF, in particular to a non-volatile DFF for FPGA based on a variable resistance resistor. Background Art

[0002] FPGA (Field Programmable Gate Array) is a hardware programmable logic device. In addition to being used in mobile communications, data centers and other fields, it is also widely used in prototype verification in integrated circuit design. It can effectively verify the correctness of circuit functions and speed up circuit design.

[0003] For FPGAs that use conventional volatile SRAM, when the DFF (D-type flip-flop) loses power, there are problems such as information loss in the DFF and low reliability, making it difficult to apply in fields such as aerospace that require frequent restarts due to particle interference or total dose effects.

[0004] At present, the non-volatile DFF based on Flash technology solves the above difficulties. However, since the Flash process requires high-voltage devices to implement the erase and programming circuits, the FPGA based on Flash technology is difficult to be compatible with the most advanced CMOS process, and the size is difficult to be less than 40nm. In addition, the Flash write operation takes 10μS to 1mS, which is a long time and has low write efficiency. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a non-volatile DFF for FPGA based on a variable resistance resistor, which implements a non-volatile DFF based on a variable resistance resistor, is compatible with the existing CMOS process, and reduces the writing time.

[0006] According to the technical solution provided by the present invention, a non-volatile DFF for FPGA based on a variable resistance resistor comprises:

[0007] The DFF functional unit body includes a latch unit and a variable resistance unit adapted to be connected to the latch unit, wherein the latch unit is correspondingly connected to the data input port and the data output end of the non-volatile DFF, wherein:

[0008] The latch unit includes at least two latch circuits that are adaptively connected, the variable resistance resistor unit includes at least two variable resistance resistors, and one latch circuit is adaptively connected to at least one variable resistance resistor;

[0009] A timing signal circuit receives a work instruction signal and configures an operation state of the DFF functional unit body based on the received work instruction signal, wherein the received work instruction signal includes a clock signal CK, a set signal SEB, a forming signal FOM, a data saving signal SET, a data recovery signal RES, and a variable resistance reset signal RET, and the configured operation state of the DFF functional unit body includes an electrical forming operation, a reset operation, a DFF function, a data saving operation SET, and / or a data recovery operation RES;

[0010] Based on the forming signal FOM, the programming voltage PHV and the setting signal SEB, an electrical forming operation is performed on all the variable resistance resistors in the DFF functional unit body, so that after the electrical forming operation, all the variable resistance resistors are configured to be in a low resistance state LRS state;

[0011] Based on the data DATA loaded from the data input port, the clock signal CK, the variable resistance reset signal RET and the set signal SEB, the variable resistance in the variable resistance unit is reset in sequence, so that after the reset operation, the corresponding variable resistance in the variable resistance unit is restored to the high resistance state HRS;

[0012] When the DFF functional unit is in the DFF function, based on the clock signal CK, the data DATA loaded by the data input port is collected and output through the data output terminal, and when the set signal SEB is valid, the data output terminal is configured to be in the set state;

[0013] Based on the data storage signal SET, the set signal SEB and the programming voltage PHV, a data storage operation SET is performed on the variable resistance unit, so that after the data storage operation SET, the output state of the data output terminal is stored by a variable resistance resistor;

[0014] After the output state of the data output terminal is stored by the variable resistance unit, a data recovery operation RES is performed on the variable resistance unit based on the data recovery signal RES and the set signal SEB, so that after the data recovery operation RES, the output state of the corresponding variable resistance storage data output terminal is restored to the adapted latch circuit.

[0015] When the latch unit includes two latch circuits, the latch unit corresponding to the data input port is used to form a first-level latch, and the latch unit corresponding to the data output port is used to form a second-level latch, wherein:

[0016] The variable resistance resistor connected to the first stage latch forms the first stage variable resistance resistor, and the variable resistance resistor connected to the second stage latch forms the second stage variable resistance resistor;

[0017] When the output state of the data output terminal is stored in the first-stage variable resistance resistor, during the data recovery operation RES, the data stored in the first-stage variable resistance resistor is restored to the first-stage latch;

[0018] When the output state of the data output terminal is stored in the second-stage variable resistance resistor, during the data recovery operation RES, the data stored in the second-stage variable resistance resistor is recovered to the second-stage latch;

[0019] The lower electrode BE of the first-stage variable resistance resistor is adaptively connected to the latch circuit of the first-stage latch, and the lower electrode BE of the second-stage variable resistance resistor is adaptively connected to the latch circuit of the second-stage latch;

[0020] The connection state between the upper electrode TE of the first-stage variable resistance resistor and the programming voltage PHV is configured through the high-voltage switch S1;

[0021] The connection state between the upper electrode TE of the second-stage variable resistance resistor and the programming voltage PHV is configured through the high-voltage switch S2;

[0022] During the electrical forming operation, the programming voltage PHV is at a first programming voltage;

[0023] At the time of the data saving operation SET, the program voltage PHV is at a second program voltage, wherein a voltage value of the second program voltage is greater than a voltage value of the first program voltage.

[0024] Based on the shaping signal FOM, the data recovery signal RES, the data storage signal SET, the variable resistance reset signal RET and the output state of the data output terminal, a high-voltage switch first control signal K0 and a high-voltage switch second control signal K1 are generated in the timing signal circuit, wherein:

[0025] Based on the first control signal K0 of the high-voltage switch, when the high-voltage switch S1 is controlled to be turned on, the upper electrode TE of the first-stage variable resistance resistor is connected to the programming voltage PHV;

[0026] Based on the second control signal K1 of the high-voltage switch, when the high-voltage switch S2 is controlled to be turned on, the upper electrode TE of the second-stage variable resistance resistor is connected to the programming voltage PHV;

[0027] During the data storage operation SET, the first high-voltage switch control signal K0 and the second high-voltage switch control signal K1 are in opposite phases.

[0028] The high-voltage switch S1 includes a PMOS tube P0, a PMOS tube P1 and a PMOS tube P2, wherein:

[0029] The drain terminal of the PMOS tube P0, the drain terminal of the PMOS tube P1 and the drain terminal of the PMOS tube P2 are connected to each other to form a POWER_IN terminal;

[0030] The gate terminal of the PMOS tube P0 is connected to the source terminal of the PMOS tube P1, the drain terminal of the NMOS tube N5 and the gate terminal of the PMOS tube P2;

[0031] The source terminal of the PMOS tube P0 is connected to the drain terminal of the NMOS tube N4 and the gate terminal of the PMOS tube P1, and the source terminal of the NMOS tube N4 and the source terminal of the NMOS tube N5 are both grounded;

[0032] The gate terminal of the NMOS tube N4 is connected to the input terminal of the inverter INV6 and forms the control terminal of the high-voltage switch;

[0033] The output end of the inverter INV6 is connected to the gate end of the NMOS tube N5, and the source end of the PMOS tube P2 is used to form the POWER_OUT end;

[0034] The high-voltage switch S1 is connected to the programming voltage PHV through the POWER_IN terminal, and the high-voltage switch S1 is connected to the upper electrode TE of the variable resistance resistor through the POWER_OUT terminal.

[0035] The high-voltage switch first control signal K0 is loaded onto the control terminal of the high-voltage switch.

[0036] The latch circuit of the first-stage latch includes an NMOS transistor N0, a NAND gate NAND0, an NMOS transistor N1 and an inverter INV0, wherein:

[0037] The drain terminal of the NMOS tube N0 is connected to the data input port, the gate terminal of the NMOS tube N0 receives the clock control signal CK_A generated by the timing signal circuit, and the source terminal of the NMOS tube N0 is connected to an input terminal of the NOT gate NAND0, the lower electrode of the first-stage variable resistance resistor, and the drain terminal of the NMOS tube N1;

[0038] The output end of the NAND gate NAND0 is adaptively connected to the source end of the NMOS tube N1 and the latch circuit of the second-stage latch, and the gate end of the NMOS tube N1 receives the clock control signal CK_B generated by the timing signal circuit;

[0039] During the electrical forming operation and the data saving operation SET, the NMOS tube N0 is always in the off state based on the clock control signal CK_A, and the NMOS tube N1 is always in the on state based on the clock control signal CK_B;

[0040] When the first-stage variable resistance resistor is reset, the NMOS tube N0 is turned on once based on the clock control signal CK_A, and the NMOS tube N1 is in the off state only when the NMOS tube N0 is turned on;

[0041] When the DFF functional unit is in the DFF function and outputs a data of the data input port through the data output terminal, the NMOS tube N0 is configured to be turned on once based on the clock control signal CK_A, and the NMOS tube N1 is turned on only when the NMOS tube N0 is in the off state;

[0042] During the data recovery operation RES, the NMOS transistor N0 is configured to be always in the off state based on the clock control signal CK_A, and the NMOS transistor N1 is configured to be in the on state based on the clock control signal CK_B.

[0043] The latch circuit of the second-stage latch includes an NMOS tube N2, a NAND gate NAND1, an NMOS tube N3 and an inverter INV1, wherein:

[0044] The output end of the NAND gate NAND1 and the input end of the inverter INV1 are both connected to the data output end; the output end of the inverter INV1 is connected to the source end of the NMOS tube N3, and the drain end of the NMOS tube N3 is connected to the lower electrode of the second-stage variable resistance resistor, the source end of the NMOS tube N2, and an input end of the NAND gate NAND1;

[0045] The drain terminal of the NMOS tube N2 is connected to the output terminal of the NAND gate NAND0 in the first-stage latch and the input terminal of the inverter INV0;

[0046] The input end of the NAND gate NAND0 and the input end of the NAND gate NAND1 both receive the set signal SEB;

[0047] The gate end of the NMOS tube N2 receives the clock control signal CK_B generated by the timing signal circuit; the gate end of the NMOS tube N3 receives the clock control signal CK_D generated by the timing signal circuit, wherein

[0048] During the electrical forming operation and the data saving operation SET, the NMOS tube N2 is always in the off state based on the clock control signal CK_C, and the NMOS tube N1 is always in the on state based on the clock control signal CK_D;

[0049] When the second-stage variable resistance resistor is reset, the NMOS transistor N2 is turned off once based on the clock control signal CK_C, and the NMOS transistor N3 is turned on only when the NMOS transistor N2 is in the off state;

[0050] When the DFF functional unit is in the DFF function and outputs a data of the data input port through the data output terminal, the NMOS tube N2 is turned off once based on the clock control signal CK_C, and the NMOS tube N3 is turned on only when the NMOS tube N0 is in the off state;

[0051] During the data recovery operation RES, the NMOS transistor N2 is configured to be always in the off state based on the clock control signal CK_C, and the NMOS transistor N3 is configured to be in the on state based on the clock control signal CK_D.

[0052] The timing signal circuit includes a clock control signal generating circuit, wherein:

[0053] The clock control signal generating circuit includes an inverter INV2, an input end of the inverter INV2 receives a clock signal CK, an output end of the inverter INV2 is connected to an input end of an inverter INV3 and an input end of an OR gate OR1, another input end of the OR gate OR1 receives a data recovery signal RES, and outputs a clock control signal CK_B via an output end of the OR gate OR1;

[0054] The output end of the inverter INV3 is connected to one input end of the NOR gate NOR1, the other input end of the NOR gate NOR1 receives the shaped signal FOM, the output end of the NOR gate NOR1 is connected to the input end of the inverter INV4, and the clock control signal CK_C is generated via the output end of the NOR gate NOR1;

[0055] The output terminal of the inverter INV4 is connected to one input terminal of the OR gate OR2 . The other input terminal of the OR gate OR2 receives the data recovery signal RES, and generates the clock control signal CK_D via the output terminal of the OR gate OR2 .

[0056] The timing signal circuit includes a high voltage switch control signal generating circuit, wherein:

[0057] The high-voltage switch control signal generating circuit includes a high-voltage switch first control signal generating circuit and a high-voltage switch second control signal generating circuit;

[0058] When the first-stage variable resistor is used to store the 0 level of the data output terminal, the high-voltage switch first control signal generating circuit includes an inverter INV5, the input terminal of the inverter INV5 is connected to the data output terminal, the output terminal of the inverter INV5 is connected to an input terminal of an AND gate AND1, the other input terminal of the AND gate AND1 receives the data storage signal SET, and the output terminal of the AND gate AND1 is connected to an input terminal of an OR gate OR3;

[0059] The input end of the OR gate OR3 also receives the shaping signal FOM, the data recovery signal RES and the variable resistance reset signal RET, and the output end of the OR gate OR3 generates the high voltage switch first control signal K0;

[0060] The high-voltage switch second control signal generating circuit comprises an AND gate AND2, the input end of the AND gate AND2 is connected to the data output end and receives the data saving signal SET, and the output end of the AND gate AND2 is connected to an input end of the OR gate OR4;

[0061] The input end of the OR gate OR4 also receives the shaping signal FOM, the data recovery signal RES and the variable resistance reset signal RET, and the output end of the OR gate OR3 generates the high voltage switch second control signal K1.

[0062] The variable resistance resistor is a MIM structure, comprising:

[0063] A first metal electrode plate of a variable resistor, used to form an upper electrode TE of a variable resistance resistor;

[0064] The second metal electrode plate of the variable resistor is used to form the lower electrode BE of the variable resistance resistor;

[0065] The switch dielectric layer is located between the first metal electrode plate of the variable resistor and the second metal electrode plate of the variable resistor, and includes HfO 2 layer and the HfO 2 Ti layer on the layer, where HfO 2 The Ti layer is located on the second metal electrode plate of the variable resistor, and the Ti layer is in contact with the first metal electrode plate of the variable resistor;

[0066] The variable resistance resistor is electrically formed before enabling the variable resistance resistor.

[0067] When the non-volatile DFF is applied in FPGA, all non-volatile DFFs receive the same clock signal CK, set signal SEB, shaping signal FOM, data preservation signal SET, data recovery signal RES and variable resistance reset signal RET;

[0068] In the FPGA, a data saving operation SET is performed on the non-volatile DFFs in the region according to the region mode, and the number of non-volatile DFFs in each region does not exceed 128.

[0069] The invention has the advantages that the non-volatile DFF is realized based on the variable resistance unit. Based on the characteristics of the variable resistance unit, the non-volatile DFF is compatible with the most advanced CMOS process, thereby improving the system scale and speed of the FPGA.

[0070] The variable resistance resistor is non-volatile storage, and the information is not lost after power failure. The data can be restored to the DFF after restart. Based on the characteristics of non-volatile DFF, all variable resistance resistors in the non-volatile DFF in the FPGA can be electrically formed at one time; the variable resistance resistor in a non-volatile DFF can be reset at least twice;

[0071] The data saving operation SET is performed on the non-volatile DFF in the FPGA in a regional mode. The number of non-volatile DFFs in each region does not exceed 128. Each region has an independent charge pump circuit to enable the variable resistance resistors in each region to perform data saving operation SET at the same time to ensure that the data can be saved in the variable resistance resistors before the power supply voltage drops below the operating voltage range, thereby reducing the writing time; after power-on, the data can be restored from the variable resistance resistors to achieve non-volatility. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Figure 1 FIG. 4 is a schematic diagram of an embodiment of a nonvolatile DFF of the present invention.

[0073] Figure 2 The figure is a circuit diagram of an embodiment of the DFF functional unit body of the present invention.

[0074] Figure 3 The following is a circuit schematic diagram of an embodiment of a clock control signal generating circuit of the present invention.

[0075] Figure 4 This is a circuit schematic diagram of an embodiment of a first control signal generating circuit for a high-voltage switch of the present invention.

[0076] Figure 5 The schematic diagram is a circuit diagram of an embodiment of a second control signal generating circuit for a high voltage switch of the present invention.

[0077] Figure 6 A schematic diagram of an embodiment of a variable resistance resistor of the present invention.

[0078] Figure 7 It is a schematic diagram of the physical properties of the variable resistance resistor of the present invention.

[0079] Figure 8 This is a circuit diagram of an embodiment of a high voltage switch S1 of the present invention.

[0080] Fig. 9 A timing diagram of an embodiment of configuring a DFF functional unit body of the present invention.

[0081] Fig.10 The figure is a schematic diagram of an embodiment of the non-volatile DFF of the present invention applied to FPGA.

[0082] Fig.11 The figure is a circuit diagram of an embodiment of a charge pump of the present invention.

[0083] Fig.12 The figure is a clock timing diagram of an embodiment of the charge pump of the present invention. DETAILED DESCRIPTION

[0084] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0085] In order to realize a non-volatile DFF based on a variable resistance resistor, a non-volatile DFF is used for an FPGA based on a variable resistance resistor. In one embodiment of the present invention, the non-volatile DFF includes:

[0086] The DFF functional unit body includes a latch unit and a variable resistance unit adapted to be connected to the latch unit, wherein the latch unit is correspondingly connected to the data input port and the data output end of the non-volatile DFF, wherein:

[0087] The latch unit includes at least two latch circuits that are adaptively connected, the variable resistance resistor unit includes at least two variable resistance resistors, and one latch circuit is adaptively connected to at least one variable resistance resistor;

[0088] A timing signal circuit receives a work instruction signal and configures an operation state of the DFF functional unit body based on the received work instruction signal, wherein the received work instruction signal includes a clock signal CK, a set signal SEB, a forming signal FOM, a data saving signal SET, a data recovery signal RES, and a variable resistance reset signal RET, and the configured operation state of the DFF functional unit body includes an electrical forming operation, a reset operation, a DFF function, a data saving operation SET, and / or a data recovery operation RES;

[0089] Based on the forming signal FOM, the programming voltage PHV and the setting signal SEB, an electrical forming operation is performed on all the variable resistance resistors in the DFF functional unit body, so that after the electrical forming operation, all the variable resistance resistors are configured to be in a low resistance state LRS state;

[0090] Based on the data DATA loaded from the data input port, the clock signal CK, the variable resistance reset signal RET and the set signal SEB, the variable resistance in the variable resistance unit is reset in sequence, so that after the reset operation, the corresponding variable resistance in the variable resistance unit is restored to the high resistance state HRS;

[0091] When the DFF functional unit is in the DFF function, based on the clock signal CK, the data DATA loaded by the data input port is collected and output through the data output terminal, and when the set signal SEB is valid, the data output terminal is configured to be in the set state;

[0092] Based on the data storage signal SET, the set signal SEB and the programming voltage PHV, a data storage operation SET is performed on the variable resistance unit, so that after the data storage operation SET, the output state of the data output terminal is stored by a variable resistance resistor;

[0093] After the output state of the data output terminal is stored by the variable resistance unit, a data recovery operation RES is performed on the variable resistance unit based on the data recovery signal RES and the set signal SEB, so that after the data recovery operation RES, the output state of the corresponding variable resistance storage data output terminal is restored to the adapted latch circuit.

[0094] Figure 1 An embodiment of the non-volatile DFF of the present invention is shown in FIG. Figure 1 Re_DFF in the figure is a non-volatile DFF. In one embodiment of the present invention, the non-volatile DFF includes a DFF functional unit body and a timing signal circuit, wherein the DFF functional unit body, as a functional unit of the non-volatile DFF, can also realize the basic functions of the non-volatile DFF, and the functions of the DFF functional unit can be configured by the timing signal circuit in the received work instruction signal. The DFF functional unit body at least includes a latch unit and a variable resistance unit. The latch unit has a latching capability, and the variable resistance unit can realize data storage. Thus, the non-volatile DFF can be formed by utilizing the storage capability of the variable resistance unit.

[0095] The latch unit generally includes at least two adaptively connected latch circuits, and the variable resistance resistor unit also includes at least two variable resistance resistors, wherein one latch circuit is adaptively connected to at least one variable resistance resistor; generally, the latch circuit and the variable resistance resistor are in one-to-one correspondence and adaptively connected, and the specific adaptive connection method will be described in detail below.

[0096] The working instruction signals that the timing signal circuit can receive may include a clock signal CK, a set signal SEB, a shaping signal FOM, a data storage signal SET, a data recovery signal RES and a variable resistance resistor reset signal RET. Therefore, in addition to the conventional data input port, data output port and clock port, the non-volatile DFF also has a set signal terminal, a shaping signal terminal, a data storage signal terminal, a data recovery signal terminal and a variable resistance resistor reset signal terminal.

[0097] Figure 1In the figure, DATA is the corresponding data input port, Q is the corresponding data output port, CK is the corresponding clock port, SEB is the corresponding set signal port, FOM is the corresponding shaping signal port, SET is the corresponding data storage signal port, RES is the corresponding data recovery signal port, and RET is the corresponding variable resistance reset signal port. When working, the clock signal CK is received through the clock port, the set signal SEB is received through the set signal port, the shaping signal FOM is received through the shaping signal port, the data storage signal SET is received through the data storage signal port, the data recovery signal RES is received through the data recovery signal port, and the variable resistance reset signal RET is received through the variable resistance reset signal port.

[0098] In specific implementation, the data DATA loaded by the data input port is a digital signal of "0" or "1", and the output state output by the data output port is a digital signal of "0" or "1". The operation state of the DFF functional unit body is generally configured to include an electrical forming operation, a reset operation, a DFF function, a data saving operation SET and / or a data recovery operation RES, wherein the electrical forming operation is mainly an operation for the variable resistance resistor unit, so that the variable resistance power supply in the variable resistance resistor unit is switched from a high resistance HRS state to a low resistance LRS state. The electrical forming operation is generally performed when the non-volatile DFF works for the first time. During the life cycle of the non-volatile DFF, the electrical forming operation is generally performed only once. When configuring to perform the electrical forming operation, at least the forming signal FOM needs to be configured to a valid level state, and the voltage of the programming voltage PHV needs to meet the voltage of the electrical forming operation of the variable resistance resistor. At this time, the set signal SEB is in a valid level state.

[0099] After the electrical formation operation, a Reset operation is required. When the configuration enters the Reset operation, the variable resistance reset signal RET needs to be in a valid level state; of course, at this time, in order to be able to perform a Reset operation on each variable resistance, it is also necessary to configure the data DATA, the clock signal CK and the set signal SEB, wherein the set signal SEB is in a non-valid level state, and the clock signal CK mainly provides a pulse clock. As mentioned above, the data DATA mainly provides a digital signal of 0 or 1. When entering the Reset operation, the specific conditions of the set signal SEB, the configuration data DATA, the clock signal CK, etc. can be referred to the following description.

[0100] After the reset operation, the variable resistance resistor can be restored to the high resistance state HRS. Generally, after the reset operation, all variable resistance resistors need to be switched from the low resistance state LRS after the electrical forming operation to the high resistance HRS state. Generally, during the life cycle of the non-volatile DFF, only one reset operation needs to be performed, and it is performed immediately after the electrical forming operation.

[0101] When the DFF functional unit is configured to be in the DFF function, the non-volatile DFF can realize the common functions of the existing DFF. At this time, the forming signal FOM, the data saving signal SET, the data recovery signal RES and the variable resistance reset signal RET are all in the ineffective level state, and the effective signal of the loading timing signal circuit only includes the clock signal CK and the data DATA; when working, under the action of the clock signal CK, the data DATA can be output from the data output terminal. Similar to the existing DFF, when the set signal SEB is valid, the output of the data output terminal will be directly configured to the set state, that is, the output of the data output terminal has nothing to do with the data DATA, and the set state is generally the "1" state.

[0102] Before the non-volatile DFF is powered off or the voltage drops to a preset threshold, a data saving operation SET needs to be configured. At this time, at least the data saving signal SET is in a valid level state, and a programming voltage PHV is applied to the end of the variable resistance resistor. In one embodiment of the present invention, the set signal SEB also needs to be configured to be in a valid level state. After the data saving operation SET is performed, the output state of the data output terminal is stored using a variable resistance resistor. As can be seen from the above description, the output state of the data output terminal is "0" or "1", so at least one variable resistance resistor needs to be used to realize the storage of "0" or "1".

[0103] Only after the data saving operation SET is performed, the non-volatile DFF can be configured to enter the data recovery operation RES. At this time, at least the data recovery signal RES needs to be configured to be in a valid level state, and the set signal SEB can be in a non-valid level state. When the data saving operation SET is performed, the output state of the corresponding variable resistance resistor storing data output terminal is restored to the latch circuit to which it is adapted.

[0104] It can be seen from the above description that for the non-volatile DFF, the data saving operation SET and the data recovery operation RES can be implemented based on the variable resistance resistor, that is, the non-volatile DFF is implemented based on the variable resistance resistor. From the characteristics of the variable resistance resistor, it can be seen that the non-volatile DFF of the present invention is compatible with the existing CMOS process and can reduce the writing time.

[0105] In one embodiment of the present invention, when the latch unit includes two latch circuits, a latch unit corresponding to a data input port is used to form a first-level latch, and a latch unit corresponding to a data output port is used to form a second-level latch, wherein:

[0106] The variable resistance resistor connected to the first stage latch forms the first stage variable resistance resistor, and the variable resistance resistor connected to the second stage latch forms the second stage variable resistance resistor;

[0107] When the output state of the data output terminal is stored in the first-stage variable resistance resistor, during the data recovery operation RES, the data stored in the first-stage variable resistance resistor is restored to the first-stage latch;

[0108] When the output state of the data output terminal is stored in the second-stage variable resistance resistor, during the data recovery operation RES, the data stored in the second-stage variable resistance resistor is recovered to the second-stage latch;

[0109] The lower electrode BE of the first-stage variable resistance resistor is adaptively connected to the latch circuit of the first-stage latch, and the lower electrode BE of the second-stage variable resistance resistor is adaptively connected to the latch circuit of the second-stage latch;

[0110] The connection state between the upper electrode TE of the first-stage variable resistance resistor and the programming voltage PHV is configured through the high-voltage switch S1;

[0111] The connection state between the upper electrode TE of the second-stage variable resistance resistor and the programming voltage PHV is configured through the high-voltage switch S2;

[0112] During the electrical forming operation, the programming voltage PHV is at a first programming voltage;

[0113] At the time of the data saving operation SET, the program voltage PHV is at a second program voltage, wherein a voltage value of the second program voltage is greater than a voltage value of the first program voltage.

[0114] To adapt to the characteristics of digital signals, the latch unit may include two latch circuits, which are distributed corresponding to the data input port and the data output port. The latch circuit corresponding to the data input port can be configured as a first-level latch, and the latch circuit corresponding to the data output port can be configured as a second-level latch.

[0115] In order to simplify the circuit form, the variable resistance resistor unit includes two variable resistance resistors. As can be seen from the above description, the two variable resistance resistors are respectively connected to the first-stage latch and the second-stage latch. Figure 2 FIG. 2 shows an embodiment in which two variable resistance resistors are respectively connected to the first-stage latch and the second-stage latch. Figure 2In the figure, Re0 is the variable resistance resistor of the first stage, and Re1 is the variable resistance resistor of the second stage. At this time, the latch circuit adapted to be connected with the variable resistance resistor Re0 is the first stage latch, and the latch circuit adapted to be connected with the variable resistance resistor Re1 is the second stage latch.

[0116] Specifically, the variable resistance resistor Re0 and the variable resistance resistor Re0 may generally adopt the same structural form, and of course, they may also adopt different forms according to needs. Figure 6 An embodiment of a variable resistance resistor Re0 or a variable resistance resistor Re1 is shown in FIG. Figure 6 and Figure 7 The case of the variable resistance resistor shown will be described.

[0117] In one embodiment of the present invention, the variable resistance resistor is a MIM structure, comprising:

[0118] A first metal electrode plate of a variable resistor, used to form an upper electrode TE of a variable resistance resistor;

[0119] The second metal electrode plate of the variable resistor is used to form the lower electrode BE of the variable resistance resistor;

[0120] The switch dielectric layer is located between the first metal electrode plate of the variable resistor and the second metal electrode plate of the variable resistor, and includes HfO 2 layer and the HfO 2 Ti layer on the layer, where HfO 2 The Ti layer is located on the second metal electrode plate of the variable resistor, and the Ti layer is in contact with the first metal electrode plate of the variable resistor;

[0121] The variable resistance resistor is electrically formed before enabling the variable resistance resistor.

[0122] Specifically, the first metal electrode plate of the variable resistor and the second metal electrode plate of the variable resistor may be made of the same material. Figure 6 An embodiment in which the first metal electrode plate of the variable resistor and the second metal electrode plate of the variable resistor are made of the same material is shown. In the figure, the first metal electrode plate of the variable resistor and the second metal electrode plate of the variable resistor are both made of TiN. Of course, other metal electrode plate materials can also be used. The specific material type can be selected according to needs to be compatible with the CMOS process and can form a variable resistance resistor.

[0123] The switch dielectric layer can be used as an insulating dielectric layer. Figure 6 An embodiment of the switch dielectric layer is shown in FIG. 2 The thickness of the Ti layer can be 10 nm, and the thickness of the Ti layer can also be 10 nm. Figure 6 The variable resistance resistor formed therein is in a stacked shape.

[0124] As can be seen from the above description, before the variable resistance resistor works, it is necessary to perform electrical formation on the variable resistance resistor, wherein during this process, the induced high voltage can make the variable resistance resistor switch from a high resistance state (HRS, or original state) to a low resistance state (LRS); the induced high voltage specifically refers to the voltage difference between the upper electrode TE and the lower electrode BE of the variable resistance resistor being a high voltage state. After electrical formation, the variable resistance resistor can switch between the high resistance state HRS and the low resistance state LRS by applying specific voltages (i.e., VSET and VRESET) to the electrodes of the variable resistance resistor.

[0125] Depend on Figure 7 It can be seen from the linear curve shown that in the figure, the horizontal axis is the voltage of the upper electrode TE, and the vertical axis is the current flowing through the variable resistance resistor. At this time, the lower electrode BE is grounded. It can be seen from the figure that when switching to the low resistance state LRS, the required VSET value is 0.57V (that is, the voltage difference between the upper electrode TE and the lower electrode BE is 0.57V), and when switching back to the high resistance state HRS, the required VRESET value is -0.7V (that is, the voltage difference between the upper electrode TE and the lower electrode BE is -0.7V).

[0126] From the above description, it can be seen that during the electrical formation operation and the data storage operation SET, it is necessary to apply the programming voltage PHV to the first-level variable resistance resistor and the second-level variable resistance resistor. In other states, it is not necessary to apply the programming voltage PHV. Therefore, in other states, the programming voltage PHV is generally 0V.

[0127] In order to realize the loading control of the programming voltage PHV, in one embodiment of the present invention, the connection state between the upper electrode TE of the first-stage variable resistance resistor and the programming voltage PHV is configured through the high-voltage switch S1, that is, the two ends of the high-voltage switch S1 are respectively connected to the upper electrode TE of the first-stage variable resistance resistor and the programming voltage PHV; at this time, when the high-voltage switch S1 is closed, the programming voltage PHV can be applied to the upper electrode TE of the first-stage variable resistance resistor; and when the high-voltage switch S1 is disconnected, the programming voltage PHV will not be applied to the upper electrode TE of the first-stage variable resistance resistor. Similarly, the connection state between the upper electrode TE of the second-stage variable resistance resistor and the programming voltage PHV is configured through the high-voltage switch S2. For the specific connection state configured by the high-voltage switch S2, reference can be made to the description of the high-voltage switch S1 here, and no further description will be given here.

[0128] In a specific implementation, during the electrical forming operation, the programming voltage PHV is at a first programming voltage; during the data storage operation SET, the programming voltage PHV is at a second programming voltage, wherein the voltage value of the second programming voltage is greater than the voltage value of the first programming voltage; Fig. 9An embodiment in which the first programming voltage is 2.5V and the second programming voltage is 5V is shown. Of course, the first programming voltage and the second programming voltage can also adopt other voltage states, which can be selected according to needs.

[0129] The high-voltage switch S1 can be in the same form as the high-voltage switch S2, or of course, in different forms, depending on the connection state of the high-voltage switch S1 and the high-voltage switch S2. The following takes the high-voltage switch S1 as an example to illustrate the circuit forms that can be used by the high-voltage switch S1 and the high-voltage switch S2.

[0130] In one embodiment of the present invention, the high voltage switch S1 includes a PMOS transistor P0, a PMOS transistor P1 and a PMOS transistor P2, wherein:

[0131] The drain terminal of the PMOS tube P0, the drain terminal of the PMOS tube P1 and the drain terminal of the PMOS tube P2 are connected to each other to form a POWER_IN terminal;

[0132] The gate terminal of the PMOS tube P0 is connected to the source terminal of the PMOS tube P1, the drain terminal of the NMOS tube N5 and the gate terminal of the PMOS tube P2;

[0133] The source terminal of the PMOS tube P0 is connected to the drain terminal of the NMOS tube N4 and the gate terminal of the PMOS tube P1, and the source terminal of the NMOS tube N4 and the source terminal of the NMOS tube N5 are both grounded;

[0134] The gate terminal of the NMOS tube N4 is connected to the input terminal of the inverter INV6 and forms the control terminal of the high-voltage switch;

[0135] The output end of the inverter INV6 is connected to the gate end of the NMOS tube N5, and the source end of the PMOS tube P2 is used to form the POWER_OUT end;

[0136] The high-voltage switch S1 is connected to the programming voltage PHV through the POWER_IN terminal, and the high-voltage switch S1 is connected to the upper electrode TE of the variable resistance resistor through the POWER_OUT terminal.

[0137] The high-voltage switch first control signal K0 is loaded onto the control terminal of the high-voltage switch.

[0138] Figure 8An embodiment of the high-voltage switch S1 is shown in FIG. 1 , in which K is the control terminal of the high-voltage switch. Generally, when the first control signal K0 of the high-voltage switch is at a high level, the high-voltage switch S1 is turned on; when the first control signal K0 of the high-voltage switch is at a low level, the high-voltage switch S1 is turned off; in specific implementation, the low level of the first control signal K0 of the high-voltage switch is generally 0 voltage; the high level of the first control signal K0 of the high-voltage switch is generally 1.5V voltage, which can be specifically referred to Fig. 9 An embodiment is shown in FIG.

[0139] When the high-voltage switch S2 adopts the circuit form of the high-voltage switch S1, the high-voltage switch S2 is controlled by the second control signal K1 of the high-voltage switch. The second control signal K1 of the high-voltage switch can be referred to. Fig. 9 The above description about the first control signal K0 of the high-voltage switch will not be repeated here.

[0140] In one embodiment of the present invention, based on the shaping signal FOM, the data recovery signal RES, the data storage signal SET, the variable resistance reset signal RET and the output state of the data output terminal, a high-voltage switch first control signal K0 and a high-voltage switch second control signal K1 are generated in the timing signal circuit, wherein:

[0141] Based on the first control signal K0 of the high-voltage switch, when the high-voltage switch S1 is controlled to be turned on, the upper electrode TE of the first-stage variable resistance resistor is connected to the programming voltage PHV;

[0142] Based on the second control signal K1 of the high-voltage switch, when the high-voltage switch S2 is controlled to be turned on, the upper electrode TE of the second-stage variable resistance resistor is connected to the programming voltage PHV;

[0143] During the data storage operation SET, the first high-voltage switch control signal K0 and the second high-voltage switch control signal K1 are in opposite phases.

[0144] It can be seen from the above description that the specific switching states of the high-voltage switches S1 and S2 are related to the operating state of the DFF functional unit. Therefore, in order to meet the operating state of the DFF functional unit, the high-voltage switch first control signal K0 and the high-voltage switch second control signal K1 can be generated based on the corresponding work instruction signal configuration. In specific implementation, during the data saving operation SET, the high-voltage switch first control signal K0 and the high-voltage switch second control signal K1 are inverted to each other to lock the level state of the data output end in the variable resistance resistor Re0 or the variable resistance resistor Re1; specifically, when the high-voltage switch first control signal K0 is high, the high-voltage switch second control signal K1 is low; and when the high-voltage switch first control signal K0 is low, the high-voltage switch second control signal K1 is high.

[0145] In order to obtain the high-voltage switch first control signal K0 and the high-voltage switch second control signal K1 in the timing signal circuit, in one embodiment of the present invention, the timing signal circuit includes a high-voltage switch control signal generating circuit, wherein:

[0146] The high-voltage switch control signal generating circuit includes a high-voltage switch first control signal generating circuit and a high-voltage switch second control signal generating circuit;

[0147] When the first-stage variable resistor is used to store the 0 level of the data output terminal, the high-voltage switch first control signal generating circuit includes an inverter INV5, the input terminal of the inverter INV5 is connected to the data output terminal, the output terminal of the inverter INV5 is connected to an input terminal of an AND gate AND1, the other input terminal of the AND gate AND1 receives the data storage signal SET, and the output terminal of the AND gate AND1 is connected to an input terminal of an OR gate OR3;

[0148] The input end of the OR gate OR3 also receives the shaping signal FOM, the data recovery signal RES and the variable resistance reset signal RET, and the output end of the OR gate OR3 generates the high voltage switch first control signal K0;

[0149] The high-voltage switch second control signal generating circuit comprises an AND gate AND2, the input end of the AND gate AND2 is connected to the data output end and receives the data saving signal SET, and the output end of the AND gate AND2 is connected to an input end of the OR gate OR4;

[0150] The input end of the OR gate OR4 also receives the shaping signal FOM, the data recovery signal RES and the variable resistance reset signal RET, and the output end of the OR gate OR3 generates the high voltage switch second control signal K1.

[0151] Figure 4 An embodiment of a high voltage switch first control signal generating circuit is shown. Figure 5 The second control signal generating circuit of the high voltage switch is shown in FIG. Figure 4 and Figure 5 In the example, the setting signal SEB is low level effective, wherein, except the setting signal SEB is low level effective, the shaping signal FOM, the data saving signal SET, the data recovery signal RES and the variable resistance reset signal RET are all high level effective. When the working instruction signal is in other level effective states, the description here can be referred to, and the operating state of the DFF functional unit body that can meet the timing signal circuit configuration shall prevail.

[0152] In one embodiment of the present invention, the latch circuit of the first-stage latch includes an NMOS transistor N0, a NAND gate NAND0, an NMOS transistor N1 and an inverter INV0, wherein:

[0153] The drain terminal of the NMOS tube N0 is connected to the data input port, the gate terminal of the NMOS tube N0 receives the clock control signal CK_A generated by the timing signal circuit, and the source terminal of the NMOS tube N0 is connected to an input terminal of the NOT gate NAND0, the lower electrode of the first-stage variable resistance resistor, and the drain terminal of the NMOS tube N1;

[0154] The output end of the NAND gate NAND0 is adaptively connected to the source end of the NMOS tube N1 and the latch circuit of the second-stage latch, and the gate end of the NMOS tube N1 receives the clock control signal CK_B generated by the timing signal circuit;

[0155] During the electrical forming operation and the data saving operation SET, the NMOS tube N0 is always in the off state based on the clock control signal CK_A, and the NMOS tube N1 is always in the on state based on the clock control signal CK_B;

[0156] When the first-stage variable resistance resistor is reset, the NMOS tube N0 is turned on once based on the clock control signal CK_A, and the NMOS tube N1 is in the off state only when the NMOS tube N0 is turned on;

[0157] When the DFF functional unit is in the DFF function and outputs a data of the data input port through the data output terminal, the NMOS tube N0 is configured to be turned on once based on the clock control signal CK_A, and the NMOS tube N1 is turned on only when the NMOS tube N0 is in the off state;

[0158] During the data recovery operation RES, the NMOS transistor N0 is configured to be always in the off state based on the clock control signal CK_A, and the NMOS transistor N1 is configured to be in the on state based on the clock control signal CK_B.

[0159] Furthermore, the latch circuit of the second-stage latch includes an NMOS transistor N2, a NAND gate NAND1, an NMOS transistor N3 and an inverter INV1, wherein:

[0160] The output end of the NAND gate NAND1 and the input end of the inverter INV1 are both connected to the data output end; the output end of the inverter INV1 is connected to the source end of the NMOS tube N3, and the drain end of the NMOS tube N3 is connected to the lower electrode of the second-stage variable resistance resistor, the source end of the NMOS tube N2, and an input end of the NAND gate NAND1;

[0161] The drain terminal of the NMOS tube N2 is connected to the output terminal of the NAND gate NAND0 in the first-stage latch and the input terminal of the inverter INV0;

[0162] The input end of the NAND gate NAND0 and the input end of the NAND gate NAND1 both receive the set signal SEB;

[0163] The gate end of the NMOS tube N2 receives the clock control signal CK_B generated by the timing signal circuit; the gate end of the NMOS tube N3 receives the clock control signal CK_D generated by the timing signal circuit, wherein

[0164] During the electrical forming operation and the data saving operation SET, the NMOS tube N2 is always in the off state based on the clock control signal CK_C, and the NMOS tube N1 is always in the on state based on the clock control signal CK_D;

[0165] When the second-stage variable resistance resistor is reset, the NMOS transistor N2 is turned off once based on the clock control signal CK_C, and the NMOS transistor N3 is turned on only when the NMOS transistor N2 is in the off state;

[0166] When the DFF functional unit is in the DFF function and outputs a data of the data input port through the data output terminal, the NMOS tube N2 is turned off once based on the clock control signal CK_C, and the NMOS tube N3 is turned on only when the NMOS tube N0 is in the off state;

[0167] During the data recovery operation RES, the NMOS transistor N2 is configured to be always in the off state based on the clock control signal CK_C, and the NMOS transistor N3 is configured to be in the on state based on the clock control signal CK_D.

[0168] Figure 2 The embodiment of the latch unit including two-stage latch circuits is shown in FIG. Figure 2 FIG. 4 also shows an embodiment in which only two variable resistance resistors are provided, specifically, a variable resistance resistor Re0 and a variable resistance resistor Re1. Figure 2 As can be seen from the above description, for the first-stage latch circuit, the conduction state of the NMOS tube N0 can be configured based on the clock control signal CK_A, and the conduction state of the NMOS tube N1 can be configured based on the clock control signal CK_B. The conduction state specifically refers to whether the NMOS tube is in the on state or the off state.

[0169] Similarly, for the latch circuit of the second stage, the conduction state of the NMOS transistor N2 can be configured based on the clock control signal CK_C, and the conduction state of the NMOS transistor N3 can be configured based on the clock control signal CK_D.

[0170] Figure 2In the embodiment, the source terminal of the NMOS tube N0, an input terminal of the NAND gate NAND0, the drain terminal of the NMOS tube N1 and the lower electrode BE of the variable resistance resistor Re0 are connected to form a node B, and the upper electrode TE of the variable resistance resistor Re0 is connected to the high voltage switch S1 to form a node A. The upper electrode TE of the variable resistance resistor Re1 is connected to the high voltage switch S2 to form a node C, and the source terminal of the NMOS tube N2, an input terminal of the NAND gate NAND1, the drain terminal of the NMOS tube N3 and the lower electrode BE of the variable resistance resistor Re1 are connected to form a node D.

[0171] In a specific implementation, the clock control signal CK_A, the clock control signal CK_B, the clock control signal CK_C and the clock control signal CK_D may be generated by a timing signal circuit; Figure 3 A circuit embodiment of a timing signal circuit generation is shown in FIG. 1 . Specifically, the timing signal circuit includes a clock control signal generation circuit, wherein:

[0172] The clock control signal generating circuit includes an inverter INV2, an input end of the inverter INV2 receives a clock signal CK, an output end of the inverter INV2 is connected to an input end of an inverter INV3 and an input end of an OR gate OR1, another input end of the OR gate OR1 receives a data recovery signal RES, and outputs a clock control signal CK_B via an output end of the OR gate OR1;

[0173] The output end of the inverter INV3 is connected to one input end of the NOR gate NOR1, the other input end of the NOR gate NOR1 receives the shaped signal FOM, the output end of the NOR gate NOR1 is connected to the input end of the inverter INV4, and the clock control signal CK_C is generated via the output end of the NOR gate NOR1;

[0174] The output terminal of the inverter INV4 is connected to one input terminal of the OR gate OR2 . The other input terminal of the OR gate OR2 receives the data recovery signal RES, and generates the clock control signal CK_D via the output terminal of the OR gate OR2 .

[0175] Figure 3 The clock control signal generating circuit shown in the figure is specifically based on the shaping signal FOM and the data recovery signal RES being in the valid level state at a high level. When the valid level state is in other situations, the form of the clock control signal generating circuit can be adjusted accordingly to generate the required clock control signal CK_A, clock control signal CK_B, clock control signal CK_C and clock control signal CK_D.

[0176] Combine the following Fig. 9 The working timing of the nonvolatile DFF of the present invention is described with examples. Fig. 9In the figure, it is shown that the nonvolatile DFF is subjected to an electrical forming operation, a reset operation, a DFF function, a data saving operation SET, a circuit power down (POWER DOWN), a data recovery operation RES, and a DFF re-operation in sequence.

[0177] The electroforming operation is Fig. 9 During the electrical forming operation, the specific configuration conditions are as follows: the forming signal FOM is in a high level state, the data DATA at the data input port is maintained at a 0 level, the set signal SEB is maintained at a valid level state of 0V, the clock signal CK is at a 0 level, and at the same time, the data save signal SET, the data recovery signal RES and the variable resistance reset signal RET are all maintained at a 0 level, and the programming voltage PHV is 2.5V. Fig. 9 The dotted line in the figure corresponds to the initial voltage state before the formation of electricity.

[0178] Based on the above configuration conditions and the above description, it can be obtained that: the clock control signal CK_A is always in a low level state of 0V, the clock control signal CK_B is always in a high level state of 1.5V, the clock control signal CK_C is always in a low level state of 0V, the clock control signal CK_D is always in a high level state of 1.5V, and the high-voltage switch first control signal K0 and the high-voltage switch second control signal K1 are both in a high level state of 1.5V; at this time, there is:

[0179] The high-voltage switch S1 and the high-voltage switch S2 are both turned on, and the programming voltage PHV is loaded onto the upper electrode TE of the variable resistance resistor Re0 and the upper electrode TE of the variable resistance resistor Re1. The corresponding voltages of the nodes A and C are both 2.5V, which is consistent with the programming voltage PHV. The NMOS tube N1 is turned on by the clock control signal CK_B. In the initial state, the node B is at a low level of 0V and the set signal SEB is at a low level of 0V. The output of the NAND gate NAND1 is at a high level. After the output of the NAND gate NAND1 passes through the inverter IINV0 and the NMOS tube N1, the node B remains at a low level of 0V.

[0180] Based on the clock control signal CK_D, the NMOS transistor N3 is turned on. Since the data output terminal is initially at a high level, the node D can also be kept at a low level of 0V after passing through the inverter INV1 and the NMOS transistor N3. At this time, for the variable resistance resistor Re0 and the variable resistance resistor Re1, the voltage difference between the upper electrode TE and the lower electrode BE is 2.5V. From the above description, it can be known that the variable resistance resistor Re0 and the variable resistance resistor Re1 can be electrically formed at the same time.

[0181] After the electrical forming operation, the forming signal FOM changes from a high level state to a low level of 0V; after the electrical forming operation, a reset operation is performed, that is, Fig. 9 The reset process (RESET) in Fig. 9 FIG. 2 shows an embodiment of resetting the variable resistance resistor Re0 first and then resetting the variable resistance resistor Re1 . Fig. 9 In the process, when resetting the variable resistance resistor Re0, it also includes a setup process and a maintenance process, wherein the data DATA and the set signal SEB maintain a high level of 1.5V from the beginning of the setup process to the end of resetting the variable resistance resistor Re0; in addition, the variable resistance reset signal RET maintains a high level of 1.5V during the entire Reset reset operation.

[0182] During the setup time, it can be seen from the above description that the clock control signal CK_A and the clock control signal CK_D are both in the low level state of 0V, the clock control signal CK_B and the clock control signal CK_C are both in the high level state of 1.5V, the high voltage switch first control signal K0 and the high voltage switch second control signal K1 are both in the low level state of 0V, and the programming voltage PHV is 0V. Since the high voltage switch S1 and the high voltage switch S2 are both disconnected, the nodes A and C are kept at 2.5V during the setup time.

[0183] When the clock control signal CK_B and the clock control signal CK_C are both at a high level of 1.5V, the NMOS tube N2 and the NMOS tube N1 are turned on. Based on the voltage of the node D, through the inverter INV0 and the NMOS tube N1, at the end of the setup time, the node B changes from a low level of 0V to a high level of 1.5V, while the node D remains at a low level of 0V.

[0184] After the setup time is over, during the hold time, the clock signal CK will have a rising edge pulse. At this time, the clock control signal CK_A will change from a low level of 0V to a high level of 1.5V, and will remain at 1.5V during the hold time; the clock control signal CK_B will change from a high level of 1.5V to a low level of 0V, the clock control signal CK_C will change from a high level of 1.5V to a low level of 0V, and the clock control signal CK_D will change from a low level of 0V to a high level of 1.5V; the high-voltage switch first control signal K0 and the high-voltage switch second control signal K1 are both low levels of 0V State, at this time, NMOS tube N0 and NMOS tube N3 are turned on, node A is still 2.5V, when NMOS tube N0 is turned on, since the data DATA is at a level of 1.5V, node B changes from 0V to 1.5V; when node D is 0V before, the output is high level through the NAND gate NAND1, and the data output end remains at 1.5V, and the node D is kept at a low level through the inverter INV1 and the NMOS tube N3; since node D is 0V, and since the variable resistance resistor Re1 is in the low resistance state LRS state, the node C changes from 2.5V to 0V.

[0185] After the holding time, the variable resistance Re0 is reset. At this time, the clock signal CK becomes 0V, the clock control signal CK_A changes from 1.5V to 0V, the clock control signal CK_B changes from 0V to 1.5V, the clock control signal CK_C changes from 0V to 1.5V, and the clock control signal CK_D changes from 1.5V to 0V. Then, the NMOS tubes N0 and NMOS tubes N3 change from on to off, and the NMOS tubes N1 and NMOS tubes N2 change from off to on. At the same time, the first control signal K0 of the high-voltage switch and the second control signal K1 of the high-voltage switch are both 1.5V, then the high-voltage switch S1 and the high-voltage switch S2 are both turned on, and since the programming voltage PHV is 0V, the voltages of node A and node C are changed to 0V, and since node B is at a high level during the holding time, node B can be maintained at a 1.5V level through the NAND gate NAND0 and the inverter INV0 and the NMOS tube N1, the NMOS tube N2 is turned on, and the output of the NAND gate NAND0 is 0V, then node D is maintained at a low level, and the data output end is maintained at a voltage of 1.5V.

[0186] From the above description, it can be seen that for the variable resistance resistor Re0, the voltage difference between the upper electrode TE and the lower electrode BE is -1.5V, and for the variable resistance resistor Re1, the voltage difference between the upper electrode TE and the lower electrode BE is 0V. Therefore, the variable resistance resistor Re0 can be reset based on the current voltage difference.

[0187] After the variable resistance Re0 is reset, when the variable resistance Re1 is reset, similar to the variable resistance Re0, there is also a setup time and a hold time; the difference is that the data DATA becomes a low level of 0V.

[0188] During the setup time, the clock control signal CK_A remains at 0V, the clock control signal CK_B remains at 1.5V, the clock control signal CK_C remains at 1.5V, the clock control signal CK_D remains at 0V, and the high-voltage switch first control signal K0 and the high-voltage switch second control signal K1 both change from a high-level state of 1.5V to a low-level state of 0V; at this time, the NMOS tube N1 and the NOS tube N2 are turned on, the high-voltage switch S1 and the high-voltage switch S2 enter the off state, the nodes A and C remain at 0V, the node B remains at 1.5V, the node D remains at 0V, and the output state of the data output terminal is 1.5V.

[0189] After the setup time is over, during the hold time, the clock signal CK will have a rising edge pulse. At this time, the clock control signal CK_A will change from a low level of 0V to a high level of 1.5V, and will remain at 1.5V during the hold time; the clock control signal CK_B will change from a high level of 1.5V to a low level of 0V, the clock control signal CK_C will change from a high level of 1.5V to a low level of 0V, and the clock control signal CK_D will change from a low level of 0V to a high level of 1.5V; the high-voltage switch first control signal K0 and the high-voltage The second switch control signal K1 is in a low level state of 0V. At this time, the NMOS tubes N0 and NMOS tubes N3 are turned on, and the node A is still 2.5V. When the NMOS tube N0 is turned on, since the data DATA is at a level of 0V, the node B changes from 1.5V to 0V, and the node C remains at 0V. When the node B is 0V, the NMOS tube N2, the NAND gate NAND1, and the set signal SEB can make the NAND gate NAND1 output 0V, and after the inverter INV1, the node D changes from 0V to 1.5V.

[0190] After the holding time, the variable resistance resistor Re1 is reset. At this time, the clock signal CK becomes 0V, the clock control signal CK_A changes from 1.5V to 0V, the clock control signal CK_B changes from 0V to 1.5V, the clock control signal CK_C changes from 0V to 1.5V, and the clock control signal CK_D changes from 1.5V to 0V. Then, the NMOS tubes N0 and NMOS tubes N3 change from on to off, and the NMOS tubes N1 and NMOS tubes N2 change from off to on. At the same time, the first control signal K0 of the high-voltage switch and the second control signal K1 of the high-voltage switch are both 1.5V, then the high-voltage switch S1 and the high-voltage switch S2 are both turned on, and since the programming voltage PHV is 0V, the voltages of nodes A and C are maintained at 0V, and since node B is at a low level during the holding time, node B can be maintained at 0V through the NAND gate NAND0 and the inverter INV0 and the NMOS tube N1, the NMOS tube N2 is turned on, and the output of the NAND gate NAND0 is 1.5V, then node D is maintained at 1.5V, and the data output end is maintained at a voltage of 0V.

[0191] From the above description, it can be seen that for the variable resistance resistor Re0, the voltage difference between the upper electrode TE and the lower electrode BE is 0V, and for the variable resistance resistor Re1, the voltage difference between the upper electrode TE and the lower electrode BE is -1.5V. Based on the current voltage difference, the variable resistance resistor Re1 can be reset.

[0192] Fig. 9 In the embodiment, after the Reset operation, the DFF function is entered. As can be seen from the above description, at this time, the set signal SEB is in an invalid level state, that is, in a high level of 1.5V, while the forming signal FOM, the data saving signal SET, the data recovery signal RES and the variable resistance reset signal RET are all in a low level state of 0V. Fig. 9 FIG. 2 shows an embodiment in which the data DATA is first in a high level state of 1.5V and then in a low level state of 0V.

[0193] When the data DATA is in a high level state of 1.5V, there will be a setup time before the rising edge of the clock signal CK. At this time, the clock control signal CK_A remains at 0V, the clock control signal CK_B remains at 1.5V, the clock control signal CK_C remains at 1.5V, the clock control signal CK_D remains at 0V, and the high-voltage switch first control signal K0 and the high-voltage switch second control signal K1 both change from a high level state of 1.5V to a low level state of 0V; at this time, the NMOS tube N1 and the NOS tube N2 are turned on, the high-voltage switch S1 and the high-voltage switch S2 enter the off state, the node A and the node C are in a floating state (Floating), the node B remains at 0V, the node D remains at 1.5V, and the output state of the data output end is 0V.

[0194] After that, the rising edge of the clock signal CK arrives and is maintained for a preset time. At this time, the clock control signal CK_A changes from a low level of 0V to a high level of 1.5V, the clock control signal CK_B changes from a high level of 1.5V to a low level of 0V, the clock control signal CK_C changes from a high level of 1.5V to a low level of 0V, and the clock control signal CK_D changes from a low level of 0V to a high level of 1.5V; the high-voltage switch first control signal K0 and the high-voltage switch second control signal K1 are both in a low level state of 0V. At this time, the NMOS tube N0 and the NMOS tube N3 are turned on, and the nodes A and C are in a floating state (Floating). When the NMOS tube N0 is turned on, since the data DATA is at a level of 1V, the node B changes from 0V to 1.5V; when the node B is 1.5V, the output of the NAND gate NAND0 is 0V, and the node D is 0V through the NMOS tube N2. At this time, the voltage of the data output end is 1.5V.

[0195] When the clock signal CK changes to 0V, at this time, the data DATA will still remain at 1.5V, the clock control signal CK_A will change from 1.5V to 0V, the clock control signal CK_B will change from 0V to 1.5V, the clock control signal CK_C will change from 0V to 1.5V, and the clock control signal CK_D will change from 1.5V to 0V, then the NMOS tube N0 and the NMOS tube N3 will change from on to off, and the NMOS tube N1 and the NMOS tube N2 will change from off to on. At the same time, the high-voltage switch first control signal K0 and the high-voltage switch second control signal K1 are both 0V, then the high-voltage switch S1 and the high-voltage switch S2 are both turned off, the node A and the node C remain in a floating state (Floating), the node B remains at 1.5V, the node D remains at 0V, and the output state of the data output end remains at 1.5V, that is, in the DFF function, when the data DATA is 1.5V, under the action of the rising edge of the clock signal CK, a high level of 1.5V can be obtained at the data output end.

[0196] When the data DATA changes from 1.5V to 0V, similar to the DFF function when DATA is 1.5V, there is also a setup time. At this time, the clock control signal CK_A remains at 0V, the clock control signal CK_B remains at 1.5V, the clock control signal CK_C remains at 1.5V, the clock control signal CK_D remains at 0V, and the high-voltage switch first control signal K0 and the high-voltage switch second control signal K1 both change from a high-level state of 1.5V to a low-level state of 0V; at this time, the NMOS tube N1 and the NOS tube N2 are turned on, the high-voltage switch S1 and the high-voltage switch S2 enter the off state, the node A and the node C are in a floating state (Floating), the node B remains at 1.5V, the node D remains at 0V, and the output state of the data output end is 1.5V.

[0197] After that, the rising edge of the clock signal CK arrives and is maintained for a preset time. At this time, the clock control signal CK_A changes from a low level of 0V to a high level of 1.5V, the clock control signal CK_B changes from a high level of 1.5V to a low level of 0V, the clock control signal CK_C changes from a high level of 1.5V to a low level of 0V, and the clock control signal CK_D changes from a low level of 0V to a high level of 1.5V; the first control signal K0 of the high-voltage switch and the second control signal K1 of the high-voltage switch are both in a low level state of 0V. At this time, the NMOS tubes N0 and NMOS tubes N3 are turned on, and nodes A and C are in a floating state (Floating). When the NMOS tube N0 is turned on, since the data DATA is at a level of 0V, the node B changes from 1.5V to 0V; when the node B is 0V, the output of the NAND gate NAND0 is 1.5V, and through the NMOS tube N2, the node D is 1.5V. At this time, the voltage of the data output end changes from 1.5V to 0V.

[0198] When the clock signal CK changes to 0V, at this time, the data DATA will still remain at 0V, the clock control signal CK_A will change from 1.5V to 0V, the clock control signal CK_B will change from 0V to 1.5V, the clock control signal CK_C will change from 0V to 1.5V, and the clock control signal CK_D will change from 1.5V to 0V, then the NMOS tube N0 and the NMOS tube N3 will change from on to off, and the NMOS tube N1 and the NMOS tube N2 will change from off to on. At the same time, the high-voltage switch first control signal K0 and the high-voltage switch second control signal K1 are both 0V, then the high-voltage switch S1 and the high-voltage switch S2 are both turned off, the node A and the node C remain in a floating state (Floating), the node B remains at 0V, the node D remains at 1.5V, and the output state of the data output end remains at 0V, that is, in the DFF function, when the data DATA is 0V, under the action of the rising edge of the clock signal CK, a low level of 0V can be obtained at the data output end.

[0199] When a data saving operation SET is required, Fig. 9 In the data saving process (SET), the data DATA needs to be 0V, the set signal SEB is in the voltage state of 1.5V, the data saving signal SET is also a high level of 1.5V, the clock signal CK, the forming signal FOM, the data recovery signal RES and the variable resistance reset signal RET are all 0V; the programming voltage PHV is 5V.

[0200] Fig. 9 In the embodiment, before the data saving operation SET, there is still a setup time, at this time, the clock control signal CK_A remains at 0V, the clock control signal CK_B remains at 1.5V, the clock control signal CK_C remains at 1.5V, the clock control signal CK_D remains at 0V, the high-voltage switch first control signal K0 and the high-voltage switch second control signal K1 are both in a low level state of 0V; at this time, the NMOS tube N1 and the NOS tube N2 are turned on, the high-voltage switch S1 and the high-voltage switch S2 are in the off state, the node A and the node C are in a floating state (Floating), the node B remains at 0V, the output of the NAND gate NAND0 is 1.5V, and when the NMOS tube N2 is turned on, the node D remains at 1.5V; since the set signal SEB is 1.5V, the output of the NAND gate NAND1 is 1.5V, and the output state of the data output terminal remains at 0V.

[0201] During the data storage operation SET, the clock control signal CK_A remains at 0V, the clock control signal CK_B remains at 1.5V, the clock control signal CK_C remains at 1.5V, and the clock control signal CK_D remains at 0V; since the output state of the data output terminal is 0V, when the data storage operation SET is at a high level, the high-voltage switch first control signal K0 is at a high level of 1.5V, and the high-voltage switch second control signal K1 is 0V; at this time, the high-voltage switch S1 is turned on, the high-voltage switch S2 remains off, and the programming voltage PHV is loaded to the variable resistance resistor Re0 through the high-voltage switch S1, the voltage of the node A is 5V, and the node C remains in a floating state (Floating). At this time, for the variable resistance resistor Re0, the voltage difference between the upper electrode TE and the lower electrode BE is greater than 0.57, which means that the variable resistance resistor Re0 can be switched from the high resistance state HRS after reset to the low configuration LRS. At this time, the output state of the data output terminal at the "0" level is realized and saved in the variable resistance resistor Re0.

[0202] When the output state of the data output terminal is 1.5V, then when the data storage operation SET is at a high level, the second control signal K1 of the high-voltage switch is at a high level of 1.5V, and the first control signal K0 of the high-voltage switch is 0V; at this time, the high-voltage switch S2 is turned on, the high-voltage switch S1 remains off, and the programming voltage PHV is loaded to the variable resistance resistor Re1 through the high-voltage switch S2, the voltage of the node C is 5V, and the node A is in a floating state (Floating). At this time, for the variable resistance resistor Re1, the voltage difference between the upper electrode TE and the lower electrode BE is greater than 0.57, which means that the variable resistance resistor Re1 can be switched from the high resistance state HRS after reset to the low configuration LRS. At this time, the output state of the data output terminal at the "1" level is realized and saved in the variable resistance resistor Re1.

[0203] In addition, during the data saving operation SET, if the output state of the current data output terminal is a high level state of "1", then different from the above, the second control signal K1 of the high-voltage switch is 1.5V, and the first control signal K0 of the high-voltage switch is 0V. When other conditions remain unchanged, the variable resistance resistor Re1 can be switched from the high resistance state HRS after reset to the low resistance state LRS. At this time, the output state of the data output terminal at the "1" level is realized and saved in the variable resistance resistor Re1.

[0204] During the operation of the non-volatile DFF, there may be circuit power failures, such as Fig. 9 The circuit in the circuit is powered off (POWERDOWN). At this time, the data DATA, the clock signal CK, the set signal SEB, the forming signal FOM, the data saving signal SET, the data recovery signal RES and the variable resistance reset signal RET are all at 0 level, the clock control signal CK_A, the clock control signal CK_B, the clock control signal CK_C, and the clock control signal CK_D will be from 0V, the high-voltage switch first control signal K0, and the high-voltage switch second control signal K1 are all at 0 level, and the nodes A to D are all at 0 level. Since the data saving operation SET has been performed before, the current level state of the data output terminal does not need to be paid attention to, that is, Fig. 9 Don’t care in the.

[0205] After the circuit is powered off and powered on again, in order to achieve non-volatility, the present invention can perform a data recovery operation RES on the non-volatile DFF, that is, Fig. 9 In the data recovery operation RES, the level state of the data DATA can be arbitrary, that is, Fig. 9 The level state of the data DATA is Do not care.

[0206] When performing the data recovery operation RES, the set signal SEB is at a high level of 1.5V, and the data recovery signal RES is also at a high level. During the data recovery operation RES, the rising edge of the clock signal CK is not required, so the clock control signal CK_A and the clock control signal CK_C are both kept at 0V. During the setup time of the data recovery operation RES, the clock control signal CK_B and the clock control signal CK_A are both kept at 0V. After the setup time, the clock control signal CK_B and the clock control signal CK_A are changed from 0V to 1.5V.

[0207] When the data recovery signal RES is at a high level, the high-voltage switch first control signal K0 and the high-voltage switch second control signal K1 are both changed from 0V to 1.5V. At this time, the high-voltage switch S1 and the high-voltage switch S2 are both turned on, that is, the upper electrode TE of the variable resistance resistor Re0 and the upper electrode TE of the variable resistance resistor Re1 are both connected to the programming voltage PHV of 0V. At this time, the nodes A and C are both 0V, the node B is also 0V, and the node D changes from 0V to 1.5V.

[0208] From the above description, we can see that Fig. 9 In the data saving operation SET, the "0" at the data output terminal is stored in the variable resistance resistor Re0. Therefore, during the data recovery operation RES, the data stored in the variable resistance resistor Re0 is restored to the node B. When the "0" level stored in the variable resistance resistor Re0 is restored to the node B, the output of the data output terminal can be 0V under the action of the next clock signal CK.

[0209] In addition, when the "1" at the data output end is stored in the variable resistance Re1, when the data recovery operation RES is performed, the "1" level stored in the variable resistance Re1 is restored to the node D, under the action of the next clock signal CK, the output of the data output end can be "1" corresponding to the high level of 1.5V.

[0210] After the data recovery operation RES, the non-volatile DFF can be configured to enter the DFF function. The situation of entering the DFF function can refer to the above description. Of course, in subsequent work, the situations of the data saving operation SET, the data recovery operation RES, etc. can all refer to the above description, which will not be repeated here.

[0211] In one embodiment of the present invention, when the non-volatile DFF is applied in an FPGA, all non-volatile DFFs receive the same clock signal CK, set signal SEB, shaping signal FOM, data save signal SET, data recovery signal RES and variable resistance reset signal RET;

[0212] In the FPGA, a data saving operation SET is performed on the non-volatile DFFs in the region according to the region mode, and the number of non-volatile DFFs in each region does not exceed 128.

[0213] Fig.10 FIG. 1 shows an embodiment of a non-volatile DFF applied to an FPGA. In the figure, IOB is an input / output port, CLB ARRAY is a programmable logic block array, and the corresponding CLB ARRAY can be selected through the cooperation of the bit line BL and the word line WL. The specific selection using the bit line BL and the word line WL can be consistent with the existing situation and will not be repeated here.

[0214] When non-volatile DFF is used in FPGA, for each non-volatile DFF, except for the data input port and data output port, all other ports are connected accordingly to form a global signal. From the above description, it can be seen that the programming voltage PHV needs to be 5V, 2.5V or 0V. Fig.10 In the embodiment, the selection and configuration of the programming voltage PHV can be realized by the high-voltage switch S2, the high-voltage switch S3 and the high-voltage switch S4. The high-voltage switches S2 to S4 can adopt the same circuit form as the above-mentioned high-voltage switch S1. The specific circuit form can refer to the above description.

[0215] From the above description, it can be seen that during the data saving operation SET, in order to ensure that the data is saved in the variable resistance resistor before the power supply voltage drops below the operating voltage range, all data saving operations SET use a high voltage of 5.0V to reduce the time of the data saving operation SET. The data saving operation SET of the variable resistance resistor can be completed within 1μS, thereby improving the reliability of the circuit.

[0216] Fig.10 In the data storage operation SET, the high voltage required is generated by the on-chip charge pump. Considering the current required for each variable resistance resistor to perform the data storage operation SET and the current driving capability of the on-chip charge pump, a regional data storage operation SET method is adopted.

[0217] Specifically, the data saving operation SET is performed in a regional mode, the number of non-volatile DFFs in each region does not exceed 128, and each region has an independent charge pump circuit to enable the variable resistance resistors in each region to simultaneously perform the data saving operation SET. After power-on, data recovery can be completed from the variable resistance resistors. For CLB ARRAY areas that are not used in the FPGA or areas that do not require data saving, the charge pump can be turned off by enabling the charge pump, thereby reducing the power consumption of the circuit.

[0218] Fig.11An embodiment of a charge pump is shown. In one embodiment of the present invention, the charge pump includes a plurality of voltage generating circuits connected in parallel, wherein:

[0219] Any voltage generating circuit includes a plurality of voltage generating units cascaded in sequence;

[0220] The voltage generating unit includes a voltage generating first NMOS tube, a voltage generating second NMOS tube and a voltage generating third NMOS tube;

[0221] The gate terminal of the first voltage generating NMOS tube is connected to the source terminal of the second voltage generating NMOS tube, one end of the second capacitor and the gate terminal of the third voltage generating NMOS tube;

[0222] The gate terminal of the second voltage generating NMOS tube is connected to the source terminal of the first voltage generating NMOS tube and one end of the first capacitor;

[0223] The drain terminal of the voltage generating first NMOS tube, the drain terminal of the voltage generating second NMOS tube and the drain terminal of the voltage generating third NMOS tube are connected to each other to form a first internal node of the voltage generating unit;

[0224] The source terminal of the voltage generating third NMOS tube is connected to one end of the third capacitor;

[0225] The other end of the first capacitor, the other end of the second capacitor and the other end of the third capacitor receive corresponding clock signals respectively.

[0226] Specifically, the charge pump includes a plurality of voltage generating circuits connected in parallel, and the plurality of voltage generating circuits connected in parallel can provide driving capability during power supply. Fig.11 The case of using four parallel voltage generating circuits is shown in FIG. 4 . The four voltage generating circuits can adopt the same circuit form. The voltage generating circuit includes a plurality of cascaded voltage generating units. The number of voltage generating units can be selected according to the needs. Fig.10 The M in the figure can be selected according to the actual needs, such as 6 or 8. The specific number can be selected according to the actual needs to meet the actual application requirements.

[0227] The voltage generating unit generally includes a first NMOS transistor for voltage generation, a second NMOS transistor for voltage generation, a third NMOS transistor for voltage generation, a first capacitor, a second capacitor and a third capacitor. Fig.101 shows an embodiment of a first-stage voltage generating unit and a last-stage voltage generating unit in a voltage generating circuit. In the figure, for the first-stage voltage generating unit, NM1 is a first NMOS tube for voltage generation, NM2 is a second NMOS tube for voltage generation, NM3 is a third NMOS tube for voltage generation, C1 is a first capacitor, C2 is a second capacitor, and C3 is a third capacitor. Similarly, for the last-stage voltage generating unit, NM4 is a first NMOS tube for voltage generation, NM5 is a second NMOS tube for voltage generation, NM6 is a third NMOS tube for voltage generation, C4 is a first capacitor, C5 is a second capacitor, and C6 is a third capacitor.

[0228] For the voltage generating unit of the first stage, the first internal node is connected to the voltage VDD, and for the other generating units, the first internal node is connected to the source terminal of the voltage generating third NMOS tube. Fig.10 In the figure, for the first-stage voltage generating unit, capacitor C1 receives the charge pump clock Φ0, capacitor C2 receives the charge pump clock Φ1, and capacitor C3 receives the charge pump clock Φ0; for the last-stage voltage generating unit, capacitor C4 receives the charge pump clock Φ2, capacitor C5 receives the charge pump clock Φ3, and capacitor C6 receives the charge pump clock Φ2.

[0229] Taking the voltage generating unit of the first stage as an example, capacitor C1, capacitor C2, the first voltage generating NMOS tube and the second voltage generating NMOS tube constitute a voltage multiplier, which controls the gate terminal of the third voltage generating NMOS tube. Capacitor C3 is the main capacitor of the charge pump, which is used to transfer the storage of charge; here, the third voltage generating NMOS tube is used as a charge transfer switch; the working principles of the voltage generating units of other stages can refer to the description here.

[0230] Fig.12 A timing diagram of an embodiment of charge pump clock Φ0 to charge pump clock Φ3 is shown in the figure, wherein the corresponding phases of charge pump clock Φ0 and charge pump clock Φ1 differ by 180°, i.e., they constitute two non-overlapping clocks; similarly, charge pump clock Φ2 and charge pump clock Φ3 also constitute two non-overlapping clocks; in the figure, the corresponding phases of charge pump clock Φ0 and charge pump clock Φ2 differ by T, and at the same time, the corresponding phases of charge pump clock Φ1 and charge pump clock Φ3 differ by T, and the size of the phase difference T can be selected as needed.

[0231] For the same voltage generating circuit, one voltage generating unit is connected to two non-overlapping clock signals, and two adjacent voltage generating units are connected to four clock signals correspondingly. Fig.11In the figure, the voltage generating unit of the first stage is controlled by the charge pump clock Φ0 and the charge pump clock Φ1, and the voltage generating power supply of the second stage is controlled by the charge pump clock Φ2 and the charge pump clock Φ3; the correspondence between other voltage generating units and clocks in the voltage generating circuit can be referred to the description here and will not be repeated here.

[0232] The method of generating voltage by cascading multiple voltage generating units can be consistent with the existing phase. In order to obtain the required voltage, the voltage generating unit of the last stage in the voltage generating circuit generally needs to be connected to the voltage reference unit. When connected to the voltage reference unit, it is generally necessary to use a voltage division form to obtain the voltage through the voltage reference unit.

Claims

1. A non-volatile DFF for FPGA based on a variable resistance resistor, characterized in that: The non-volatile DFF includes: The DFF functional unit body includes a latch unit and a variable resistance unit adapted to be connected to the latch unit, wherein the latch unit is correspondingly connected to the data input port and the data output end of the non-volatile DFF, wherein: The latch unit includes at least two latch circuits that are adaptively connected, the variable resistance resistor unit includes at least two variable resistance resistors, and one latch circuit is adaptively connected to at least one variable resistance resistor; A timing signal circuit receives a work instruction signal and configures an operation state of the DFF functional unit body based on the received work instruction signal, wherein the received work instruction signal includes a clock signal CK, a set signal SEB, a forming signal FOM, a data saving signal SET, a data recovery signal RES, and a variable resistance reset signal RET, and the configured operation state of the DFF functional unit body includes an electrical forming operation, a reset operation, a DFF function, a data saving operation SET, and / or a data recovery operation RES; Based on the forming signal FOM, the programming voltage PHV and the setting signal SEB, an electrical forming operation is performed on all the variable resistance resistors in the DFF functional unit body, so that after the electrical forming operation, all the variable resistance resistors are configured to be in a low resistance state LRS state; Based on the data DATA loaded from the data input port, the clock signal CK, the variable resistance reset signal RET and the set signal SEB, the variable resistance in the variable resistance unit is reset in sequence, so that after the reset operation, the corresponding variable resistance in the variable resistance unit is restored to the high resistance state HRS; When the DFF functional unit is in the DFF function, based on the clock signal CK, the data DATA loaded by the data input port is collected and output through the data output terminal, and when the set signal SEB is valid, the data output terminal is configured to be in the set state; Based on the data storage signal SET, the set signal SEB and the programming voltage PHV, a data storage operation SET is performed on the variable resistance unit, so that after the data storage operation SET, the output state of the data output terminal is stored by a variable resistance resistor; After the output state of the data output terminal is stored by the variable resistance unit, a data recovery operation RES is performed on the variable resistance unit based on the data recovery signal RES and the set signal SEB, so that after the data recovery operation RES, the output state of the corresponding variable resistance storage data output terminal is restored to the latch circuit adapted to be connected; When the non-volatile DFF is applied in FPGA, all non-volatile DFFs receive the same clock signal CK, set signal SEB, shaping signal FOM, data preservation signal SET, data recovery signal RES and variable resistance reset signal RET; In the FPGA, a data saving operation SET is performed on the non-volatile DFFs in the region according to the region mode, and the number of non-volatile DFFs in each region does not exceed 128; When the latch unit includes two latch circuits, the latch unit corresponding to the data input port is used to form a first-level latch, and the latch unit corresponding to the data output port is used to form a second-level latch, wherein: The variable resistance resistor connected to the first stage latch forms the first stage variable resistance resistor, and the variable resistance resistor connected to the second stage latch forms the second stage variable resistance resistor; When the output state of the data output terminal is stored in the first-stage variable resistance resistor, during the data recovery operation RES, the data stored in the first-stage variable resistance resistor is restored to the first-stage latch; When the output state of the data output terminal is stored in the second-stage variable resistance resistor, during the data recovery operation RES, the data stored in the second-stage variable resistance resistor is recovered to the second-stage latch; The lower electrode BE of the first-stage variable resistance resistor is adaptively connected to the latch circuit of the first-stage latch, and the lower electrode BE of the second-stage variable resistance resistor is adaptively connected to the latch circuit of the second-stage latch; The connection state between the upper electrode TE of the first-stage variable resistance resistor and the programming voltage PHV is configured through the high-voltage switch S1; The connection state between the upper electrode TE of the second-stage variable resistance resistor and the programming voltage PHV is configured through the high-voltage switch S2; During the electrical forming operation, the programming voltage PHV is at a first programming voltage; At the time of the data saving operation SET, the program voltage PHV is at a second program voltage, wherein a voltage value of the second program voltage is greater than a voltage value of the first program voltage.

2. The non-volatile DFF for FPGA based on variable resistance resistor according to claim 1, characterized in that: Based on the shaping signal FOM, the data recovery signal RES, the data storage signal SET, the variable resistance reset signal RET and the output state of the data output terminal, a high-voltage switch first control signal K0 and a high-voltage switch second control signal K1 are generated in the timing signal circuit, wherein: Based on the first control signal K0 of the high-voltage switch, when the high-voltage switch S1 is controlled to be turned on, the upper electrode TE of the first-stage variable resistance resistor is connected to the programming voltage PHV; Based on the second control signal K1 of the high-voltage switch, when the high-voltage switch S2 is controlled to be turned on, the upper electrode TE of the second-stage variable resistance resistor is connected to the programming voltage PHV; During the data storage operation SET, the first high-voltage switch control signal K0 and the second high-voltage switch control signal K1 are in opposite phases.

3. The non-volatile DFF for FPGA based on variable resistance resistor according to claim 2, characterized in that: The high-voltage switch S1 includes a PMOS tube P0, a PMOS tube P1 and a PMOS tube P2, wherein: The drain terminal of the PMOS tube P0, the drain terminal of the PMOS tube P1 and the drain terminal of the PMOS tube P2 are connected to each other to form a POWER_IN terminal; The gate terminal of the PMOS tube P0 is connected to the source terminal of the PMOS tube P1, the drain terminal of the NMOS tube N5 and the gate terminal of the PMOS tube P2; The source terminal of the PMOS tube P0 is connected to the drain terminal of the NMOS tube N4 and the gate terminal of the PMOS tube P1, and the source terminal of the NMOS tube N4 and the source terminal of the NMOS tube N5 are both grounded; The gate terminal of the NMOS tube N4 is connected to the input terminal of the inverter INV6 and forms the control terminal of the high-voltage switch; The output end of the inverter INV6 is connected to the gate end of the NMOS tube N5, and the source end of the PMOS tube P2 is used to form the POWER_OUT end; The high-voltage switch S1 is connected to the programming voltage PHV through the POWER_IN terminal, and the high-voltage switch S1 is connected to the upper electrode TE of the variable resistance resistor through the POWER_OUT terminal. The high-voltage switch first control signal K0 is loaded onto the control terminal of the high-voltage switch.

4. The non-volatile DFF for FPGA based on variable resistance resistor according to claim 1, characterized in that: The latch circuit of the first-stage latch includes an NMOS transistor N0, a NAND gate NAND0, an NMOS transistor N1 and an inverter INV0, wherein: The drain terminal of the NMOS tube N0 is connected to the data input port, the gate terminal of the NMOS tube N0 receives the clock control signal CK_A generated by the timing signal circuit, and the source terminal of the NMOS tube N0 is connected to an input terminal of the NOT gate NAND0, the lower electrode of the first-stage variable resistance resistor, and the drain terminal of the NMOS tube N1; The output end of the NAND gate NAND0 is adaptively connected to the source end of the NMOS tube N1 and the latch circuit of the second-stage latch, and the gate end of the NMOS tube N1 receives the clock control signal CK_B generated by the timing signal circuit; During the electrical forming operation and the data saving operation SET, the NMOS tube N0 is always in the off state based on the clock control signal CK_A, and the NMOS tube N1 is always in the on state based on the clock control signal CK_B; When the first-stage variable resistance resistor is reset, the NMOS tube N0 is turned on once based on the clock control signal CK_A, and the NMOS tube N1 is in the off state only when the NMOS tube N0 is turned on; When the DFF functional unit is in the DFF function and outputs a data of the data input port through the data output terminal, the NMOS tube N0 is configured to be turned on once based on the clock control signal CK_A, and the NMOS tube N1 is turned on only when the NMOS tube N0 is in the off state; During the data recovery operation RES, the NMOS transistor N0 is configured to be always in the off state based on the clock control signal CK_A, and the NMOS transistor N1 is configured to be in the on state based on the clock control signal CK_B.

5. The non-volatile DFF for FPGA based on variable resistance resistor according to claim 3, characterized in that: The latch circuit of the second-stage latch includes an NMOS tube N2, a NAND gate NAND1, an NMOS tube N3 and an inverter INV1, wherein: The output end of the NAND gate NAND1 and the input end of the inverter INV1 are both connected to the data output end; the output end of the inverter INV1 is connected to the source end of the NMOS tube N3, and the drain end of the NMOS tube N3 is connected to the lower electrode of the second-stage variable resistance resistor, the source end of the NMOS tube N2, and an input end of the NAND gate NAND1; The drain terminal of the NMOS tube N2 is connected to the output terminal of the NAND gate NAND0 in the first-stage latch and the input terminal of the inverter INV0; The input end of the NAND gate NAND0 and the input end of the NAND gate NAND1 both receive the set signal SEB; The gate end of the NMOS tube N2 receives the clock control signal CK_B generated by the timing signal circuit; the gate end of the NMOS tube N3 receives the clock control signal CK_D generated by the timing signal circuit, wherein During the electrical forming operation and the data saving operation SET, the NMOS tube N2 is always in the off state based on the clock control signal CK_C, and the NMOS tube N1 is always in the on state based on the clock control signal CK_D; When the second-stage variable resistance resistor is reset, the NMOS tube N2 is turned off once based on the clock control signal CK_C, and the NMOS tube N3 is turned on only when the NMOS tube N2 is in the off state; When the DFF functional unit is in the DFF function and outputs a data of the data input port through the data output terminal, the NMOS tube N2 is turned off once based on the clock control signal CK_C, and the NMOS tube N3 is turned on only when the NMOS tube N0 is in the off state; During the data recovery operation RES, the NMOS transistor N2 is configured to be always in the off state based on the clock control signal CK_C, and the NMOS transistor N3 is configured to be in the on state based on the clock control signal CK_D.

6. The non-volatile DFF for FPGA based on variable resistance resistor according to claim 5, characterized in that: The timing signal circuit includes a clock control signal generating circuit, wherein: The clock control signal generating circuit includes an inverter INV2, an input end of the inverter INV2 receives a clock signal CK, an output end of the inverter INV2 is connected to an input end of an inverter INV3 and an input end of an OR gate OR1, another input end of the OR gate OR1 receives a data recovery signal RES, and outputs a clock control signal CK_B via an output end of the OR gate OR1; The output end of the inverter INV3 is connected to one input end of the NOR gate NOR1, the other input end of the NOR gate NOR1 receives the shaped signal FOM, the output end of the NOR gate NOR1 is connected to the input end of the inverter INV4, and the clock control signal CK_C is generated via the output end of the NOR gate NOR1; The output terminal of the inverter INV4 is connected to one input terminal of the OR gate OR2 . The other input terminal of the OR gate OR2 receives the data recovery signal RES, and generates the clock control signal CK_D via the output terminal of the OR gate OR2 .

7. The non-volatile DFF for FPGA based on variable resistance resistor according to claim 2, characterized in that: The timing signal circuit includes a high voltage switch control signal generating circuit, wherein: The high-voltage switch control signal generating circuit comprises a high-voltage switch first control signal generating circuit and a high-voltage switch second control signal generating circuit; When the first-stage variable resistor is used to store the 0 level of the data output terminal, the high-voltage switch first control signal generating circuit includes an inverter INV5, the input terminal of the inverter INV5 is connected to the data output terminal, the output terminal of the inverter INV5 is connected to an input terminal of an AND gate AND1, the other input terminal of the AND gate AND1 receives the data storage signal SET, and the output terminal of the AND gate AND1 is connected to an input terminal of an OR gate OR3; The input end of the OR gate OR3 also receives the shaping signal FOM, the data recovery signal RES and the variable resistance reset signal RET, and the output end of the OR gate OR3 generates the high voltage switch first control signal K0; The high-voltage switch second control signal generating circuit comprises an AND gate AND2, the input end of the AND gate AND2 is connected to the data output end and receives the data saving signal SET, and the output end of the AND gate AND2 is connected to an input end of the OR gate OR4; The input end of the OR gate OR4 also receives the shaping signal FOM, the data recovery signal RES and the variable resistance reset signal RET, and the output end of the OR gate OR3 generates the high voltage switch second control signal K1.

8. The non-volatile DFF for FPGA based on variable resistance resistor according to any one of claims 1 to 7, characterized in that: The variable resistance resistor is a MIM structure, comprising: A first metal electrode plate of a variable resistor, used to form an upper electrode TE of a variable resistance resistor; The second metal electrode plate of the variable resistor is used to form the lower electrode BE of the variable resistance resistor; a switch dielectric layer, located between the first metal electrode plate of the variable resistor and the second metal electrode plate of the variable resistor, comprising a HfO2 layer and a Ti layer located on the HfO2 layer, wherein the HfO2 layer is located on the second metal electrode plate of the variable resistor, and the Ti layer is in contact with the first metal electrode plate of the variable resistor; The variable resistance resistor is electrically formed before enabling the variable resistance resistor.

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