A semiconductor power device and a method of manufacturing the same

Abstract

The application provides a semiconductor power device and a preparation method thereof. The semiconductor power device comprises: a plurality of main well regions arranged at intervals in a drift layer; a source region in the main well region; a channel region in a top region of the main well region, the channel region being adjacent to a sidewall of the source region; an auxiliary well region and a JFET region in the drift layer between adjacent main well regions, the auxiliary well region being spaced apart from the main well region, the JFET region being in contact with the sidewall of the channel region away from the source region, the conduction type of the JFET region being opposite to that of the main well region; the JFET region comprises a first JFET region between the auxiliary well region and the main well region; the first JFET region has opposite first and second sidewalls, the first sidewall being in contact with the sidewall of the main well region, and the second sidewall being in contact with the sidewall of the auxiliary well region; and the first and second sidewalls are arranged in the same direction and are curved. The semiconductor power device reduces the resistance of the channel region and improves the reverse breakdown voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor power device and a preparation method thereof. BACKGROUND

[0002] SiC power MOSFET is a unipolar voltage control device, mainly applied in power supply, power processing system, playing a role in controlling power conversion. Compared with traditional Si-based power devices, SiC devices are more likely to achieve high voltage, low loss and high power density, and thus gradually become the mainstream of the market. Generally, SiC power MOSFET has a vertical structure, the source and the gate are located on the upper surface of the MOSFET, and the drain is located below the substrate of the MOSFET. Based on this vertical structure, when the SiC power MOSFET works in the reverse off state, the electric field is easy to concentrate in the JFET zone, and the middle part of the surface of the JFET zone is the strongest. And the gate oxide above the JFET zone will be broken down due to the concentration of the electric field, thereby causing the failure of the device. At the same time, in order to reduce the on-resistance of the device, the doping of the JFET zone is usually increased. However, the doping of the JFET zone will cause the electric field to further concentrate on the surface of the JFET zone, increasing the risk of device failure. On the other hand, the lateral PN junction electric field formed by the JFET zone and the side wall of the well region will also affect the shortest length of the channel region. The length of the channel region cannot be too short to prevent channel punch-through, which also limits the reduction of the channel resistance. Therefore, when designing the JFET zone and the well region nearby, the maximum electric field at the gate oxide, the breakdown voltage, the channel punch-through characteristics, the channel resistance, and the JFET zone resistance need to be designed in a compromise. SUMMARY

[0003] Therefore, the technical problem to be solved by the present application is to solve the problem of how to reduce the channel resistance and improve the reverse breakdown voltage in the prior art, so as to provide a semiconductor power device and a preparation method thereof.

[0004] The application provides a semiconductor power device, comprising: a semiconductor substrate layer; a drift layer on the semiconductor substrate layer; a plurality of main well regions arranged at intervals in the drift layer, the main well regions having a conductive type opposite to that of the drift layer; a source region in the main well region; a channel region in a top region of the main well region, the channel region being adjacent to a sidewall of the source region; an auxiliary well region and a JFET region in the drift layer between adjacent main well regions, the auxiliary well region being spaced apart from the main well region, the auxiliary well region having a conductive type same as that of the main well region, the JFET region being in contact with the channel region away from the sidewall of the source region, the JFET region having a conductive type opposite to that of the main well region; the JFET region comprising a first JFET region between the auxiliary well region and the main well region; the first JFET region having first and second opposite sidewalls arranged in a length direction of the channel region, the first sidewall being in contact with a sidewall of the main well region, and the second sidewall being in contact with a sidewall of the auxiliary well region; and the first and second sidewalls being arranged in a same direction.

[0005] Optionally, the second sidewall is arranged in a convex curve towards the auxiliary well region; and the first sidewall is arranged in a concave curve towards an inner portion of the first JFET region.

[0006] Optionally, the second sidewall is arranged in a concave curve towards an inner portion of the first JFET region; and the first sidewall is arranged in a convex curve towards the main well region.

[0007] Optionally, a top surface of the auxiliary well region and a partial top surface of the drift layer are coincident; a bottom surface of the auxiliary well region is higher than a bottom surface of the main well region; the first JFET region is in contact with the channel region away from the sidewall of the source region; and the semiconductor power device further comprises: a second JFET region at a bottom of the auxiliary well region and the first JFET region, a top surface of the second JFET region being in contact with a bottom surface of the auxiliary well region and a bottom surface of the first JFET region respectively, and sidewalls on both sides of the second JFET region in the length direction of the channel region being in contact with partial sidewalls of the main well region.

[0008] Optionally, when the second sidewall is convexly curved towards the auxiliary well region and the first sidewall is concavely curved towards the inside of the first JFET region, the width of the auxiliary well region decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region first decreases and then increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region; when the second sidewall is concavely curved towards the inside of the first JFET region and the first sidewall is convexly curved towards the main well region, the width of the auxiliary well region increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region first increases and then decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region.

[0009] Optionally, the top surface of the auxiliary well region and the top surface of the drift layer are spaced apart and higher than the bottom surface of the main well region, and the bottom surface of the auxiliary well region is higher than the bottom surface of the main well region; the semiconductor power device further comprises: a second JFET region located at the bottom of the auxiliary well region and the first JFET region, the top surface of the second JFET region being in contact with the bottom surface of the auxiliary well region and the bottom surface of the first JFET region respectively, the sidewalls on both sides of the second JFET region in the length direction of the channel region being in contact with part of the sidewalls of the main well region; and a third JFET region located at the top of the auxiliary well region and the first JFET region, the bottom surface of the third JFET region being in contact with the top surface of the auxiliary well region and the top surface of the first JFET region respectively, the sidewalls on both sides of the third JFET region in the length direction of the channel region being in contact with the sidewalls of the channel region away from the source region.

[0010] Optionally, when the second sidewall is convexly curved towards the auxiliary well region and the first sidewall is concavely curved towards the inside of the first JFET region, the width of the auxiliary well region decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region first decreases and then increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region; when the second sidewall is concavely curved towards the inside of the first JFET region and the first sidewall is convexly curved towards the main well region, the width of the auxiliary well region increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region first increases and then decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region.

[0011] Optionally, the top surface of the auxiliary well region and the top surface of the drift layer are spaced apart and higher than the bottom surface of the main well region, and the bottom surface of the auxiliary well region is higher than the bottom surface of the main well region; the semiconductor power device further comprises: a second JFET region located at the bottom of the auxiliary well region and the first JFET region, the top surface of the second JFET region being in contact with the bottom surface of the auxiliary well region and the bottom surface of the first JFET region respectively, the sidewalls on both sides of the second JFET region in the length direction of the channel region being in contact with part of the sidewalls of the main well region; and a third JFET region located at the top of the auxiliary well region and the first JFET region, the bottom surface of the third JFET region being in contact with the top surface of the auxiliary well region and the top surface of the first JFET region respectively, the sidewalls on both sides of the third JFET region in the length direction of the channel region being in contact with the sidewalls of the channel region away from the source region.

[0012] Optionally, when the second sidewall is convexly curved towards the auxiliary well region and the first sidewall is concavely curved towards the inside of the first JFET region, the width of the auxiliary well region decreases first and then increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region; when the second sidewall is concavely curved towards the inside of the first JFET region and the first sidewall is convexly curved towards the main well region, the width of the auxiliary well region increases first and then decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region.

[0013] Optionally, the top surface of the auxiliary well region and the top surface of the drift layer are spaced apart and higher than the bottom surface of the main well region, and the bottom surface of the auxiliary well region is flush with or lower than the bottom surface of the main well region; the semiconductor power device further comprises a third JFET region located on the top of the auxiliary well region and the first JFET region, and the bottom surface of the third JFET region is in contact with the top surface of the auxiliary well region and the top surface of the first JFET region, respectively, and the sidewalls on both sides of the third JFET region in the length direction of the channel region are in contact with the sidewalls of the channel region away from the source region.

[0014] Optionally, when the second sidewall is convexly curved towards the auxiliary well region and the first sidewall is concavely curved towards the inside of the first JFET region, the width of the auxiliary well region increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region decreases first and then increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region; when the second sidewall is concavely curved towards the inside of the first JFET region and the first sidewall is convexly curved towards the main well region, the width of the auxiliary well region decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region increases first and then decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region.

[0015] Optionally, the lateral distance between the first sidewall and the second sidewall fluctuates less than or equal to 0.3 μm from top to bottom.

[0016] Optionally, the first sidewall and the second sidewall are arranged in parallel.

[0017] Optionally, the lateral distance between the first sidewall and the second sidewall is 0.05 μm to 1 μm.

[0018] Optionally, the projection of the auxiliary well region on the surface of the semiconductor substrate layer and the projection of the main well region on the surface of the semiconductor substrate layer have an overlapping region, and the projection of the auxiliary well region on the surface of the semiconductor substrate layer is located inside the projection of the main well region on the surface of the semiconductor substrate layer at both side edges in the length direction of the channel region.

[0019] Optionally, the width of the overlapping region is 0.1 μm to 1 μm.

[0020] Optionally, the doping concentration of the JFET region is greater than the doping concentration of the drift layer.

[0021] Optionally, the doping concentration of the JFET region is 20 times to 50 times the doping concentration of the drift layer.

[0022] Optionally, further comprising: a connecting well region located on both sides of the main well region, the auxiliary well region and the JFET region in a first direction, the connecting well region being connected with the auxiliary well region, the main well region and the JFET region respectively, the first direction being perpendicular to the length direction of the channel region and parallel to the upper surface of the semiconductor substrate layer.

[0023] The application further provides a semiconductor power device manufacturing method, comprising: providing a semiconductor substrate layer; forming a drift layer on the semiconductor substrate layer; forming an auxiliary well region in the drift layer, the conduction type of the auxiliary well region being opposite to the conduction type of the drift layer; forming a plurality of main well regions arranged at intervals in the drift layer, the conduction type of the main well region being opposite to the conduction type of the drift layer; the auxiliary well region being located between adjacent main well regions and spaced apart from the main well regions; forming a source region in the main well region; the main well region having a channel region in the top region thereof, the channel region being adjacent to the sidewall of the source region; the drift layer between adjacent main well regions having a JFET region, the JFET region being in contact with the sidewall of the source region away from the channel region, the conduction type of the JFET region being opposite to the conduction type of the main well region, the JFET region comprising a first JFET region located between the auxiliary well region and the main well region; the first JFET region having first and second sidewalls arranged in the length direction of the channel region and opposite to each other, the first sidewall being in contact with the sidewall of the main well region, and the second sidewall being in contact with the sidewall of the auxiliary well region; and the first and second sidewalls being arranged in the same direction and curved.

[0024] Optionally, the step of forming the auxiliary well region, the main well region and the JFET region comprises: performing a first ion implantation on the drift layer to form first doped regions in the drift layer, the first doped regions being of a conductive type opposite to that of the drift layer; forming a first mask layer on a top surface of the drift layer, the first mask layer being located above part of the first doped regions; performing a second ion implantation on the drift layer with the first mask layer as a mask to form second doped regions in the drift layer on both sides of the first mask layer along the length direction of the channel region, the second doped regions also extending to part of the bottom of the first mask layer, and the first doped regions located at the bottom of the first mask layer and between the second doped regions forming the auxiliary well region, the second doped regions being of a conductive type opposite to that of the auxiliary well region; forming first side walls on both sides of the first mask layer along the length direction of the channel region; performing a third ion implantation on the second doped regions with the first side walls and the first mask layer as masks to form the main well region in the drift layer on both sides of the first side walls and the first mask layer along the length direction of the channel region, the main well region also extending to part of the bottom of the first side walls, and the JFET region being formed in the drift layer at the bottom of the first side walls and the first mask layer and between adjacent main well regions, the second doped regions between the main well region and the auxiliary well region forming the first JFET region; and removing the first mask layer and the first side walls.

[0025] Optionally, the step of forming the auxiliary well region, the main well region and the JFET region comprises: performing a first ion implantation on the drift layer to form first doped regions in the drift layer, the first doped regions being of a conductive type opposite to that of the drift layer; forming a second mask layer on a top surface of the drift layer, the second mask layer having mask openings above part of the first doped regions; performing a fourth ion implantation on the drift layer at the bottom of the mask openings with the second mask layer as a mask to form third doped regions in the drift layer at the bottom of the mask openings, the third doped regions also extending to part of the bottom of the second mask layer, and the first doped regions located at the bottom of the second mask layer and on both sides of the third doped regions along the length direction of the channel region forming the main well region, the third doped regions being of a conductive type opposite to that of the main well region; forming second side walls on both sides of the mask openings along the length direction of the channel region; performing a fifth ion implantation on the third doped regions with the second side walls and the second mask layer as masks to form the auxiliary well region in the drift layer at the bottom of the mask openings, the auxiliary well region also extending to part of the bottom of the second side walls, and the JFET region being formed in the drift layer between adjacent main well regions, the third doped regions between the main well region and the auxiliary well region forming the first JFET region; and removing the second mask layer and the second side walls.

[0026] The technical scheme of the present application has the following beneficial effects:

[0027] The semiconductor power device of the technical scheme of the present application can reduce the depletion degree of the channel region when the semiconductor power device works in the reverse blocking state, thus reducing the occurrence threshold of the channel region punch-through, thus making the channel region shorter and reducing the forward resistance of the channel region. Secondly, the total area of the projection of the auxiliary well region and the main well region on the semiconductor substrate layer is increased, and when the semiconductor power device works in the reverse blocking state (the gate structure is closed and the potential of the source region is lower than that of the drain region), the shielding effect of the auxiliary well region and the main well region on the electric field is enhanced, the electric field intensity at the gate oxide layer position is reduced, the occurrence threshold of the gate oxide layer breakdown is reduced, and the reverse breakdown voltage is improved.

[0028] Secondly, compared with the prior art, the number of JFET paths is increased, and each auxiliary well region has two first JFET regions on both sides, each first JFET region independently performs the trade-off of the breakdown voltage, the electric field, the channel region punch-through, and the on-resistance, and the increase of the JFET paths reduces the on-resistance. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical scheme in the specific embodiments of the present application or the prior art, the drawings needed in the specific embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0030] Figure 1 The schematic diagram of the semiconductor power device provided by an embodiment of the present application is shown in the figure;

[0031] Figure 2 The schematic diagram of the semiconductor power device provided by another embodiment of the present application is shown in the figure; Figure 1 The top view schematic diagram of the well region and the JFET region is shown in the figure;

[0032] Figure 3 The schematic diagram of the semiconductor power device provided by another embodiment of the present application is shown in the figure;

[0033] Figure 4 The schematic diagram of the semiconductor power device provided by another embodiment of the present application is shown in the figure;

[0034] Figure 5 The schematic diagram of the semiconductor power device provided by another embodiment of the present application is shown in the figure;

[0035] Figure 6 The schematic diagram of the semiconductor power device provided by another embodiment of the present application is shown in the figure;

[0036] Figure 7 The schematic diagram of the semiconductor power device provided by another embodiment of the present application is shown in the figure;

[0037] Figures 8 to 17 A schematic diagram of a semiconductor power device manufacturing process is provided for another embodiment of the present application.

[0038] Figures 18 to 24 A schematic diagram of a semiconductor power device manufacturing process is provided for another embodiment of the present application. DETAILED DESCRIPTION

[0039] The present application provides a semiconductor power device and a manufacturing method thereof. The semiconductor power device comprises: a semiconductor substrate layer; a drift layer located on the semiconductor substrate layer; a plurality of main well regions arranged at intervals in the drift layer, the main well regions having a conductive type opposite to that of the drift layer; a source region located in the main well region; a channel region in a top region of the main well region, the channel region being adjacent to a sidewall of the source region; an auxiliary well region and a JFET region in the drift layer between adjacent main well regions, the auxiliary well region being spaced apart from the main well region, the auxiliary well region having the same conductive type as the main well region, the JFET region being in contact with the sidewall of the source region away from the channel region, the JFET region having a conductive type opposite to that of the main well region; the JFET region comprising a first JFET region between the auxiliary well region and the main well region; the first JFET region having first and second opposite sidewalls arranged in a length direction of the channel region, the first sidewall being in contact with a sidewall of the main well region, and the second sidewall being in contact with a sidewall of the auxiliary well region; and the first and second sidewalls being arranged in a same direction with a curvature. The semiconductor power device can reduce the resistance of the channel region and improve the reverse breakdown voltage.

[0040] The first and second sidewalls are arranged in the same direction with a curvature, in particular, the second sidewall is arranged with a convex curvature towards the auxiliary well region; the first sidewall is arranged with a concave curvature towards the inside of the first JFET region; or, the second sidewall is arranged with a concave curvature towards the inside of the first JFET region; and the first sidewall is arranged with a convex curvature towards the main well region.

[0041] The technical solutions of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present application.

[0042] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0043] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0044] In addition, the technical features involved in the different embodiments of the application described below can be combined with each other as long as there is no conflict.

[0045] Embodiment 1

[0046] An embodiment of the present application provides a semiconductor power device, referring to Figure 1 , comprising:

[0047] a semiconductor substrate layer 100;

[0048] a drift layer 110 located on the semiconductor substrate layer 100;

[0049] a plurality of main well regions 120 arranged at intervals in the drift layer 110, the conductivity type of the main well region 120 being opposite to the conductivity type of the drift layer 110;

[0050] a source region 130 located in the main well region 120; the main well region 120 has a channel region in the top region, and the channel region is adjacent to the sidewall of the source region 130;

[0051] The auxiliary well region 121 and the JFET region in the drift layer 110 between the adjacent main well regions 120, the auxiliary well region 121 is spaced from the main well region 120, the auxiliary well region 121 has the same conductivity type as the main well region 120, the JFET region contacts the sidewall of the channel region away from the source region 130, the conductivity type of the JFET region is opposite to the conductivity type of the main well region 120; the JFET region includes a first JFET region 101 between the auxiliary well region 121 and the main well region 120; the first JFET region 101 has opposite first and second sidewalls 101a and 101b arranged in the length direction of the channel region, the first sidewall 101a contacts the sidewall of the main well region 120, and the second sidewall 101b contacts the sidewall of the auxiliary well region 121; the first and second sidewalls 101a and 101b are arranged in the same direction.

[0052] In the embodiment, since the first and second sidewalls 101a and 101b are arranged in the same direction, the depletion degree of the channel region can be reduced when the semiconductor power device works in the reverse blocking state, so that the threshold of the channel region punch-through is reduced, the channel region can be shorter, and the forward resistance of the channel region is reduced. In addition, the total area of the projections of the auxiliary well region 121 and the main well region 120 on the semiconductor substrate layer 100 is increased, and when the semiconductor power device works in the reverse blocking state (the gate structure is closed and the potential of the source region 130 is lower than that of the drain region), the shielding effect of the auxiliary well region 121 and the main well region 120 on the electric field is enhanced, the electric field intensity at the gate oxide layer position is reduced, the threshold of the gate oxide layer breakdown is reduced, and the reverse breakdown voltage is improved.

[0053] In the embodiment, the semiconductor power device is a power MOSFET device.

[0054] In the embodiment, the semiconductor power device is taken as a SiC-based semiconductor power device as an example for description, and correspondingly, the semiconductor substrate layer 100 is silicon carbide (SiC) doped with conductive ions. The new generation of semiconductor power devices based on SiC have higher reverse voltage resistance, lower forward conduction loss, faster switching frequency and stronger environmental tolerance, and are therefore considered as a new hope in the field of electric energy conversion. It should be noted that in the embodiment, the material of the semiconductor substrate layer 100 is not limited. In one embodiment, the conductive ions in the semiconductor substrate layer 100 are N-type ions.

[0055] In one embodiment, the drift layer 110 is doped with N-type conductive ions, which can be phosphorus ions or nitrogen ions. Further, the material of the drift layer 110 is silicon carbide doped with N-type conductive ions. It is to be noted that in other embodiments, the material of the drift layer 110 can also be other materials.

[0056] The conductivity type of the main well region 120 is opposite to that of the drift layer 110. In the present embodiment, when the conductivity type of the drift layer 110 is N-type, the conductivity type of the main well region 120 is P-type.

[0057] The conductivity type of the source region 130 is opposite to that of the main well region 120. In the present embodiment, when the conductivity type of the main well region 120 is P-type, the conductivity type of the source region 130 is N-type.

[0058] The conductivity type of the auxiliary well region 121 is the same as that of the main well region 120. In the present embodiment, when the conductivity type of the main well region 120 is P-type, the conductivity type of the auxiliary well region 121 is P-type.

[0059] The arrangement direction of the first side wall 101a and the second side wall 101b is parallel to the length direction of the channel region in the main well region.

[0060] In the present embodiment, the second side wall 101b is convexly curved towards the auxiliary well region 121, and the first side wall 101a is concavely curved towards the inside of the first JFET region 101.

[0061] In the present embodiment, the top surface of the auxiliary well region 121 coincides with part of the top surface of the drift layer 110, and the bottom surface of the auxiliary well region 121 is flush with the bottom surface of the main well region 120. The JFET region only includes the first JFET region 101. It is to be noted that in other embodiments, the top surface of the auxiliary well region coincides with part of the top surface of the drift layer, the bottom surface of the auxiliary well region is lower than the bottom surface of the main well region and is spaced apart from the bottom surface of the drift layer, and the JFET region only includes the first JFET region.

[0062] Further, when the second side wall 101b is convexly curved towards the auxiliary well region 121, and the first side wall 101a is concavely curved towards the inside of the first JFET region 101, the width of the auxiliary well region 121 first decreases and then increases from the direction of the top surface of the auxiliary well region 121 to the bottom surface of the auxiliary well region 121. Further, the width of the top surface of the auxiliary well region is greater than, equal to, or less than the width of the bottom surface of the auxiliary well region, Figure 1The width of the auxiliary well region 121 is equal to the width of the bottom surface of the auxiliary well region 121, for example. It should be noted that the width direction of the auxiliary well region 121 is parallel to the length direction of the channel region in the source region.

[0063] In this embodiment, the first sidewall 101a and the second sidewall 101b are arranged in the same direction, the lateral distance from the center of the top region of the first JFET region 101 to the channel region is smaller than the lateral distance from the center of the middle region of the first JFET region 101 to the channel region, and the lateral distance from the top region of the auxiliary well region 121 to the channel region is smaller than the lateral distance from the middle region of the auxiliary well region 121 to the channel region. In this way, the top region of the auxiliary well region 121 is expanded towards the channel region, the width of the top region of the auxiliary well region 121 is larger, and the width of the first JFET region 101 between the top region of the auxiliary well region 121 and the channel region is smaller. Therefore, when the semiconductor power device works in the reverse blocking state, the top region of the first JFET region 101 and the auxiliary well region 121 are more depleted, thereby reducing the degree of depletion of the top region of the first JFET region 101 and the channel region, and reducing the threshold of the channel region punch-through.

[0064] The center of the bottom region of the first JFET region 101 extends towards the main well region 120 relative to the center of the middle region of the first JFET region 101. In this way, the line connecting the majority carriers in the drift layer 110 at the bottom of the auxiliary well region 121 to the direction of the channel region must pass through the auxiliary well region 121. Therefore, the majority carriers in the drift layer 110 at the bottom of the auxiliary well region 121 are preferentially depleted and the majority carriers in the auxiliary well region 121 are depleted, and do not move to the channel region. This avoids the depletion of the majority carriers in the drift layer 110 at the bottom of the auxiliary well region 121 and the channel region, and reduces the threshold of the channel region punch-through.

[0065] In this embodiment, the projection of the auxiliary well region 121 on the surface of the semiconductor substrate layer 100 and the projection of the main well region 120 on the surface of the semiconductor substrate layer 100 have an overlapping region, and the projection of the auxiliary well region 121 on the surface of the semiconductor substrate layer 100 falls inside the projection of the main well region 120 on the surface of the semiconductor substrate layer 100 on both sides of the length direction of the channel region. In this way, when the semiconductor power device works in the reverse blocking state, the shielding effect of the auxiliary well region 121 and the main well region 120 on the electric field is enhanced, the electric field intensity at the gate oxide layer position is further reduced, the threshold of the gate oxide layer breakdown is further reduced, and the reverse breakdown voltage is further improved. In other embodiments, this is not limited.

[0066] Further, when the projection of the auxiliary well region 121 on the surface of the semiconductor substrate layer 100 and the projection of the main well region 120 on the surface of the semiconductor substrate layer 100 have an overlapping region, the width of the overlapping region is 0.1 μm to 1 μm, for example, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm or 1 μm. When the semiconductor power device works in the reverse blocking state, the shielding effect of the auxiliary well region 121 and the main well region 120 on the electric field is further enhanced. The width direction of the overlapping region is parallel to the length direction of the channel region. If the width of the overlapping region is greater than 1 μm, the current path is too long when the semiconductor power device works in the forward conducting state, and the forward conducting resistance is affected. The width direction of the overlapping region is parallel to the length direction of the channel region.

[0067] In one embodiment, the lateral distance between the first sidewall 101a and the second sidewall 101b fluctuates less than or equal to 0.3 μm from top to bottom, for example, the lateral distance between the first sidewall 101a and the second sidewall 101b fluctuates 0.3 μm, 0.2 μm, 0.1 μm, 0.05 μm or 0 μm from top to bottom. The advantage is that the protection of the channel region and the position of the gate oxide layer is ensured, and the local resistance in the narrow area is not increased by the JFET effect. In a specific embodiment, the first sidewall 101a and the second sidewall 101b are arranged in parallel, and at this time, the lateral distance between the first sidewall 101a and the second sidewall 101b fluctuates zero from top to bottom.

[0068] In one embodiment, the lateral distance between the first sidewall 101a and the second sidewall 101b is 0.05 μm to 1 μm, for example, 0.05 μm, 0.08 μm, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm or 1 μm. The advantage is that if the lateral distance between the first sidewall 101a and the second sidewall 101b is greater than 1 μm, the degree of reduction of the majority carriers and the channel region depletion in the first JFET region 101 is smaller; if the lateral distance between the first sidewall 101a and the second sidewall 101b is less than 0.05 μm, the current path in the first JFET region 101 is too narrow when the semiconductor power device works in the forward conducting state, which is not conducive to the reduction of the forward conducting resistance.

[0069] In one embodiment, the bending arc of the first sidewall 101a from top to bottom is less than π, for example, 2π / 3 degrees, π / 2, π / 4 or π / 6, and the bending arc of the second sidewall 101b from top to bottom is less than π, for example, 2π / 3 degrees, π / 2, π / 4 or π / 6.

[0070] In one embodiment, the system further includes a current extension region 150 located in the drift layer 110 at the bottom of the main well region 120, the JFET region, and the auxiliary well region 121. The conductivity type of the current extension region 150 is the same as that of the drift layer 110, and the doping concentration of the current extension region 150 is greater than that of the drift layer 110. In other embodiments, the current extension region may not be provided.

[0071] The doping concentration of the current extension region 150 is lower than that of the JFET region. In one embodiment, the doping concentration of the current extension region 150 is 5 to 10 times that of the drift layer 110. The doping concentration of the current extension region 150 should not be too high, otherwise the reverse breakdown voltage will be reduced.

[0072] The doping concentration of the JFET region is greater than that of the drift layer 110, which can appropriately reduce the forward conduction resistance of the JFET region.

[0073] In one embodiment, the doping concentration of the JFET region is 20 to 50 times that of the drift layer 110, for example, 20, 25, 30, 35, 40, 45, or 50 times. In a specific embodiment, the doping concentration of the JFET region is 1 × 10⁻⁶. 16 atom / cm 3 ~5×10 17 atom / cm 3 For example, 1×10 16 atom / cm 3 1×10 17 atom / cm 3 3×10 17 atom / cm 3 Or 5×10 17 atom / cm 3 In this embodiment, the doping concentration of the JFET region is greater than that of the JFET region in the prior art, which further reduces the forward conduction resistance of the JFET region.

[0074] In this embodiment, the lateral distance between the first sidewall 101a and the second sidewall 101b is small, and the special configuration of the JFET region's topography results in a smaller degree of depletion in the JFET region and channel region when the semiconductor power device operates in reverse blocking mode. Therefore, even if the doping concentration of the JFET region is appropriately increased, channel punch-through can be avoided. Because the lateral distance between the first sidewall 101a and the second sidewall 101b is small, even if the doping concentration of the JFET region is appropriately increased, the surface electric field at the gate oxide layer location will not increase. Increasing the doping concentration of the JFET region reduces the forward conduction resistance of the semiconductor power device.

[0075] In one embodiment, the doping concentration of the JFET region is equal to or different from the doping concentration of the auxiliary well region 121, and the doping concentration of the JFET region is equal to or different from the doping concentration of the main well region 120.

[0076] When the doping concentration of the JFET region is different from the doping concentration of the main well region 120, the doping concentration of the JFET region is less than the doping concentration of the main well region 120, or the doping concentration of the JFET region is greater than the doping concentration of the main well region 120. When the doping concentration of the JFET region is different from the doping concentration of the auxiliary well region 121, the doping concentration of the JFET region is less than the doping concentration of the auxiliary well region 121, or the doping concentration of the JFET region is greater than the doping concentration of the auxiliary well region 121.

[0077] Preferably, the doping concentration of the auxiliary well region 121 is less than the doping concentration of the JFET region, so that the width of the depletion layer of the PN junction formed by the auxiliary well region 121 and the first JFET region 101 extending in the first JFET region 101 is smaller than the width of the depletion layer extending in the auxiliary well region 121 when the semiconductor power device is in forward conduction, so that the path of the current in the first JFET region 101 is not too narrow, so that the forward conduction resistance of the semiconductor power device is smaller.

[0078] When the doping concentration of the main well region 120 is less than the doping concentration of the JFET region, the width of the depletion layer of the PN junction formed by the main well region 120 and the first JFET region 101 extending in the first JFET region 101 is smaller than the width of the depletion layer extending in the main well region 120 when the semiconductor power device is in forward conduction, so that the path of the current in the first JFET region 101 is not too narrow, so that the forward conduction resistance of the semiconductor power device is smaller. When the doping concentration of the main well region 120 is greater than the doping concentration of the JFET region, it is easy to control the structure of the main well region 120 and the JFET region in the process, and the difficulty of the process is reduced.

[0079] In one embodiment, the length of the channel region is 0.2 μm-0.5 μm, for example, 0.2 μm, 0.3 μm, 0.4 μm or 0.5 μm.

[0080] In this embodiment, reference is made to Figure 2The well region J in the drift layer includes a main well region 120, an auxiliary well region 121, and a connection well region J1. The connection well region J1 is located on both sides of the main well region 120 and the auxiliary well region 121 and the JFET region in a first direction, which is perpendicular to the length direction of the channel region and parallel to the upper surface of the semiconductor substrate layer. The auxiliary well region 121 is connected to the connection well region J1, the main well region 120 is connected to the connection well region J1, and the connection well region J1 is connected to the JFET region. The advantage is that, due to the connection of the auxiliary well region 121 to the connection well region J1 and the connection of the main well region 120 to the connection well region J1, and the application of the potential on the source region 130 to the ground potential, the auxiliary well region 121 is interconnected through the connection well region J1 and the main well region 120 to ensure that the semiconductor power device can complete the high-speed switching action, and the change of the hole charge region in the auxiliary well region 121 can easily follow the change of the potential of the drain region.

[0081] The PN junction formed by the auxiliary well region 121 and the drift layer at the bottom of the auxiliary well region 121 shields the electric field, reduces the electric field at the top surface of the auxiliary well region 121, and reduces the electric field intensity borne by the subsequent gate oxide layer. Further, in the embodiment, the top region of the auxiliary well region 121 extends towards the channel region, and the auxiliary well region 121 is interconnected through the connection well region J1 and the main well region 120, so that the potential of the larger area of the top surface of the auxiliary well region 121 is lower, which reduces the electric field intensity borne by the gate oxide layer in a larger range and reduces the threshold value of the breakdown of the gate oxide layer.

[0082] In the embodiment, the interconnection of the auxiliary well region 121 through the connection well region J1 and the main well region 120 can also improve the ratio of the input capacitance (Ciss) to the transfer capacitance (Crss) to improve the stability of the application of the semiconductor power device.

[0083] In the embodiment, the gate structure 180 is further included, which is located above the auxiliary well region 121 and the JFET region and across the part of the source region 130 and the channel region on both sides of the auxiliary well region 121. The gate structure 180 includes a gate oxide layer 181 and a gate electrode layer 182, and the gate electrode layer 182 is located on the gate oxide layer 181. The material of the gate oxide layer 181 includes silicon oxide, and the material of the gate electrode layer 182 includes polysilicon.

[0084] In this embodiment, the semiconductor power device further comprises a front electrode 170 in contact with the source region 130, and an isolation dielectric layer 190 surrounding the side surfaces and the top surface of the gate electrode layer 182. The front electrode 170 covers the gate structure 180, and the isolation dielectric layer 190 separates the front electrode 170 and the gate electrode layer 182. The material of the isolation dielectric layer 190 comprises silicon oxide. The semiconductor power device further comprises an ohmic contact region 140 in the main well region 120 and in contact with the source region 130, and the front electrode 170 is also in contact with the ohmic contact region 140. The drain region 160 is located on the side surface of the semiconductor substrate layer 100 away from the drift layer 110. The current spreading region 150 is also located in the drift layer 110 at the bottom of the ohmic contact region 140.

[0085] It should be noted that in other embodiments, the top surface of the auxiliary well region and part of the top surface of the drift layer coincide, the bottom surface of the auxiliary well region is lower than the bottom surface of the main well region and is spaced apart from the bottom surface of the drift layer, and the JFET region only comprises the first JFET region. The other descriptions of the semiconductor power device are all with reference to the semiconductor power device of the above embodiment 1. Figure 1 The description of the semiconductor power device is for example.

[0086] Embodiment 2

[0087] This embodiment provides a semiconductor power device, which is different from the embodiment 1 in that with reference to the semiconductor power device of the above embodiment 1, Figure 3 the top surface of the auxiliary well region 1211 and part of the top surface of the drift layer 110 coincide, and the bottom surface of the auxiliary well region 1211 is higher than the bottom surface of the main well region 120. The JFET region comprises a first JFET region 1011 and a second JFET region 102, the first JFET region 1011 is located between the auxiliary well region 1211 and the main well region 120, and the second JFET region 102 is located at the bottom of the auxiliary well region 1211 and the first JFET region 1011, the top surface of the second JFET region 102 is in contact with the bottom surface of the auxiliary well region 1211 and the bottom surface of the first JFET region 1011 respectively, and the side walls on both sides of the second JFET region 102 in the length direction of the channel region are in contact with part of the side walls of the main well region 120. The first JFET region 1011 is in contact with the side wall of the channel region away from the source region 130. The first JFET region 1011 has first and second side walls 1011a and 1011b arranged in the length direction of the channel region and opposite to each other, the first side wall 1011a is in contact with the side wall of the main well region 120, and the second side wall 1011b is in contact with the side wall of the auxiliary well region 1211; the first and second side walls 1011a and 1011b are arranged in the same direction and are curved. Specifically, the second side wall 1011b is curved and protrudes towards the auxiliary well region 1211, and the first side wall 1011a is curved and recessed towards the inside of the first JFET region 1011.

[0088] Further, referring to Figure 3 When the second side wall 1011b is convexly curved towards the auxiliary well region 1211 and the first side wall 1011a is concavely curved towards the inside of the first JFET region 1011, the width of the auxiliary well region 1211 decreases from the top surface of the auxiliary well region 1211 to the bottom surface of the auxiliary well region 1211.

[0089] The other contents of the present embodiment are the same as those of Embodiment 1 and will not be described in detail.

[0090] Embodiment 3

[0091] The present embodiment is different from Embodiment 2 in that referring to Figure 4 , the width of the auxiliary well region 1212 decreases first and then increases from the top surface of the auxiliary well region 1212 to the bottom surface of the auxiliary well region.

[0092] In one embodiment, the width of the top surface of the auxiliary well region 1212 is greater than the width of the bottom surface of the auxiliary well region 1212. In other embodiments, there is no limitation.

[0093] Referring to Figure 4 , the top surface of the auxiliary well region 1212 and part of the top surface of the drift layer 110 coincide, and the bottom surface of the auxiliary well region 1212 is higher than the bottom surface of the main well region 120. The JFET region includes a first JFET region 1012 and a second JFET region 1021, the first JFET region 1012 is located between the auxiliary well region 1212 and the main well region 120, and the second JFET region 1021 is located at the bottom of the auxiliary well region 1212 and the first JFET region 1012, the top surface of the second JFET region 1021 contacts the bottom surface of the auxiliary well region 1212 and the bottom surface of the first JFET region 1012, respectively, and the side walls on both sides of the second JFET region 1021 in the length direction of the channel region contact part of the side walls of the main well region 120. The first JFET region 1012 contacts the side wall of the channel region away from the source region 130. The first JFET region 1012 has first and second side walls 1012a and 1012b arranged in the length direction of the channel region and curved in the same direction, specifically, the second side wall 1012b is convexly curved towards the auxiliary well region 1212, and the first side wall 1012a is concavely curved towards the inside of the first JFET region 1012.

[0094] The other contents of the present embodiment are the same as those of Embodiment 2 and will not be described in detail.

[0095] Embodiment 4

[0096] The embodiment is different from the embodiment 1 in that, referring to Figure 5 , the top surface of the auxiliary well region 1213 and the top surface of the drift layer 110 are spaced apart from and higher than the bottom surface of the main well region 120, and the bottom surface of the auxiliary well region 1213 is higher than the bottom surface of the main well region 120; the JFET region includes a first JFET region 1013, a second JFET region 1022, and a third JFET region 103. The first JFET region 1013 is located between the auxiliary well region 1213 and the main well region 120. The second JFET region 1022 is located at the bottom of the auxiliary well region 1213 and the first JFET region 1013, the top surface of the second JFET region 1022 is in contact with the bottom surface of the auxiliary well region 1213 and the bottom surface of the first JFET region 1013, respectively, the sidewalls on both sides of the second JFET region 1022 in the length direction of the channel region are in contact with the partial sidewalls of the main well region 120, and the third JFET region 103 is located at the top of the auxiliary well region 1213 and the first JFET region 1013, the bottom surface of the third JFET region 103 is in contact with the top surface of the auxiliary well region 1213 and the top surface of the first JFET region 1013, respectively, and the sidewalls on both sides of the third JFET region 103 in the length direction of the channel region are in contact with the sidewalls of the channel region away from the source region.

[0097] The first JFET region 1013 has first and second opposite sidewalls 1013a and 1013b arranged in the length direction of the channel region, the first sidewall 1013a is in contact with the sidewall of the main well region 120, and the second sidewall 1013b is in contact with the sidewall of the auxiliary well region 1213. The first and second sidewalls 1013a and 1013b are arranged in the same direction and are curved, specifically, the second sidewall 1013b is curved and protrudes towards the auxiliary well region 1213, and the first sidewall 1013a is curved and recessed towards the inside of the first JFET region 1013.

[0098] Further, referring to Figure 5 , when the second sidewall 1013b is curved and protrudes towards the auxiliary well region 1213, and the first sidewall 1013a is curved and recessed towards the inside of the first JFET region 1013, the width of the auxiliary well region 1213 first decreases and then increases from the top surface of the auxiliary well region 1213 to the bottom surface of the auxiliary well region 1213. Further, the width of the top surface of the auxiliary well region is greater than, equal to, or less than the width of the bottom surface of the auxiliary well region, Figure 5 , taking the example that the width of the top surface of the auxiliary well region 1213 is equal to the width of the bottom surface of the auxiliary well region 1213.

[0099] In other embodiments, when the second sidewall is convexly curved towards the auxiliary well region and the first sidewall is concavely curved towards the inside of the first JFET region, the width of the auxiliary well region decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region.

[0100] The other contents of the present embodiment are the same as those of Embodiment 1, and will not be described in detail.

[0101] Embodiment 5

[0102] The present embodiment is different from Embodiment 1 in that, referring to Figure 6 , the top surface of the auxiliary well region 1214 and the top surface of the drift layer 110 are spaced apart and higher than the bottom surface of the main well region 120, and the bottom surface of the auxiliary well region 1214 is flush with the bottom surface of the main well region 120; the JFET region includes a first JFET region 1014 and a third JFET region 1031. The first JFET region 1014 is located between the auxiliary well region 1214 and the main well region 120. The third JFET region 1031 is located on top of the auxiliary well region 1214 and the first JFET region 1014, the bottom surface of the third JFET region 1031 is in contact with the top surface of the auxiliary well region 1214 and the top surface of the first JFET region 1014, respectively, and the sidewalls on both sides of the third JFET region 1031 in the length direction of the channel region are in contact with the sidewalls of the channel region away from the source region.

[0103] The first JFET region 1014 has opposite first and second sidewalls 1014a and 1014b arranged in the length direction of the channel region, the first sidewall 1014a is in contact with the sidewall of the main well region 120, and the second sidewall 1014b is in contact with the sidewall of the auxiliary well region 1214. The first and second sidewalls 1014a and 1014b are curved in the same direction, specifically, the second sidewall 1014b is convexly curved towards the auxiliary well region 1214, and the first sidewall 1014a is concavely curved towards the inside of the first JFET region 1014.

[0104] Further, referring to Figure 6 , when the second sidewall 1014b is convexly curved towards the auxiliary well region 1214 and the first sidewall 1014a is concavely curved towards the inside of the first JFET region 1014, the width of the auxiliary well region 1214 increases from the top surface of the auxiliary well region 1214 to the bottom surface of the auxiliary well region 1214. In other embodiments, when the second sidewall is convexly curved towards the auxiliary well region and the first sidewall is concavely curved towards the inside of the first JFET region, the width of the auxiliary well region first decreases and then increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region.

[0105] The other contents about this embodiment are the same as those of Embodiment 1, and will not be described in detail.

[0106] Embodiment 6

[0107] The difference between this embodiment and Embodiment 5 is that the top surface of the auxiliary well region and the top surface of the drift layer are spaced apart from and higher than the bottom surface of the main well region, and the bottom surface of the auxiliary well region is lower than the bottom surface of the main well region.

[0108] The other contents about this embodiment are the same as those of Embodiment 5, and will not be described in detail.

[0109] Embodiment 7

[0110] The difference between this embodiment and Embodiment 1 is that the reference Figure 7 , the JFET region only includes the first JFET region 1015, the first JFET region 1015 has the first side wall 1015a and the second side wall 1015b arranged in the length direction of the channel region and opposite to each other, the first side wall 1015a is in contact with the side wall of the main well region 120, and the second side wall 1015b is in contact with the side wall of the auxiliary well region 1215; the first side wall 1015a and the second side wall 1015b are arranged in the same direction and are curved, specifically, the second side wall 1015b is concavely curved towards the inside of the first JFET region 1015, and the first side wall 1015a is convexly curved towards the main well region 120.

[0111] In this embodiment, the top surface of the auxiliary well region 1215 and part of the top surface of the drift layer 110 coincide, the bottom surface of the auxiliary well region 1215 is flush with the bottom surface of the main well region 120, and the JFET region only includes the first JFET region 1015. It should be noted that in other embodiments, the top surface of the auxiliary well region and part of the top surface of the drift layer coincide, the bottom surface of the auxiliary well region is lower than the bottom surface of the main well region and is spaced apart from the bottom surface of the drift layer, and the JFET region only includes the first JFET region.

[0112] Further, when the second side wall 1015b is concavely curved towards the inside of the first JFET region 1015, and the first side wall 1015a is convexly curved towards the main well region 120, the width of the auxiliary well region 1215 first increases and then decreases from the top surface of the auxiliary well region 1215 to the bottom surface of the auxiliary well region 1215. Further, the width of the top surface of the auxiliary well region is greater than, equal to, or less than the width of the bottom surface of the auxiliary well region.

[0113] Since the first side wall 1015a and the second side wall 1015b are arranged in the same direction, the degree of depletion of the channel region can be reduced when the semiconductor power device works in the reverse blocking state, so that the threshold of the occurrence of the channel region punch-through is reduced, so that the channel region can be made shorter, and the forward resistance of the channel region is reduced. Secondly, the total area of the projection of the auxiliary well region 1215 and the main well region 120 on the semiconductor substrate layer is increased, and the shielding effect of the auxiliary well region 1215 and the main well region 120 on the electric field is enhanced when the semiconductor power device works in the reverse blocking state, the electric field intensity at the position of the gate oxide layer is reduced, the threshold of the breakdown of the gate oxide layer is reduced, and the reverse breakdown voltage is improved.

[0114] Since the first side wall 1015a and the second side wall 1015b are arranged in the same direction, the distance between the first side wall 1015a and the second side wall 1015b can be controlled to be small. The width of the top region of the first JFET region 1015 is small, so that the degree of depletion of the top region of the first JFET region 1015 and the channel region is reduced, and the threshold of the occurrence of the channel region punch-through is reduced.

[0115] The center of the middle region of the first JFET region 1015 extends towards the main well region 120 relative to the bottom region of the first JFET region 1015, so that the line connecting the majority carriers in the drift layer 110 at the bottom of the auxiliary well region 1215 to the direction of the channel region must pass through the auxiliary well region 1215, and the majority carriers in the drift layer 110 at the bottom of the auxiliary well region 1215 are preferentially exhausted in the auxiliary well region 1215 and cannot move to the channel region, avoiding the depletion of the majority carriers in the drift layer 110 at the bottom of the auxiliary well region 1215 and the channel region, and reducing the threshold of the occurrence of the channel region punch-through.

[0116] In the embodiment, the projection of the auxiliary well region 1215 on the surface of the semiconductor substrate layer 100 and the projection of the main well region 120 on the surface of the semiconductor substrate layer 100 have an overlapping region, and the projection of the auxiliary well region 1215 on the surface of the semiconductor substrate layer 100 falls inside the projection of the main well region 120 on the surface of the semiconductor substrate layer 100 at both side edges in the length direction of the channel region. In this way, the shielding effect of the auxiliary well region 1215 and the main well region 120 on the electric field is enhanced when the semiconductor power device works in the reverse blocking state, the electric field intensity at the position of the gate oxide layer is further reduced, the threshold of the breakdown of the gate oxide layer is further reduced, and the reverse breakdown voltage is further improved. In other embodiments, this is not limited.

[0117] Further, when the projection of the auxiliary well region 1215 on the surface of the semiconductor substrate layer 100 and the projection of the main well region 120 on the surface of the semiconductor substrate layer 100 have an overlapping region, the width of the overlapping region is 0.1 μιη to 1 μιη, such as 0.1 μιη, 0.2 μιη, 0.3 μιη, 0.4 μιη, 0.5 μιη, 0.6 μιη, 0.7 μιη, 0.8 μιη, 0.9 μιη, or 1 μιη. The width of the overlapping region is further to enhance the shielding effect of the auxiliary well region 1215 and the main well region 120 together on the electric field when the semiconductor power device is working in the reverse blocking state. If the width of the overlapping region is greater than 1 μιη, the current path is too long when the device is working in the forward conducting state, and the forward conducting resistance is affected. The width direction of the overlapping region is parallel to the length direction of the channel region.

[0118] In one embodiment, the lateral distance between the first sidewall 1015a and the second sidewall 1015b fluctuates less than or equal to 0.3 μιη from top to bottom, such as 0.3 μιη, 0.2 μιη, 0.1 μιη, 0.05 μιη, or 0 μιη. In a specific embodiment, the first sidewall 1015a and the second sidewall 1015b are parallel.

[0119] In one embodiment, the lateral distance between the first sidewall 1015a and the second sidewall 1015b is 0.05 μιη to 1 μιη, such as 0.05 μιη, 0.08 μιη, 0.1 μιη, 0.2 μιη, 0.3 μιη, 0.4 μιη, 0.5 μιη, 0.6 μιη, 0.7 μιη, 0.8 μιη, 0.9 μιη, or 1 μιη.

[0120] In one embodiment, the first sidewall 1015a has a bending arc from top to bottom less than π, such as 2π / 3 degrees, π / 2, π / 4, or π / 6, and the second sidewall 1015b has a bending arc from top to bottom less than π, such as 2π / 3 degrees, π / 2, π / 4, or π / 6.

[0121] In one embodiment, the length of the channel region is 0.2 μιη to 0.8 μιη, such as 0.2 μιη, 0.3 μιη, 0.4 μιη, 0.5 μιη, or 0.8 μιη.

[0122] The descriptions of the doping concentration of the JFET region, the doping concentration of the main well region 120, the doping concentration of the auxiliary well region 1215, and the doping concentration of the current spreading region 150 refer to Embodiment 1.

[0123] The well regions in the drift layer include the main well region 120, the auxiliary well region 1215, and the connecting well region. The descriptions of the main well region 120, the auxiliary well region 1215, and the connecting well region refer to Embodiment 1, and are not repeated here.

[0124] The same as other contents of Embodiment 1 in this embodiment, refer to Embodiment 1, and no longer detailed.

[0125] Embodiment 8

[0126] The difference between this embodiment and Embodiment 7 is that the top surface of the auxiliary well region and part of the top surface of the drift layer are coincident, and the bottom surface of the auxiliary well region is higher than the bottom surface of the main well region. The JFET region includes a first JFET region and a second JFET region, the first JFET region is located between the auxiliary well region and the main well region, the first JFET region contacts the sidewall of the channel region away from the source region, the first JFET region has opposite first and second sidewalls arranged in the length direction of the channel region, the first sidewall contacts the sidewall of the main well region, and the second sidewall contacts the sidewall of the auxiliary well region, the first and second sidewalls are arranged in the same direction and are curved, specifically, the second sidewall is curved inwardly toward the inside of the first JFET region, and the first sidewall is curved outwardly toward the main well region; the second JFET region is located at the bottom of the auxiliary well region and the first JFET region, the top surface of the second JFET region contacts the bottom surface of the auxiliary well region and the bottom surface of the first JFET region, respectively, and the sidewalls on both sides of the second JFET region in the length direction of the channel region contact part of the sidewalls of the main well region.

[0127] Further, when the second sidewall is curved inwardly toward the inside of the first JFET region, and the first sidewall is curved outwardly toward the main well region, the width of the auxiliary well region increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region.

[0128] Further, when the second sidewall is curved inwardly toward the inside of the first JFET region, and the first sidewall is curved outwardly toward the main well region, the width of the auxiliary well region first increases and then decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, further, the width of the top surface of the auxiliary well region is less than the width of the bottom surface of the auxiliary well region, and in other embodiments, no limitation is made.

[0129] As for other same contents of Embodiment 7 in this embodiment, refer to Embodiment 7, and no longer detailed.

[0130] Embodiment 9

[0131] The embodiment is different from embodiment 7 in that: the top surface of the auxiliary well region and the top surface of the drift layer are spaced apart and higher than the bottom surface of the main well region, and the bottom surface of the auxiliary well region is higher than the bottom surface of the main well region; the JFET region comprises a first JFET region, a second JFET region and a third JFET region, the first JFET region is located between the auxiliary well region and the main well region, the second JFET region is located at the bottom of the auxiliary well region and the first JFET region, the top surface of the second JFET region is in contact with the bottom surface of the auxiliary well region and the bottom surface of the first JFET region respectively, the sidewalls on both sides of the second JFET region in the length direction of the channel region are in contact with part of the sidewalls of the main well region, and the third JFET region is located at the top of the auxiliary well region and the first JFET region, the bottom surface of the third JFET region is in contact with the top surface of the auxiliary well region and the top surface of the first JFET region respectively, and the sidewalls on both sides of the third JFET region in the length direction of the channel region are in contact with the sidewalls of the channel region away from the source region.

[0132] The first JFET region has first and second opposite sidewalls arranged in the length direction of the channel region, the first sidewall is in contact with the sidewall of the main well region, and the second sidewall is in contact with the sidewall of the auxiliary well region. The first and second sidewalls are arranged in the same direction and are curved, specifically, the second sidewall is concavely curved towards the inside of the first JFET region, and the first sidewall is convexly curved towards the main well region.

[0133] When the second sidewall is concavely curved towards the inside of the first JFET region and the first sidewall is convexly curved towards the main well region, the width of the auxiliary well region first increases and then decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, further, the width of the top surface of the auxiliary well region is greater than, equal to or less than the width of the bottom surface of the auxiliary well region; or when the second sidewall is concavely curved towards the inside of the first JFET region and the first sidewall is convexly curved towards the main well region, the width of the auxiliary well region decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region.

[0134] The same content as embodiment 7 is not described in detail.

[0135] Embodiment 10

[0136] The embodiment is different from embodiment 7 in that the top surface of the auxiliary well region and the top surface of the drift layer are spaced apart from and higher than the bottom surface of the main well region, and the bottom surface of the auxiliary well region is flush with or lower than the bottom surface of the main well region. The JFET region includes a first JFET region and a third JFET region, the first JFET region is located between the auxiliary well region and the main well region, and the third JFET region is located on top of the auxiliary well region and the first JFET region, the bottom surface of the third JFET region is in contact with the top surface of the auxiliary well region and the top surface of the first JFET region respectively, and the sidewalls of the third JFET region on both sides of the channel region in the length direction of the channel region are in contact with the sidewalls of the channel region away from the source region.

[0137] The first JFET region has first and second opposite sidewalls arranged in the length direction of the channel region, the first sidewall is in contact with the sidewall of the main well region, and the second sidewall is in contact with the sidewall of the auxiliary well region; the first and second sidewalls are arranged in the same direction. Specifically, the second sidewall is concavely arranged towards the inside of the first JFET region, and the first sidewall is convexly arranged towards the main well region.

[0138] When the second sidewall is concavely arranged towards the inside of the first JFET region, and the first sidewall is convexly arranged towards the main well region, the width of the auxiliary well region decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region first increases and then decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region.

[0139] The same content as embodiment 7 is not described in detail.

[0140] Embodiment 11

[0141] The embodiment provides a semiconductor power device manufacturing method, comprising the following steps: providing a semiconductor substrate layer; forming a drift layer on the semiconductor substrate layer; forming an auxiliary well region in the drift layer, the auxiliary well region being opposite in conductive type to the drift layer; forming a plurality of main well regions in the drift layer, the main well regions being opposite in conductive type to the drift layer, and the auxiliary well region being located between and spaced from the main well regions; forming a source region in the main well region; the main well region having a channel region in a top region of the main well region, the channel region being adjacent to a sidewall of the source region; the drift layer between the adjacent main well regions having a JFET region, the JFET region being in contact with the sidewall of the channel region away from the source region, the JFET region being opposite in conductive type to the main well region, and the JFET region comprising a first JFET region located between the auxiliary well region and the main well region; the first JFET region having first and second opposite sidewalls arranged in a length direction of the channel region, the first sidewall being in contact with a sidewall of the main well region, and the second sidewall being in contact with a sidewall of the auxiliary well region; and the first and second sidewalls being arranged in the same direction.

[0142] In one embodiment, the steps of forming the auxiliary well region, the main well region and the JFET region comprise: performing a first ion implantation on the drift layer to form a first doped region in the drift layer, the first doped region being opposite in conductive type to the drift layer; forming a first mask layer on a top surface of the drift layer, the first mask layer being located above part of the first doped region; performing a second ion implantation on the drift layer with the first mask layer as a mask to form a second doped region in the drift layer on both sides of the first mask layer in the length direction of the channel region, the second doped region also extending to part of a bottom of the first mask layer, and the first doped region located at the bottom of the first mask layer and between the second doped regions forming the auxiliary well region, the second doped region being opposite in conductive type to the auxiliary well region; forming a first sidewall on both sides of the first mask layer arranged in the length direction of the channel region; and performing a third ion implantation on the second doped region with the first sidewall and the first mask layer as a mask to form the main well region in the drift layer on both sides of the first sidewall and the first mask layer in the length direction of the channel region, the main well region also extending to part of the bottom of the first sidewall, and the JFET region being formed in the drift layer at the bottom of the first sidewall and the first mask layer and between the adjacent main well regions, the second doped region between the main well region and the auxiliary well region forming the first JFET region; and removing the first mask layer and the first sidewall.

[0143] Reference will be made to the following Figures 8 to 17 The manufacturing process of the semiconductor power device in the embodiment is described in detail.

[0144] Reference is made to Figure 8providing a semiconductor substrate layer 100; forming a drift layer 110 on the semiconductor substrate layer 100.

[0145] Referring to Figure 9 and Figure 10 , Figure 9 to provide a schematic diagram, Figure 8 Figure 10 is a top view of Figure 9 , a first ion implantation is performed on the drift layer 110 without a mask, and a first doped region C1 is formed in the drift layer 110, the first doped region C1 having a conductive type opposite to that of the drift layer 110.

[0146] In this embodiment, a current spreading region 150 is also formed in the drift layer 110, the current spreading region 150 being located at the bottom of the first doped region C1 and in contact with the bottom surface of the first doped region C1. The current spreading region 150 has the same conductive type as the drift layer 110, and has a doping concentration greater than that of the drift layer 110.

[0147] In one embodiment, the first doped region C1 is formed after the current spreading region 150 is formed, or the current spreading region 150 is formed after the first doped region C1 is formed. In other embodiments, the current spreading region is not formed.

[0148] In one embodiment, the implantation direction of the first ion implantation is perpendicular to the top surface of the drift layer 110.

[0149] Referring to Figure 11 and Figure 12 , Figure 11 to provide a schematic diagram, Figure 9 Figure 12 to provide a schematic diagram, Figure 10 Figure 12 is a top view of Figure 11 , a first mask layer Y1 is formed on the top surface of the drift layer 110, the first mask layer Y1 being located above part of the first doped region C1; a second ion implantation is performed on the drift layer with the first mask layer Y1 as a mask, and a second doped region C2 is formed in the drift layer 110 on both sides of the first mask layer Y1 along the length direction of the channel region, the second doped region C2 also extending to part of the bottom of the first mask layer Y1, and the first doped region C1 located at the bottom of the first mask layer Y1 and between the second doped regions C2 forming an auxiliary well region 121, the second doped region C2 having a conductive type opposite to that of the auxiliary well region 121.

[0150] ​​​The first doped region C1 in the drift layer 110 on both sides of the first mask layer Y1 along the length direction of the channel region and the partial first doped region C1 at the bottom of the first mask layer Y1 are formed into the second doped region C2 after the second ion implantation.

[0151] The second ion implantation is an oblique ion implantation, and the volume size of the second doped region C2 extending to the bottom region of the first mask layer Y1 is controlled by adjusting the implantation angle of the second ion implantation, so that the subsequent bending degree of the second sidewall is controlled.

[0152] In one embodiment, the implantation concentration of the region implanted by the second ion implantation increases first and then decreases from bottom to top.

[0153] Reference Figure 13 and Figure 14 , Figure 13 is a schematic view based on Figure 11 , and Figure 14 is a schematic view based on Figure 12 , and Figure 14 is a top view of Figure 13 , the two side walls of the first mask layer Y1 arranged along the length direction of the channel region form the first side wall Y2; the second doped region C2 is subjected to the third ion implantation with the first side wall Y2 and the first mask layer Y1 as masks, the main well region 120 is formed in the drift layer 110 on both sides of the first side wall Y2 and the first mask layer Y1 along the length direction of the channel region, the main well region 120 also extends to the partial bottom of the first side wall Y2, and the JFET region is formed in the drift layer 110 at the bottom of the first side wall Y2 and the first mask layer Y1 and between the adjacent main well regions 120, and the second doped region C2 between the main well region 120 and the auxiliary well region 121 constitutes the first JFET region 101.

[0154] The second doped region C2 in the drift layer 110 on both sides of the first side wall Y2 and the first mask layer Y1 along the length direction of the channel region and the partial second doped region C2 at the bottom of the first side wall Y2 are formed into the main well region 120 after the third ion implantation.

[0155] The third ion implantation is an oblique ion implantation, and the volume size of the main well region 120 extending to the bottom region of the first side wall Y2 is controlled by adjusting the implantation angle of the third ion implantation, so that the subsequent bending degree of the first sidewall is controlled.

[0156] Specifically, the second doped region C2 in the drift layer 110 on both sides of the first side wall Y2 and the first mask layer Y1 along the first direction is formed into the junction well region J1 after the third ion implantation. The first direction is perpendicular to the length direction of the channel region and parallel to the upper surface of the semiconductor substrate layer.

[0157] In this embodiment, the morphology of the auxiliary well region 121 and the JFET can be jointly controlled by the second and third ion implantations. The morphology of the auxiliary well region and the JFET achieves self-alignment, and the width of the first JFET region can be significantly reduced.

[0158] In one embodiment, the implantation concentration in the region implanted by the third ion implantation first increases and then decreases from bottom to top.

[0159] refer to Figure 15 and Figure 16 , Figure 15 for Figure 13 A basic diagram. Figure 16 for Figure 14 A basic diagram. Figure 16 for Figure 15 The top view, with the first mask layer Y1 and the first sidewall Y2 removed.

[0160] refer to Figure 17 , Figure 17 In order to be in Figure 15 Based on the schematic diagram, a source region 130 is formed in the main well region 120; an ohmic contact region 140 is formed in the main well region 120, which contacts the source region 130; a gate structure 180 is formed, which is located above the auxiliary well region 121 and the JFET region and spans a portion of the source region 130 and the channel region on both sides of the auxiliary well region 121; an isolation dielectric layer 190 is formed, which surrounds the side surface and top surface of the gate electrode layer 182; a front electrode 170 is formed, which contacts the source region 130, and further, the front electrode 170 also contacts the ohmic contact region 140; and a drain region 160 is formed on the side surface of the semiconductor substrate layer 100 opposite to the drift layer 110.

[0161] The gate structure 180 includes a gate oxide layer 181 and a gate electrode layer 182, with the gate electrode layer 182 located on the gate oxide layer 181. The gate oxide layer 181 is made of silicon oxide, and the gate electrode layer 182 is made of polysilicon. The width direction of the gate structure 180 is parallel to the length direction of the channel region. The front electrode 170 covers the gate structure 180, and an isolation dielectric layer 190 isolates the front electrode 170 and the gate electrode layer 182. The isolation dielectric layer 190 is made of silicon oxide.

[0162] Example 12

[0163] The difference between this embodiment and embodiment 11 is that the top surface of the first doped region formed by the first ion implantation is spaced from the top surface of the drift layer, and the first doped region and part of the drift layer on both sides of the channel region in the length direction of the channel region, and the part of the first doped region and the part of the drift layer at the bottom of the first mask layer are formed into the second doped region after the second ion implantation. After the third ion implantation, the drift layer at the top of the auxiliary well region and between adjacent main well regions constitutes the third JFET region.

[0164] Embodiment 13

[0165] The difference between this embodiment and embodiment 11 is that the bottom surface of the second doped region is lower than the bottom surface of the first doped region by controlling the implantation depth of the second ion implantation. After the third ion implantation, the drift region at the bottom of the auxiliary well region and between adjacent main well regions constitutes the second JFET region.

[0166] Embodiment 14

[0167] The difference between this embodiment and embodiment 11 is that the top surface of the first doped region formed by the first ion implantation is spaced from the top surface of the drift layer, and the first doped region and part of the drift layer on both sides of the channel region in the length direction of the channel region, and the part of the first doped region and the part of the drift layer at the bottom of the first mask layer are formed into the second doped region after the second ion implantation. After the third ion implantation, the drift layer at the top of the auxiliary well region and between adjacent main well regions constitutes the third JFET region. The bottom surface of the second doped region is lower than the bottom surface of the first doped region by controlling the implantation depth of the second ion implantation. After the third ion implantation, the drift region at the bottom of the auxiliary well region and between adjacent main well regions constitutes the second JFET region.

[0168] Embodiment 15

[0169] The difference between this embodiment and Embodiment 11 is that the steps for forming the auxiliary well region, main well region, and JFET region include: performing a maskless first ion implantation on the drift layer to form a first doped region in the drift layer, the conductivity type of the first doped region being opposite to that of the drift layer; forming a second mask layer on the top surface of the drift layer, the second mask layer having a mask opening located above a portion of the first doped region; performing a fourth ion implantation on the drift layer at the bottom of the mask opening using the second mask layer as a mask, forming a third doped region in the drift layer at the bottom of the mask opening, the third doped region also extending to a portion of the bottom of the second mask layer, and being located at the bottom of the second mask layer. The first doped regions located on both sides of the third doped region along the length of the channel region constitute the main well region, and the conductivity type of the third doped region is opposite to that of the main well region; the two sidewalls arranged along the length of the channel region of the mask opening form the second sidewalls; the third doped region is implanted with the second sidewalls and the second mask layer as masks to form the third doped region, and the auxiliary well region is formed in the drift layer at the bottom of the mask opening. The auxiliary well region also extends to part of the bottom of the second sidewall and forms the JFET region in the drift layer between the adjacent main well regions. The third doped region located between the main well region and the auxiliary well region constitutes the first JFET region; the second mask layer and the second sidewall are removed.

[0170] refer to Figure 18 and Figure 19 , Figure 18 In order to be in Figure 9 A basic diagram. Figure 19 This is a diagram based on 10. Figure 19 for Figure 18 A top view shows that a second mask layer Y3 is formed on the top surface of the drift layer 110, and the second mask layer Y3 has a mask opening located above a portion of the first doped region C1; using the second mask layer Y3 as a mask, a fourth ion implantation is performed on the drift layer 110 at the bottom of the mask opening, forming a third doped region C3 in the drift layer 110 at the bottom of the mask opening, and the third doped region C3 also extends to a portion of the bottom of the second mask layer Y3, and the first doped regions C1 located at the bottom of the second mask layer Y3 and on both sides of the third doped region Y3 along the length direction of the channel region constitute the main well region 120, and the conductivity type of the third doped region C3 is opposite to the conductivity type of the main well region 120.

[0171] In this embodiment, the first doped region C1 at the bottom of the mask opening and a portion of the first doped region C1 at the bottom of the first mask layer Y1 and the second mask layer Y3 are implanted with fourth ions to form the third doped region C3.

[0172] The fourth ion implantation is an oblique ion implantation. The implantation angle of the fourth ion implantation is adjusted so that the third doped region C3 extends to the volume size of the bottom region of the second mask layer Y3, and the subsequent bending degree of the second sidewall is controlled.

[0173] In one embodiment, the injection concentration of the region injected by the fourth ion implantation increases first and then decreases from bottom to top.

[0174] Reference is made to Figure 20 and Figure 21 , Figure 20 is a schematic view based on Figure 18 , Figure 21 is a schematic view based on 19, Figure 21 is a top view of Figure 20 , the two side walls arranged along the length direction of the channel region form the second side wall Y4; the third doped region C3 is subjected to a fifth ion implantation with the second side wall Y4 and the second mask layer Y3 as masks, an auxiliary well region 1215 is formed in the drift layer 110 at the bottom of the mask opening, the auxiliary well region 1215 also extends to part of the bottom of the second side wall Y4, and a JFET region is formed in the drift layer 110 between adjacent main well regions 120, the third doped region C3 between the main well region 120 and the auxiliary well region 1215 constitutes a first JFET region 1015.

[0175] In the embodiment, the third doped region C3 at the bottom of the mask opening, the second mask layer Y3, the second side wall Y4 and part of the third doped region C3 at the bottom are formed into the auxiliary well region 1215 after the fifth ion implantation.

[0176] The fifth ion implantation is an oblique ion implantation. The implantation angle of the fifth ion implantation is adjusted so that the auxiliary well region 1215 extends to the volume size of the bottom region of the first side wall Y2, and the subsequent bending degree of the second sidewall is controlled.

[0177] In one embodiment, the injection concentration of the region injected by the fifth ion implantation increases first and then decreases from bottom to top.

[0178] Specifically, the first doped region C1 in the drift layer 110 at the bottom of the second mask layer Y3 and on both sides of the second side wall Y4 and the second mask layer Y3 along a first direction constitutes a junction well region J1. The first direction is perpendicular to the length direction of the channel region and parallel to the upper surface of the semiconductor substrate layer.

[0179] Reference is made to Figure 22 and Figure 23 , Figure 22 is a schematic view based on Figure 20 , Figure 23 is a schematic view based on 21, Figure 23 is a top view of Figure 22A top view showing the removal of the second mask layer Y3 and the second sidewall Y4.

[0180] refer to Figure 24 , Figure 24 In order to be in Figure 22 Based on the schematic diagram, a source region 130 is formed in the main well region 120; an ohmic contact region 140 is formed in the main well region 120, which contacts the source region 130; a gate structure 180 is formed, which is located above the auxiliary well region 121 and the JFET region and spans a portion of the source region 130 and the channel region on both sides of the auxiliary well region 121; an isolation dielectric layer 190 is formed, which surrounds the side surface and top surface of the gate electrode layer 182; a front electrode 170 is formed, which contacts the source region 130, and further, the front electrode 170 also contacts the ohmic contact region 140; and a drain region 160 is formed on the side surface of the semiconductor substrate layer 100 opposite to the drift layer 110.

[0181] Example 16

[0182] The difference between this embodiment and embodiment 15 is that the implantation depth of the fourth ion implantation is controlled so that the top surface of the third doped region formed by the fourth ion implantation is spaced apart from the top surface of the drift layer. The part of the first doped region at the bottom of the mask opening and the part of the first doped region at the bottom of the first mask layer and the second mask layer are formed into the third doped region after being implanted by the fourth ion. After the fifth ion implantation, the third doped region located at the top of the auxiliary well region and located between the adjacent main well regions constitutes the third JFET region.

[0183] Example 17

[0184] The difference between this embodiment and embodiment 15 is that the implantation depth of the fourth ion implantation is controlled so that the bottom surface of the third doped region is lower than the bottom surface of the first doped region; after the fifth ion implantation, the drift layer located at the bottom of the auxiliary well region and between the adjacent main well regions constitutes the second JFET region.

[0185] Example 18

[0186] The difference between the embodiment and the embodiment 15 is that the implant depth of the fourth ion implantation is controlled so that the top surface of the third doped region formed by the fourth ion implantation is spaced from the top surface of the drift layer, and the portion of the first doped region at the bottom of the mask opening and the portion of the first doped region at the bottom of the first mask layer and the second mask layer are formed into the third doped region after the fourth ion implantation; and the third doped region located at the top of the auxiliary well region and between the adjacent main well regions constitutes the third JFET region after the fifth ion implantation. The implant depth of the fourth ion implantation is controlled so that the bottom surface of the third doped region is lower than the bottom surface of the first doped region; and the drift layer located at the bottom of the auxiliary well region and between the adjacent main well regions constitutes the second JFET region after the fifth ion implantation.

[0187] Obviously, the above-mentioned embodiments are only examples for clearly illustrating the present application, but not limitation on the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments are not required to be enumerated. The changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. A semiconductor power device, characterized by, The semiconductor power device comprises: a semiconductor substrate layer; a drift layer on the semiconductor substrate layer; a plurality of main well regions arranged in the drift layer, the main well regions having a conductivity type opposite to that of the drift layer; a source region in the main well region, the main well region having a channel region in a top region thereof, the channel region being adjacent to a sidewall of the source region; an auxiliary well region and a JFET region in the drift layer between adjacent main well regions, the auxiliary well region being spaced apart from the main well region, the auxiliary well region having a conductivity type same as that of the main well region, the JFET region being in contact with the channel region away from the sidewall of the source region, the JFET region having a conductivity type opposite to that of the main well region, the JFET region comprising a first JFET region between the auxiliary well region and the main well region, the first JFET region having first and second opposite sidewalls arranged in a length direction of the channel region, the first sidewall being in contact with the sidewall of the main well region, the second sidewall being in contact with the sidewall of the auxiliary well region, the first and second sidewalls being arranged in a same direction and being curved.

2. The semiconductor power device of claim 1, wherein, The second sidewall is curved convexly towards the auxiliary well region, and the first sidewall is curved concavely towards an inner portion of the first JFET region.

3. The semiconductor power device of claim 1, wherein, The second sidewall is curved concavely towards an inner portion of the first JFET region, and the first sidewall is curved convexly towards the main well region.

4. The semiconductor power device of claim 1, wherein, A top surface of the auxiliary well region coincides with a part of a top surface of the drift layer, and a bottom surface of the auxiliary well region is higher than a bottom surface of the main well region. The first JFET region is in contact with the channel region away from the sidewall of the source region. The semiconductor power device further comprises a second JFET region at a bottom of the auxiliary well region and the first JFET region, a top surface of the second JFET region being in contact with a bottom surface of the auxiliary well region and a bottom surface of the first JFET region respectively, and sidewalls of the second JFET region on both sides in the length direction of the channel region being in contact with part of the sidewalls of the main well region.

5. The semiconductor power device of claim 4, wherein, When the second sidewall is curved convexly towards the auxiliary well region, and the first sidewall is curved concavely towards an inner portion of the first JFET region, a width of the auxiliary well region decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region first decreases and then increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region. When the second sidewall is curved concavely towards an inner portion of the first JFET region, and the first sidewall is curved convexly towards the main well region, the width of the auxiliary well region increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region first increases and then decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region.

6. The semiconductor power device of claim 1, wherein, The top surface of the auxiliary well region coincides with a part of the top surface of the drift layer. The bottom surface of the auxiliary well region is flush with the bottom surface of the main well region, or the bottom surface of the auxiliary well region is lower than the bottom surface of the main well region and is spaced apart from the bottom surface of the drift layer; The JFET region only includes a first JFET region.

7. The semiconductor power device of claim 6, wherein, When the second sidewall is convexly curved towards the auxiliary well region and the first sidewall is concavely curved towards the inside of the first JFET region, the width of the auxiliary well region first decreases and then increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region. When the second sidewall is concavely curved towards the inside of the first JFET region and the first sidewall is convexly curved towards the main well region, the width of the auxiliary well region first increases and then decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region.

8. The semiconductor power device of claim 1, wherein, The top surface of the auxiliary well region is spaced apart from the top surface of the drift layer and is higher than the bottom surface of the main well region, and the bottom surface of the auxiliary well region is higher than the bottom surface of the main well region. The semiconductor power device further includes: a second JFET region located at the bottom of the auxiliary well region and the first JFET region, the top surface of the second JFET region is in contact with the bottom surface of the auxiliary well region and the bottom surface of the first JFET region respectively, and the sidewalls on both sides of the second JFET region in the length direction of the channel region are in contact with part of the sidewalls of the main well region; and a third JFET region located at the top of the auxiliary well region and the first JFET region, the bottom surface of the third JFET region is in contact with the top surface of the auxiliary well region and the top surface of the first JFET region respectively, and the sidewalls on both sides of the third JFET region in the length direction of the channel region are in contact with the sidewalls of the channel region away from the source region.

9. The semiconductor power device of claim 8, wherein, When the second sidewall is convexly curved towards the auxiliary well region and the first sidewall is concavely curved towards the inside of the first JFET region, the width of the auxiliary well region first decreases and then increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region. When the second sidewall is concavely curved towards the inside of the first JFET region and the first sidewall is convexly curved towards the main well region, the width of the auxiliary well region first increases and then decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region.

10. The semiconductor power device of claim 1, wherein, The top surface of the auxiliary well region and the top surface of the drift layer are spaced apart and higher than the bottom surface of the main well region, and the bottom surface of the auxiliary well region is flush with or lower than the bottom surface of the main well region; the semiconductor power device further comprises: a third JFET region located on top of the auxiliary well region and the first JFET region, the bottom surface of the third JFET region is in contact with the top surface of the auxiliary well region and the top surface of the first JFET region respectively, and the sidewalls of the third JFET region on both sides of the length direction of the channel region are in contact with the sidewalls of the channel region away from the source region.

11. The semiconductor power device of claim 10, wherein, When the second sidewall is arranged as a convex curve towards the auxiliary well region, and the first sidewall is arranged as a concave curve towards the inside of the first JFET region, the width of the auxiliary well region increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region first decreases and then increases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region. When the second sidewall is arranged as a concave curve towards the inside of the first JFET region, and the first sidewall is arranged as a convex curve towards the main well region, the width of the auxiliary well region decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region, or the width of the auxiliary well region first increases and then decreases from the top surface of the auxiliary well region to the bottom surface of the auxiliary well region.

12. The semiconductor power device according to any one of claims 1 to 11, characterized by, The lateral distance between the first sidewall and the second sidewall fluctuates less than or equal to 0.3 μm from top to bottom.

13. The semiconductor power device of claim 12, wherein, The first sidewall and the second sidewall are arranged in parallel.

14. The semiconductor power device of claim 12, wherein, The lateral distance between the first sidewall and the second sidewall is 0.05 μm to 1 μm.

15. The semiconductor power device according to any one of claims 1 to 11, characterized by, The projection of the auxiliary well region on the surface of the semiconductor substrate layer and the projection of the main well region on the surface of the semiconductor substrate layer have an overlapping area, and the projection of the auxiliary well region on the surface of the semiconductor substrate layer falls inside the projection of the main well region on the surface of the semiconductor substrate layer on both sides of the length direction of the channel region.

16. The semiconductor power device of claim 15, wherein, The width of the overlapping area is 0.1 μm to 1 μm.

17. The semiconductor power device of claim 1, wherein, The doping concentration of the JFET region is greater than the doping concentration of the drift layer.

18. The semiconductor power device of claim 17, wherein, The doping concentration of the JFET region is 20 times to 50 times the doping concentration of the drift layer.

19. The semiconductor power device according to any one of claims 1 to 11, characterized by, Further comprising: a connecting well region located on both sides of the main well region, the auxiliary well region and the JFET region in the first direction, the connecting well region is connected with the auxiliary well region, the main well region and the JFET region respectively, and the first direction is perpendicular to the length direction of the channel region and parallel to the upper surface of the semiconductor substrate layer.

20. A method of fabricating a semiconductor power device, characterized by, Comprising: providing a semiconductor substrate layer; forming a drift layer on the semiconductor substrate layer; forming an auxiliary well region in the drift layer, the conduction type of the auxiliary well region being opposite to the conduction type of the drift layer; forming a plurality of main well regions spaced apart in the drift layer, the conduction type of the main well region being opposite to the conduction type of the drift layer; the auxiliary well region is located between adjacent main well regions and is spaced apart from the main well region; forming a source region in the main well region; the main well region has a channel region in the top region, and the channel region is adjacent to the sidewall of the source region; The drift layer between adjacent main well regions has a JFET region, which contacts the sidewall of the channel region away from the source region, the conductivity type of the JFET region is opposite to that of the main well region, the JFET region includes a first JFET region between the auxiliary well region and the main well region; the first JFET region has first and second opposite sidewalls arranged in the length direction of the channel region, the first sidewall contacts the sidewall of the main well region, and the second sidewall contacts the sidewall of the auxiliary well region; the first and second sidewalls are arranged in the same direction.

21. The method of manufacturing a semiconductor power device according to claim 20, wherein The steps of forming the auxiliary well region, the main well region and the JFET region include: performing a first ion implantation on the drift layer without a mask to form a first doped region in the drift layer, the conductivity type of the first doped region being opposite to that of the drift layer; forming a first mask layer on the top surface of the drift layer, the first mask layer being located above part of the first doped region; performing a second ion implantation on the drift layer with the first mask layer as a mask to form a second doped region in the drift layer on both sides of the first mask layer in the length direction of the channel region, the second doped region also extending to part of the bottom of the first mask layer, and the first doped region located at the bottom of the first mask layer and between the second doped regions forming the auxiliary well region, the conductivity type of the second doped region being opposite to that of the auxiliary well region; forming a first sidewall on the two sidewalls of the first mask layer arranged in the length direction of the channel region; performing a third ion implantation on the second doped region with the first sidewall and the first mask layer as a mask to form a main well region in the drift layer on both sides of the first sidewall and the first mask layer in the length direction of the channel region, the main well region also extending to part of the bottom of the first sidewall, and a JFET region being formed in the drift layer at the bottom of the first sidewall and the first mask layer and between adjacent main well regions, the second doped region between the main well region and the auxiliary well region forming a first JFET region; removing the first mask layer and the first sidewall.

22. The method of manufacturing a semiconductor power device according to claim 20, wherein The step of forming the auxiliary well region, the main well region and the JFET region comprises: performing a first ion implantation on the drift layer without a mask to form first doped regions in the drift layer, the first doped regions being of an opposite conductivity type to that of the drift layer; forming a second mask layer on a top surface of the drift layer, the second mask layer having a mask opening above part of the first doped regions; performing a fourth ion implantation on the drift layer at the bottom of the mask opening with the second mask layer as a mask to form third doped regions in the drift layer at the bottom of the mask opening, the third doped regions also extending to part of the bottom of the second mask layer, and the first doped regions located at the bottom of the second mask layer and on both sides of the third doped regions along the length direction of the channel region forming the main well region, the third doped regions being of an opposite conductivity type to that of the main well region; forming second side walls on both side walls of the mask opening arranged along the length direction of the channel region; performing a fifth ion implantation on the third doped regions with the second side walls and the second mask layer as masks to form an auxiliary well region in the drift layer at the bottom of the mask opening, the auxiliary well region also extending to part of the bottom of the second side walls, and a JFET region in the drift layer between adjacent main well regions, the third doped regions between the main well region and the auxiliary well region forming a first JFET region; and removing the second mask layer and the second side walls.

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