Single-channel cellular structure and layout structure of integrated junction barrier Schottky diode

Abstract

The invention provides a single-channel cellular structure and layout structure of an integrated junction barrier Schottky diode. The single-channel cellular structure comprises a substrate; the first conductive type epitaxial region is arranged on the front surface of the substrate; the second conductive type body region is formed in a partial region of one side, deviating from the substrate, of the first conductive type epitaxial region; the first conductive type source region is formed in a partial region of one side, deviating from the substrate, of the second conductive type body region; the plurality of second conductive type source regions are formed on one side, deviating from the substrate, of the second conductive type body region; the JFET region is formed on the side, away from the substrate, of the first conductive type epitaxial region; the oxide layer partially covers the JFET region, the second conductive type body region, the first conductive type source region and the second conductive type source region; the grid electrode is arranged in the oxide layer; a Schottky metal layer covering the bottom of the trench; the source electrode metal layer-covers the Schottky metal layer and fills the groove; and the drain metal layer is arranged on the back surface of the substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a single-channel cell structure and layout structure of an integrated junction barrier Schottky diode. Background Technology

[0002] Silicon carbide (4H-SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) benefit from their wide bandgap material, exhibiting superior critical electric field strength and thermal conductivity compared to conventional silicon-based high-voltage devices such as superjunction MOSFETs. This makes them widely used in high-temperature, high-voltage, and high-frequency applications. However, their wider bandgap results in a forward voltage drop of more than twice that of conventional silicon-based MOSFETs when the body diode is in freewheeling mode, significantly increasing the conduction losses during switching. Furthermore, the bipolar degradation caused by screw dislocations introduced during silicon carbide epitaxy further deteriorates the switching characteristics of SiC MOSFETs, and hole bombardment of the gate oxide during body diode conduction leads to threshold voltage instability. Therefore, in various applications, Schottky barrier diodes (SBDs) are often integrated to optimize switching characteristics.

[0003] However, due to the low barrier provided by conventional SBDs, MOSFET devices are easily integrated at the integrated SBD, so device structure optimization often revolves around protecting the SBD. In addition, the introduction of SBDs will inevitably increase the theoretical minimum cell size of SiC MOSFET devices, leading to an increase in specific on-resistance (Rsp). Summary of the Invention

[0004] This invention provides a single-channel cell structure and layout structure for an integrated junction barrier Schottky diode to solve the technical problem of high on-resistance of traditional devices.

[0005] This invention provides a single-channel cell structure for an integrated junction barrier Schottky diode, comprising:

[0006] A substrate having a front side and a back side disposed opposite to each other; A first conductivity type epitaxial region is disposed on the front side of the substrate; The second conductivity type body region is formed by ion implantation of a portion of the first conductivity type epitaxial region on the side opposite to the substrate. The first conductivity type source region is formed by ion implantation of a portion of the second conductivity type body region on the side opposite to the substrate; Multiple second conductivity type source regions are formed by ion implantation on the side of the second conductivity type body region away from the substrate, and each second conductivity type source region is in contact with the first conductivity type source region; The JFET region is formed by ion implantation from the region of the first conductivity type epitaxial region on the side away from the substrate and which is not the location of the second conductivity type body region. An oxide layer partially covers the JFET region, the second conductivity type body region, the first conductivity type source region, and the second conductivity type source region, to form a trench on the side of the first conductivity type body region facing away from the substrate, such that the JFET region, the second conductivity type body region, the first conductivity type source region, and the second conductivity type source region are partially exposed to the bottom of the trench; A gate electrode is disposed within the oxide layer; A Schottky metal layer covers the bottom of the trench to form a junction barrier Schottky diode with the first conductivity type source region and the second conductivity type source region; A source metal layer that covers the Schottky metal layer and fills the trench; A drain metal layer is disposed on the back side of the substrate.

[0007] In one embodiment of the present invention, the gate and the channel region partially overlap in a direction perpendicular to the front side of the substrate, and the area of ​​the overlapping region is less than a preset area threshold.

[0008] In one embodiment of the present invention, the junction barrier Schottky diode is disposed close to the JFET region.

[0009] In one embodiment of the present invention, the conductive region below the junction barrier Schottky diode in the JFET region is adjacent, and the "below" refers to the direction in which the junction barrier Schottky diode faces the substrate.

[0010] The present invention also provides a layout structure comprising a plurality of single-channel cell structures of the integrated junction barrier Schottky diodes, wherein the single-channel cell structures of each integrated junction barrier Schottky diode are arranged in a non-mirror periodic pattern.

[0011] The present invention also provides a method for manufacturing a single-channel cell structure of the integrated junction barrier Schottky diode, the method comprising: A substrate is provided, the substrate having a front side and a back side disposed opposite to each other; An epitaxial region of a first conductivity type is formed on the front side of the substrate; A second conductivity type body region is formed by ion implantation in a portion of the first conductivity type epitaxial region on the side opposite to the substrate; A first conductivity type source region is formed by ion implantation in a portion of the second conductivity type body region on the side opposite to the substrate; Multiple second conductivity type source regions are formed by ion implantation on the side of the second conductivity type body region away from the substrate, and each second conductivity type source region is in contact with the first conductivity type source region; A JFET region is formed by ion implantation in the region of the first conductivity type epitaxial region that is away from the substrate and is not the location of the second conductivity type body region. An oxide layer is formed, which partially covers the JFET region, the second conductivity type body region, the first conductivity type source region, and the second conductivity type source region. At the same time, a trench is formed on the side of the first conductivity type body region away from the substrate, so that the JFET region, the second conductivity type body region, the first conductivity type source region, and the second conductivity type source region are partially exposed to the bottom of the trench. A gate is formed, wherein the gate is disposed within the oxide layer; A Schottky metal layer is formed, which covers the bottom of the trench; A source metal layer is formed, which covers the Schottky metal layer and fills the trench; A drain metal layer is formed on the back side of the substrate.

[0012] The beneficial effects of this invention are as follows: The single-channel cell structure and layout structure of the integrated junction barrier Schottky diode proposed in this invention can greatly reduce the gate-drain capacitance Cgd by introducing a single channel, thereby reducing device switching losses and preventing gate oxide breakdown caused by the high electric field in the center of the channel region of conventional devices. The body region of the single-channel device occupies a smaller proportion of the unit chip area, resulting in less heat generated per unit area through the body region during UIS testing, thus enhancing its EAS capability. By integrating the junction barrier Schottky diode, the deeper body region can provide secondary protection for the Schottky interface, effectively preventing breakdown of the Schottky barrier and increasing the upper limit of the breakdown voltage of the ideal device design. Through layout optimization, the cell size is reduced while injecting a large number of electrons into the drift region and below the JBS through the channel region when the device is turned on, expanding the electron conduction path and further optimizing the on-resistance of the device. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0014] In the attached diagram: Figure 1 This is a top view schematic diagram of the layout structure corresponding to the single-channel cell structure of an integrated junction barrier Schottky diode provided in an embodiment of the present invention. Figure 2 for Figure 1 A schematic cross-sectional view of the AA' surface of the central layout structure; Figure 3 for Figure 1 A cross-sectional schematic diagram of the BB' surface of the Chinese layout structure; Figure 4 for Figure 1 A cross-sectional schematic diagram of the CC' plane of the Chinese layout structure; Figure 5 This is a schematic flowchart illustrating a method for manufacturing a single-channel cell structure of an integrated junction barrier Schottky diode according to an embodiment of the present invention. Figure 6-12 for Figure 5 The structural schematic diagram obtained from the corresponding steps in the manufacturing method.

[0015] The attached figures are labeled as follows: 1-Substrate; 2-Epipolar region of first conductivity type; 3-Bulk region of second conductivity type; 4-Source region of first conductivity type; 5-Source region of second conductivity type; 6-JFET region; 7-Oxide layer; 8-Gate; 9-Schottky metal layer; 10-Source metal layer; 11-Drain metal layer. Detailed Implementation

[0016] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0017] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0018] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0019] Please see Figure 1 , Figure 1 This is a top view schematic diagram of the layout structure corresponding to the single-channel cell structure of an integrated junction barrier Schottky diode provided in an embodiment of the present invention. The layout structure includes multiple single-channel cell structures of integrated junction barrier Schottky diodes, and each single-channel cell structure of the integrated junction barrier Schottky diode adopts a non-mirror periodic arrangement, that is, based on the translation or rotation of individual cells, a layout structure covering the entire layout without repetition or symmetry is formed. Each cell structure contains at least two second conductivity type source regions 5, which are in contact with a first conductivity type source region 4. A Schottky metal layer 9 (not shown in the figure) is also covered on the second conductivity type source regions 5 and the first conductivity type source regions 4, so that the first conductivity type source region 4, the second conductivity type source region 5, and the Schottky metal layer 9 constitute a junction barrier Schottky diode. Figure 1 As shown, since the two second conductivity type source regions 5 are aligned, by fabricating a suitable Schottky metal layer 9, the Schottky metal layer 9 can simultaneously contact the second conductivity type source region 5, the second conductivity type body region 3, the first conductivity type source region 4, and the channel region 6. The specific dimensions of the Schottky metal layer can be set and adjusted according to actual application requirements.

[0020] Please see Figure 2-4 , Figure 2 for Figure 1 A cross-sectional schematic diagram of the AA' surface of the Chinese layout structure. Figure 3 for Figure 1 A cross-sectional schematic diagram of the BB' surface of the Chinese layout structure. Figure 4 for Figure 1A cross-sectional schematic diagram of the CC' plane of the cellular structure. This cell structure includes: a substrate 1 having a front side and a back side disposed opposite to each other; a first conductivity type epitaxial region 2 disposed on the front side of the substrate 1; a second conductivity type body region 3 formed by ion implantation of a portion of the first conductivity type epitaxial region 2 away from the substrate 1; a first conductivity type source region 4 formed by ion implantation of a portion of the second conductivity type body region 3 away from the substrate 1; a plurality of second conductivity type source regions 5 formed by ion implantation of the second conductivity type body region 3 away from the substrate 1, and each second conductivity type source region 5 contacting the first conductivity type source region 4 to form a junction barrier Schottky diode; and a JFET region 6 formed by ion implantation of the first conductivity type epitaxial region 2 away from the substrate 1. A region on one side of substrate 1, excluding the second conductivity type body region 3, is formed by ion implantation. An oxide layer 7 partially covers the JFET region 6, the second conductivity type body region 3, the first conductivity type source region 4, and the second conductivity type source region 5, forming a trench on the side of the first conductivity type body region away from the substrate 1, such that the JFET region 6, the second conductivity type body region 3, the first conductivity type source region 4, and the second conductivity type source region 5 are partially exposed to the bottom of the trench. A gate 8 is disposed within the oxide layer 7. A Schottky metal layer 9 covers the bottom of the trench. A source metal layer 10 covers the Schottky metal layer 9 and fills the trench. A drain metal layer 11 is disposed on the back side of substrate 1. Specifically, the first conductivity type epitaxial region 2 is made of doped silicon carbide. The second conductivity type body region 3 is formed in the entire region outside the first conductivity type by high-temperature ion implantation (exemplarily, aluminum ions can be implanted). A first conductivity type source region 4 is formed within the second conductivity type body region 3 by high-temperature donor ion implantation (exemplarily, nitrogen ions may be implanted). A second conductivity type source region 5 is formed within the second conductivity type body region 3 by acceptor ion implantation (exemplarily, aluminum ions may be implanted). The top-view structure of the cell formed by ion implantation is as follows. Figure 1As shown. Further, a thin oxide protective layer can be deposited on top of the first conductivity type source region 4 and the second conductivity type source region 5. Then, ion implantation (e.g., nitrogen ion implantation) is performed on the first conductivity type epitaxial region 2 to form a JEFT region (i.e., JFET region 6), and the channel region is thermally activated by high-temperature annealing. Further, a hot gate oxide layer 7 is formed by thermal growth, and a gate 8 trench is formed. Polysilicon is deposited on the gate 8 trench, and the gate 8 is formed by etching. Passivation is then performed on the gate 8 trench to form an inter-gate-source dielectric layer. This hot gate oxide layer 7 and the inter-gate-source dielectric layer together constitute the aforementioned oxide layer 7. Trenches or openings can be formed on the inter-gate-source dielectric layer for depositing nickel metal to form a Schottky metal layer 9. This Schottky metal layer 9 can simultaneously form ohmic contacts with the second conductivity type source region 5 and the channel region at high temperatures. A source metal layer 10 is deposited on top of the Schottky metal layer 9 to form the source. This source metal layer 10 can be made of a low-resistivity trace metal, which can be selected according to the actual application requirements and is not limited here. Finally, metal can be deposited on the back side of the substrate 1 to form the drain.

[0021] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. The first conductivity type source region 4 can be heavily doped to obtain an N+ type source region, and the second conductivity type source region 5 can also be heavily doped to form a P+ type source region. The specific doping concentration can be set and adjusted according to actual application requirements, and is not limited here.

[0022] The above cell structure is the cell structure of a SiC MOSFET device. The gate 8 and the channel region partially overlap in the direction perpendicular to the front side of the substrate 1. The device adopts a single-channel design. Under the same minimum process size, compared with the traditional dual-channel SiC MOSFET device, the overlap area between the polysilicon gate 8 and the N-type JFET region in the device of the present invention is extremely small. For example, the overlap area can be less than 1% of the area of ​​the JFET region. Of course, the specific size of the overlap area can be set and adjusted according to the actual application requirements, and there is no limitation here.

[0023] Please see Figure 5 , Figure 5 This is a schematic flowchart illustrating a method for manufacturing a single-channel cell structure of an integrated junction barrier Schottky diode according to an embodiment of the present invention. The method includes the following steps: Step S500: Provide a substrate 1, the substrate 1 having a front side and a back side disposed opposite to each other; Step S501: A first conductivity type epitaxial region 2 is formed on the front side of the substrate 1; resulting in... Figure 6 The structure shown.

[0024] Step S502: A second conductivity type body region 3 is formed by ion implantation in a portion of the first conductivity type epitaxial region 2 on the side opposite to the substrate 1; resulting in... Figure 7 The structure shown.

[0025] Step S503: In a portion of the second conductivity type body region 3 facing away from the substrate 1, a first conductivity type source region 4 is formed by ion implantation; resulting in... Figure 8 The structure shown.

[0026] Step S504: Ion implantation is performed on the side of the second conductivity type body region 3 facing away from the substrate 1 to form a plurality of second conductivity type source regions 5, and each second conductivity type source region 5 is in contact with the first conductivity type source region 4; thus obtaining... Figure 9 The structure shown.

[0027] Step S505: In the region of the first conductivity type epitaxial region 2 facing away from the substrate 1 and not located in the second conductivity type body region 3, a JFET region 6 is formed by ion implantation; thus obtaining... Figure 10 The structure shown.

[0028] Step S506: An oxide layer 7 is formed, which partially covers the JFET region 6, the second conductivity type body region 3, the first conductivity type source region 4, and the second conductivity type source region 5, to form a trench on the side of the first conductivity type body region away from the substrate 1, such that the JFET region 6, the second conductivity type body region 3, the first conductivity type source region 4, and the second conductivity type source region 5 are partially exposed at the bottom of the trench.

[0029] Step S507: Forming a gate 8, wherein the gate 8 is disposed within the oxide layer 7; specifically, a trench can be formed in the oxide layer 7 and filled with polysilicon, the gate 8 is formed by etching the polysilicon, and then a gate-source isolation layer is formed on the gate 8. This isolation layer can be made of the same material as the oxide layer 7, and forms a connection with the oxide layer 7 as follows: Figure 11 The structure shown.

[0030] Step S508: A Schottky metal layer 9 is formed, which covers the bottom of the trench; Step S509: Form a source metal layer 10, which covers the Schottky metal layer 9 and fills the trench.

[0031] Step S510: A drain metal layer 11 is formed on the back side of the substrate 1 to obtain the following... Figure 12 The structure shown.

[0032] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An integrated junction barrier Schottky diode single channel cell structure, characterized by, The method comprises: providing a substrate having a front side and a back side oppositely arranged; forming a first-conductivity-type epitaxial region on the front side of the substrate; forming a second-conductivity-type body region on a portion of the first-conductivity-type epitaxial region away from the substrate by ion implantation; forming a first-conductivity-type source region on a portion of the second-conductivity-type body region away from the substrate by ion implantation; forming a plurality of second-conductivity-type source regions on the second-conductivity-type body region away from the substrate by ion implantation, and each of the second-conductivity-type source regions is in contact with the first-conductivity-type source region; forming a JFET region on the first-conductivity-type epitaxial region away from the substrate and not on the region where the second-conductivity-type body region is located by ion implantation; forming an oxide layer partially covering the JFET region, the second-conductivity-type body region, the first-conductivity-type source region, and the second-conductivity-type source region to form a trench on a side of the first-conductivity-type body region away from the substrate, so that the JFET region, the second-conductivity-type body region, the first-conductivity-type source region, and the second-conductivity-type source region are partially exposed to the bottom of the trench; forming a gate in the oxide layer; forming a Schottky metal layer covering the bottom of the trench to form a junction barrier Schottky diode with the first-conductivity-type source region and the second-conductivity-type source region; forming a source metal layer covering the Schottky metal layer and filling the trench; forming a drain metal layer on the back side of the substrate.

2. The single-channel cell structure of an integrated JBS diode according to claim 1, wherein The gate and the channel region partially overlap in a direction perpendicular to the front side of the substrate, and the overlapping area is less than a predetermined area threshold.

3. The single-channel cell structure of an integrated JBS diode according to claim 1, wherein The junction barrier Schottky diode is arranged close to the JFET region.

4. The integrated JBS diode single cell structure of claim 1, wherein, The JFET region is adjacent to a conductive region below the junction barrier Schottky diode, and the below is the direction of the junction barrier Schottky diode towards the substrate.

5. A layout structure, characterized by, The method comprises:

6. A method of manufacturing a single-channel cell structure of an integrated junction barrier Schottky diode as claimed in any one of claims 1 to 4, characterized by, providing a substrate having a front side and a back side oppositely arranged; forming a first-conductivity-type epitaxial region on the front side of the substrate; forming a second-conductivity-type body region on a portion of the first-conductivity-type epitaxial region away from the substrate by ion implantation; forming a first-conductivity-type source region on a portion of the second-conductivity-type body region away from the substrate by ion implantation; forming a plurality of second-conductivity-type source regions on the second-conductivity-type body region away from the substrate by ion implantation, and each of the second-conductivity-type source regions is in contact with the first-conductivity-type source region; forming a JFET region on the first-conductivity-type epitaxial region away from the substrate and not on the region where the second-conductivity-type body region is located by ion implantation; ​ An oxide layer is formed, which partially covers the JFET region, the second conductivity type body region, the first conductivity type source region, and the second conductivity type source region. Meanwhile, a trench is formed on the side of the first conductivity type body region away from the substrate, so that the JFET region, the second conductivity type body region, the first conductivity type source region, and the second conductivity type source region are partially exposed at the bottom of the trench. A gate is formed, wherein the gate is disposed within the oxide layer; A Schottky metal layer is formed, which covers the bottom of the trench; A source metal layer is formed, which covers the Schottky metal layer and fills the trench; A drain metal layer is formed on the back side of the substrate.

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