Semiconductor structure and method of fabricating the same

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises: a substrate and semiconductor channels on the substrate, each of the semiconductor channels is used for constituting a first transistor; a plurality of first bit lines, each of the first bit lines is in contact with a first doped region arranged along a first direction; a plurality of first word lines, the first word lines surround the channel region; a gate conductive layer is in contact with a second doped region; a channel layer is arranged on the outer side of the gate conductive layer; a first semiconductor doped layer and a second semiconductor doped layer are arranged on the outer side of the channel layer, the first semiconductor doped layer, the second semiconductor doped layer, the channel layer and the gate conductive layer are used for constituting a second transistor; a second bit line is in contact with one of the first semiconductor doped layer or the second semiconductor doped layer; and a second word line is in contact with the other of the first semiconductor doped layer or the second semiconductor doped layer, so that a new 2T0C DRAM structure can be provided.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for fabricating the same. Background Technology

[0002] With the continuous growth of demand in the semiconductor market, semiconductor memory technology has developed rapidly, especially Dynamic Random Access Memory (DRAM), which occupies the most important position in the memory market. A common DRAM cell consists of a transistor and a capacitor, forming a 1T1C structure. In order to improve cell performance and reduce cell area, it is necessary to fabricate capacitors with large capacitance values ​​per unit area.

[0003] With increasingly stringent requirements for DRAM cell performance and size, 1T1C cells face significant challenges. Research indicates that transistors, under certain dimensions and with appropriate doping, can also store small amounts of charge without requiring any capacitor, as the transistor gate is a natural capacitor. By forming a 2T0C embedded DRAM structure, a structure with two transistors and no capacitor can be fabricated; therefore, it is necessary to provide a novel 2T0C DRAM structure. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for manufacturing the same, and can at least provide a new 2T0C DRAM structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a substrate and a plurality of semiconductor channels arranged at intervals along a first direction and a second direction on the substrate, each semiconductor channel including a first doped region, a channel region, and a second doped region arranged sequentially along a third direction, each semiconductor channel being used to form a first transistor; a plurality of first bit lines extending along the first direction and arranged at intervals along the second direction, the first bit lines being located between the substrate and the semiconductor channels, each first bit line contacting the first doped region arranged along the first direction; a plurality of first word lines extending along the second direction and arranged at intervals along the first direction, the first word lines surrounding the channel region; and a gate conductive layer, the gate conductive layer being connected to the first doped region along the first direction. The second doped region is in contact with the channel region and is located on the side of the second doped region away from the channel region; a channel layer is disposed around the outer side of the gate conductive layer; a first semiconductor doped layer and a second semiconductor doped layer are disposed on the outer side of the channel layer and are spaced apart from each other, the first semiconductor doped layer, the second semiconductor doped layer, the channel layer and the gate conductive layer are used to form a second transistor; a second bit line is electrically connected to one of the first semiconductor doped layer or the second semiconductor doped layer; a second word line is electrically connected to the other of the first semiconductor doped layer or the second semiconductor doped layer.

[0006] In some embodiments, the semiconductor structure further includes: a first gate dielectric layer, the first gate dielectric layer surrounding the surface of the gate conductive layer and contacting the gate conductive layer; a channel layer surrounding the surface of the first gate dielectric layer and contacting the first gate dielectric layer; and a first isolation layer, the first isolation layer surrounding a portion of the surface of the channel layer and contacting the channel layer.

[0007] In some embodiments, the system further includes a second isolation layer located between an adjacent first semiconductor doped layer and an adjacent second semiconductor doped layer.

[0008] In some embodiments, the first isolation layer and the second isolation layer are made of different materials.

[0009] In some embodiments, the channel layer is doped with a first doped ion, the first semiconductor doped layer has a second doped ion, and the ion type of the first doped ion is different from that of the second doped ion.

[0010] In some embodiments, the gate conductive layer and the semiconductor channel are an integral structure.

[0011] In some embodiments, the channel region includes a flat portion and a protruding portion, the protruding portion surrounding the gate conductive layer, the flat portion being connected to the protruding portion, a first semiconductor doped layer being disposed on the outer side of the protruding portion arranged along one of the first direction or the second direction, and contacting and connecting with the top surface of the flat portion, and a second semiconductor doped layer being disposed on the outer side of the protruding portion arranged along the other of the first direction or the second direction, and contacting and connecting with the top surface of the flat portion.

[0012] In some embodiments, in the first direction, the width of the gate conductive layer is smaller than the width of the semiconductor channel in the second doped region.

[0013] In some embodiments, the first semiconductor doped layer is arranged along the first direction, and two adjacent gate conductive layers in the first direction are connected to the same first semiconductor doped layer.

[0014] In some embodiments, the system further includes: a protective layer covering the top surface of the channel layer, a portion of the surface of the first semiconductor doped layer and a portion of the surface of the second semiconductor doped layer; the second bit line passing through the protective layer and contacting one of the first semiconductor doped layer or the second semiconductor doped layer; and the second word line passing through the protective layer and contacting the other of the first semiconductor doped layer or the second semiconductor doped layer.

[0015] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming a plurality of semiconductor channels and gate conductive layers spaced apart along a first direction and a second direction on the substrate, wherein each semiconductor channel includes a first doped region, a channel region, and a second doped region arranged sequentially along a third direction, each semiconductor channel being used to constitute a first transistor, the gate conductive layer being in contact with the second doped region and located on the side of the second doped region away from the channel region; forming a plurality of first bit lines extending along the first direction and spaced apart along the second direction, the first bit lines being located between the substrate and the semiconductor channels, each first bit line being in contact with the first doped region arranged along the first direction; forming a plurality of first bit lines extending along the second direction and spaced apart along the second direction. A first word line extends and is spaced apart along the first direction, the first word line surrounding the channel region; a channel layer is formed, the channel layer surrounding the outer side of the gate conductive layer; a first semiconductor doped layer and a second semiconductor doped layer are formed, the first semiconductor doped layer and the second semiconductor doped layer are disposed on the outer side of the channel layer, and the first semiconductor doped layer and the second semiconductor doped layer are spaced apart, the first semiconductor doped layer, the second semiconductor doped layer, the channel layer and the gate conductive layer are used to constitute a second transistor; a second bit line is formed, the second bit line is contacted and connected to one of the first semiconductor doped layer or the second semiconductor doped layer; a second word line is formed, the second word line is contacted and connected to the other of the first semiconductor doped layer or the second semiconductor doped layer.

[0016] In some embodiments, the method of forming the semiconductor channel and the gate conductive layer includes: forming an initial semiconductor channel located on the substrate and spaced apart along a first direction and a second direction, the initial semiconductor channel including a first doped region, the channel region and a second initial doped region arranged sequentially along the third direction; etching a portion of the second initial doped region to form a second doped region and a gate conductive layer.

[0017] In some embodiments, before forming the channel layer, the method further includes: forming a first gate dielectric layer, the first gate dielectric layer surrounding the surface of the gate conductive layer and contacting the gate conductive layer; after forming the channel layer, the method further includes: forming a first isolation layer, the first isolation layer surrounding the surface of the channel layer and contacting the channel layer.

[0018] In some embodiments, the channel layer includes a flat portion and a protrusion, the protrusion surrounding the gate conductive layer, the flat portion being connected to the protrusion, and a method for forming the first isolation layer including: forming a first initial isolation layer covering the entire surface of the channel layer; etching the first initial isolation layer to expose the top surface of the protrusion and the top surface of the flat portion, leaving the remaining first initial isolation layer as the first isolation layer.

[0019] In some embodiments, the method of forming the first semiconductor doped layer and the second semiconductor doped layer includes: forming an initial doped layer that covers the surfaces of the first isolation layer and the channel layer; etching the initial doped layer to expose the top surfaces of the first isolation layer and the channel layer, leaving the remaining initial doped layer as a doped layer; etching the doped layer to form a groove that exposes a portion of the sidewalls of the first isolation layer and the top surface of the flat portion, leaving the remaining doped layer as the first semiconductor doped layer and the second semiconductor doped layer.

[0020] In some embodiments, the method of etching the doped layer includes: forming a mask layer covering the top surface of the doped layer, the mask layer including a target pattern, the length of the target pattern being equal to the spacing between adjacent first isolation layers in a first direction, and the width of the target pattern being equal to the spacing between adjacent first isolation layers in a second direction; and etching the doped layer using the mask layer as a mask to form the first semiconductor doped layer and the second semiconductor doped layer.

[0021] In some embodiments, the method of etching the doped layer includes: etching the doped layer using a self-aligned process to form an initial groove, the initial groove penetrating the doped layer; and etching the doped layer within the initial groove using an over-etching method to form the groove, the first semiconductor doped layer, and the second semiconductor doped layer.

[0022] In some embodiments, the method further includes forming a second isolation layer located between an adjacent first semiconductor doped layer and an adjacent second semiconductor doped layer.

[0023] The technical solution provided by the embodiments of this disclosure has at least the following advantages: by setting a semiconductor channel to form a first transistor, connecting the first bit line to the first doped region, and surrounding the channel region with a first word line to control the turn-off of the first transistor, and delivering and storing charge to the gate conductive layer of the second transistor, the gate conductive layer can receive charge from the first transistor by contacting the second doped region, and the second transistor is formed by the gate conductive layer, the channel layer, the first semiconductor doped layer and the second semiconductor doped layer to form a 2TOC DRAM structure. By connecting the second bit line to one of the first semiconductor doped layer or the second semiconductor doped layer, and the second word line to the other of the first semiconductor doped layer or the second semiconductor doped layer, the read function of the entire semiconductor structure can be realized. The embodiments of this disclosure reduce the manufacturing difficulty of the entire production process by using transistors instead of capacitors, and the 2TOC DRAM structure provided by the embodiments of this disclosure has a higher integration density. Attached Figure Description

[0024] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A circuit diagram corresponding to a semiconductor structure provided in one embodiment of this disclosure;

[0026] Figure 2 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure;

[0027] Figure 3 A perspective view of a semiconductor structure provided in an embodiment of this disclosure;

[0028] Figure 4 A cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure;

[0029] Figures 5 to 21 This is a schematic diagram of the steps in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure. Detailed Implementation

[0030] As can be seen from the background technology, as the integration density continues to shrink, the process of forming capacitors becomes increasingly difficult.

[0031] This disclosure provides a semiconductor structure and its fabrication method. It achieves read / write functionality by using transistors instead of capacitors. A semiconductor channel is configured to form a first transistor. A first bit line contacts and connects to a first doped region to deliver charge to the gate conductive layer of a second transistor. A first word line surrounds the channel region to control the turn-off of the first transistor. The gate conductive layer contacts the second doped region to receive charge from the first transistor. The gate conductive layer, channel layer, first semiconductor doped layer, and second semiconductor doped layer constitute the second transistor, forming a 2TOC DRAM structure. A second bit line contacts either the first or second semiconductor doped layer, and a second word line contacts the other, enabling the reading function of the entire semiconductor structure.

[0032] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0033] refer to Figure 1 , Figure 1 This is a circuit diagram of a 2TOC DRAM structure provided in an embodiment of the present disclosure. The writing operation principle is as follows: a high voltage is provided to the first word line WWL and the first bit line WBL. The first word line WWL controls the conduction of the first transistor. Charge is provided to the gate of the second transistor through the first bit line WBL. The charge is stored in the gate of the second transistor, completing the writing "1". A high voltage is provided to the first word line WWL and a low voltage is provided to the first bit line WBL. At this time, the charge stored in the gate of the second transistor flows to the first bit line WBL and is discharged through the first bit line WBL. There is no charge in the gate of the second transistor, completing the writing "0". The reading operation principle is as follows: when the gate of the second transistor stores charge, the second transistor can conduct. Current can flow between the second word line RWL and the second bit line RBL, completing the reading "1". When there is no charge in the gate of the second transistor, the second transistor cannot conduct. There is no current between the second word line RWL and the second bit line RBL, completing the reading "0".

[0034] refer to Figures 2 to 4 , Figure 2 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 3 This is a perspective view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 4 An embodiment of this disclosure provides a method for... Figure 3Cross-sectional view along the dashed line.

[0035] Specifically, the semiconductor structure includes: a substrate 100 and a plurality of semiconductor channels 110 arranged at intervals along a first direction X and a second direction Y on the substrate 100. Each semiconductor channel 110 includes a first doped region 111, a channel region 112, and a second doped region 113 arranged sequentially along a third direction Z. Each semiconductor channel 110 is used to form a first transistor; a plurality of first lines 120 extending along the first direction X and arranged at intervals along the second direction Y, the first lines 120 being located between the substrate 100 and the semiconductor channels 110, each first line 120 being in contact with the first doped region 111 arranged along the first direction X; a plurality of first word lines 130 extending along the second direction Y and arranged at intervals along the first direction X, the first word lines 130 surrounding the channel region 112; and a gate conductive layer 140 in contact with the second doped region 113. The second doped region 113 is located on the side away from the channel region 112; the channel layer 150 is disposed around the outer side of the gate conductive layer 140; the first semiconductor doped layer 160 and the second semiconductor doped layer 170 are disposed on the outer side of the channel region 112, and the first semiconductor doped layer 160 and the second semiconductor doped layer 170 are spaced apart, and the first semiconductor doped layer 160, the second semiconductor doped layer 170, the channel layer 150 and the gate conductive layer 140 are used to form the second transistor; the second bit line 180 is electrically connected to one of the first semiconductor doped layer 160 or the second semiconductor doped layer 170; the second word line 190 is electrically connected to the other of the first semiconductor doped layer 160 or the second semiconductor doped layer 170.

[0036] By setting the first doped region 111 of the semiconductor channel 110 as either the source or drain of the first transistor, the channel region 112 as the channel of the first transistor, and the second doped region 113 as either the source or drain of the first transistor, the first word line 130 surrounding the channel region 112 serves as the gate of the first transistor, and the first bit line 120 contacts the first doped region 111. Thus, when the first word line 130 controls the first transistor to turn on, the first bit line 120 can deliver charge to the second doped region 113, thereby transferring the charge to the gate conductive layer 140. The gate conductive layer 140 serves as the gate of the second transistor, the channel layer 150 serves as the channel of the second transistor, and the first semiconductor doped layer 160 and the second semiconductor doped layer 170 serve as the source and drain of the second transistor. The second bit line 180 and the second word line 190 can be used to determine whether the gate of the second transistor stores charge, thereby allowing the signal stored in the semiconductor structure to be read.

[0037] In some embodiments, the substrate 100 may be made of an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material may be silicon or germanium; the crystalline inorganic compound semiconductor material may be silicon carbide, silicon germanide, gallium arsenide, or indium gallium ionide, etc. Furthermore, doping may be performed on the substrate 100.

[0038] Furthermore, if the substrate 100, the first line 120, and the semiconductor channel 110 have the same semiconductor elements, then the semiconductor channel 110 and the first line 120 can be formed using the same film structure, which is composed of semiconductor elements, so that the semiconductor channel 110 and the first line 120 are an integral structure, thereby improving the interface state defects between the semiconductor channel 110 and the first line 120 and improving the performance of the semiconductor structure.

[0039] The semiconductor element may include at least one of silicon, carbon, germanium, arsenic, gallium, and indium. In one example, both the bit line 120 and the semiconductor channel 110 include silicon. In other examples, both the bit line and the semiconductor channel may include germanium, or both may include silicon and germanium, or both may include silicon and carbon, or both may include arsenic and gallium, or both may include gallium and indium.

[0040] Specifically, the material of the first line 120 includes a metal-semiconductor compound. Compared to unmetallized semiconductor materials, metal-semiconductor compounds have relatively low resistivity. Therefore, compared to the semiconductor channel 110, the resistivity of the first line 120 is lower, which helps to reduce the resistance of the first line 120 and the contact resistance between the first line 120 and the first doped region 111, further improving the electrical performance of the semiconductor structure. Furthermore, the resistivity of the first line 120 is also lower than the resistivity of the substrate 100.

[0041] In some embodiments, the first line 120 may be partially made of a metal semiconductor compound. For example, a portion of the first line 120 not covered by the first doped region 111 may be made of a metal semiconductor compound. In other embodiments, the first line 120 may be entirely made of a metal semiconductor compound.

[0042] In some embodiments, the first line 120 may contact the first doped regions 111 arranged along the first direction X. For example, in the illustration, the first line 120 contacts four first doped regions 111 arranged along the first direction X. That is, charge can be delivered to four second transistors through one first line 120. The above correspondence is merely illustrative and can be adjusted according to actual circumstances.

[0043] In some embodiments, the device formed by the semiconductor channel 110 is a junctionless transistor, that is, the dopant ions in the first doped region 111, the channel region 112 and the second doped region 113 are of the same type, for example, the dopant ions are all N-type ions. Furthermore, the dopant ions in the first doped region 111, the channel region 112 and the second doped region 113 can be the same. Here, "junctionless" refers to the absence of a PN junction, meaning that the transistor formed by the semiconductor channel 110 does not have a PN junction. This means the doping concentration of the dopant ions in the first doped region 111, channel region 112, and second doped region 113 is the same. The advantages of this include: firstly, it eliminates the need for additional doping of the first doped region 111 and second doped region 113, thus avoiding the difficulty in controlling the doping process of these regions. This is especially true as transistor sizes shrink further; additional doping of the first doped region 111 and second doped region 113 would make doping concentration control even more challenging. Secondly, since the device is a junctionless transistor, it avoids the use of ultra-steep source-drain concentration gradient doping processes to create ultra-steep PN junctions at the nanoscale. This avoids problems such as threshold voltage drift and increased leakage current caused by abrupt doping changes, and also helps suppress short-channel effects, allowing operation at the nanometer scale. Therefore, it contributes to further improving the integration density and electrical performance of the semiconductor structure. It is understood that the additional doping here refers to doping performed to make the dopant ion type of the first doped region 111 and the second doped region 113 different from the dopant ion type of the channel region 112.

[0044] In some embodiments, the first word line 130 surrounds the channel region 112. The first word line 130 surrounding the channel region 112 can increase the ability of the first word line 130 to control the first transistor. The first word line 130 can control the first transistor to be turned on. That is, the first word line 130 selects the first transistor to be turned on. The first word line 120 delivers or transfers charge to the second transistor. The cooperation between the first word line 130 and the first word line 120 completes the writing process of the semiconductor structure.

[0045] In some embodiments, the semiconductor structure further includes a first insulating layer 200, which fills the spaces between the semiconductor channels 110 to isolate the semiconductor channels 110.

[0046] In some embodiments, the material of the first insulating layer 200 may be silicon oxide, silicon nitride, etc., and may serve as shallow trench isolation (STI) for semiconductor structures.

[0047] In some embodiments, the semiconductor structure further includes a second insulating layer 210, which is located between adjacent first word lines 130 and can be used to isolate adjacent first word lines 130, thereby improving the insulation performance between adjacent first word lines 130 and preventing adjacent first word lines 130 from contacting each other. The second insulating layer 210 can also cover at least a portion of the top surface of the first word lines 130, thereby also protecting the first word lines 130 and improving the reliability of the semiconductor structure.

[0048] In some embodiments, the material of the second insulating layer 210 may be an insulating material such as silicon nitride.

[0049] In some embodiments, the semiconductor structure may further include a second gate dielectric layer 220, which is located between the first word line 130 and the channel region 112, serving as the gate dielectric layer of the first transistor, thereby preventing carriers of the semiconductor channel 110 from flowing directly into the first word line 130.

[0050] In some embodiments, the second gate dielectric layer 220 may be a material such as silicon oxide or germanium oxide.

[0051] In some embodiments, the gate conductive layer 140 is located on the top surface of the semiconductor channel 110 and is in contact with the second doped region 113, thereby receiving charge carriers from the semiconductor channel 110. The gate conductive layer 140 can serve as the gate of the second transistor to realize the storage of charge in the semiconductor structure and to determine whether the second transistor is turned on, thereby determining whether the level state corresponding to the second transistor is "1" or "0".

[0052] In some embodiments, the gate conductive layer 140 can be integral with the semiconductor channel 110. Here, integral structure means that the gate conductive layer 140 is formed in the same process step as the semiconductor channel 110. That is, the semiconductor channel 110 and the gate conductive layer 140 are formed from the same initial film layer through various process steps. By setting the gate conductive layer 140 and the semiconductor channel 110 as integral structure, the tightness of the connection between the gate conductive layer 140 and the semiconductor channel 110 can be improved, the conductivity between the gate conductive layer 140 and the semiconductor channel 110 can be improved, the interface state between the gate conductive layer 140 and the semiconductor channel 110 can be improved, and the performance of the semiconductor structure can be improved.

[0053] In other embodiments, the gate conductive layer 140 and the semiconductor channel 110 may not be an integral structure. The gate conductive layer 140 can be formed according to actual needs, and the shape, material and other properties of the required gate conductive layer 140 can be adjusted.

[0054] In some embodiments, in the first direction X, the width of the gate conductive layer 140 is smaller than the width of the semiconductor channel 110 of the second doped region 113. That is, the projection of the gate conductive layer 140 on the substrate 100 is located within the projection of the second doped region 113 on the substrate 100. By setting the width of the gate conductive layer 140 to be smaller than the width of the semiconductor channel 110 of the second doped region 113, the spacing between the second transistors can be increased, thereby reducing the parasitic capacitance between adjacent second transistors.

[0055] In some embodiments, the gate conductive layer 140 is cubic in shape, and its width is the distance between two sides of the cube spaced apart along the first direction X. In some embodiments, the gate conductive layer 140 is cylindrical in shape, and its width is the diameter of the cross-section of the cylinder along the first direction. Similarly, the semiconductor channel 110 is cubic in shape, and its width is the distance between two sides of the cube spaced apart along the first direction X. The semiconductor channel 110 is also cylindrical in shape, and its width is the diameter of the cross-section of the cylinder along the first direction. In other embodiments, the gate conductive layer and the semiconductor channel can also be other shapes, and the width of the gate conductive layer can be the longest distance of the projected pattern of the gate conductive layer on the substrate along the first direction X.

[0056] In some embodiments, the material of the gate conductive layer 140 may be silicon or germanium.

[0057] In some embodiments, the channel layer 150 surrounds the outer side of the gate conductive layer 140, and the channel layer 150 is also located on the top surface of the second insulating layer 210. Taking the gate conductive layer 140 as a cubic shape as an example, the channel layer 150 covers the four sides of the gate conductive layer 140 and the top surface of the second insulating layer 210 between adjacent gate conductive layers 140. The channel layer 150 covering the top surface of the second insulating layer 210 is used to make contact and electrical connection with the first semiconductor doped layer 160 and the second semiconductor doped layer 170. In other embodiments, the channel layer 150 may only surround the outer side of the gate conductive layer 140. In this case, the first semiconductor doped layer 160 and the second semiconductor doped layer 170 need to make contact and connection with the channel layer 150 in other ways. In still other embodiments, the channel layer surrounds the outer side of the gate conductive layer and covers part of the top surface of the second insulating layer. It is only necessary to enable the channel layer to make contact and electrical connection with the first semiconductor doped layer and the second semiconductor doped layer.

[0058] In some embodiments, the thickness of the channel layer 150 can be 3 to 10 nm, such as 5 nm or 7 nm. It is understood that by setting the thickness of the channel layer 150 to 3 to 10 nm, the second transistor can have better performance. When the thickness of the channel layer 150 is less than 3 nm, the thickness of the channel of the second transistor is low, which makes it easy for electrical breakdown to occur, resulting in low reliability of the second transistor. When the thickness of the channel layer 150 is greater than 10 nm, the thickness of the channel of the second transistor is too thick, which leads to a decrease in the performance of the second transistor.

[0059] In some embodiments, the material of the channel layer 150 may be polycrystalline silicon with P-type doping.

[0060] In some embodiments, the first semiconductor doped layer 160 can serve as either the source or the drain of the second transistor, and the second semiconductor doped layer 170 can serve as either the source or the drain of the second transistor. Taking the first semiconductor doped layer 160 as the source and the second semiconductor doped layer 170 as the drain as an example, the first semiconductor doped layer 160, the second semiconductor doped layer 170, the channel layer 150, and the gate conductive layer 140 respectively constitute the source, drain, channel, and gate of the second transistor. The second transistor can only be turned on when the gate conductive layer 140 stores charge. The charge carriers between the first semiconductor doped layer 160 and the second semiconductor doped layer 170 flow through the channel layer 150.

[0061] It is understandable that both the first semiconductor doped layer 160 and the second semiconductor doped layer 170 are electrically connected to the channel layer 150 to enable the flow of charge carriers in the second transistor.

[0062] In some embodiments, the first semiconductor doped layer 160 is arranged along the first direction X, and two adjacent gate conductive layers 140 in the first direction X are connected to the same first semiconductor doped layer 160. Taking the first semiconductor doped layer 160 as the source, that is, two second transistors arranged along the first direction X share the same source. By setting adjacent gate conductive layers 140 in the first direction X and connecting them to the same first semiconductor doped layer 160, the process steps for forming the semiconductor structure can be reduced, and the integration density of the semiconductor structure can be improved.

[0063] In some embodiments, the second semiconductor doped layer 170 is arranged along the second direction Y, and adjacent gate conductive layers 140 in the second direction Y are connected to the same second semiconductor doped layer 170. Taking the second semiconductor doped layer 170 as the drain as an example, that is, the second transistors arranged along the second direction Y share a common drain. By setting adjacent gate conductive layers 140 in the second direction Y and connecting them to the same second semiconductor doped layer 170, the process steps for forming the semiconductor structure can be reduced, and the integration density of the semiconductor structure can be improved.

[0064] In some embodiments, the materials of the first semiconductor doped layer 160 and the second semiconductor doped layer 170 may be polycrystalline silicon materials with N-type doping.

[0065] In some embodiments, the channel layer 150 includes a flat portion 151 and a protrusion 152, the protrusion 152 surrounding the gate conductive layer 140, the flat portion 151 being connected to the protrusion 152, a first semiconductor doped layer 160 being disposed on the outer side of the protrusion 152 arranged along one of the first direction X or the second direction Y, and in contact with the top surface of the flat portion 151, and a second semiconductor doped layer 170 being disposed on the outer side of the protrusion 152 arranged along the other of the first direction X or the second direction Y, and in contact with the top surface of the flat portion 151. The flat portion 151 of the channel layer 150 can be the channel layer 150 between adjacent gate conductive layers 140. Corresponding to the figure, it is the portion of the channel layer 150 covering the surface of the second insulating layer 210. The protruding portion 152 of the channel layer 150 is the portion of the channel layer 150 located on the sidewall of the gate conductive layer 140 and the top surface of the gate conductive layer 140. By providing the flat portion 151, the channel layer 150 can be contacted and connected with the first semiconductor doped layer 160 and the second semiconductor doped layer 170. By providing the protruding portion 152, the channel length of the second transistor can be increased, thereby improving the control capability of the gate conductive layer 140 as a gate and improving the performance of the second transistor.

[0066] In some embodiments, the channel layer 150 is doped with a first doped ion, and the first semiconductor doped layer 160 has a second doped ion. The ion types of the first doped ion and the second doped ion are different. The ion type of the first doped ion can be a P-type ion, and the ion type of the second doped ion can be an N-type ion. By setting the doped ions of the channel layer 150 and the first semiconductor doped layer 160 to be different, a PN junction is formed to constitute a second transistor.

[0067] In some embodiments, the dopant ion type of the second semiconductor doped layer 170 is the same as that of the first semiconductor doped layer 160, and the doping concentration is the same.

[0068] In some embodiments, the second bit line 180 may extend along the first direction X and be electrically connected to a plurality of first semiconductor doped layers 160 arranged along the first direction X, thereby detecting whether there is current in the first semiconductor doped layer 160. The second word line 190 may extend along the second direction Y and be electrically connected to a plurality of second semiconductor doped layers 170 arranged along the second direction Y, thereby detecting whether there is current in the second semiconductor doped layer 170. The current level state of the semiconductor structure can then be read through the second bit line 180 and the second word line 190.

[0069] In some embodiments, the second bit line 180 may be formed by stacking multiple film layers, such as including a bit line conductive layer and a bit line protective layer. Signal transmission is performed through the bit line conductive layer, and the bit line protective layer protects the bit line conductive layer. The bit line conductive layer may also be formed by stacking multiple film layers, such as including a first bit line conductive layer and a second bit line conductive layer. The first bit line conductive layer may be made of a semiconductor material, and the second bit line conductive layer may be made of a metal material. It should be noted that the specific structure of the second bit line 180 can be set according to actual needs; in other embodiments, the second bit line 180 may also be a single film layer.

[0070] In some embodiments, the second word line 190 may be formed by stacking multiple film layers, such as a word line conductive layer and a word line protective layer. Signal transmission is performed through the word line conductive layer, and the word line protective layer protects the word line conductive layer. The word line conductive layer may also be formed by stacking multiple film layers, such as a first word line conductive layer and a second word line conductive layer. The first word line conductive layer may be made of a semiconductor material, and the second word line conductive layer may be made of a metal material. It should be noted that the specific structure of the second word line 190 can be set according to actual needs; in other embodiments, the second word line 190 may also be a single film layer.

[0071] In some embodiments, the semiconductor structure may further include: a first gate dielectric layer 230, which surrounds the surface of the gate conductive layer 140 and is in contact with the gate conductive layer 140; the first gate dielectric layer 230 may serve as the gate dielectric layer of the second transistor, thereby preventing the carriers of the source and drain of the second transistor from flowing directly into the gate.

[0072] In some embodiments, the first gate dielectric layer 230 may be a material such as silicon oxide used as a gate dielectric layer.

[0073] In some embodiments, the channel layer 150 surrounds the surface of the first gate dielectric layer 230 and is in contact with the first gate dielectric layer 230, that is, the channel layer 150 and the gate conductive layer 140 are spaced apart by the first gate dielectric layer 230.

[0074] In some embodiments, the semiconductor structure further includes a first isolation layer 240, which surrounds a portion of the surface of the channel layer 150 and is in contact with the channel layer 150. By providing the first isolation layer 240, it can be used to isolate adjacent first semiconductor doped layers 160 and second semiconductor doped layers 170, thereby avoiding direct contact between adjacent first semiconductor doped layers 160 and second semiconductor doped layers 170 and improving the reliability of the semiconductor structure.

[0075] In some embodiments, the system further includes a second isolation layer 250, which is located between an adjacent first semiconductor doped layer 160 and an adjacent second semiconductor doped layer 170. The second isolation layer 250 can isolate the adjacent first semiconductor doped layer 160 and the adjacent second semiconductor doped layer 170, thereby avoiding direct contact between the first semiconductor doped layer 160 and the second semiconductor doped layer 170 and improving the reliability of the semiconductor structure.

[0076] It is understood that the first semiconductor doped layer 160 and the second semiconductor doped layer 170 can be isolated by the first isolation layer 240 and the second isolation layer 250, so that the first semiconductor doped layer 160 and the second semiconductor doped layer 170 can contact the channel layer 150 through the flat portion 151 of the channel layer 150. This achieves both isolation between the adjacent first semiconductor doped layer 160 and the second semiconductor doped layer 170 and contact connection between the first semiconductor doped layer 160 and the second semiconductor doped layer 170 and the channel layer 150.

[0077] In some embodiments, the first isolation layer 240 and the second isolation layer 250 may be made of different materials. Using different materials for the first isolation layer 240 and the second isolation layer 250 facilitates the manufacturing process. In other embodiments, the first isolation layer 240 and the second isolation layer 250 may be made of the same material, and the materials of the first isolation layer 240 and the second isolation layer 250 can be adjusted according to actual needs.

[0078] In some embodiments, the material of the first isolation layer 240 may be silicon oxide. By setting the material of the first isolation layer 240 to silicon oxide, it can be directly formed by oxidizing part of the gate conductive layer 140, which can facilitate the manufacturing process.

[0079] In some embodiments, the material of the second isolation layer 250 may be silicon nitride. By setting the material of the second isolation layer 250 to silicon nitride, the insulation performance between the adjacent first semiconductor doped layer 160 and the second semiconductor doped layer 170 can be improved.

[0080] In some embodiments, the semiconductor structure further includes: a protective layer 260, which covers the top surface of the channel layer 150, a portion of the surface of the first semiconductor doped layer 160, and a portion of the surface of the second semiconductor doped layer 170; a second bit line 180 penetrates the protective layer 260 and is in contact with one of the first semiconductor doped layer 160 or the second semiconductor doped layer 170; and a second word line 190 penetrates the protective layer 260 and is in contact with the other of the first semiconductor doped layer 160 or the second semiconductor doped layer 170. Taking the connection between the second bit line 180 and the first semiconductor doped layer 160 as an example, by providing the protective layer 260, the second bit line 180 and the second semiconductor doped layer 170 can be separated, thereby preventing the second bit line 180 from being connected to the second semiconductor doped layer 170. Similarly, by providing the protective layer 260, the second word line 190 can also be isolated from the first semiconductor doped layer 160, thereby preventing the second word line 190 from being electrically connected to the first semiconductor doped layer 160.

[0081] In some embodiments, the material of the protective layer 260 may be an insulating material such as silicon oxide.

[0082] In some embodiments, the semiconductor structure may further include a conductive plug 280 that penetrates the protective layer 260. The second bit line 180 may be electrically connected to one of the first semiconductor doped layer 160 or the second semiconductor doped layer 170 through the conductive plug 280, and the second word line 190 may be electrically connected to the other of the first semiconductor doped layer 160 or the second semiconductor doped layer 170 through the conductive plug 280.

[0083] In some embodiments, the semiconductor structure may further include a third insulating layer 270, which covers the top surface and sidewalls of the second bit line 180. By providing the third insulating layer 270, the second bit line 180 and the second word line 190 can be isolated, thereby preventing electrical connection between the second bit line 180 and the second word line 190. Furthermore, by providing the third insulating layer 270, a supporting foundation can be provided for forming the second word line 190.

[0084] In some embodiments, the material of the third insulating layer 270 may be an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0085] It should be noted that the materials mentioned in the embodiments of this disclosure are for illustrative purposes only and are not limited to the film material. Materials with the same properties that can satisfy the purpose of the embodiments of this disclosure can also be used.

[0086] This disclosure provides a semiconductor structure in which a first doped region 111 of a semiconductor channel 110 serves as either the source or drain of a first transistor, a channel region 112 serves as the channel of the first transistor, and a second doped region 113 serves as either the source or drain of the first transistor. A first word line 130 surrounding the channel region 112 serves as the gate of the first transistor, and a first bit line 120 contacts the first doped region 111. When the first word line 130 controls the first transistor to turn on, the first bit line 120 can deliver charge to the second doped region 113, thereby transferring the charge to the gate conductive layer 140. The gate conductive layer 140 serves as the gate of the second transistor, the channel layer 150 serves as the channel of the second transistor, and the first semiconductor doped layer 160 and the second semiconductor doped layer 170 serve as the source and drain of the second transistor. The second bit line 180 and the second word line 190 can be used to determine whether the gate of the second transistor stores charge, thereby allowing the signal stored in the semiconductor structure to be read.

[0087] Another embodiment of this disclosure also provides a method for fabricating a semiconductor structure, which can be used to form the above-mentioned semiconductor structure. The method for fabricating a semiconductor structure provided by another embodiment of this disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the foregoing embodiments can be referred to the corresponding descriptions of the foregoing embodiments, and will not be repeated below.

[0088] refer to Figures 5 to 21 and Figures 2 to 4 ,in, Figures 6 to 14 and Figure 4 For along Figure 5 A cross-sectional view along the direction of the dashed line. Figure 15 , Figures 18 to 21 and Figure 2 The first image is a top view of the semiconductor structure; the remaining images are 3D views.

[0089] Specifically, the method for fabricating a semiconductor structure provided in this disclosure includes: providing a substrate 100; forming a plurality of semiconductor channels 110 and gate conductive layers 140 arranged at intervals along a first direction X and a second direction Y on the substrate 100, wherein each semiconductor channel 110 includes a first doped region 111, a channel region 112, and a second doped region 113 arranged sequentially along a third direction Z, each semiconductor channel 110 constituting a first transistor, the gate conductive layer 140 being in contact with the second doped region 113 and located on the side of the second doped region 113 away from the channel region 112; forming a plurality of first lines 120 extending along the first direction X and arranged at intervals along the second direction Y, the first lines 120 being located between the substrate 100 and the semiconductor channels 110, each first line 120 being in contact with the first doped region 111 arranged along the first direction X; forming a plurality of first lines 120 extending along the second direction Y and arranged at intervals along the first direction X. A first word line 130 is arranged at intervals and surrounds a channel region 112; a channel layer 150 is formed and surrounds the outer surface of a gate conductive layer 140; a first semiconductor doped layer 160 and a second semiconductor doped layer 170 are formed and disposed on the outer surface of the channel layer 150, with the first semiconductor doped layer 160 and the second semiconductor doped layer 170 spaced apart; the first semiconductor doped layer 160, the second semiconductor doped layer 170, the channel layer 150, and the gate conductive layer 140 are used to form a second transistor; a second bit line 180 is formed and electrically connected to one of the first semiconductor doped layer 160 or the second semiconductor doped layer 170; a second word line 190 is formed and electrically connected to the other of the first semiconductor doped layer 160 or the second semiconductor doped layer 170.

[0090] By forming a first doped region 111 as either the source or drain of the first transistor, using a channel region 112 as the gate of the first transistor, and forming a second doped region 113 as the other of the source or drain of the first transistor, and by forming a first bit line 120 in contact with the first doped region 111, charge can be stored in the gate of the second transistor or the charge can be discharged from the gate of the second transistor when the first transistor is turned on. The first word line 130 surrounding the channel region 112 controls the conduction of the first transistor. A gate conductive layer 140 is formed as the gate of the second transistor, a channel layer 150 is formed as the channel of the second transistor, and a first semiconductor doped layer 160 and... The second semiconductor doped layer 170 serves as the source and drain of the second transistor. When the gate of the second transistor receives charge from the first transistor, the conduction of the second transistor can be controlled. By measuring the voltage difference between the second bit line 180 electrically connected to one of the first semiconductor doped layer 160 or the second semiconductor doped layer 170 and the second word line 190 electrically connected to the other of the first semiconductor doped layer 160 or the second semiconductor doped layer 170, the voltage level of the transistor corresponding to the second word line 190 and the second bit line 180 can be determined. The semiconductor structure fabrication method provided in this embodiment can reduce the fabrication difficulty of semiconductor structures and improve the integration of semiconductor structures.

[0091] refer to Figures 5 to 8 The method for forming a semiconductor channel 110 and a gate conductive layer 140 includes: forming an initial semiconductor channel 114, the initial semiconductor channel 114 being located on a substrate 100 and arranged at intervals along a first direction X and a second direction Y, the initial semiconductor channel 114 including a first doped region 111, a channel region 112, and a second initial doped region 115 arranged sequentially along a third direction Z; etching a portion of the second initial doped region 115 to form a second doped region 113 and a gate conductive layer 140. By etching a portion of the second initial doped region 115 of the initial semiconductor channel 114, the spacing between adjacent gate conductive layers 140 can be increased, thereby improving the insulation performance between adjacent gate conductive layers 140.

[0092] refer to Figure 6 , Figure 6 For along Figure 5 The sectional view along the dashed line does not show... Figure 5 The structure shown is used for the following process steps.

[0093] refer to Figure 7In some embodiments, the semiconductor structure further includes: a first insulating layer 200 filling the spaces between initial semiconductor channels 114; a second insulating layer 210 located between adjacent first word lines 130; and a second gate dielectric layer 220 located between the first word lines 130 and the channel region 112, serving as the gate dielectric layer of the first transistor. The method of forming the semiconductor channel 110 and the gate conductive layer 140 further includes: etching the second insulating layer 210 to expose the top surface and sidewalls of the second initial doped region 115.

[0094] refer to Figure 8 The initial semiconductor channel 114 is etched to form the second doped region 113 and the gate conductive layer 140. In some embodiments, the initial semiconductor channel 114 may be etched using a wet etching method. In other embodiments, the initial semiconductor channel may also be etched using a dry etching method or the like.

[0095] It is understood that the above-described method of forming the second doped region 113 and the gate conductive layer 140 by etching is a method of forming the semiconductor channel 110 and the gate conductive layer 140 as a single unit. In other embodiments, the second doped region 113 and the gate conductive layer 140 can also be a separate structure. The method of forming the second doped region 113 and the gate conductive layer 140 can be to deposit semiconductor material on the surface of the second doped region 113 to form the gate conductive layer 140.

[0096] refer to Figures 9 to 12 Before forming the channel layer 150, the method further includes: forming a first gate dielectric layer 230, which surrounds the surface of the gate conductive layer 140 and contacts the gate conductive layer 140; after forming the channel layer 150, the method further includes: forming a first isolation layer 240, which surrounds the surface of the channel layer 150 and contacts the channel layer 150. The formation of the first gate dielectric layer 230 can be used to isolate the gate conductive layer 140 from the channel layer 150, thereby preventing direct connection between the gate of the second transistor and the channel. The formation of the first isolation layer 240 can be used to subsequently isolate the adjacent first semiconductor doped layer 160 and second semiconductor doped layer 170.

[0097] refer to Figure 9 In some embodiments, the first gate dielectric layer 230 can be formed by directly oxidizing part of the gate conductive layer 140. In other embodiments, the first gate dielectric layer 230 can also be formed by atomic deposition. The first gate dielectric layer 230 formed by oxidation has better density and better performance as a gate dielectric layer, while the first gate dielectric layer 230 formed by atomic deposition has better uniformity.

[0098] refer to Figure 10A channel layer 150 is formed. In some embodiments, the channel layer 150 covers the surface of the first gate dielectric layer 230, and the channel layer 150 also covers the entire surface of the second insulating layer 210. In other words, the formation of the channel layer 150 is a full-surface deposition, meaning that the channel layer 150 covers the entire surface of the second insulating layer 210. Figure 9 The entire top surface of the semiconductor structure is shown. In other embodiments, the channel layers may also be spaced apart, that is, the channel layers are arranged at intervals along the first direction X and the second direction Y, with one channel layer corresponding to one gate conductive layer.

[0099] refer to Figure 11 and Figure 12 The channel layer 150 includes a planar portion 151 and a protrusion 152. The protrusion 152 surrounds the gate conductive layer 140, and the planar portion 151 is connected to the protrusion 152. The method of forming the first isolation layer 240 includes: forming a first initial isolation layer 241, the first initial isolation layer 241 covering the entire surface of the channel layer 150; etching the first initial isolation layer 241 to expose the top surface of the protrusion 152 and the top surface of the planar portion 151, with the remaining first initial isolation layer 241 serving as the first isolation layer 240. The first isolation layer 240 formed by first forming the first initial isolation layer 241 and then etching to form the first isolation layer 240 has better performance, and by etching to expose the top surface of the planar portion 151, a process basis is provided for the subsequent contact connection between the channel layer 150 and the first semiconductor doped layer and the second semiconductor doped layer.

[0100] In some embodiments, the first initial isolation layer 241 may be formed by oxidizing the channel layer 150. In other embodiments, the first initial isolation layer 241 may also be formed by atomic deposition. The first initial isolation layer 241 formed by oxidation has a higher density and the thickness of the channel layer 150 can be adjusted. The first initial isolation layer 241 formed by atomic deposition has better uniformity.

[0101] refer to Figures 13 to 19In some embodiments, the method of forming the first semiconductor doped layer 160 and the second semiconductor doped layer 170 includes: forming an initial doped layer 161, the initial doped layer 161 covering the surfaces of the first isolation layer 240 and the channel layer 150; etching the initial doped layer 161 to expose the top surfaces of the first isolation layer 240 and the channel layer 150, with the remaining initial doped layer 161 serving as a doped layer 162; etching the doped layer 162 to form a groove, the groove exposing a portion of the sidewalls of the first isolation layer 240 and the top surface of the flat portion 151, with the remaining doped layer 162 serving as the first semiconductor doped layer 160 and the second semiconductor doped layer 170. An initial doped layer 161 is first formed by full-surface deposition, with the top surface of the initial doped layer 161 being higher than the top surface of the channel layer 150. Then, a doped layer 162 with its top surface flush with the top surface of the channel layer 150 is formed by etching. Finally, a first semiconductor doped layer 160 and a second semiconductor doped layer 170 are formed by etching. This separates adjacent first semiconductor doped layers 160 and second semiconductor doped layers 170, thereby preventing direct contact between adjacent first semiconductor doped layers 160 and second semiconductor doped layers 170, which in turn prevents direct connection between the source and drain of the second transistor.

[0102] refer to Figure 13 The material is filled into the initial doped layer 161 to form the initial doped layer 161.

[0103] refer to Figure 14 The initial doped layer 161 is etched, or part of the initial doped layer 161 is removed by grinding to form the doped layer 162.

[0104] refer to Figure 15 and Figure 16 , Figure 15 for Figure 14 The top view of the semiconductor structure shown. Figure 16 for Figure 14 The three-dimensional diagram of the semiconductor structure shown does not depict any manufacturing processes.

[0105] refer to Figures 17 to 19 In some embodiments, the method of etching the doped layer 162 includes: etching the doped layer 162 using a self-aligned process to form an initial groove, the initial groove penetrating the doped layer 162; and etching the doped layer 162 within the initial groove using an over-etching method to form the groove, a first semiconductor doped layer 160, and a second semiconductor doped layer 170. The pattern of the self-aligned process can be the same pattern used when forming the semiconductor channel, which can reduce one step of forming a mask pattern, simplify the process steps, and reduce the process difficulty.

[0106] refer to Figure 17A protective layer 260 is formed, and an initial groove is formed using a self-aligned process. The protective layer 260 covers the surface of the doped layer 162 and the channel layer 150. The protective layer 260 can be used to prevent the etching solution from contacting the channel layer 150, thereby preventing the channel layer 150 from being contaminated and improving the reliability of the semiconductor structure.

[0107] refer to Figure 18 , Figure 18 for Figure 17 As shown in the top view of the semiconductor structure, it can be seen that the initial groove did not form the first semiconductor doped layer 160 and the second semiconductor doped layer 170 arranged at intervals along the first direction X and the second direction Y. Therefore, it is necessary to etch part of the doped layer 162 by over-etching.

[0108] refer to Figure 19 The doped layer 162 is etched to form a first semiconductor doped layer 160 and a second semiconductor doped layer 170 arranged at intervals.

[0109] Continue to refer to Figures 17 to 19 In other embodiments, the method of etching the doped layer 162 includes: forming a mask layer (not shown) covering the top surface of the doped layer 162, and the mask layer including a target pattern, the length of which is equal to the spacing between adjacent first isolation layers 240 in the first direction X, and the width of which is equal to the spacing between adjacent first isolation layers 240 in the second direction Y; etching the doped layer 162 using the mask layer as a mask to form a first semiconductor doped layer 160 and a second semiconductor doped layer 170; wherein the target pattern corresponds to the final desired pattern, that is, the first semiconductor doped layer 160 and the second semiconductor doped layer 170 arranged at intervals, that is, the first semiconductor doped layer 160 and the second semiconductor doped layer 170 are directly formed by mask etching, and the pattern formed by mask etching is more accurate.

[0110] Continue to refer to Figure 19 In some embodiments, the method further includes forming a second isolation layer 250, which is located between an adjacent first semiconductor doped layer 160 and an adjacent second semiconductor doped layer 170. The second isolation layer 250 fills the groove formed by etching the doped layer 162. By forming the second isolation layer 250, the insulation between the first semiconductor doped layer 160 and the adjacent second semiconductor doped layer 170 can be improved, and filling the gap between the first semiconductor doped layer 160 and the second semiconductor doped layer 170 can facilitate subsequent process steps.

[0111] refer to Figure 20In some embodiments, before forming the second bit line, the method further includes forming a conductive plug 280 located on the top surface of either the first semiconductor doped layer 160 or the second semiconductor doped layer 170, for contacting and electrically connecting with the subsequently formed second bit line.

[0112] refer to Figure 21 This forms the second position line 180.

[0113] refer to Figure 2 , Figure 3 and Figure 4 A conductive plug 280, a third insulating layer 270, and a second word line 190 are formed sequentially. It can be understood that the conductive plug 280 formed in this step is located on the top surface of either the first semiconductor doped layer 160 or the second semiconductor doped layer 170, and is used to make contact and electrical connection with the second word line 190. The third insulating layer 270 is used to isolate the second bit line 180 and the second word line 190. The conductive plug formed in this step also penetrates the third insulating layer 270.

[0114] This embodiment of the disclosure forms a first doped region 111 as either the source or drain of a first transistor, a channel region 112 as the gate of the first transistor, and a second doped region 113 as the other of the source or drain of the first transistor. A first bit line 120 contacting the first doped region 111 can store charge on the gate of the second transistor or discharge charge from the gate of the second transistor when the first transistor is turned on. A first word line 130 surrounding the channel region 112 controls the conduction of the first transistor. A gate conductive layer 140 is formed as the gate of the second transistor, a channel layer 150 is formed as the channel of the second transistor, and a first semiconductor doped layer 16 is formed. The second semiconductor doped layer 160 and the second semiconductor doped layer 170 serve as the source and drain of the second transistor, respectively. When the gate of the second transistor receives a charge from the first transistor, the conduction of the second transistor can be controlled. By measuring the voltage difference between the second bit line 180, which is electrically connected to one of the first semiconductor doped layer 160 or the second semiconductor doped layer 170, and the second word line 190, which is electrically connected to the other of the first semiconductor doped layer 160 or the second semiconductor doped layer 170, the voltage level of the transistor corresponding to the second word line 190 and the second bit line 180 can be determined. The semiconductor structure fabrication method provided in this embodiment can reduce the fabrication difficulty of the semiconductor structure and improve the integration of the semiconductor structure.

[0115] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate and a plurality of semiconductor channels arranged at intervals along a first direction and a second direction on the substrate, the semiconductor channels including a first doped region, a channel region and a second doped region arranged sequentially along a third direction, each of the semiconductor channels being used to form a first transistor; Multiple first bit lines extending along the first direction and spaced apart along the second direction, the first bit lines being located between the substrate and the semiconductor channel, each of the first bit lines being in contact with the first doped region arranged along the first direction; Multiple first character lines extending along the second direction and spaced apart along the first direction, the first character lines surrounding the channel area; A gate conductive layer, wherein the gate conductive layer is in contact with the second doped region and is located on the side of the second doped region away from the channel region; A channel layer is disposed around the outer side of the gate conductive layer; A first semiconductor doped layer and a second semiconductor doped layer are disposed on the outer side of the channel layer and are spaced apart from each other. The first semiconductor doped layer, the second semiconductor doped layer, the channel layer and the gate conductive layer are used to form a second transistor. The second bit line is electrically connected to one of the first semiconductor doped layer or the second semiconductor doped layer. The second word line is electrically connected to the other of the first semiconductor doped layer or the second semiconductor doped layer.

2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A first gate dielectric layer surrounds the surface of the gate conductive layer and is in contact with the gate conductive layer; The channel layer surrounds the surface of the first gate dielectric layer and is in contact with the first gate dielectric layer; A first isolation layer surrounds a portion of the surface of the channel layer and is in contact with the channel layer.

3. The semiconductor structure according to claim 2, characterized in that, Also includes: A second isolation layer is located between an adjacent first semiconductor doped layer and an adjacent second semiconductor doped layer.

4. The semiconductor structure according to claim 3, characterized in that, The first isolation layer is made of a different material than the second isolation layer.

5. The semiconductor structure according to claim 1, characterized in that, The channel layer is doped with a first doped ion, and the first semiconductor doped layer has a second doped ion, wherein the ion type of the first doped ion is different from that of the second doped ion.

6. The semiconductor structure according to claim 1, characterized in that, The gate conductive layer and the semiconductor channel are an integral structure.

7. The semiconductor structure according to claim 1, characterized in that, The channel region includes a flat portion and a protruding portion. The protruding portion surrounds the gate conductive layer. The flat portion is connected to the protruding portion. A first semiconductor doped layer is disposed on the outer side of the protruding portion arranged along one of the first direction or the second direction and is in contact with the top surface of the flat portion. A second semiconductor doped layer is disposed on the outer side of the protruding portion arranged along the other of the first direction or the second direction and is in contact with the top surface of the flat portion.

8. The semiconductor structure according to claim 1, characterized in that, In the first direction, the width of the gate conductive layer is smaller than the width of the semiconductor channel in the second doped region.

9. The semiconductor structure according to claim 1, characterized in that, The first semiconductor doped layer is arranged along the first direction, and two adjacent gate conductive layers in the first direction are connected to the same first semiconductor doped layer.

10. The semiconductor structure according to claim 1, characterized in that, Also includes: A protective layer covers the top surface of the channel layer, a portion of the surface of the first semiconductor doped layer, and a portion of the surface of the second semiconductor doped layer. The second bit line passes through the protective layer and contacts one of the first semiconductor doped layer or the second semiconductor doped layer. The second word line passes through the protective layer and contacts the other of the first semiconductor doped layer or the second semiconductor doped layer.

11. A method for fabricating a semiconductor structure, characterized in that, include Provide a base; A plurality of semiconductor channels and gate conductive layers are formed on the substrate and spaced apart along a first direction and a second direction. The semiconductor channels include a first doped region, a channel region and a second doped region arranged sequentially along a third direction. Each semiconductor channel is used to form a first transistor. The gate conductive layer is in contact with the second doped region and is located on the side of the second doped region away from the channel region. Multiple first bit lines are formed, extending along the first direction and spaced apart along the second direction. The first bit lines are located between the substrate and the semiconductor channel, and each first bit line is in contact with the first doped region arranged along the first direction. Multiple first character lines are formed that extend along the second direction and are spaced apart along the first direction, the first character lines surrounding the channel area; A channel layer is formed, the channel layer being disposed around the outer side of the gate conductive layer; A first semiconductor doped layer and a second semiconductor doped layer are formed, the first semiconductor doped layer and the second semiconductor doped layer are disposed on the outer side of the channel layer, and the first semiconductor doped layer and the second semiconductor doped layer are spaced apart. The first semiconductor doped layer, the second semiconductor doped layer, the channel layer and the gate conductive layer are used to form a second transistor. A second bit line is formed, and the second bit line is electrically connected to one of the first semiconductor doped layer or the second semiconductor doped layer. A second word line is formed, which is electrically connected to the other of the first semiconductor doped layer or the second semiconductor doped layer.

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The method of forming the semiconductor channel and the gate conductive layer includes: An initial semiconductor channel is formed, the initial semiconductor channel being located on the substrate and arranged at intervals along the first direction and the second direction, the initial semiconductor channel including a first doped region, the channel region and a second initial doped region arranged sequentially along the third direction; The second initial doped region is etched to form the second doped region and the gate conductive layer.

13. The method for fabricating a semiconductor structure according to claim 11, characterized in that, Before forming the channel layer, the method further includes: forming a first gate dielectric layer, the first gate dielectric layer surrounding the surface of the gate conductive layer and in contact with the gate conductive layer; After forming the channel layer, the method further includes: forming a first isolation layer that surrounds the surface of the channel layer and is in contact with the channel layer.

14. The method for fabricating a semiconductor structure according to claim 13, characterized in that, The channel layer includes a flat portion and a protruding portion, the protruding portion surrounding the gate conductive layer, the flat portion being connected to the protruding portion, and the method of forming the first isolation layer includes: forming a first initial isolation layer, the first initial isolation layer covering the entire surface of the channel layer; The first initial isolation layer is etched to expose the top surface of the protrusion and the top surface of the flat portion, leaving the remaining first initial isolation layer as the first isolation layer.

15. The method for fabricating a semiconductor structure according to claim 14, characterized in that, The method for forming the first semiconductor doped layer and the second semiconductor doped layer includes: An initial doped layer is formed, which covers the surfaces of the first isolation layer and the channel layer; The initial doped layer is etched to expose the top surface of the first isolation layer and the channel layer, and the remaining initial doped layer is used as a doped layer. The doped layer is etched to form a groove, the groove exposing a portion of the sidewall of the first isolation layer and the top surface of the flat portion, the remaining doped layer serving as the first semiconductor doped layer and the second semiconductor doped layer.

16. The method for fabricating a semiconductor structure according to claim 15, characterized in that, The method of etching the doped layer includes: forming a mask layer that covers the top surface of the doped layer, and the mask layer includes a target pattern, the length of which is equal to the spacing between adjacent first isolation layers in a first direction, and the width of which is equal to the spacing between adjacent first isolation layers in a second direction; The doped layer is etched using a mask layer as a mask to form the first semiconductor doped layer and the second semiconductor doped layer.

17. The method for fabricating a semiconductor structure according to claim 15, characterized in that, The method of etching the doped layer includes: etching the doped layer using a self-aligned process to form an initial groove, the initial groove penetrating the doped layer; and etching the doped layer within the initial groove using an over-etching method to form the groove, the first semiconductor doped layer, and the second semiconductor doped layer.

18. The method for fabricating a semiconductor structure according to claim 11, characterized in that, Also includes: A second isolation layer is formed, which is located between an adjacent first semiconductor doped layer and an adjacent second semiconductor doped layer.

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