Semiconductor structure and method of forming the same
By designing the placement of contact plugs and fuse structures on the substrate, the problem of synchronous formation of the fuse structure and transistor gate was solved, resulting in better electrical performance and smaller memory cell size, simplifying the manufacturing process and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-09-21
- Publication Date
- 2026-05-12
AI Technical Summary
In existing dynamic random access memory (DRAM), the fuse structure is formed synchronously with the transistor gate, which increases manufacturing complexity, occupies a larger area, has a small breakdown current, is prone to misjudgment, and reduces the electrical performance of the semiconductor structure.
A contact plug is placed on the substrate, and a fuse structure is placed on its protruding end. The breakdown position of the fuse structure is located above the substrate. A larger breakdown current is achieved through the breakdown of the fuse dielectric layer, which reduces the probability of false reading, while simplifying the manufacturing process and reducing the occupied area.
It improves the electrical performance of the semiconductor structure, reduces the probability of false reads, simplifies the manufacturing process, reduces costs, and reduces the size of the memory cell, which helps to further miniaturize.
Smart Images
Figure CN117794234B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.
[0003] Fuse structures, as one-time programmable structures, can be implemented using capacitors. However, in dynamic random access memory (DRAM), the capacitor in a fuse structure is formed synchronously with the gate in a transistor, and its structure is similar to that of the transistor gate. This not only increases the manufacturing complexity of the fuse structure but also occupies a large area within the memory cell, hindering further miniaturization of the semiconductor structure. Furthermore, because the breakdown site of the fuse structure is located within the substrate, the breakdown current is relatively small, making it prone to misjudgments and thus reducing the electrical performance of the semiconductor structure.
[0004] Therefore, how to improve the electrical performance of semiconductor structures while further reducing their size is a pressing technical problem that needs to be solved. Summary of the Invention
[0005] This disclosure provides semiconductor structures and methods for forming the same in some embodiments, which are used to further reduce the size of semiconductor structures while improving their electrical performance.
[0006] According to some embodiments, this disclosure provides a semiconductor structure, including:
[0007] A substrate, wherein the substrate includes a first doped region;
[0008] A fuse assembly includes a contact plug and a fuse structure. The contact plug includes a first end electrically connected to a first doped region and a second end extending out of the substrate along a first direction. The fuse structure is located above the second end along the first direction and includes a fuse electrode and a fuse dielectric layer located between the fuse electrode and the contact plug. The first direction is perpendicular to the top surface of the substrate.
[0009] In some embodiments, the substrate further includes a channel region and a second doped region located along a second direction on the side of the channel region away from the first doped region, the second direction being parallel to the top surface of the substrate; the semiconductor structure further includes:
[0010] The bit line is electrically connected to the second doped region, and the material of the contact plug is the same as that of the bit line, and the contact plug is disposed in the same layer as the bit line.
[0011] In some embodiments, the contact plug extends along the first direction, and the first end of the contact plug extends into the interior of the first doped region; or,
[0012] The contact plug extends along the first direction, and the first end of the contact plug is located on the top surface of the first doped region.
[0013] In some embodiments, the fuse structure extends along the first direction, and the fuse structure includes a bottom end connected to the contact plug, and a top end of the fuse structure opposite to the bottom end of the fuse structure along the first direction;
[0014] The width of the bottom end of the fuse structure along the second direction is smaller than the width of the top end of the fuse structure along the second direction, and the second direction is parallel to the top surface of the substrate.
[0015] In some embodiments, the fuse assembly further includes:
[0016] A first conductive interconnect layer is located on the second end of the contact plug, with one end of the first conductive interconnect layer electrically connected to the contact plug and the other end connected to the fuse structure.
[0017] In some embodiments, the first conductive interconnect layer extends along the second direction; the semiconductor structure further includes:
[0018] The transistor gate is located on the channel region;
[0019] Along the second direction, the fuse structure is located at the end of the first conductive interconnect layer away from the transistor gate.
[0020] In some embodiments, along the first direction, the bottom surface of the fuse structure is located above the top surface of the transistor gate.
[0021] In some embodiments, the first conductive interconnect layer includes a first portion and a second portion that are distributed opposite to each other along a second direction;
[0022] The first portion is located on the second end of the contact plug, the second portion extends out of the contact plug along the second direction, and the fuse structure is located on the second portion.
[0023] In some embodiments, the fuse structure includes:
[0024] The main body extends along the first direction, and the main body at least partially covers the top surface of the second part;
[0025] An extension portion is connected to the main body portion and extends out of the main body portion along the first direction, the extension portion at least covering the sidewall of the second portion.
[0026] In some embodiments, it also includes:
[0027] Peripheral circuitry, used to receive external control signals;
[0028] The second conductive interconnect layer is located on the top surface of the bit line. One end of the second conductive interconnect layer is electrically connected to the bit line, and the other end is electrically connected to the peripheral circuit. The second conductive interconnect layer is disposed on the same layer as the first conductive interconnect layer.
[0029] In some embodiments, the projection of the first conductive interconnect layer on the top surface of the substrate completely coincides with the projection of the contact plug on the top surface of the substrate, and the projection of the fuse structure on the top surface of the substrate completely coincides with the projection of the first conductive interconnect layer on the top surface of the substrate.
[0030] The first conductive interconnect layer extends along the first direction, and the bottom surface of the first conductive interconnect layer is electrically connected to the second end of the contact plug, and the top surface of the first conductive interconnect layer is connected to the fuse structure.
[0031] In some embodiments, the fuse structure has a groove;
[0032] The first conductive interconnect layer extends along the first direction and is embedded in the groove.
[0033] In some embodiments, the fuse structure extends along the first direction and is embedded in the interior of the second end of the contact plug along the first direction.
[0034] According to other embodiments, this disclosure also provides a method for forming a semiconductor structure, comprising the following steps:
[0035] A substrate is formed, wherein the substrate includes a first doped region;
[0036] A fuse assembly is formed on the substrate. The fuse assembly includes a contact plug and a fuse structure. The contact plug includes a first end electrically connected to the first doped region and a second end extending out of the substrate along a first direction. The fuse structure is located above the second end along the first direction and includes a fuse electrode and a fuse dielectric layer located between the fuse electrode and the contact plug. The first direction is perpendicular to the top surface of the substrate.
[0037] In some embodiments, the substrate further includes a channel region and a second doped region located along a second direction on the side of the channel region away from the first doped region, the second direction being parallel to the top surface of the substrate; the step of forming a fuse assembly on the substrate includes:
[0038] A contact plug extending in the first direction is formed above the first doped region, and a bit line extending in the first direction is formed above the second doped region.
[0039] The fuse structure is formed above the contact plug.
[0040] In some embodiments, the specific steps of forming the fuse structure above the contact plug include:
[0041] A first conductive interconnect layer electrically connected to the second end is formed on the second end of the contact plug;
[0042] The fuse structure is formed on the first conductive interconnect layer.
[0043] In some embodiments, the first conductive interconnect layer includes a first portion and a second portion distributed opposite to each other along a second direction, the first portion being located on the second end of the contact plug, and the second portion extending out of the contact plug along the second direction, the second direction being parallel to the top surface of the substrate; the specific steps for forming the fuse structure on the first conductive interconnect layer include:
[0044] The filament structure is formed on the second portion, and the filament structure at least covers the top surface and sidewalls of the second portion.
[0045] The semiconductor structure and its formation method provided in some embodiments of this disclosure, by setting a contact plug electrically connected to a first doped region and setting a fuse structure on the second end of the contact plug protruding from the substrate, ensures that the breakdown position of the fuse structure is located above the substrate, thereby reducing the probability of false reads when the fuse dielectric layer in the fuse structure is broken down, thus improving the electrical performance of the semiconductor structure. Furthermore, the contact plug and fuse structure in some embodiments of this disclosure have simple structures, not requiring a transistor gate structure, which not only simplifies the manufacturing process of the fuse assembly and reduces the manufacturing cost of the semiconductor structure, but also reduces the area occupied by the fuse assembly on the substrate, thereby reducing the size of the memory cell with the fuse assembly and contributing to further miniaturization of the semiconductor structure. Attached Figure Description
[0046] Appendix Figure 1 This is a cross-sectional schematic diagram of the semiconductor structure in the first embodiment of the present disclosure;
[0047] Appendix Figure 2 This is a cross-sectional schematic diagram of the semiconductor structure in the second embodiment of the present disclosure;
[0048] Appendix Figure 3 This is a cross-sectional schematic diagram of the semiconductor structure in the third embodiment of the specific implementation of this disclosure;
[0049] Appendix Figure 4 This is a cross-sectional schematic diagram of the semiconductor structure in the fourth embodiment of the specific implementation of this disclosure;
[0050] Appendix Figure 5 This is a cross-sectional schematic diagram of the semiconductor structure in the fifth embodiment of the specific implementation of this disclosure;
[0051] Appendix Figure 6 This is a flowchart of a method for forming a semiconductor structure according to a specific embodiment of this disclosure. Detailed Implementation
[0052] The specific embodiments of the semiconductor structure and its formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.
[0053] This specific embodiment provides a semiconductor structure, with appended... Figure 1 This is a cross-sectional schematic diagram of the semiconductor structure in the first embodiment of the present disclosure, with attached... Figure 2 This is a cross-sectional schematic diagram of the semiconductor structure in the second embodiment of the present disclosure, with attached... Figure 3 This is a cross-sectional schematic diagram of the semiconductor structure in the third embodiment of the present disclosure, with attached... Figure 4 This is a cross-sectional schematic diagram of the semiconductor structure in the fourth embodiment of the present disclosure, with attached... Figure 5 This is a cross-sectional schematic diagram of the semiconductor structure in the fifth embodiment of this disclosure. (See attached diagram.) Figures 1-5 As shown, the semiconductor structure includes:
[0054] Substrate 10, wherein the substrate 10 includes a first doped region 11;
[0055] The fuse assembly includes a contact plug 13 and a fuse structure. The contact plug 13 includes a first end electrically connected to the first doped region 11 and a second end extending out of the substrate 10 along a first direction D1. The fuse structure is located above the second end along the first direction D1 and includes a fuse electrode 18 and a fuse dielectric layer 17 located between the fuse electrode 18 and the contact plug 13. The first direction D1 is perpendicular to the top surface of the substrate 10.
[0056] The semiconductor structure described in this specific embodiment can be, but is not limited to, DRAM. The following description uses DRAM as an example. The substrate 10 can be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example. In other embodiments, the substrate 10 can also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. For example, the substrate 10 is a silicon substrate including P-type doped ions, and the first doped region 11 includes N-type doped ions. In one example, the substrate 10 further includes an N-type deep well region 19. The substrate 10 can include a plurality of memory cells arranged in an array along a direction parallel to the top surface of the substrate 10. Each memory cell includes a transistor structure and a capacitor structure to form a 1T1C structure, wherein the transistor structure serves as a switching device for the memory cell. In this specific embodiment, the top surface of the substrate 10 refers to the surface of the substrate 10 facing the fuse structure.
[0057] This specific embodiment provides a contact plug 13 for connecting the first doped region 11 and the fuse structure, with the fuse structure located on the second end of the contact plug 13 protruding from the substrate 10. This allows the fuse structure to be programmed (i.e., broken down) during programming. By applying a voltage to the fuse electrode 18 in the fuse structure, the fuse dielectric layer 17 breaks down. Since the current breakdown location of the fuse assembly (i.e., the location of the fuse dielectric layer 17) is above the substrate 10, the breakdown current is much larger than when the breakdown location is inside the substrate 10. This avoids read errors caused by insufficient breakdown current (e.g., a read error occurs when a first read value (e.g., "1") is mistakenly identified as a second read value (e.g., "0") due to insufficient breakdown current), thereby improving the electrical performance of the semiconductor structure and increasing its reliability. In addition, in this specific embodiment, the contact plug 13 with a columnar structure is electrically connected to the first doped region 11, and the fuse structure includes the fuse electrode 18 and the fuse dielectric layer 17 covering at least the bottom surface and part of the sidewall of the fuse electrode 18. This simplifies the structure of the fuse assembly, reduces the area occupied by the fuse assembly on the substrate 10, and shrinks the size of the memory cell, which helps to further miniaturize the semiconductor structure and further improve the internal integration of the semiconductor structure.
[0058] In one example, the material of the fuse dielectric layer 17 can be an insulating dielectric material such as an oxide (e.g., silicon dioxide). The specific thickness of the fuse dielectric layer 17 can be selected by those skilled in the art according to actual needs, such as setting it according to the required breakdown current. The material of the fuse electrode 18 can be the same as the material of the contact plug 13, such as conductive materials such as tungsten.
[0059] In some embodiments, the substrate 10 further includes a channel region and a second doped region 12 located along a second direction D2 on the side of the channel region away from the first doped region 11, the second direction D2 being parallel to the top surface of the substrate 10; the semiconductor structure further includes:
[0060] Bit line 15 is electrically connected to the second doped region 12, and the material of the contact plug 13 is the same as that of the bit line 15, and the contact plug 13 and the bit line 15 are disposed in the same layer.
[0061] Specifically, the first doped region 11 is either the source region or the drain region in the transistor structure within the memory cell, and correspondingly, the second doped region 12 is either the source region or the drain region in the transistor structure within the same memory cell. The first doped region 11 and the second doped region 12 have the same type of dopant ions, for example, both including N-type dopant ions. The following explanation uses the example of the first doped region 11 being the drain region and the second doped region 12 being the source region. The contact plug 13 is made of the same material as the bit line 15, and the contact plug 13 and the bit line 15 are disposed in the same layer, thus allowing the contact plug 13 and the bit line 15 to be formed simultaneously, thereby simplifying the semiconductor structure manufacturing process and reducing the manufacturing cost of the semiconductor structure. In one example, the material of the contact plug 13 and the material of the bit line 15 are both conductive materials such as tungsten.
[0062] In some embodiments, the contact plug 13 extends along the first direction D1, and the first end of the contact plug 13 extends into the interior of the first doped region 11; or,
[0063] The contact plug 13 extends along the first direction D1, and the first end of the contact plug 13 is located on the top surface of the first doped region 11.
[0064] In one example, the first end of the contact plug 13 extends into the interior of the first doped region 11, thereby increasing the contact area between the contact plug 13 and the first doped region 11 and reducing the contact resistance between the contact plug 13 and the first doped region 11, thus further improving the electrical performance of the semiconductor structure. At this time, the bit line 15, formed simultaneously with the contact plug 13, also extends along the first direction D1, and the bottom surface of the bit line 13 extends into the interior of the second doped region 12.
[0065] In another example, the first end of the contact plug 13 is located on the top surface of the first doped region 11. This allows the first doped region 11 to serve as an etching stop layer when etching the plug hole for forming the contact plug 13 (which is subsequently formed by filling the plug hole with conductive material). This prevents the plug hole from penetrating the first doped region 11 due to over-etching, thus simplifying the semiconductor fabrication process and avoiding damage to the substrate 10. At this time, the bit line 15, formed simultaneously with the contact plug 13, also extends along the first direction D1, and the bottom surface of the bit line 13 is located on the top surface of the second doped region 12.
[0066] In some embodiments, the contact plug 13 extends only into the interior of the first doped region 11, such as Figure 1 As shown. In other embodiments, such as Figure 5 As shown, the semiconductor structure also includes an isolation structure 20 located between adjacent memory cells. The contact plug 13 extends into the isolation structure 20 and the first doped region 11, and the extension depth of the contact plug 13 in the isolation structure 20 is greater than the extension depth of the contact plug 13 in the first doped region 11, thereby increasing the contact area between the contact plug 13 and the substrate 10. This not only improves the connection stability between the contact plug 13 and the substrate 10, but also reduces the contact resistance between the contact plug 13 and the first doped region 11, thereby further improving the performance of the semiconductor structure.
[0067] In some embodiments, the fuse structure extends along the first direction D1, and the fuse structure includes a bottom end connected to the contact plug 13, and a top end of the fuse structure opposite to the bottom end of the fuse structure along the first direction D1;
[0068] The width of the bottom end of the fuse structure along the second direction D2 is smaller than the width of the top end of the fuse structure along the second direction D2, and the second direction D2 is parallel to the top surface of the substrate 10.
[0069] Specifically, the fuse dielectric layer 17 in the fuse structure covers the entire bottom surface and sidewall of the fuse electrode 18, such that the top surface of the fuse dielectric layer 17 is flush with the top surface of the fuse electrode 18. The fact that the width of the bottom end of the fuse structure along the second direction D2 is smaller than the width of the top end of the fuse structure along the second direction D2 means that the width of the bottom end of the entire structure formed by the fuse dielectric layer 17 and the fuse electrode 18 it covers along the second direction D2 is smaller than the width of its top end along the second direction D2. Designing the bottom end of the fuse structure to be smaller facilitates the breakdown of the fuse dielectric layer 17 through tip discharge, making it easier to break down the fuse dielectric layer 17 and further improving the electrical performance of the semiconductor structure.
[0070] In some embodiments, the fuse assembly further includes:
[0071] A first conductive interconnect layer 14 is located on the second end of the contact plug 13, with one end of the first conductive interconnect layer 14 electrically connected to the contact plug 13 and the other end connected to the fuse structure.
[0072] In some embodiments, the first conductive interconnect layer 14 extends along the second direction D2; the semiconductor structure further includes:
[0073] The transistor gate 21 is located on the channel region;
[0074] Along the second direction D2, the fuse structure is located at the end of the first conductive interconnect layer 14 away from the transistor gate 21.
[0075] Specifically, the memory cell further includes a transistor structure, which includes a transistor gate dielectric layer 23, a transistor gate contact layer 22 on the transistor gate dielectric layer 23, and a transistor gate 21 on the transistor gate contact layer 22. In one example, the transistor gate dielectric layer 23 is made of an insulating dielectric material such as an oxide (e.g., silicon dioxide), the transistor gate contact layer 22 is made of a conductive material such as polysilicon, and the transistor gate 21 is made of a conductive material such as tungsten. The semiconductor structure includes at least two memory cells spaced apart along the second direction D2, and a bit line 15 is electrically connected to the transistor structures in the two memory cells located on opposite sides along the second direction D2. By placing the fuse structure at the end of the first conductive interconnect layer 14 away from the transistor gate 21, the distance between the fuse structures in the two memory cells spaced apart along the second direction D2 can be increased, thereby reducing signal crosstalk between adjacent memory cells.
[0076] In order to reduce the mutual influence between the fuse structure and the transistor gate 21, thereby further improving the electrical performance of the semiconductor structure, in some embodiments, the bottom surface of the fuse structure is located above the top surface of the transistor gate 21 along the first direction D1.
[0077] In some embodiments, such as Figure 1 As shown, the first conductive interconnect layer 14 includes a first portion and a second portion that are relatively distributed along the second direction D2;
[0078] The first portion is located on the second end of the contact plug 13, the second portion extends out of the contact plug 13 along the second direction D2, and the fuse structure is located on the second portion.
[0079] Specifically, such as Figure 1As shown, along the first direction D1, the first axis of the first conductive interconnect layer 14 is offset from the second axis of the contact plug 13. For example, the first axis of the first conductive interconnect layer 14 is offset by a predetermined distance relative to the second axis of the contact plug 13 along the second direction D2. Here, the first axis refers to the axis that passes through the center of the first conductive interconnect layer 14 and extends along the first direction D1, and the second axis refers to the axis that passes through the center of the contact plug 13 and extends along the first direction D1.
[0080] In this specific embodiment, the contact plug 13 and the fuse structure are bridged by the first conductive interconnect layer 14. On the one hand, this helps to increase the process window for forming the fuse structure, thereby reducing the manufacturing difficulty of the semiconductor structure. On the other hand, it also enables the manufacturing process of the contact plug 13 to be compatible with the manufacturing process of the metal interconnect layer in the semiconductor structure, thereby further simplifying the manufacturing process of the semiconductor structure.
[0081] In some embodiments, the fuse structure includes:
[0082] The main body extends along the first direction D1, and the main body at least partially covers the top surface of the second part;
[0083] An extension portion is connected to the main body portion and extends out of the main body portion along the first direction D1, the extension portion at least covering the sidewall of the second portion.
[0084] Specifically, the main body includes the fuse electrode 18 and a fuse dielectric layer 17 covering the surface of the fuse electrode 18, and the extension also includes the fuse electrode 18 and the fuse dielectric layer 17 covering the surface of the fuse electrode 18. By providing the main body and the extension in the fuse structure, on the one hand, the contact area between the fuse structure and the first conductive interconnect layer 14 can be increased, improving the connection stability between the first conductive interconnect layer 14 and the fuse structure; on the other hand, multiple sharp corners can be formed in the fuse structure (e.g., the angle at the contact interface between the main body and the first conductive interconnect layer 14, and the sharp corner at the contact interface between the extension and the first conductive layer 14), thereby facilitating the breakdown of the fuse dielectric layer 17 through tip discharge, further improving the performance of the semiconductor structure.
[0085] In some embodiments, the semiconductor structure further includes:
[0086] Peripheral circuitry, used to receive external control signals;
[0087] The second conductive interconnect layer 16 is located on the top surface of the bit line 15. One end of the second conductive interconnect layer 16 is electrically connected to the bit line 15, and the other end is electrically connected to the peripheral circuit. The second conductive interconnect layer 16 is disposed on the same layer as the first conductive interconnect layer 14. At this time, the first conductive interconnect layer 14 and the second conductive interconnect layer 16 can be formed simultaneously to further simplify the manufacturing process of the semiconductor structure.
[0088] In other embodiments, such as Figure 2 As shown, the projection of the first conductive interconnect layer 14 on the top surface of the substrate 10 completely coincides with the projection of the contact plug 13 on the top surface of the substrate 10, and the projection of the fuse structure on the top surface of the substrate 10 completely coincides with the projection of the first conductive interconnect layer 14 on the top surface of the substrate 10.
[0089] The first conductive interconnect layer 14 extends along the first direction D1, and the bottom surface of the first conductive interconnect layer 14 is electrically connected to the second end of the contact plug 13, and the top surface of the first conductive interconnect layer 14 is connected to the fuse structure. In this case, the space occupied by the fuse assembly is further reduced, thereby contributing to further miniaturization of the semiconductor structure.
[0090] In other embodiments, such as Figure 3 As shown, the fuse structure has grooves;
[0091] The first conductive interconnect layer 14 extends along the first direction D1 and is embedded in the groove. This allows for a further increase in the contact area between the fuse structure and the first conductive interconnect layer 14, and also further reduces the size of the semiconductor structure.
[0092] In other embodiments, such as Figure 4 As shown, the fuse structure extends along the first direction D1 and is embedded in the interior of the second end of the contact plug 13 along the first direction D1. In one example, the width of the fuse structure embedded inside the contact plug 13 (e.g., the width along the second direction D2) is smaller than the width of the fuse structure located outside the contact plug 13 (e.g., the width along the second direction D2), which not only facilitates the breakdown of the fuse dielectric layer 17 by tip discharge, but also further reduces the size of the memory cell and simplifies the manufacturing process of the semiconductor structure.
[0093] This specific embodiment also provides a method for forming a semiconductor structure, attached... Figure 6 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of this disclosure. A schematic diagram of the semiconductor structure formed according to this embodiment can be found in [reference needed]. Figures 1-5 .like Figures 1-6 As shown, the method for forming the semiconductor structure includes the following steps:
[0094] Step S61: Form a substrate 10, wherein the substrate 10 includes a first doped region 11;
[0095] Step S62: Form a fuse assembly on the substrate 10. The fuse assembly includes a contact plug 13 and a fuse structure. The contact plug 13 includes a first end electrically connected to the first doped region 11 and a second end extending out of the substrate 10 along a first direction D1. The fuse structure is located above the second end along the first direction D1, and the fuse structure includes a fuse electrode 18 and a fuse dielectric layer 17 located between the fuse electrode 18 and the contact plug 13. The first direction D1 is perpendicular to the top surface of the substrate 10.
[0096] In some embodiments, the substrate 10 further includes a channel region and a second doped region 12 located along a second direction D2 on the side of the channel region away from the first doped region 11, the second direction D2 being parallel to the top surface of the substrate 10; the step of forming a fuse assembly on the substrate 10 includes:
[0097] A contact plug 13 extending along the first direction D1 is formed above the first doped region 11, and a bit line 15 extending along the first direction D1 is formed above the second doped region 12.
[0098] The fuse structure is formed above the contact plug 13.
[0099] Specifically, after doping the substrate 10 to form the first doped region 11 and the second doped region 12, conductive materials such as tungsten metal or polysilicon can be deposited simultaneously on the first doped region 11 and the second doped region 12 to simultaneously form the contact plug 13 and the bit line 15.
[0100] In some embodiments, the specific steps of forming the fuse structure above the contact plug 13 include:
[0101] A first conductive interconnect layer 14 electrically connected to the second end is formed on the second end of the contact plug 13;
[0102] The filament structure is formed on the first conductive interconnect layer 14.
[0103] In some embodiments, the step of forming a first conductive interconnect layer 14 electrically connected to the second end of the contact plug 13 includes:
[0104] A first conductive interconnect layer 14 electrically connected to the second end of the contact plug 13 is formed on the second end, and a second conductive interconnect layer 16 electrically connected to the bit line 15 is formed above the bit line 15. The second conductive interconnect layer 16 is used to electrically connect to a peripheral circuit, which is used to receive external control signals.
[0105] Specifically, after forming the contact plug 13 and the bit line 15, conductive materials such as tungsten metal or TiN can be deposited simultaneously on the top surface of the contact plug 13 and the top surface of the bit line 15 to simultaneously form the first conductive interconnect layer 14 and the second conductive interconnect layer 16.
[0106] In some embodiments, the first conductive interconnect layer 14 includes a first portion and a second portion that are relatively distributed along a second direction D2, the first portion being located on the second end of the contact plug 13, and the second portion extending out of the contact plug 13 along the second direction D2, the second direction D2 being parallel to the top surface of the substrate 10; the specific steps for forming the fuse structure on the first conductive interconnect layer 14 include:
[0107] The fuse structure is formed on the second portion, and the fuse structure at least covers the top surface and sidewalls of the second portion, such as... Figure 1 As shown.
[0108] In some embodiments, the first conductive interconnect layer 14 extends along the first direction D1; the specific steps of forming the fuse structure on the first conductive interconnect layer 14 include:
[0109] The filament structure is formed to cover the top surface and sidewalls of the first conductive interconnect layer 14, such as... Figure 2 As shown.
[0110] In some embodiments, the specific steps of forming the fuse structure above the contact plug 13 include:
[0111] A fuse structure extending along the first direction D1 is formed on the contact plug 13, and the fuse structure is embedded in the interior of the second end of the contact plug 13 along the first direction D1, such as... Figure 4 As shown.
[0112] The semiconductor structure and its formation method provided in some embodiments of this specific implementation improve the electrical performance of the semiconductor structure by setting a contact plug electrically connected to a first doped region and a fuse structure on the second end of the contact plug protruding from the substrate. This ensures that the breakdown position of the fuse structure is located above the substrate, guaranteeing a large breakdown current when the fuse dielectric layer in the fuse structure is broken down, reducing the probability of false reads. Furthermore, the contact plug and fuse structure in some embodiments of this specific implementation are simple in structure and do not need to resemble transistor gate structures. This simplifies the manufacturing process of the fuse assembly, reduces the manufacturing cost of the semiconductor structure, and reduces the area occupied by the fuse assembly on the substrate, thereby reducing the size of the memory cell with the fuse assembly and contributing to further miniaturization of the semiconductor structure.
[0113] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.
Claims
1. A semiconductor structure, characterized in that, include: A substrate, wherein the substrate includes a first doped region; A fuse assembly includes a contact plug and a fuse structure. The contact plug includes a first end electrically connected to the first doped region and a second end extending out of the substrate along a first direction. The fuse structure is located above the second end along the first direction and includes a fuse electrode and a fuse dielectric layer located between the fuse electrode and the contact plug. The first direction is perpendicular to the top surface of the substrate. The substrate also includes a channel region; The semiconductor structure further includes: a transistor gate located on the channel region; Along the first direction, the bottom surface of the fuse structure is located above the top surface of the transistor gate.
2. The semiconductor structure according to claim 1, characterized in that, The substrate further includes a second doped region located along a second direction on the side of the channel region away from the first doped region, and the second direction is parallel to the top surface of the substrate; The semiconductor structure also includes: The bit line is electrically connected to the second doped region, and the material of the contact plug is the same as that of the bit line, and the contact plug is disposed in the same layer as the bit line.
3. The semiconductor structure according to claim 1, characterized in that, The contact plug extends along the first direction, and the first end of the contact plug extends into the interior of the first doped region; or, The contact plug extends along the first direction, and the first end of the contact plug is located on the top surface of the first doped region.
4. The semiconductor structure according to claim 1, characterized in that, The fuse structure extends along the first direction, and the fuse structure includes a bottom end connected to the contact plug, and a top end of the fuse structure opposite to the bottom end of the fuse structure along the first direction; The width of the bottom end of the fuse structure along the second direction is smaller than the width of the top end of the fuse structure along the second direction, and the second direction is parallel to the top surface of the substrate.
5. The semiconductor structure according to claim 2, characterized in that, The fuse assembly further includes: a first conductive interconnect layer located on the second end of the contact plug, one end of the first conductive interconnect layer being electrically connected to the contact plug and the other end being connected to the fuse structure.
6. The semiconductor structure according to claim 5, characterized in that, The first conductive interconnect layer extends along the second direction; Along the second direction, the fuse structure is located at the end of the first conductive interconnect layer away from the transistor gate.
7. The semiconductor structure according to claim 5, characterized in that, The first conductive interconnect layer includes a first portion and a second portion that are distributed opposite to each other along a second direction; The first portion is located on the second end of the contact plug, the second portion extends out of the contact plug along the second direction, and the fuse structure is located on the second portion.
8. The semiconductor structure according to claim 7, characterized in that, The fuse structure includes: The main body extends along the first direction, and the main body at least partially covers the top surface of the second part; An extension portion is connected to the main body portion and extends out of the main body portion along the first direction, the extension portion at least covering the sidewall of the second portion.
9. The semiconductor structure according to claim 7, characterized in that, Also includes: Peripheral circuitry, used to receive external control signals; The second conductive interconnect layer is located on the top surface of the bit line. One end of the second conductive interconnect layer is electrically connected to the bit line, and the other end is electrically connected to the peripheral circuit. The second conductive interconnect layer is disposed on the same layer as the first conductive interconnect layer.
10. The semiconductor structure according to claim 5, characterized in that, The projection of the first conductive interconnect layer on the top surface of the substrate completely coincides with the projection of the contact plug on the top surface of the substrate, and the projection of the fuse structure on the top surface of the substrate completely coincides with the projection of the first conductive interconnect layer on the top surface of the substrate. The first conductive interconnect layer extends along the first direction, and the bottom surface of the first conductive interconnect layer is electrically connected to the second end of the contact plug, and the top surface of the first conductive interconnect layer is connected to the fuse structure.
11. The semiconductor structure according to claim 5, characterized in that, The fuse structure has grooves; The first conductive interconnect layer extends along the first direction and is embedded in the groove.
12. The semiconductor structure according to claim 1, characterized in that, The fuse structure extends along the first direction and is embedded in the interior of the second end of the contact plug along the first direction.
13. A method for forming a semiconductor structure, characterized in that, Includes the following steps: A substrate is formed, wherein the substrate includes a first doped region; A fuse assembly is formed on the substrate. The fuse assembly includes a contact plug and a fuse structure. The contact plug includes a first end electrically connected to the first doped region and a second end extending out of the substrate along a first direction. The fuse structure is located above the second end along the first direction and includes a fuse electrode and a fuse dielectric layer located between the fuse electrode and the contact plug. The first direction is perpendicular to the top surface of the substrate. The substrate also includes a channel region; The semiconductor structure further includes: a transistor gate located on the channel region; Along the first direction, the bottom surface of the fuse structure is located above the top surface of the transistor gate.
14. The method for forming a semiconductor structure according to claim 13, characterized in that, The substrate further includes a channel region and a second doped region located along a second direction on the side of the channel region away from the first doped region, the second direction being parallel to the top surface of the substrate; The step of forming the fuse assembly on the substrate includes: A contact plug extending in the first direction is formed above the first doped region, and a bit line extending in the first direction is formed above the second doped region. The fuse structure is formed above the contact plug.
15. The method for forming a semiconductor structure according to claim 14, characterized in that, The specific steps for forming the fuse structure above the contact plug include: A first conductive interconnect layer electrically connected to the second end is formed on the second end of the contact plug; The fuse structure is formed on the first conductive interconnect layer.
16. The method for forming a semiconductor structure according to claim 15, characterized in that, The first conductive interconnect layer includes a first portion and a second portion that are distributed opposite to each other along a second direction. The first portion is located on the second end of the contact plug, and the second portion extends out of the contact plug along the second direction, which is parallel to the top surface of the substrate. The specific steps for forming the fuse structure on the first conductive interconnect layer include: The filament structure is formed on the second portion, and the filament structure at least covers the top surface and sidewalls of the second portion.