Liquid crystal handwriting board and method for manufacturing the same

Abstract

The present disclosure provides a liquid crystal handwriting board, comprising: a first substrate and a second substrate, and a bistable liquid crystal layer between the first substrate and the second substrate, the first substrate comprising: a first substrate substrate; a plurality of pixel units on the side of the first substrate substrate close to the second substrate, the pixel unit comprising: a thin film transistor and a pixel electrode electrically connected to the first electrode of the thin film transistor; a passivation layer on the side of the thin film transistor away from the first substrate substrate and in contact with the thin film transistor; the pixel electrode is between the first substrate substrate and the passivation layer; a spacer on the side of the passivation layer away from the first substrate substrate and in contact with the passivation layer. The present disclosure also provides a preparation method of a liquid crystal handwriting board.

Description

Technical Field

[0001] This invention relates to the field of display, and in particular to a liquid crystal handwriting tablet and its manufacturing method. Background Technology

[0002] As a simple input device, LCD writing tablets are popular among users because they enable handwriting and drawing. Currently, most LCD writing tablets utilize bistable liquid crystals, achieving visibility by reflecting ambient light, and feature low power consumption. However, the related technologies involved in LCD writing tablets have complex structures and complex manufacturing processes. Summary of the Invention

[0003] In a first aspect, embodiments of this disclosure provide a liquid crystal handwriting tablet, comprising: a first substrate and a second substrate, and a bistable liquid crystal layer located between the first substrate and the second substrate, wherein the first substrate comprises;

[0004] First substrate;

[0005] A plurality of pixel units are located on the side of the first substrate near the second substrate, the pixel unit comprising: a thin film transistor and a pixel electrode electrically connected to a first electrode of the thin film transistor;

[0006] A passivation layer is located on the side of the thin-film transistor away from the first substrate and is in contact with the thin-film transistor; the pixel electrode is located between the first substrate and the passivation layer;

[0007] A spacer is located on the side of the passivation layer away from the first substrate and is in contact with the passivation layer.

[0008] In some embodiments, the thin-film transistor includes: a gate, an active layer, a first electrode, and a second electrode, wherein the first electrode and the second electrode are located on the side of the active layer away from the first substrate.

[0009] The passivation layer is in contact with the first electrode and / or the second electrode.

[0010] In some embodiments, the gate is located on the side of the active layer close to the first substrate, and a gate insulating layer is formed between the gate and the active layer;

[0011] The pixel electrode is located between the gate insulating layer and the passivation layer, or the pixel electrode is located between the gate insulating layer and the first substrate.

[0012] In some embodiments, the pixel electrode is located on the side of the gate near the first substrate.

[0013] In some embodiments, the array substrate includes a first conductive layer and a second conductive layer, wherein the second conductive layer is located on the side of the first conductive layer away from the first substrate.

[0014] The first conductive layer includes the pixel electrode and a first conductive structure disposed in the same layer as the pixel electrode;

[0015] The second conductive layer includes the gate and a second conductive structure disposed in the same layer as the gate;

[0016] The orthographic projection of the first conductive layer on the first substrate covers the orthographic projection of the second conductive layer on the first substrate.

[0017] In some embodiments, the pixel electrode and the gate are disposed on the same layer.

[0018] In some embodiments, the pixel electrode is electrically connected to the corresponding first electrode through a first conductive connection structure;

[0019] The passivation layer includes vias, and at least a portion of the first conductive connection structure is located in the vias of the passivation layer;

[0020] The projected area of ​​the first conductive connection structure on the substrate is smaller than the projected area of ​​the pixel electrode connected to the first conductive connection structure on the substrate.

[0021] In some embodiments, the passivation layer is formed with a first via, the first via being connected from the surface of the passivation layer away from the first substrate to the first electrode and the pixel electrode corresponding to the first electrode;

[0022] At least a portion of the first conductive connection structure is located within the first via, and the first conductive connection structure is in contact with the first electrode and the pixel electrode corresponding to the first electrode, respectively.

[0023] In some embodiments, the orthographic projection of the first conductive connection structure on the first substrate overlaps with the orthographic projection of the first via on the first substrate.

[0024] In some embodiments, the passivation layer is formed with a second via group, the second via group including at least two second vias, at least one of the second vias in the second via group being connected to the first electrode from the surface of the passivation layer away from the first substrate, and at least one of the second vias in the second via group being connected to the pixel electrode corresponding to the first electrode from the surface of the passivation layer away from the first substrate.

[0025] The first conductive connection structure corresponds one-to-one with the second via group. The first conductive connection structure includes at least two first conductive connection substructures and at least two second conductive connection substructures.

[0026] The first conductive connection substructure corresponds one-to-one with the second via in the corresponding second via group. The first conductive connection substructure is located in the corresponding second via and is in contact with the first electrode or the pixel electrode.

[0027] The second conductive connection substructure is located on the side of the passivation layer away from the first substrate, and the second conductive connection substructure is connected to the first conductive connection substructure so that the first electrode is electrically connected to the pixel electrode.

[0028] In some embodiments, for any one of the second vias in the second via group, the second via has a first orthographic projection on the first substrate, and the first conductive connection structure corresponding to the second via has a second orthographic projection on the first substrate.

[0029] The first orthographic projection is located within the area covered by the second orthographic projection, and the distance from any point on the edge of the first orthographic projection to any point on the edge of the second orthographic projection is greater than or equal to 1 μm.

[0030] In some embodiments, for any one of the second vias in the second via group that is connected to the first electrode by the surface of the passivation layer away from the first substrate, the second via has a third orthographic projection on the first substrate, and the first electrode corresponding to the second via has a fourth orthographic projection on the first substrate.

[0031] The third orthographic projection is located within the area covered by the fourth orthographic projection, and the distance from any point on the edge of the third orthographic projection to any point on the edge of the fourth orthographic projection is greater than or equal to 1 μm.

[0032] In some embodiments, for any one of the second vias in the second via group that is connected to the pixel electrode by the surface of the passivation layer away from the first substrate, the second via has a fifth orthographic projection on the first substrate, and the pixel electrode corresponding to the second via has a sixth orthographic projection on the first substrate.

[0033] The fifth orthographic projection is located within the area covered by the sixth orthographic projection, and the distance from any point on the edge of the fifth orthographic projection to any point on the edge of the sixth orthographic projection is greater than or equal to 1 μm.

[0034] In some embodiments, the material of the first conductive connection structure includes a transparent conductive material, wherein the transparent conductive material includes a metal oxide;

[0035] The sum of the contact surface areas between the first conductive connection structure and the connected first electrode is 100 μm. 2 ~400um 2 Within the range;

[0036] The sum of the contact areas between the first conductive connection structure and the connected pixel electrode is 100 μm. 2 ~400um 2 Within the range.

[0037] In some embodiments, the material of the first conductive connection structure includes a metallic material;

[0038] The sum of the contact surface areas between the first conductive connection structure and the connected first electrode is less than 0.25 μm. 2 ~2.25um 2 Within the range;

[0039] The sum of the contact area between the first conductive connection structure and the connected pixel electrode is less than 0.25 μm. 2 ~2.25um 2 Within the range.

[0040] In some embodiments, it also includes:

[0041] Multiple pads are located in the peripheral area of ​​the liquid crystal handwriting board, and the pads are disposed on the same layer as the gate of the thin film transistor;

[0042] A third via is formed on the passivation layer, which communicates with the pad. A second conductive connection structure is formed on the sidewall of the third via and on the surface of the pad away from the first substrate.

[0043] The second conductive connection structure is disposed in the same layer as the first conductive connection structure.

[0044] In some embodiments, a portion of the pixel electrode overlaps the corresponding first electrode on the side surface away from the first substrate.

[0045] In some embodiments, the orthographic projection of the active layer on the first substrate covers the orthographic projections of the first electrode and the second electrode on the first substrate.

[0046] In some embodiments, the density of the spacers is 100 to 500 per mm².

[0047] In some embodiments, the second substrate is a flexible substrate.

[0048] Secondly, embodiments of this disclosure also provide a method for preparing a liquid crystal handwriting tablet as described in the first aspect, comprising:

[0049] The first substrate and the second substrate are prepared separately;

[0050] The first substrate and the second substrate are aligned, and a bistable liquid crystal layer is formed between the first substrate and the second substrate.

[0051] The steps for preparing the second substrate include:

[0052] Provide a first substrate;

[0053] A plurality of pixel units are formed on one side of the first substrate, the pixel unit comprising: a thin film transistor and a pixel electrode electrically connected to a first electrode of the thin film transistor;

[0054] A passivation layer is formed on the side of the thin-film transistor and the pixel electrode away from the first substrate, and the passivation layer is in contact with the thin-film transistor;

[0055] A spacer is formed on the side of the passivation layer away from the first substrate, and the spacer is in contact with the passivation layer.

[0056] In some embodiments, the step of forming a plurality of pixel units on one side of the first substrate includes: forming a pixel electrode and forming a gate;

[0057] The steps of forming pixel electrodes and forming gate electrodes include:

[0058] Forming a first conductive material thin film;

[0059] A second conductive material film is formed on the side of the first conductive material film away from the first substrate.

[0060] The first conductive material thin film and the second conductive material thin film are patterned using a halftone mask patterning process to obtain the pattern of the first conductive layer and the pattern of the second conductive layer. The first conductive layer includes the pixel electrode and a first conductive structure disposed in the same layer as the pixel electrode. The second conductive layer includes the gate and a second conductive structure disposed in the same layer as the gate. The orthogonal projection of the first conductive layer on the first substrate covers the orthogonal projection of the second conductive layer on the first substrate.

[0061] In some embodiments, the step of forming a plurality of pixel units on one side of the first substrate further includes: forming an active layer and forming a first electrode and a second electrode;

[0062] The steps for forming the active layer and the first and second electrodes include:

[0063] Forming an active material thin film;

[0064] A third conductive material film is formed on the side of the active material film away from the first substrate.

[0065] The active material thin film and the third conductive material thin film are patterned using a halftone mask patterning process to obtain the pattern of the active layer and the pattern of the third conductive layer. The third conductive layer includes the first electrode, the second electrode, and a third conductive structure disposed in the same layer as the first electrode and the second electrode. The orthogonal projection of the active layer on the first substrate covers the orthogonal projection of the first electrode and the second electrode on the first substrate.

[0066] In some embodiments, the pixel electrode is electrically connected to the corresponding first electrode through a first conductive connection structure, and the passivation layer includes a via.

[0067] The procedure, following the step of forming the passivation layer and preceding the step of forming the septum, further includes:

[0068] A first conductive connection structure is formed, wherein the pixel electrode is electrically connected to the corresponding first electrode through the corresponding first conductive connection structure, and at least a portion of the first conductive connection structure is located in the via of the passivation layer. Attached Figure Description

[0069] Figure 1 A cross-sectional schematic diagram of a portion of the liquid crystal handwriting tablet involved in the related technology;

[0070] Figure 2 A cross-sectional schematic diagram of a portion of the first substrate within the liquid crystal handwriting tablet involved in the related technology;

[0071] Figure 3 This is a cross-sectional schematic diagram of a portion of a liquid crystal handwriting tablet provided in an embodiment of the present disclosure.

[0072] Figure 4 A top view schematic diagram of a portion of the display area on a first substrate provided in an embodiment of this disclosure;

[0073] Figure 5 for Figure 4 A schematic diagram of a cross-section along the A-A' direction;

[0074] Figure 6 This is a schematic diagram of a circuit structure for a pixel unit in an embodiment of this disclosure;

[0075] Figure 7Another top view schematic diagram of a portion of the display area on the first substrate provided in an embodiment of this disclosure;

[0076] Figure 8A for Figure 7 A schematic diagram of a cross section along the B-B' direction;

[0077] Figure 8B for Figure 7 A magnified view of a portion of the Q region;

[0078] Figure 9A and Figure 9B These are two other cross-sectional schematic diagrams of a portion of the display area on the first substrate in this embodiment of the present disclosure;

[0079] Figure 10A and Figure 10B These are two more cross-sectional schematic diagrams of a portion of the display area on the first substrate in this embodiment of the present disclosure;

[0080] Figure 11 and Figure 12 These are two more cross-sectional schematic diagrams of a portion of the display area on the first substrate in an embodiment of this disclosure;

[0081] Figure 13A This is a cross-sectional schematic diagram of a portion of the display area and peripheral area of ​​the first substrate in an embodiment of this disclosure;

[0082] Figure 13B This is a cross-sectional schematic diagram of a portion of the display area and peripheral area of ​​the first substrate in an embodiment of this disclosure;

[0083] Figure 14 This is another cross-sectional schematic diagram of a portion of the display area on the first substrate in an embodiment of this disclosure;

[0084] Figure 15A and Figure 15B This is another cross-sectional schematic diagram of a portion of the display area on the first substrate in an embodiment of this disclosure;

[0085] Figure 16 A cross-sectional schematic diagram of a portion of a liquid crystal handwriting tablet provided in an embodiment of this disclosure;

[0086] Figure 17A A flowchart illustrating a method for preparing a liquid crystal handwriting tablet according to an embodiment of this disclosure;

[0087] Figure 17B This is a flowchart of a method for preparing a first substrate according to an embodiment of this disclosure;

[0088] Figure 18 This is a flowchart of an optional implementation method of step S2 in the embodiments of this disclosure;

[0089] Figure 19 This is a flowchart of an optional implementation method of step S201 in the embodiments of this disclosure;

[0090] Figure 20 This is a schematic diagram of a process flow for fabricating gate and pixel electrodes using halftone mask patterning in an embodiment of this disclosure.

[0091] Figure 21 This is a flowchart of an optional implementation method of step S203 in the embodiments of this disclosure;

[0092] Figure 22 This is a schematic diagram of a process flow for fabricating an active layer, a first electrode, and a second electrode using a halftone mask patterning process in an embodiment of this disclosure.

[0093] Figure 23 This is a flowchart illustrating a method for preparing a first substrate according to an embodiment of the present disclosure. Detailed Implementation

[0094] The present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, not all parts in the drawings are drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

[0095] Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the components, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without following these specific details.

[0096] In this disclosure, the range within A to B, or the range A to B, is defined by the two endpoint values ​​A and B.

[0097] Furthermore, each transistor involved in the embodiments of this disclosure can be independently selected from one of polycrystalline silicon thin-film transistors, amorphous silicon thin-film transistors, oxide thin-film transistors, and organic thin-film transistors. In this disclosure, "first electrode" specifically refers to the drain of the transistor, and correspondingly, "second electrode" specifically refers to the drain of the transistor. Of course, those skilled in the art should understand that the "first electrode" and "second electrode" are interchangeable.

[0098] Furthermore, in the embodiments of this disclosure, the “cross section” of a certain structure refers to the cross section of the structure in a plane parallel to the plane where the first substrate is located.

[0099] Figure 1 This is a cross-sectional schematic diagram of a portion of the liquid crystal handwriting tablet involved in the related technology. Figure 2This is a cross-sectional schematic diagram of a portion of the first substrate within the liquid crystal writing tablet involved in the related technology, such as... Figure 1 and Figure 2 As shown, the liquid crystal handwriting tablet involved in the related technology includes a first substrate 1000 and a second substrate 2000 disposed opposite to each other, and a liquid crystal layer 18 is disposed between the first substrate 1000 and the second substrate 2000.

[0100] The first substrate includes a first substrate 100 and a plurality of pixel units located on the side of the first substrate 100 facing the second substrate 2000. Each pixel unit includes a thin-film transistor (TFT) 3 and a pixel electrode 1 connected to the first electrode 7 of the TFT 3. Generally, since the distance between the first electrode 7 and the second electrode 8 of the TFT 3 (i.e., the channel length of the TFT 3) is relatively small, to avoid short circuits between the first electrode 7 and the second electrode 8 due to simultaneous contact between conductive foreign objects and the first electrode 7 and the second electrode 8 during use, a passivation layer 13 in contact with the TFT 3 is generally prepared above the TFT 3. The passivation layer 13 can fill the gap between the first electrode 7 and the second electrode 8 and cover the first electrode 7 and the second electrode 8, thus effectively preventing short circuits between the first electrode 7 and the second electrode 8 during use. The pixel electrode 1 is located on the side of the passivation layer 13 away from the first substrate 100, and the pixel electrode 1 is connected to the corresponding first electrode 7 of the TFT 3 through a via on the passivation layer 13.

[0101] The second substrate 2000 includes a second substrate 200 and a common electrode 2 located on the side of the second substrate 200 facing the first substrate 1000.

[0102] The liquid crystal layer 18 is a bistable liquid crystal layer. Specifically, the bistable liquid crystal layer includes a bistable liquid crystal material. For example, the bistable liquid crystal material can be a cholesteric liquid crystal (CLC) that has a bistable state.

[0103] Bistable cholesteric liquid crystals possess planar texture (P-state), focal conic texture (FC-state), and hometropic texture (H-state). The P-state and FC-state are stable states that do not require voltage maintenance, while the H-state is unstable and is exhibited under continuous power application. By applying voltage to the pixel electrode 1 of the pixel unit or applying pressure to the region where the pixel unit is located in different ways, the state of the liquid crystal in the region where the pixel unit is located can be controlled.

[0104] The LCD handwriting tablet has a writing function, and its working principle is as follows:

[0105] When the liquid crystal writing tablet is in its initial state, the liquid crystal is in the FC state. The helical axis of the liquid crystal in the FC state is randomly distributed, and the liquid crystal orientation is roughly parallel to the plane of the first substrate 100. The cholesteric liquid crystal in the FC state exhibits a multi-domain state, and the helical structure within each domain still exists, thus enabling it to scatter incident light; that is, the liquid crystal in the pixel unit can scatter incident light under zero electric field. A background structure 4 (e.g., a black PET film) is provided on the back of the liquid crystal writing tablet. At this time, the incident light will be scattered within the pixel unit and illuminate the surface of the background structure 4. Some of the light can be reflected on the surface of the background structure 4, and the reflected light passes through the pixel unit again and is backscattered, that is, the pixel unit presents the background color (e.g., black) in the initial state. Of course, in some cases, the background structure 4 may not be necessary, and the light transmitted from the bottom of the liquid crystal writing tablet (e.g., ambient light) can be used as the background color.

[0106] When a pixel unit is pressed using a touch object, the liquid crystal within the pixel unit enters a "P-state." Liquid crystal in the P-state has a periodic spiral structure, with its spiral axis substantially perpendicular to the plane of the first substrate 100. At this time, the liquid crystal in the P-state can selectively reflect light with a wavelength λ = p1 * n1, where p1 is the pitch and n1 is the equivalent refractive index of the liquid crystal; that is, the liquid crystal in the P-state can reflect light of a specific color (determined by the liquid crystal material, for example, green). The pixel unit then displays a specific color, i.e., it displays "handwriting."

[0107] When it is necessary to erase the "handwriting", the thin film transistor contained in the pixel unit in the erasure area is turned on and an initialization voltage is sent to the thin film transistor to charge the pixel electrode in the erasure area. An initialization electric field is formed between the pixel electrode 1 and the common electrode 2. Under the action of the initialization electric field, the liquid crystal re-presents the FC state, the pixel unit presents the background color, and the handwriting written in the erasure area can be erased.

[0108] It should be noted that, generally, to facilitate local erasure, each pixel unit is independently controlled by a thin-film transistor, which allows the erasure unit to be made smaller. When erasing an LCD handwriting tablet, the thin-film transistors in the erasure area need to be turned on, while those in the non-erasure area need to be turned off. At this time, the writing in the non-erasure area does not change, thus enabling local erasure of the LCD handwriting tablet.

[0109] In practical applications, it has been found that conductive foreign objects may exist within the liquid crystal layer 18. When the liquid crystal writing tablet is pressed, due to the relatively large size of both the pixel electrode 1 and the common electrode 2, these conductive foreign objects are highly susceptible to contact with both, leading to a short circuit between the pixel electrode 1 and the common electrode 2, and consequently, failure of the pixel unit at the corresponding location. To avoid this problem, in related technologies, an insulating protective layer 17 (generally made of inorganic insulating materials, such as silicon oxide or silicon nitride) is formed on the side of the pixel electrode 1 away from the substrate. The insulating protective layer 17 covers the pixel electrode 1, thereby preventing conductive foreign objects from contacting the pixel electrode 1 and thus preventing a short circuit between the pixel electrode 1 and the common electrode 2. However, the addition of the insulating protective layer 17 complicates the overall structure of the first substrate and increases the complexity of the first substrate fabrication process.

[0110] To address at least one of the technical problems existing in related technologies, this disclosure provides a novel liquid crystal handwriting tablet and its preparation method.

[0111] Figure 3 This is a cross-sectional schematic diagram of a portion of a liquid crystal handwriting tablet provided in an embodiment of this disclosure. Figure 4 This is a top view schematic diagram of a portion of the display area on the first substrate provided in an embodiment of this disclosure. Figure 5 for Figure 4 A schematic diagram of a cross-section along line A-A'. Figure 6 This is a schematic diagram of a circuit structure for a pixel unit in an embodiment of this disclosure, as shown below. Figures 3 to 6 As shown, the liquid crystal handwriting tablet includes: a first substrate 1000 and a second substrate 2000 disposed opposite to each other, and a bistable liquid crystal layer 18 located between the first substrate 1000 and the second substrate 2000.

[0112] The first substrate includes: a first substrate 100, a plurality of pixel units, a passivation layer 13, and spacers 15.

[0113] The first substrate 100 can be a rigid substrate, such as a glass substrate; or it can be a flexible substrate, such as a resin substrate. The first substrate 100 includes a display area and a peripheral area.

[0114] Multiple gate lines 9 and multiple data lines 10 are formed in the display area, defining multiple pixel units. The pixel units are located on one side of the first substrate 100. Each pixel unit includes a thin-film transistor 3 and a pixel electrode 1 electrically connected to the first electrode 7 of the thin-film transistor 3. Generally, the gate lines 9 are disposed on the same layer as the gate 5 of the thin-film transistor 3, and the data lines 10 are disposed on the same layer as the first electrode 7 and the second electrode 8 of the thin-film transistor 3.

[0115] In some embodiments, the line width of the gate line 9 is 3µm to 10µm; the line width of the data line 10 is 3µm to 10µm.

[0116] It should be noted that, in the embodiments of this disclosure, the two structures being arranged in the same layer means that the two structures can be fabricated simultaneously using the same patterning process based on the same material thin film. The distances between the two structures arranged in the same layer and the substrate may be equal or unequal.

[0117] Furthermore, the "patterning process" in this embodiment refers to processes including photoresist coating, exposure, development, thin film etching, and photoresist stripping. When the material thin film to be patterned is a material thin film with photoresist properties, the patterning of the material thin film can be completed by exposure and development steps alone.

[0118] The passivation layer 13 is located on the side of the thin film transistor 3 away from the first substrate 100 and is in contact with the thin film transistor 3; the pixel electrode 1 is located between the first substrate 100 and the passivation layer 13.

[0119] In some embodiments, the pixel electrode 1 may be made of a transparent conductive material; optionally, the transparent conductive material includes a metal oxide, such as indium tin oxide.

[0120] In some embodiments, the spacer 15 is located on the side of the passivation layer 13 away from the first substrate 100 and is in contact with the passivation layer 13. It is understood that the spacer 15 can be directly fabricated on the passivation layer 13 and provide support for the second substrate 2000.

[0121] In some embodiments, an isolation layer may be further included between the passivation layer 13 and the bistable liquid crystal layer 18. The material of the isolation layer may be, for example, polyimide (PI). The isolation layer may be located between the passivation layer 13 and the spacer 15; alternatively, the isolation layer may be prepared after the spacer 15 is prepared on the passivation layer 13, for example, the isolation layer may cover or partially cover the spacer 15. In some embodiments, the isolation layer may also be located on the second substrate 2000, for example, the isolation layer may be located between the second substrate 200 and the bistable liquid crystal layer 18. The isolation layer can further insulate the surface, better prevent short circuits caused by foreign objects, and improve product reliability.

[0122] In some embodiments, the spacer 15 may be fabricated on the second substrate 2000 and contact the first substrate 1000 to provide support; the spacer 15 may be in contact with the passivation layer 13. When the isolation layer is located between the passivation layer 13 and the bistable liquid crystal layer 18, the spacer 15 may be in contact with the isolation layer.

[0123] The spacer 15 has a circular, square, or polygonal (e.g., regular octagonal) cross-sectional shape parallel to the plane of the first substrate 100. In some embodiments, the cross-sectional area of ​​one end of the spacer 15 in contact with the passivation layer 13 is 100 μm. 2 ~225um 2 Within the range.

[0124] In this embodiment of the disclosure, since the pixel unit is large in size, in order to ensure the support reliability, it is necessary to place part of the spacer 15 in the area where the pixel electrode 1 is located; at this time, in order to avoid the spacer 15 blocking the light in the liquid crystal layer, a transparent resin material can be used to prepare the spacer 15.

[0125] With a fixed size of spacers, the density of the spacers affects the thickness of the handwriting. A higher density spacer makes it harder to press down on the writing surface, resulting in finer handwriting; conversely, a lower density spacer makes it easier to press down on the writing surface, resulting in thicker handwriting. Considering the thickness of the handwriting, in some embodiments, the density of the spacers is 100 spacers / mm². 2 ~500 pieces / mm 2 It can achieve a handwriting thickness range of 1mm to 5mm; it has been verified that the density of the spacer is 324 particles / mm. 2 At that time, the thickness of the handwriting was approximately 3mm.

[0126] Compared to the related technologies where the pixel electrode 1 is fabricated on the side of the passivation layer 13 away from the first substrate 100, in this embodiment, the pixel electrode 1 is disposed between the first substrate 100 and the passivation layer 13. In this case, at least one passivation layer 13 exists on the side of the pixel electrode 1 away from the first substrate 100. This passivation layer 13 can effectively cover the pixel electrode 1 to function as an insulating protective layer in the related technologies. Through the above design, the first substrate provided in this embodiment does not require a separate "insulating protective layer." Therefore, compared to the first substrate in the related technologies, the structure of the first substrate in this embodiment is simpler, and correspondingly, the structure of the liquid crystal writing tablet provided in this embodiment is simpler. Since the "insulating protective layer" is omitted structurally, the fabrication process of the insulating protective layer is eliminated during the fabrication of the first substrate, simplifying the fabrication process of the first substrate and consequently simplifying the overall fabrication process of the liquid crystal writing tablet.

[0127] In some embodiments, the passivation layer 13 on the first substrate 1000 is one and only one layer, which helps to simplify the process.

[0128] In some embodiments, the thin-film transistor 3 includes: a gate 5, an active layer 6, a first electrode 7 and a second electrode 8, wherein the first electrode 7 and the second electrode 8 are located on the side of the active layer 6 away from the first substrate 100; and a passivation layer 13 is in contact with the first electrode 7 and / or the second electrode 8.

[0129] In some embodiments, the width-to-length ratio of the channel in the active layer 6 ranges from 40:5 to 80:5. In some embodiments, the channel length is approximately 5 μm and the channel width is between 40 μm and 80 μm.

[0130] It should be noted that the thin-film transistor 3 in this embodiment can be not only the bottom-gate type thin-film transistor shown in the figure, but also, for example, a top-gate type or any other type of thin-film transistor. Furthermore, the pixel unit can include not only the aforementioned thin-film transistor, but also other structures, such as those other than... Figure 6 Other transistors besides thin-film transistors or capacitor structures. The technical solution disclosed herein does not limit the specific structure of the pixel unit or the specific structure of the thin-film transistor.

[0131] In some embodiments, the pixel electrode 1 is not in direct contact with the corresponding first electrode 7. Instead, the pixel electrode 1 is electrically connected to the corresponding first electrode 7 through a corresponding first conductive connection structure 12. The passivation layer 13 includes vias, and at least a portion of the first conductive connection structure 12 is located in the vias of the passivation layer 13. In some embodiments, the orthographic projection area of ​​the first conductive connection structure 12 on the first substrate 100 is smaller than the orthographic projection area of ​​the pixel electrode 1 connected to the first conductive connection structure 12 on the first substrate 100.

[0132] Optionally, the ratio of the projected area of ​​a first conductive connection structure 12 on the first substrate 100 to the projected area of ​​a connected pixel electrode 1 on the first substrate 100 is less than 1:100. Preferably, the ratio of the projected area of ​​a first conductive connection structure 12 on the first substrate 100 to the projected area of ​​a connected pixel electrode 1 on the first substrate 100 is less than 0.3:100. As an example, the projected area of ​​a pixel electrode 1 on the first substrate 100 is approximately 500um*500um to 4000um*4000um, and the projected area of ​​a first conductive connection structure 12 on the first substrate 100 is approximately 5um*5um to 50um*50um.

[0133] It should be noted that although the method of electrically connecting the pixel electrode 1 to the corresponding first electrode 7 using the first conductive connection structure 12 will allow the first conductive connection structure 12 to directly contact the liquid crystal in the liquid crystal layer after cell assembly, the area of ​​the first conductive connection structure 12 is extremely small (less than one percent of the area of ​​the pixel electrode 1). Therefore, the probability of conductive foreign objects coming into contact with both the first conductive connection structure 12 and the common electrode is extremely small, that is, the probability of a short circuit between the pixel electrode 1 and the common electrode is extremely small.

[0134] See also Figure 5 As shown, a first via 14a is formed on the passivation layer 13. The first via 14a connects the first electrode 7 and the pixel electrode 1 corresponding to the first electrode 7 to the surface of the passivation layer 13 away from the first substrate 100. At least a portion of the first conductive connection structure 12 is located in the first via 14a, and the first conductive connection structure 12 is in contact with the first electrode 7 and the pixel electrode 1 corresponding to the first electrode 7.

[0135] Furthermore, when designing the position of the first via 14a, the contact area between the first conductive connection structure 12 and the first electrode 7 and the pixel electrode 1 must also be considered. Optionally, the first conductive connection structure 12 and the first electrode 7 have a first contact area, and the first conductive connection structure 12 and the pixel electrode 1 have a second contact area, wherein the first contact area and the second contact area are equal or approximately equal.

[0136] The first via 14a can be a circular via, a square via, a polygonal via, etc. This disclosure does not limit the specific shape of the first via 14a.

[0137] In some embodiments, the orthographic projection of the first conductive connection structure 12 onto the first substrate 100 overlaps with the orthographic projection of the first via 14a onto the first substrate 100. That is, all the first conductive connection structures 12 are located within the corresponding first vias 14a, and there are no first conductive connection structures 12 on the side of the passivation layer 13 away from the first substrate 100. This design allows the size of the first conductive connection structure 12 to be as small as possible, which helps to reduce the probability of the first conductive connection structure 12 coming into contact with conductive foreign matter.

[0138] Figure 7 This is another top view schematic diagram of a portion of the display area on the first substrate provided in an embodiment of this disclosure. Figure 8A for Figure 7 A schematic diagram of a cross-section along the B-B' direction. Figure 8B for Figure 7 A magnified view of a portion of the Q region, as shown below. Figures 7 to 8BAs shown, in some embodiments, a second via group is formed on the passivation layer 13. The second via group includes at least two second vias 14b. At least one second via 14b in the second via group is connected to the first electrode 7 from the surface of the passivation layer 13 away from the first substrate 100. At least one second via 14b in the second via group is connected to the pixel electrode 1 corresponding to the first electrode 7 from the surface of the passivation layer 13 away from the first substrate 100. A first conductive connection structure 12 corresponds one-to-one with the second via group. The first conductive connection structure 12 includes at least two first conductive connection substructures and second conductive connection substructures. The first conductive connection substructure corresponds one-to-one with the second via 14b in the corresponding second via group. The first conductive connection substructure is located in the corresponding second via 14b and is in contact with the first electrode 7 or the pixel electrode 1. The second conductive connection substructure is located on the side of the passivation layer 13 away from the first substrate 100 and is connected to the first conductive connection substructure.

[0139] exist Figure 4 and Figure 5 In the scheme shown for opening the first via 14a, the first via 14a needs to be located in the edge region of the first electrode 7 to ensure that the first via 14a can connect to both the first electrode 7 and the pixel electrode 1. Compared to Figure 4 and Figure 5 The scheme of opening the first via 14a in the middle, in Figure 7 The second via group scheme shown in Figure 8 offers greater flexibility in the placement of the second vias 14b. However, since a second conductive connector must be placed above the first passivation layer 13, the total cross-sectional area of ​​all second vias 14b in a second via group is equal to... Figure 4 and Figure 5 The cross-sectional area of ​​the first through hole 14a, and Figure 4 and Figure 5 When the first conductive connection structure 12 is entirely located within the first via 14a, Figure 7 The cross-sectional area of ​​the first conductive connection structure 12 in Figure 8 is greater than that of the first conductive connection structure 12 in Figure 8. Figure 4 and Figure 5 The cross-sectional area of ​​the first conductive connection structure 12.

[0140] Furthermore, since the first via 14a needs to connect to both the first electrode 7 and the pixel electrode 1, while the second via 14b only needs to connect to either the first electrode 7 or the pixel electrode 1, the cross-sectional area of ​​the second via 14b is smaller than that of the first via 14a. Because the second via 14b is relatively small, it can effectively fill the second via 14b during the fabrication of the first conductive connection structure 12. The cell thickness in the area where the second via 14b is located is essentially the same as the standard cell thickness in the area where the second via 14b is not located. In other words, the light output brightness in the area where the second via 14b is present is essentially the same as that in the area where the second via 14b is not present. Therefore, compared to... Figure 4 and Figure 5 Medium pixel unit, Figure 7 The uniformity of light output brightness within the area where the pixel unit is located, as shown in Figure 8, will be better.

[0141] In practical applications, the smaller the contact area between the first conductive connection structure and the pixel electrode 1 or the first electrode 7, the smaller the required size of the first via 14a / second via 14b. However, the greater the resistance of the portion located within the first via 14a / second via 14b, the greater the power consumption of the portion of the first conductive connection structure located within the first via 14a / second via 14b, given a constant average current (typically around 37mA) during single pixel charging and erasing. Conversely, the larger the contact area between the first conductive connection structure and the pixel electrode 1 or the first electrode 7, the larger the required size of the first via 14a / second via 14b. This also leads to a larger size of the first conductive connection structure itself, increasing the likelihood of conductive foreign objects interacting with the first conductive connection. The probability of contact between the 12 phases of the electrical connection structure increases. In addition, since the liquid crystal cell thickness (Gap) in the area where the first via 14a / second via 14b is located is greater than the liquid crystal cell thickness in the area where the first via 14a / second via 14b is not located, the liquid crystal cell thickness in the area where the first via 14a / second via 14b is not located is taken as the standard cell thickness. Then the liquid crystal cell thickness in the area where the first via 14a / second via 14b is located is an abnormal cell thickness. The brightness of the reflected light in the standard cell thickness area and the abnormal cell thickness area are different. At this time, the larger the size of the first via 14a / second via 14b, the larger the abnormal cell thickness area, the worse the uniformity of the liquid crystal cell thickness, and the worse the uniformity of the emitted light brightness in the area where the pixel unit is located.

[0142] Based on the above considerations, in some embodiments, the material of the first conductive connection structure 12 includes a transparent conductive material, which includes a metal oxide (e.g., indium tin oxide). The sum of the contact area between the first conductive connection structure 12 and the connected first electrode 7 is less than 100 μm. 2 Within the range of ~400um², the sum of the contact surface areas between the first conductive connection structure 12 and the connected pixel electrode 1 is within 100um. 2~400um 2 Within the range.

[0143] As an example, when the material of the first conductive connection structure 12 is a transparent conductive metal oxide material, Figure 4 and Figure 5 In the illustrated scheme, one first via 14a corresponds to one pixel unit, and the cross-sectional area of ​​the first via 14a is 200µm. 2 ~800um 2 The cross-sectional area of ​​the portion connecting the bottom to the first pole 7 is 100 μm. 2 ~400um 2 The cross-sectional area of ​​the portion connected to pixel electrode 1 is 100µm. 2 ~400um 2 .

[0144] As an example, when the material of the first conductive connection structure 12 is a transparent conductive metal oxide material, Figure 7 In the scheme shown in Figure 8, each pixel unit corresponds to eight second vias 14b, of which four second vias 14b are connected to the pixel electrode 1, and the other four first vias 14b are connected to the first electrode 7. The cross-sectional area at the bottom of each first via is 25 μm. 2 ~100um 2 .

[0145] In other embodiments, the material of the first conductive connection structure 12 includes a metallic material (e.g., aluminum, molybdenum). Since the conductivity of metals is superior to that of metal oxides, the contact area between the first conductive connection structure 12 and the first electrode 7 and the pixel electrode can be relatively small. Specifically, the sum of the contact area between the first conductive connection structure 12 and the connected first electrode 7 is less than 0.25 μm. 2 ~2.25um 2 Within the range; the sum of the contact surface areas between the first conductive connection structure 12 and the connected pixel electrode 1 is within 0.25 μm. 2 ~2.25um 2 Within the range.

[0146] Since the light transmittance of metallic materials is inferior to that of transparent conductive materials, when the first conductive connection structure is made of metallic materials, the first conductive connection structure will block the light directed toward the background structure to a certain extent, affecting the display effect of the pixel unit when presenting the background color.

[0147] It should be noted that, Figure 4 The example only shows one pixel unit corresponding to one first via 14a; Figure 7The illustration shows a pixel unit corresponding to a second via 14b, where four of the second vias 14b are connected to the first electrode 7 and the other four are connected to the pixel electrode 1. The above illustration is only for reference and does not limit the technical solution of this disclosure.

[0148] As one aspect, in actual production lines, due to process fluctuations during the etching process of the passivation layer 13 (the actual position of the second via 14b will deviate from the design position), and the alignment error between the first conductive connection structure 12 and the passivation layer 13 during the fabrication process of the first conductive connection structure 12, there may be situations where the first conductive connection structure 12 cannot completely cover one or more of the second vias 14b, resulting in product defects.

[0149] To effectively address the aforementioned technical problems, in some embodiments, for any second via 14b within the second via group, the second via 14b has a first orthographic projection on the first substrate 100, and the first conductive connection structure 12 corresponding to the second via 14b has a second orthographic projection on the first substrate 100. During the design phase, the first orthographic projection is located within the area covered by the second orthographic projection, and the distance from any point on the edge of the first orthographic projection to any point on the edge of the second orthographic projection is greater than or equal to 2.5 μm. In actual manufacturing, this design ensures that even with fluctuations in the etching process of the passivation layer 13 and alignment errors between the first conductive connection structure 12 and the passivation layer 13, the first conductive connection structure 12 can still completely cover all the second vias 14b. Verification showed that when the distance from any point on the edge of the first orthographic projection to any point on the edge of the second orthographic projection was designed to be greater than or equal to 2.5 μm during the design phase, the distance L1 from any point on the edge of the first orthographic projection to any point on the edge of the second orthographic projection in the actual manufactured product was greater than or equal to 1 μm. This means that there is still a certain gap between the edges of the first and second orthographic projections, which can cope with larger passivation layer etching process fluctuations and larger alignment errors, and is conducive to improving the yield of the production line.

[0150] On the other hand, in actual production lines, due to process fluctuations during the etching process of the passivation layer 13 and the alignment error between the passivation layer 13 and the first electrode 7, one or more second vias 14b that need to be connected to the first electrode 7 may no longer be located in the area where the first electrode 7 is located. This can lead to an abnormal connection between the subsequently formed first conductive connection structure 12 and the first electrode 7, resulting in product defects.

[0151] To effectively address the aforementioned technical issues, in some embodiments, for any second via 14b connected to the first electrode 7 within the second via group, the second via 14b has a third orthographic projection on the first substrate 100, and the first electrode 7 corresponding to the second via 14b has a fourth orthographic projection on the first substrate 100. During the design phase, the third orthographic projection is located within the area covered by the fourth orthographic projection, and the distance from any point on the edge of the third orthographic projection to any point on the edge of the fourth orthographic projection is greater than or equal to 2.5 μm. In actual manufacturing, this design ensures that, even with fluctuations in the etching process of the passivation layer 13 and alignment errors between the passivation layer 13 and the first electrode 7, all second vias 14b connected to the first electrode 7 are located within the area of ​​the first electrode 7, thereby guaranteeing the reliability of the connection between the subsequently formed first conductive connection structure 12 and the first electrode 7. Verification showed that when the distance from any point on the edge of the third orthographic projection to any point on the edge of the fourth orthographic projection is greater than or equal to 2.5 μm during the design phase, the distance L2 from any point on the edge of the third orthographic projection to any point on the edge of the fourth orthographic projection in the actual manufactured product is greater than or equal to 1 μm. This means that there is still a certain gap between the edges of the third and fourth orthographic projections, which can cope with larger fluctuations in the passivation layer etching process and larger alignment errors, and is beneficial to improving the yield of the production line.

[0152] As another aspect, in actual production lines, due to process fluctuations during the etching process of the passivation layer 13 and the alignment error between the passivation layer 13 and the pixel electrode 1, one or more second vias 14b that need to be connected to the pixel electrode 1 may no longer be located in the area where the pixel electrode 1 is located. This can lead to an abnormal connection between the subsequently formed first conductive connection structure 12 and the pixel electrode 1, resulting in product defects.

[0153] To effectively address the aforementioned technical issues, in some embodiments, for any second via 14b connected to the pixel electrode 1 within the second via group, the second via 14b has a fifth orthographic projection on the first substrate 100, and the pixel electrode 1 corresponding to the second via 14b has a sixth orthographic projection on the first substrate 100. During the design phase, the fifth orthographic projection is located within the area covered by the sixth orthographic projection, and the distance from any point on the edge of the fifth orthographic projection to any point on the edge of the sixth orthographic projection is greater than or equal to 2.5 μm. In actual manufacturing, this design ensures that, in the event of fluctuations in the etching process of the passivation layer 13 or alignment errors between the passivation layer 13 and the pixel electrode 1, all second vias 14b connected to the pixel electrode 1 are located within the area where the pixel electrode 1 is situated, thereby guaranteeing the reliability of the connection between the subsequently formed first conductive connection structure 12 and the pixel electrode 1. Verification showed that when the distance from any point on the edge of the fifth orthographic projection to any point on the edge of the sixth orthographic projection is greater than or equal to 2.5 μm during the design phase, the distance L3 from any point on the edge of the fifth orthographic projection to any point on the edge of the sixth orthographic projection in the actual manufactured product is greater than or equal to 1 μm. This means that there is still a certain gap between the edges of the fifth and sixth orthographic projections, which can cope with larger fluctuations in the passivation layer etching process and larger alignment errors, and is beneficial to improving the yield of the production line.

[0154] In some embodiments, the material of the first conductive connection structure 12 includes a transparent conductive material. The transparent conductive material may be a metal oxide material, such as indium tin oxide.

[0155] See Figure 5 and Figure 8A As shown, in some embodiments, the gate 5 is located on the side of the active layer 6 near the first substrate 100, a gate insulating layer 16 is formed between the gate 5 and the active layer 6, and the pixel electrode 1 is located between the gate insulating layer 16 and the first substrate 100.

[0156] In some embodiments, the number of gate insulating layers 16 on the first substrate 1000 is one and only one.

[0157] Furthermore, in Figure 5 and Figure 8A In the illustrated scheme, the pixel electrode 1 is located on the side of the gate 5 near the first substrate 100.

[0158] In some embodiments, the first substrate includes a first conductive layer 1a and a second conductive layer, the second conductive layer being located on the side of the first conductive layer 1a away from the first substrate 100; the first conductive layer 1a includes a pixel electrode 1 and a first conductive structure disposed in the same layer as the pixel electrode 1 (e.g., a portion located directly below the gate line 9, a portion located directly below the gate 5); the second conductive layer includes the gate 5 and a second conductive structure disposed in the same layer as the gate 5 (e.g., the gate line 9); the orthographic projection of the first conductive layer 1a on the first substrate 100 covers the orthographic projection of the second conductive layer on the first substrate 100.

[0159] In this embodiment, when the pixel electrode 1 is disposed on the side of the gate 5 close to the first substrate 100, the pixel electrode 1 and the gate 5 can be fabricated in a single mask process based on a half-tone mask (HTM) patterning process. This reduces the number of mask processes during the first substrate fabrication process and helps to lower production costs. For the process of fabricating the pixel electrode 1 and the gate 5 using a half-tone mask patterning process, please refer to the following description.

[0160] Figure 9A and Figure 9B These are two other cross-sectional schematic diagrams of a portion of the display area on the first substrate in this embodiment of the present disclosure, such as... Figure 9A and Figure 9B As shown, with Figure 5 and Figure 8A The pixel electrode 1 shown is located on the side of the gate 5 closer to the first substrate 100, which is different from the case where the pixel electrode 1 is located on the side of the gate 5 closer to the first substrate 100. Figure 9A and Figure 9B In the illustrated scheme, both pixel electrode 1 and gate electrode 5 are in contact with the first substrate 100. The pixel electrode and gate electrode are fabricated using different materials; for example, the pixel electrode is made of a transparent conductive material (e.g., metal oxide), and the gate electrode is made of a metal material. Therefore, pixel electrode 1 and gate electrode 5 need to be fabricated separately using different patterning processes (requiring the use of different masks).

[0161] Figure 10A and Figure 10B These are two more cross-sectional schematic diagrams of a portion of the display area on the first substrate in this embodiment of the present disclosure, such as... Figure 10A and Figure 10B As shown, in some embodiments, the pixel electrode and the gate are disposed in the same layer, that is, the pixel electrode and the gate are fabricated based on the same material thin film (e.g., a metal material thin film). In this case, the pixel electrode can be fabricated simultaneously based on the existing gate fabrication process, which helps to reduce the number of masking processes.

[0162] It should be noted that when the pixel electrode is made of metal, it can be reused as a background structure to reflect light, so there is no need to add an additional background structure.

[0163] Figure 11 and Figure 12 These are two more cross-sectional schematic diagrams of a portion of the display area on the first substrate in an embodiment of this disclosure, as shown below. Figure 11 and Figure 12 As shown, with Figure 5 , Figures 8A to 10B The pixel electrode 1 shown is located between the gate insulating layer 16 and the first substrate 100, which is different from the case shown. Figure 11 and Figure 12 In the scheme shown, the pixel electrode 1 is located between the gate insulating layer 16 and the passivation layer 13.

[0164] Figure 13A This is a cross-sectional schematic diagram of a portion of the display area and peripheral area of ​​the first substrate in an embodiment of this disclosure, such as... Figure 13A As shown, in some embodiments, the first substrate further includes a plurality of pads 21 located in the peripheral region. The pads 21 are disposed on the same layer as the gate 5 of the thin-film transistor 3. A third via 14c is formed on the passivation layer 13, connecting the side surface of the passivation layer 13 away from the first substrate 100 to the pads 21. The metal pointer on the flexible printed circuit (FPC) can be bonded to the pads 21 through the third via 14c.

[0165] It should be noted that when the pixel electrode 1 and the gate 5 are fabricated using a halftone mask patterning process, since the pad 21 and the gate 5 are set on the same layer, there is also a part set on the same layer as the pixel electrode below the pad 21.

[0166] In practical applications, it was found that the metal pointer on the FPC can only contact the pad 21 located at the bottom of the third via 14c through the lower surface. The contact area is relatively small, and the bonding reliability is not high.

[0167] Figure 13B This is a cross-sectional schematic diagram of a portion of the display area and peripheral area of ​​the first substrate in an embodiment of this disclosure, such as... Figure 13BAs shown, to effectively improve the above-mentioned technical problems, in this embodiment, a second conductive connection structure 22 is formed on the sidewall of the third via 14c and on the surface of the pad 21 away from the first substrate 100. In this case, the second conductive connection structure 22 can be tightly connected to the pad 21 below. When the metal pointer on the FPC is bonded to the first substrate, the metal pointer can contact not only the second conductive connection structure 22 located at the bottom of the third via 14c, but also the second conductive connection structure 22 located on the sidewall of the third via 14c, thereby increasing the contact area of ​​the metal pointer and effectively improving the bonding reliability.

[0168] In some embodiments, when a first conductive connection structure 12 exists on the first substrate 1000, a second conductive connection structure 22 is disposed in the same layer as the first conductive connection structure 12. In this case, the first conductive connection structure 12 and the second conductive connection structure can be fabricated simultaneously based on the same patterning process, which is beneficial to reduce the number of fabrication process steps.

[0169] It should be noted that, Figure 13A and Figure 13B The image only shows the pixel units within the display area as an example. Figure 8A As shown, this situation is for illustrative purposes only; in this embodiment of the disclosure, Figure 13A and Figure 13B Other schemes may be used for the pixel units in the central display area, and this disclosure does not limit them.

[0170] Figure 14 This is another cross-sectional schematic diagram of a portion of the display area on the first substrate in an embodiment of this disclosure, as shown below. Figure 14 As shown, unlike the previous embodiment where the pixel electrode 1 is not in contact with the corresponding first electrode 7, but is electrically connected to the corresponding first electrode 7 through the first conductive connection structure 12, in... Figure 14 In the scheme shown, pixel electrode 1 is in direct contact with the corresponding first electrode 7.

[0171] In some embodiments, a portion of the pixel electrode 1 overlaps with the corresponding first electrode 7 on the side surface away from the first substrate 100.

[0172] See also Figure 5 , Figures 8A to 14As shown, in some embodiments, the orthographic projection of the active layer 6 onto the first substrate 100 overlaps the orthographic projections of the first electrode 7 and the second electrode 8 onto the first substrate 100. This design allows the active layer 6, the first electrode 7, and the second electrode 8 to be fabricated in a single mask process using a halftone mask patterning technique. This reduces the number of mask processes required in the first substrate fabrication process, thus lowering production costs. For details on the process of fabricating the active layer 6, the first electrode 7, and the second electrode 8 using a halftone mask patterning technique, please refer to the following description.

[0173] exist Figure 14 In the scheme shown, in order to reduce the number of MASK processes, the halftone mask patterning process is used to prepare the active layer 6, the first electrode 7, and the second electrode 8. This will cause the side surfaces of the first electrode 7 and the second electrode 8 facing the first substrate 100 to always be in contact with the active layer 6. Therefore, the pixel electrode 1 cannot be set to be in contact with the side surface of the first electrode 7 facing the first substrate 100.

[0174] Figure 15A and Figure 15B This is another cross-sectional schematic diagram of a portion of the display area on the first substrate in an embodiment of this disclosure, as shown below. Figure 15A and Figure 15B As shown, without considering reducing the number of masking processes, the active layer 6 and the first electrode 7 can be fabricated using different masking processes. In this case, the pixel electrode 1 and the surface of the first electrode 7 facing the first substrate 100 can be brought into contact, that is, a portion of the first electrode 7 overlaps on the surface of the pixel electrode 1 away from the first substrate 100. Figure 15A (as shown); or, the first electrode 7 contacts the side of the pixel electrode 1 away from the first substrate 100 through a via on the gate insulating layer 16. Figure 15B (as shown in the image).

[0175] Figure 16 A cross-sectional schematic diagram of a portion of the liquid crystal handwriting tablet provided in an embodiment of this disclosure, such as... Figure 16 As shown, the liquid crystal writing tablet includes a first substrate and a second substrate disposed opposite to the first substrate, with a liquid crystal layer disposed between the first substrate and the second substrate. The first substrate may be the same as the one described in the previous embodiments; for a detailed description of the first substrate, please refer to the content in the previous embodiments, which will not be repeated here.

[0176] The second substrate includes a second substrate 200 and a common electrode 2 located on the side of the second substrate 200 facing the first substrate.

[0177] In some embodiments, the second substrate 200 is a flexible substrate. Therefore, when external pressure is applied, the force is more easily transmitted to the bistable liquid crystal layer, which is beneficial for improving the writing effect of the liquid crystal writing tablet. Specifically, the material of the second substrate 200 includes PET, such as a PET film.

[0178] In some embodiments, a background structure 4 is provided on the side of the first substrate 1000 away from the second substrate 2000 or on the side of the second substrate away from the first substrate.

[0179] Optionally, the background structure 4 includes a background film 51 (e.g., a black PET film) with a preset background color, so that the LCD handwriting tablet presents the preset background color in the initial state.

[0180] In some embodiments, when the background film 51 is a semi-permeable film, a reflective film 52 (e.g., a silver film) is provided on the side of the background film 51 away from the first substrate. The reflective film 52 can reflect the light transmitted through the background film 51, and part of the reflected light can be transmitted through the background film 51 and then scattered again by the pixel unit, thereby further improving the background brightness.

[0181] Based on the same inventive concept, this disclosure also provides a method for preparing a liquid crystal handwriting tablet, which can be used to prepare the liquid crystal handwriting tablet provided in the previous embodiments.

[0182] Figure 17A This is a flowchart illustrating a method for manufacturing a liquid crystal handwriting tablet according to an embodiment of the present disclosure. Figure 17B This is a flowchart of a method for preparing a first substrate according to an embodiment of this disclosure, as shown below. Figure 17A and Figure 17B As shown, the method for manufacturing this liquid crystal handwriting tablet includes:

[0183] Sa, respectively prepares the first substrate and the second substrate.

[0184] Sb, The first substrate and the second substrate are aligned, and a bistable liquid crystal layer is formed between the first substrate and the second substrate.

[0185] See Figure 17B As shown, step Sa includes:

[0186] Step S1: Provide a first substrate.

[0187] Step S2: A plurality of pixel units are formed on one side of the first substrate. Each pixel unit includes a thin-film transistor and a pixel electrode electrically connected to the first electrode of the thin-film transistor.

[0188] Step S3: A passivation layer is formed on the side of the thin-film transistor and pixel electrode away from the first substrate, and the passivation layer is in contact with the thin-film transistor.

[0189] Step S4: A spacer is formed on the side of the passivation layer away from the first substrate, and the spacer is in contact with the passivation layer.

[0190] In this embodiment, the pixel electrode is disposed between the first substrate and the passivation layer. At least one passivation layer exists on the side of the pixel electrode away from the first substrate, effectively covering the pixel electrode to function as an insulating protective layer in related technologies. Through this design, the first substrate provided in this embodiment does not require a separate "insulating protective layer," thus its structure is simpler than that of the first substrate in related technologies. Since the "insulating protective layer" is omitted, the fabrication process of the insulating protective layer is eliminated during the fabrication of the first substrate, simplifying the fabrication process of the first substrate and consequently simplifying the overall fabrication process of the liquid crystal writing tablet.

[0191] Figure 18 This is a flowchart of an optional implementation method of step S2 in the embodiments of this disclosure, such as... Figure 18 As shown, in some embodiments, step S2 includes:

[0192] Step S201: Forming pixel electrodes and forming gate electrodes.

[0193] Step S202: Form a gate insulating layer on the side of the gate away from the first substrate.

[0194] Step S202: Forming an active layer and forming the first and second electrodes.

[0195] Figure 19 This is a flowchart of an optional implementation method of step S201 in the embodiments of this disclosure, such as... Figure 19 As shown, in some embodiments, step S201 includes:

[0196] Step S2011: Form a first conductive material thin film.

[0197] A first conductive material thin film can be formed on one side of a first substrate through a deposition process. Optionally, the first conductive material includes a transparent conductive material, such as indium tin oxide.

[0198] Step S2012: A second conductive material film is formed on the side of the first conductive material film away from the first substrate.

[0199] The second conductive material film can be formed on the side of the first conductive material film away from the first substrate by a deposition process. Optionally, the second conductive material includes a metallic material or alloy, such as aluminum or molybdenum.

[0200] Step S2013: The first conductive material thin film and the second conductive material thin film are patterned using a halftone mask patterning process to obtain the pattern of the first conductive layer and the pattern of the second conductive layer.

[0201] Figure 20 This is a schematic diagram of a process flow for fabricating gate and pixel electrodes using a halftone mask patterning process in an embodiment of this disclosure, as shown below. Figure 20 As shown, firstly, a first photoresist 33 is coated on the side of the second conductive material film 32 away from the first substrate; then, the first photoresist 33 is exposed using a halftone mask; next, the first photoresist 33 is developed using a developer, at which point the portion of the first photoresist 33 located in the area where the pattern to be formed of the second conductive layer is subsequently formed is completely preserved, the portion of the first photoresist 33 located in the area where the pattern to be formed of the pixel electrode is subsequently formed is partially preserved (thickness reduction), and the first photoresist 33 located in other areas is completely removed; then, the second conductive material film 32 and the first conductive material film 33 are further processed. The photoresist 31 is etched to obtain the pattern of the first conductive layer and the semi-finished pattern of the second conductive layer. Then, the first photoresist 33 is ashed so that part of the area where the pattern of the second conductive layer is to be formed is partially retained (thickness reduction), and the part of the first photoresist 33 located in the pattern where the pixel electrode is to be formed is partially and completely removed. Then, the semi-finished pattern of the second conductive layer is further etched to remove the second conductive material covering the surface of the pixel electrode, so as to obtain the final pattern of the second conductive layer. Finally, the remaining first photoresist 33 is stripped.

[0202] The pattern of the first conductive layer includes a pixel electrode 1 and a first conductive structure disposed in the same layer as the pixel electrode 1 (e.g., the portion located directly below the gate line, the portion located directly below the gate). The pattern of the second conductive layer includes a gate 5 and a second conductive structure disposed in the same layer as the gate 5 (e.g., gate line, pad). The orthographic projection of the first conductive layer on the first substrate covers the orthographic projection of the second conductive layer on the first substrate.

[0203] Figure 21 This is a flowchart of an optional implementation method of step S203 in an embodiment of this disclosure, such as... Figure 21 As shown, in some embodiments, step S203 includes:

[0204] Step S2031: Form an active material thin film.

[0205] In this process, a thin film of active material can be formed on the side of the gate insulating layer away from the substrate through a deposition process. Optionally, the active material includes semiconductor materials such as amorphous silicon, polycrystalline silicon, or metal oxides.

[0206] Step S2032: A third conductive material thin film is formed on the side of the active material thin film away from the first substrate.

[0207] A third conductive material film can be formed on the side of the active material film away from the first substrate using a deposition process. Optionally, the third conductive material includes a metallic material or alloy, such as aluminum or molybdenum.

[0208] Step S2033: The active material thin film and the third conductive material thin film are patterned using a halftone mask patterning process to obtain the patterns of the active layer and the third conductive layer.

[0209] Figure 22 This is a schematic diagram of a process flow for fabricating an active layer, a first electrode, and a second electrode using a halftone mask patterning process in an embodiment of this disclosure, as shown below. Figure 22 As shown, firstly, a second photoresist 43 is coated on the side of the third conductive material film 42 away from the first substrate; then, the second photoresist 43 is exposed using a halftone mask; next, the second photoresist 43 is developed using a developer, at which point the portion of the second photoresist 43 in the area where the pattern to be formed of the third conductive layer is subsequently formed is completely preserved, the portion of the second photoresist 43 in the channel area where the active layer is subsequently formed is partially preserved (thickness reduction), and the second photoresist 43 in other areas is completely removed; then, the third... The conductive material film 42 and the active material film 41 are etched respectively to obtain the pattern of the active layer 6 and the semi-finished pattern of the third conductive layer. Then, the second photoresist 43 is ashed, so that part of the area where the pattern of the third conductive layer will be formed is partially retained (thickness reduction), and the part of the second photoresist 43 located in the channel region of the active layer is partially and completely removed. Then, the semi-finished pattern of the third conductive layer is further etched to remove the second conductive material covering the surface of the pixel electrode, so as to obtain the final pattern of the second conductive layer. Finally, the remaining second photoresist 43 is stripped.

[0210] The third conductive layer includes a first electrode 7, a second electrode 8, and a third conductive structure (e.g., a data line) disposed in the same layer as the first electrode 7 and the second electrode 8. The orthogonal projection of the active layer 6 on the first substrate 100 covers the orthogonal projection of the first electrode 6 and the second electrode 7 on the first substrate 100.

[0211] Figure 23 This is a flowchart of a method for fabricating a first substrate provided in an embodiment of the present disclosure, as shown below. Figure 23As shown, when the first substrate includes a first conductive connection structure, there will be a via (such as the first via or the second via described in the previous embodiment) in step S3 that connects to the first pole and / or the second pole. Step S4a is also included between step S3 and step S4. Only step S4a will be described in detail below.

[0212] Step S4a: Form a first conductive connection structure. The pixel electrode is electrically connected to the corresponding first electrode through the corresponding first conductive connection structure. At least a portion of the first conductive connection structure is located in the via of the passivation layer.

[0213] Of course, when the peripheral area of ​​the first substrate is provided with a second conductive connection structure, the second conductive connection structure will also be formed simultaneously in step S4a.

[0214] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A liquid crystal handwriting tablet, comprising: A first substrate and a second substrate, and a bistable liquid crystal layer located between the first substrate and the second substrate, wherein the first substrate includes; First substrate; A plurality of pixel units are located on the side of the first substrate near the second substrate, the pixel unit comprising: a thin film transistor and a pixel electrode electrically connected to a first electrode of the thin film transistor; A passivation layer is located on the side of the thin-film transistor away from the first substrate and in contact with the thin-film transistor; the pixel electrode is located between the first substrate and the passivation layer. A spacer is located on the side of the passivation layer away from the first substrate and is in contact with the passivation layer; The second substrate includes: a second substrate and a common electrode located on the side of the second substrate facing the first substrate; The thin-film transistor includes: a gate, an active layer, a first electrode, and a second electrode, wherein the first electrode and the second electrode are located on the side of the active layer away from the first substrate; the passivation layer is in contact with the first electrode and / or the second electrode; the gate is located on the side of the active layer close to the first substrate, and a gate insulating layer is formed between the gate and the active layer; The pixel electrode is located between the gate insulating layer and the passivation layer, and the pixel electrode is in direct contact with the corresponding first electrode; or, the pixel electrode is located between the gate insulating layer and the first substrate, and the first electrode is in contact with the side surface of the pixel electrode away from the first substrate through a via on the gate insulating layer. The pixel electrode is completely insulated from the liquid crystal layer by the passivation layer; The LCD handwriting tablet also includes: Multiple pads are located in the peripheral area of ​​the liquid crystal handwriting board, and the pads are disposed on the same layer as the gate of the thin film transistor; A third via is formed on the passivation layer, which communicates with the pad. A second conductive connection structure is formed on the sidewall of the third via and on the surface of the pad away from the first substrate. The liquid crystal writing tablet further includes a background structure disposed on the side of the first substrate away from the second substrate or on the side of the second substrate away from the first substrate; the background structure includes a background film with a preset background color, so that the liquid crystal writing tablet presents the preset background color in the initial state; When the background film is a semi-transparent film, the liquid crystal handwriting tablet also includes a reflective film on the side of the background film away from the first substrate.

2. The liquid crystal handwriting tablet according to claim 1, wherein, The first substrate includes a first conductive layer and a second conductive layer, wherein the second conductive layer is located on the side of the first conductive layer away from the first substrate. The first conductive layer includes a first conductive structure; The second conductive layer includes the gate and a second conductive structure disposed in the same layer as the gate; The orthographic projection of the first conductive layer on the first substrate covers the orthographic projection of the second conductive layer on the first substrate.

3. The liquid crystal handwriting tablet according to claim 1, wherein, The pixel electrode is partially attached to the surface of the corresponding first electrode on the side away from the first substrate.

4. The liquid crystal handwriting tablet according to any one of claims 1 to 3, wherein, The orthographic projection of the active layer on the first substrate covers the orthographic projections of the first electrode and the second electrode on the first substrate.

5. The liquid crystal handwriting tablet according to any one of claims 1 to 3, wherein, The density of the spacers is 100 per mm. 2 ~500 pieces / mm 2 .

6. The liquid crystal handwriting tablet according to any one of claims 1 to 3, wherein, The second substrate is a flexible substrate.

7. A method for preparing a liquid crystal handwriting tablet as described in any one of claims 1 to 6, wherein, include: The first substrate and the second substrate are prepared separately; The first substrate and the second substrate are aligned, and a bistable liquid crystal layer is formed between the first substrate and the second substrate. The steps for preparing the first substrate include: Provide a first substrate; A plurality of pixel units are formed on one side of the first substrate. Each pixel unit includes a thin-film transistor and a pixel electrode electrically connected to a first electrode of the thin-film transistor. The pixel electrode is in direct contact with the corresponding first electrode. A passivation layer is formed on the side of the thin-film transistor and the pixel electrode away from the first substrate. The passivation layer is in contact with the thin-film transistor. The thin-film transistor includes: a gate, an active layer, a first electrode, and a second electrode. The first electrode and the second electrode are located on the side of the active layer away from the first substrate. The passivation layer is in contact with the first electrode and / or the second electrode. The gate is located on the side of the active layer close to the first substrate. A gate insulating layer is formed between the gate and the active layer. The pixel electrode is located between the gate insulating layer and the passivation layer, and the pixel electrode is in direct contact with the corresponding first electrode. Alternatively, the pixel electrode is located between the gate insulating layer and the first substrate, and the first electrode is in contact with the surface of the pixel electrode away from the first substrate through a via on the gate insulating layer. The pixel electrode is completely insulated from the liquid crystal layer by the passivation layer; A spacer is formed on the side of the passivation layer away from the first substrate, and the spacer is in contact with the passivation layer; The steps for preparing the second substrate include: Provide a second substrate; A common electrode is formed on the side of the second substrate facing the first substrate; It also includes: when forming the gate, forming a plurality of pads in the peripheral region, wherein the pads are disposed in the same layer as the gate of the thin-film transistor; A third via is formed on the passivation layer, communicating with the pad, and a second conductive connection structure is formed on the sidewall of the third via and the surface of the pad away from the first substrate. It also includes: forming a background structure on the side of the first substrate away from the second substrate or on the side of the second substrate away from the first substrate; the background structure includes a background film with a preset background color, so that the liquid crystal writing tablet displays the preset background color in the initial state; When the background film is a semi-permeable film, a reflective film is formed on the side of the background film away from the first substrate.

8. The preparation method according to claim 7, wherein, The step of forming a plurality of pixel units on one side of the first substrate includes: forming a pixel electrode and forming a gate; The steps of forming pixel electrodes and forming gate electrodes include: Forming a first conductive material thin film; A second conductive material film is formed on the side of the first conductive material film away from the first substrate. The first conductive material thin film and the second conductive material thin film are patterned using a halftone mask patterning process to obtain the pattern of the first conductive layer and the pattern of the second conductive layer. The first conductive layer includes a first conductive structure, and the second conductive layer includes the gate and a second conductive structure disposed in the same layer as the gate. The orthogonal projection of the first conductive layer on the first substrate covers the orthogonal projection of the second conductive layer on the first substrate.

9. The preparation method according to claim 7 or 8, wherein, The step of forming a plurality of pixel units on one side of the first substrate further includes: forming an active layer and forming a first electrode and a second electrode; The steps for forming the active layer and the first and second electrodes include: Forming an active material thin film; A third conductive material film is formed on the side of the active material film away from the first substrate. The active material thin film and the third conductive material thin film are patterned using a halftone mask patterning process to obtain the pattern of the active layer and the pattern of the third conductive layer. The third conductive layer includes the first electrode, the second electrode, and a third conductive structure disposed in the same layer as the first electrode and the second electrode. The orthogonal projection of the active layer on the first substrate covers the orthogonal projection of the first electrode and the second electrode on the first substrate.

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