Display substrate and display device

Abstract

A display substrate and a display device, the display substrate comprising: a display area and a non-display area, the display area being provided with pixel circuits arranged in an array, the non-display area being provided with M light-emitting drive circuits, M control drive circuits and M reset drive circuits; an odd-numbered light-emitting drive circuit being electrically connected to a first light-emitting clock signal line and a second light-emitting clock signal line, an even-numbered light-emitting drive circuit being connected to a third light-emitting clock signal line and a fourth light-emitting clock signal line; and / or, an odd-numbered control drive circuit being electrically connected to a first control clock signal line and a second control clock signal line, an even-numbered control drive circuit being connected to a third control clock signal line and a fourth control clock signal line; and / or, an odd-numbered reset drive circuit being electrically connected to a first reset clock signal line and a second reset clock signal line, an even-numbered reset drive circuit being connected to a third reset clock signal line and a fourth reset clock signal line.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, embodiments of this disclosure provide a display substrate, including: a display area and a non-display area, wherein the display area is provided with an array of pixel circuits, and the display area is divided into M partitions along a first direction; the pixel circuits include: a write transistor, an anode reset transistor, a gate control transistor, a light-emitting transistor, and a first scan signal line, a second scan signal line, a third scan signal line, and a light-emitting signal line extending along a second direction, wherein the first scan signal line is electrically connected to the write transistor, the second scan signal line is electrically connected to the gate control transistor, the third scan signal line is electrically connected to the anode reset transistor, and the light-emitting signal line is connected to the light-emitting transistor, wherein M is a positive integer greater than or equal to 2;

[0005] The non-display area is provided with a light-emitting driving circuit group, a control driving circuit group, a reset driving circuit group, a first light-emitting clock signal line to a fourth light-emitting clock signal line, a first control clock signal line to a fourth control clock signal line, and a first reset clock signal line to a fourth reset clock signal line.

[0006] The light-emitting driving circuit group includes: M light-emitting driving circuits, the i-th light-emitting driving circuit is connected to the light-emitting signal line in the pixel circuit of the i-th partition, the light-emitting shift register in the odd-numbered light-emitting driving circuit is electrically connected to the first light-emitting clock signal line and the second light-emitting clock signal line, and the light-emitting shift register in the even-numbered light-emitting driving circuit is connected to the third light-emitting clock signal line and the fourth light-emitting clock signal line, i = 1, 2, ..., M;

[0007] And / or, the control drive circuit group includes: M control drive circuits, the i-th control drive circuit is connected to the second scan signal line in the pixel circuit of the i-th partition, the odd-numbered control drive circuit is electrically connected to the first control clock signal line and the second control clock signal line, and the even-numbered control drive circuit is connected to the third control clock signal line and the fourth control clock signal line.

[0008] And / or, the reset drive circuit group includes: M reset drive circuits, the i-th reset drive circuit is connected to the third scan signal line in the pixel circuit of the i-th partition, the odd-numbered reset drive circuit is electrically connected to the first reset clock signal line and the second reset clock signal line, and the even-numbered reset drive circuit is connected to the third reset clock signal line and the fourth reset clock signal line.

[0009] In some exemplary embodiments, the first partition includes the first row of pixel circuits to the N1th row of pixel circuits, and the jth partition includes: the Nth row of pixel circuits. j-1 +1 row pixel circuit to the Nth j Pixel circuit, j = 2, ..., M;

[0010] The light-emitting driving circuit includes: a light-emitting shift register, which includes: a cascaded signal output terminal, a signal input terminal, a first signal output terminal, a second signal output terminal, a third signal output terminal, and a fourth signal output terminal;

[0011] The first light-emitting driving circuit includes: N1 / 4 cascaded light-emitting shift registers. The cascaded signal output terminal of the x-th stage light-emitting shift register in the first light-emitting driving circuit is connected to the signal input terminal of the (x+1)-th stage light-emitting shift register. The first, second, third, and fourth signal output terminals of the x-th stage light-emitting shift register in the first light-emitting driving circuit are respectively connected to the light-emitting signal lines of the 4x-3 row pixel circuit, the 4x-2 row pixel circuit, the 4x-1 row pixel circuit, and the 4x row pixel circuit, where x = 1, 2, ..., N1 / 4.

[0012] The j-th light-emitting driving circuit includes: (N) j -N j-1 () / 4 cascaded light-emitting shift registers, the cascaded signal output terminal of the y-th stage light-emitting shift register in the j-th light-emitting driver circuit is connected to the signal input terminal of the (y+1)-th stage light-emitting shift register, and the first, second, third, and fourth signal output terminals of the y-th stage light-emitting shift register in the j-th light-emitting driver circuit are respectively connected to the N-th stage light-emitting shift register. j-1 +4y-3 row pixel circuit light-emitting signal line, Nth j-1+4y-2 row pixel circuit light-emitting signal line, Nth j-1 +4y-1 row pixel circuit light-emitting signal line and Nth j-1 The light-emitting signal lines of the +4y row pixel circuit are connected, y = 1, 2, ..., (N) j -N j-1 ) / 4.

[0013] In some exemplary embodiments, the light-emitting shift register further includes: a first clock signal terminal and a second clock signal terminal;

[0014] The first clock signal terminal of the light-emitting shift register in the odd-numbered light-emitting driving circuit is connected to one of the first light-emitting clock signal line and the second light-emitting clock signal line, and the second clock signal terminal is connected to the other light-emitting clock signal line among the first light-emitting clock signal line and the second light-emitting clock signal line. Furthermore, the first clock signal terminals of adjacent light-emitting shift registers are connected to different light-emitting clock signal lines.

[0015] In the even-numbered light-emitting driver circuit, the first clock signal terminal of the light-emitting shift register is connected to one of the third and fourth light-emitting clock signal lines, and the second clock signal terminal is connected to the other of the third and fourth light-emitting clock signal lines. Furthermore, the first clock signal terminals of adjacent light-emitting shift registers are connected to different light-emitting clock signal lines.

[0016] In some exemplary embodiments, the control drive circuit includes: a control shift register, which includes: a cascaded signal output terminal, a signal input terminal, a first signal output terminal, a second signal output terminal, a third signal output terminal, and a fourth signal output terminal;

[0017] The first control drive circuit includes: N1 / 4 cascaded control shift registers. The cascaded signal output terminal of the x-th stage control shift register in the first control drive circuit is connected to the signal input terminal of the (x+1)-th stage control shift register. The first, second, third, and fourth signal output terminals of the x-th stage control shift register in the first control drive circuit are respectively connected to the second scan signal lines of the 4x-3 row pixel circuit, the 4x-2 row pixel circuit, the 4x-1 row pixel circuit, and the 4x row pixel circuit, where x = 1, 2, ..., N1 / 4.

[0018] The j-th control drive circuit includes: (N) j -N j-1() / 4 cascaded control shift registers, the cascaded signal output terminal of the y-th stage control shift register in the j-th control drive circuit is connected to the signal input terminal of the (y+1)-th stage control shift register, and the first, second, third, and fourth signal output terminals of the y-th stage control shift register in the j-th control drive circuit are respectively connected to the N-th stage control shift register. j-1 The second scan signal line of the +4y-3 row pixel circuit, the Nth j-1 The second scan signal line of the +4y-2 row pixel circuit, the Nth... j-1 The second scan signal line and the Nth row pixel circuit of +4y-1 j-1 The second scan signal line of the +4y row pixel circuit is connected, y = 1, 2, ..., (N) j -N j-1 ) / 4.

[0019] In some exemplary embodiments, the control shift register further includes: a first clock signal terminal and a second clock signal terminal;

[0020] The first clock signal terminal of the control shift register in the odd-numbered control drive circuit is connected to one of the first control clock signal lines and the second control clock signal line, and the second clock signal terminal is connected to the other control clock signal line among the first and second control clock signal lines. Furthermore, the first clock signal terminals of adjacent control shift registers are connected to different control clock signal lines.

[0021] In the even-numbered control drive circuit, the first clock signal terminal of the control shift register is connected to one of the third and fourth control clock signal lines, and the second clock signal terminal is connected to the other of the third and fourth control clock signal lines. Furthermore, the first clock signal terminals of adjacent control shift registers are connected to different control clock signal lines.

[0022] In some exemplary embodiments, the reset drive circuit includes a reset shift register, which includes a cascaded signal output terminal, a signal input terminal, a first signal output terminal, a second signal output terminal, a third signal output terminal, and a fourth signal output terminal.

[0023] The first reset drive circuit includes: N1 / 4 cascaded reset shift registers. The cascaded signal output terminal of the x-th stage reset shift register in the first reset drive circuit is connected to the signal input terminal of the (x+1)-th stage reset shift register. The first, second, third, and fourth signal output terminals of the x-th stage reset shift register in the first reset drive circuit are respectively connected to the third scan signal lines of the 4x-3 row pixel circuit, the 4x-2 row pixel circuit, the 4x-1 row pixel circuit, and the 4x row pixel circuit, where x = 1, 2, ..., N1 / 4.

[0024] The j-th reset drive circuit includes: (N j -N j-1 A cascaded reset shift register system consists of four stages. The cascaded signal output of the y-th stage reset shift register in the j-th reset driver circuit is connected to the signal input of the (y+1)-th stage reset shift register. The first, second, third, and fourth signal outputs of the y-th stage reset shift register in the j-th reset driver circuit are respectively connected to the N-th stage reset shift register. j-1 The third scan signal line of the +4y-3 row pixel circuit, the Nth j-1 The third scan signal line of the +4y-2 row pixel circuit, the Nth j-1 The third scan signal line and the Nth line of the +4y-1 row pixel circuit j-1 The third scan signal line of the +4y row pixel circuit is connected, y = 1, 2, ..., (N j -N j-1 ) / 4.

[0025] In some exemplary embodiments, the reset shift register further includes: a first clock signal terminal and a second clock signal terminal;

[0026] The first clock signal terminal of the reset shift register in the odd-numbered reset drive circuit is connected to one of the first reset clock signal lines and the second reset clock signal line, and the second clock signal terminal is connected to the other of the first reset clock signal lines and the second reset clock signal line. Furthermore, the first clock signal terminals of adjacent reset shift registers are connected to different reset clock signal lines.

[0027] In the even-numbered reset drive circuit, the first clock signal terminal of the reset shift register is connected to one of the third and fourth reset clock signal lines, and the second clock signal terminal is connected to the other of the third and fourth reset clock signal lines. Furthermore, the first clock signal terminals of adjacent reset shift registers are connected to different reset clock signal lines.

[0028] In some exemplary embodiments, the shift register includes: a first node control sub-circuit, a second node control sub-circuit, a third node control word circuit, and an output control sub-circuit; the shift register also includes: an emissive shift register, a control shift register, and a reset shift register.

[0029] The first node control sub-circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the signal input terminal, the first node, and the second node, respectively, and is configured to provide the first power supply terminal or the second clock signal terminal to the first node under the control of the first clock signal terminal, the signal input terminal, and the second node;

[0030] The second node control sub-circuit is electrically connected to the second clock signal terminal, the first power supply terminal, the signal input terminal, and the second node, respectively, and is configured to provide the first power supply terminal or the second clock signal terminal to the second node under the control of the signal input terminal and the second clock signal terminal;

[0031] The third node control sub-circuit is electrically connected to the first node, the second node, the third node and the first clock signal terminal respectively, and is configured to provide the third node with a signal from the first clock signal terminal or the second power supply terminal under the control of the first clock signal terminal, the first node and the second node.

[0032] The output control sub-circuit is electrically connected to the first node, the third node, the first power supply terminal, the second power supply terminal, the cascaded signal output terminal, the first signal output terminal, the second signal output terminal, the third signal output terminal, and the fourth signal output terminal, respectively. It is configured to provide the first power supply terminal or the second power supply terminal signal to the cascaded signal output terminal, the first signal output terminal, the second signal output terminal, the third signal output terminal, and the fourth signal output terminal under the control of the first node, the third node, and the first power supply terminal.

[0033] In some exemplary embodiments, the shift register includes: a first node control sub-circuit, a second node control sub-circuit, a third node control word circuit, and an output control sub-circuit; the shift register also includes: an emissive shift register, a control shift register, and a reset shift register.

[0034] The first node control sub-circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the signal input terminal, the first node, and the second node, respectively, and is configured to provide the first node with a signal from the first clock signal terminal or the second clock signal terminal under the control of the first clock signal terminal, the signal input terminal, and the second node.

[0035] The second node control sub-circuit is electrically connected to the second clock signal terminal, the first power supply terminal, the signal input terminal, and the second node, respectively, and is configured to provide the first power supply terminal or the second clock signal terminal to the second node under the control of the signal input terminal and the second clock signal terminal;

[0036] The third node control sub-circuit is electrically connected to the first node, the second node, the third node and the first clock signal terminal respectively, and is configured to provide the third node with a signal from the first clock signal terminal or the second power supply terminal under the control of the first clock signal terminal, the first node and the second node.

[0037] The output control sub-circuit is electrically connected to the first node, the third node, the first power supply terminal, the second power supply terminal, the cascaded signal output terminal, the first signal output terminal, the second signal output terminal, the third signal output terminal, and the fourth signal output terminal, respectively. It is configured to provide the first power supply terminal or the second power supply terminal signal to the cascaded signal output terminal, the first signal output terminal, the second signal output terminal, the third signal output terminal, and the fourth signal output terminal under the control of the first node, the third node, and the first power supply terminal.

[0038] In some exemplary embodiments, the shift register further includes: a noise reduction sub-circuit;

[0039] The noise reduction sub-circuit is electrically connected to the noise reduction signal terminal, the first clock signal terminal, the first power supply terminal, the first node, and the third node, respectively, and is configured to provide the first clock signal terminal to the first node and the first power supply terminal to the third node under the control of the noise reduction signal terminal.

[0040] In some exemplary embodiments, the first node control sub-circuit includes: a first transistor, a second transistor, a tenth transistor, and an eleventh transistor;

[0041] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the first power supply terminal, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor.

[0042] The control electrode of the second transistor is electrically connected to the signal input terminal, and the second electrode of the second transistor is electrically connected to the first node.

[0043] The control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor.

[0044] The control terminal of the eleventh transistor is electrically connected to the first clock signal terminal, and the second terminal of the eleventh transistor is electrically connected to the second clock signal terminal.

[0045] In some exemplary embodiments, the first node control sub-circuit includes: a first transistor, a second transistor, a tenth transistor, and an eleventh transistor;

[0046] The control electrode and the first electrode of the first transistor are electrically connected to the first clock signal terminal, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor.

[0047] The control electrode of the second transistor is electrically connected to the signal input terminal, and the second electrode of the second transistor is electrically connected to the first node.

[0048] The control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor.

[0049] The control terminal of the eleventh transistor is electrically connected to the first clock signal terminal, and the second terminal of the eleventh transistor is electrically connected to the second clock signal terminal.

[0050] In some exemplary embodiments, the second node control sub-circuit includes: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

[0051] The control electrode of the third transistor is electrically connected to the second clock signal terminal, the first electrode of the third transistor is electrically connected to the first power supply terminal, and the second electrode of the third transistor is electrically connected to the second node.

[0052] The control electrode of the fourth transistor is electrically connected to the signal input terminal, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor.

[0053] The control electrode of the fifth transistor is electrically connected to the signal input terminal, and the second electrode of the fifth transistor is electrically connected to the second clock signal terminal;

[0054] The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the second electrode of the fourth transistor.

[0055] In some exemplary embodiments, the third node control sub-circuit includes: a seventh transistor, an eighth transistor, a ninth transistor, and a first capacitor;

[0056] The control electrode of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the first clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor.

[0057] The control terminal of the eighth transistor is electrically connected to the first clock signal terminal, and the second terminal of the eighth transistor is electrically connected to the third node.

[0058] The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the third node, and the second electrode of the ninth transistor is electrically connected to the second power supply terminal.

[0059] The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the second electrode of the seventh transistor.

[0060] In some exemplary embodiments, the output control sub-circuit includes: a twelfth transistor to a twenty-second transistor, a second capacitor, and a third capacitor;

[0061] The control electrode of the twelfth transistor is electrically connected to the first power supply terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the fourth node.

[0062] The control electrode of the thirteenth transistor is electrically connected to the fourth node, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the cascaded signal output terminal.

[0063] The control electrode of the fourteenth transistor is electrically connected to the third node, the first electrode of the fourteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourteenth transistor is electrically connected to the cascaded signal output terminal.

[0064] The control electrode of the fifteenth transistor is electrically connected to the fourth node, the first electrode of the fifteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifteenth transistor is electrically connected to the first signal output terminal.

[0065] The control electrode of the sixteenth transistor is electrically connected to the third node, the first electrode of the sixteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the sixteenth transistor is electrically connected to the first signal output terminal.

[0066] The control electrode of the seventeenth transistor is electrically connected to the fourth node, the first electrode of the seventeenth transistor is electrically connected to the first power supply terminal, and the second electrode of the seventeenth transistor is electrically connected to the second signal output terminal.

[0067] The control electrode of the eighteenth transistor is electrically connected to the third node, the first electrode of the eighteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the eighteenth transistor is electrically connected to the second signal output terminal.

[0068] The control electrode of the nineteenth transistor is electrically connected to the fourth node, the first electrode of the nineteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the nineteenth transistor is electrically connected to the third signal output terminal.

[0069] The control electrode of the twentieth transistor is electrically connected to the third node, the first electrode of the twentieth transistor is electrically connected to the second power supply terminal, and the second electrode of the twentieth transistor is electrically connected to the third signal output terminal.

[0070] The control electrode of the 21st transistor is electrically connected to the fourth node, the first electrode of the 21st transistor is electrically connected to the first power supply terminal, and the second electrode of the 21st transistor is electrically connected to the fourth signal output terminal.

[0071] The control electrode of the 22nd transistor is electrically connected to the third node, the first electrode of the 22nd transistor is electrically connected to the second power supply terminal, and the second electrode of the 22nd transistor is electrically connected to the fourth signal output terminal.

[0072] The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the first signal output terminal.

[0073] The first terminal of the third capacitor is electrically connected to the third node, and the second terminal of the third capacitor is electrically connected to the second power supply terminal.

[0074] In some exemplary embodiments, the output control sub-circuit includes: a twelfth to a twenty-eighth transistor, a second capacitor, and a third capacitor;

[0075] The control electrode of the twelfth transistor is electrically connected to the first power supply terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the fourth node.

[0076] The control electrode of the thirteenth transistor is electrically connected to the fourth node, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the cascaded signal output terminal.

[0077] The control electrode of the fourteenth transistor is electrically connected to the third node, the first electrode of the fourteenth transistor is electrically connected to the fifth node, and the second electrode of the fourteenth transistor is electrically connected to the cascaded signal output terminal.

[0078] The control electrode of the fifteenth transistor is electrically connected to the fourth node, the first electrode of the fifteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifteenth transistor is electrically connected to the first signal output terminal.

[0079] The control electrode of the sixteenth transistor is electrically connected to the third node, the first electrode of the sixteenth transistor is electrically connected to the fifth node, and the second electrode of the sixteenth transistor is electrically connected to the first signal output terminal.

[0080] The control electrode of the seventeenth transistor is electrically connected to the fourth node, the first electrode of the seventeenth transistor is electrically connected to the first power supply terminal, and the second electrode of the seventeenth transistor is electrically connected to the second signal output terminal.

[0081] The control electrode of the eighteenth transistor is electrically connected to the third node, the first electrode of the eighteenth transistor is electrically connected to the fifth node, and the second electrode of the eighteenth transistor is electrically connected to the second signal output terminal.

[0082] The control electrode of the nineteenth transistor is electrically connected to the fourth node, the first electrode of the nineteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the nineteenth transistor is electrically connected to the third signal output terminal.

[0083] The control electrode of the twentieth transistor is electrically connected to the third node, the first electrode of the twentieth transistor is electrically connected to the fifth node, and the second electrode of the twentieth transistor is electrically connected to the third signal output terminal.

[0084] The control electrode of the 21st transistor is electrically connected to the fourth node, the first electrode of the 21st transistor is electrically connected to the first power supply terminal, and the second electrode of the 21st transistor is electrically connected to the fourth signal output terminal.

[0085] The control electrode of the 22nd transistor is electrically connected to the third node, the first electrode of the 22nd transistor is electrically connected to the fifth node, and the second electrode of the 22nd transistor is electrically connected to the fourth signal output terminal.

[0086] The control electrode of the 23rd transistor is electrically connected to the third node, the first electrode of the 22nd transistor is electrically connected to the second power supply terminal, and the second electrode of the 22nd transistor is electrically connected to the fifth node.

[0087] The control electrode of the 24th transistor is electrically connected to the third node, the first electrode of the 24th transistor is electrically connected to the second power supply terminal, and the second electrode of the 22nd transistor is electrically connected to the fifth node.

[0088] The control electrode of the 25th transistor is electrically connected to the third node, the first electrode of the 25th transistor is electrically connected to the second power supply terminal, and the second electrode of the 25th transistor is electrically connected to the fifth node.

[0089] The control electrode of the 26th transistor is electrically connected to the third node, the first electrode of the 26th transistor is electrically connected to the second power supply terminal, and the second electrode of the 26th transistor is electrically connected to the fifth node.

[0090] The control electrode of the 27th transistor is electrically connected to the third node, the first electrode of the 27th transistor is electrically connected to the second power supply terminal, and the second electrode of the 27th transistor is electrically connected to the fifth node.

[0091] The control electrode of the 28th transistor is electrically connected to the third node, the first electrode of the 28th transistor is electrically connected to the second power supply terminal, and the second electrode of the 28th transistor is electrically connected to the fifth node.

[0092] The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the first signal output terminal.

[0093] The first terminal of the third capacitor is electrically connected to the third node, and the second terminal of the third capacitor is electrically connected to the second power supply terminal.

[0094] In some exemplary embodiments, the noise reduction sub-circuit includes: a twenty-ninth transistor and a thirtieth transistor;

[0095] The control electrode of the 29th transistor is electrically connected to the noise reduction signal terminal, the first electrode of the 29th transistor is electrically connected to the first clock signal terminal, and the second electrode of the 29th transistor is electrically connected to the first node.

[0096] The control electrode of the thirtieth transistor is electrically connected to the noise reduction signal terminal, the first electrode of the thirtieth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirtieth transistor is electrically connected to the third node.

[0097] In some exemplary embodiments, it further includes: an initial light emission signal line; the signal input terminal of the first-stage light emission shift register in the M light emission driving circuits is electrically connected to the initial light emission signal line;

[0098] The initial light-emitting signal line consists of M valid level pulse signals, and the i-th valid level pulse signal is the signal input terminal of the first-stage light-emitting shift register in the i-th light-emitting driving circuit.

[0099] The time difference between the start time of the i-th effective level pulse signal of the initial light emission signal line and the start time of the (i+1)-th effective level pulse signal of the initial light emission signal line is Hi*H, where Hi is the row number corresponding to the resolution of the i-th partition, and H is the data writing time of a row of pixel circuits.

[0100] The data write time Hmin*H of the lowest resolution partition is greater than the duration T of the effective level pulse signal of the initial emission signal line, where Hmin is the number of rows corresponding to the resolution of the lowest resolution partition.

[0101] In some exemplary embodiments, the content displayed on the display substrate includes: a plurality of display frames, wherein when the end time of the first effective level pulse signal of the first light-emitting clock signal line is earlier than the start time of the first effective level pulse signal of the second light-emitting clock signal line, the first light-emitting clock signal line is a first reference light-emitting clock signal line; when the end time of the first effective level pulse signal of the second light-emitting clock signal line is earlier than the start time of the first effective level pulse signal of the first light-emitting clock signal line, the second light-emitting clock signal line is a first reference light-emitting clock signal line; when the end time of the first effective level pulse signal of the third light-emitting clock signal line is earlier than the start time of the first effective level pulse signal of the fourth light-emitting clock signal line, the third light-emitting clock signal line is a second reference light-emitting clock signal line; when the end time of the first effective level pulse signal of the fourth light-emitting clock signal line is earlier than the start time of the first effective level pulse signal of the third light-emitting clock signal line, the fourth light-emitting clock signal line is a second reference light-emitting clock signal line.

[0102] Within a display frame, the signals of the first reference light-emitting clock signal line include: M1 signal areas, where M1 is the number of odd numbers in M, and within the s-th signal area, the output signal of the 2s-1-th light-emitting driving circuit, s = 1, 2, ..., M1;

[0103] Within the s-th signal region, the number of valid level pulse signals on the first reference light-emitting clock signal line satisfies EMNum_s=H 2s-1 / N0+M0 / H 2s-1 N0 = 2H 2s-1 / Hmin, M0=Hmin*T / 2;

[0104] Within a display frame, the signals of the second reference light-emitting clock signal line include: M2 signal areas; M2 is the number of even numbers in M; within the t-th signal area, the 2t-th light-emitting driving circuit outputs a signal, t = 1, 2, ..., M2;

[0105] Within the t-th signal region, the number of valid level pulse signals on the second reference light-emitting clock signal line satisfies EMNum_t≥H 2t / N1+M0 / H 2t N1 = 2H 2t / Hmin.

[0106] In some exemplary embodiments, it further includes: a control initial signal line; the signal input terminal of the first-stage control shift register in the M control drive circuits is electrically connected to the control initial signal line;

[0107] The control initial signal line consists of M valid level pulse signals, and the i-th valid level pulse signal is the signal input terminal of the first-stage control shift register in the i-th control drive circuit.

[0108] The time difference between the start time of the i-th valid level pulse signal of the control initial signal line and the start time of the (i+1)-th valid level pulse signal of the control initial signal line is Hi*H, where Hi is the row number corresponding to the resolution of the i-th partition, and H is the data writing time of a row of pixel circuits.

[0109] The data write time Hmin*H for the lowest resolution partition is greater than the duration T of the effective level pulse signal of the control initial signal line, where Hmin is the number of rows corresponding to the resolution of the lowest resolution partition.

[0110] In some exemplary embodiments, the content displayed on the display substrate includes: a plurality of display frames, wherein when the end time of the first valid level pulse signal of the first control clock signal line is earlier than the start time of the first valid level pulse signal of the second control clock signal line, the first control clock signal line is a first reference control clock signal line; when the end time of the first valid level pulse signal of the second control clock signal line is earlier than the start time of the first valid level pulse signal of the first control clock signal line, the second control clock signal line is a first reference control clock signal line; when the end time of the first valid level pulse signal of the third control clock signal line is earlier than the start time of the first valid level pulse signal of the fourth control clock signal line, the third control clock signal line is a second reference control clock signal line; when the end time of the first valid level pulse signal of the fourth control clock signal line is earlier than the start time of the first valid level pulse signal of the third control clock signal line, the fourth control clock signal line is a second reference control clock signal line.

[0111] Within a display frame, the signals of the first reference control clock signal line include: M1 signal areas, where M1 is the number of odd numbers in M, and within the s-th signal area, the output signal of the 2s-1-th control drive circuit, where s = 1, 2, ..., M1;

[0112] Within the s-th signal region, the number of valid level pulse signals on the first reference control clock signal line satisfies G2Num_s=H 2s-1 / N0+M0 / H 2s-1 N0 = 2H 2s-1 / Hmin, M0=Hmin*T / 2;

[0113] Within a display frame, the signals of the second reference control clock signal line include: M2 signal areas; M2 is the number of even numbers in M, and within the t-th signal area, the 2t-th control drive circuit outputs a signal, t = 1, 2, ..., M2;

[0114] Within the t-th signal region, the number of valid level pulses on the second reference control clock signal line satisfies G2Num_t≥H 2t / N1+M0 / H 2t N1 = 2H 2t / Hmin.

[0115] In some exemplary embodiments, it further includes: a reset initial signal line; the signal input terminal of the first-stage reset shift register in the M reset drive circuits is electrically connected to the reset initial signal line;

[0116] The reset initial signal line consists of M valid level pulse signals, and the i-th valid level pulse signal is the signal input terminal of the first-stage reset shift register in the i-th reset drive circuit.

[0117] The time difference between the start time of the i-th valid level pulse signal of the reset initial signal line and the start time of the (i+1)-th valid level pulse signal of the reset initial signal line is Hi*H, where Hi is the row number corresponding to the resolution of the i-th partition, and H is the data writing time of a row of pixel circuits.

[0118] The data write time Hmin*H for the lowest resolution partition is greater than the duration T of the effective level pulse signal of the reset initial signal line, where Hmin is the number of rows corresponding to the resolution of the lowest resolution partition.

[0119] In some exemplary embodiments, the content displayed on the display substrate includes: a plurality of display frames, wherein when the end time of the first valid level pulse signal of the first reset clock signal line is earlier than the start time of the first valid level pulse signal of the second reset clock signal line, the first reset clock signal line is a first reference reset clock signal line; when the end time of the first valid level pulse signal of the second reset clock signal line is earlier than the start time of the first valid level pulse signal of the first reset clock signal line, the second reset clock signal line is a first reference reset clock signal line; when the end time of the first valid level pulse signal of the third reset clock signal line is earlier than the start time of the first valid level pulse signal of the fourth reset clock signal line, the third reset clock signal line is a second reference reset clock signal line; when the end time of the first valid level pulse signal of the fourth reset clock signal line is earlier than the start time of the first valid level pulse signal of the third reset clock signal line, the fourth reset clock signal line is a second reference reset clock signal line.

[0120] Within a display frame, the signals of the first reference reset clock signal line include: M1 signal areas, where M1 is the number of odd numbers in M, and within the s-th signal area, the 2s-1-th reset drive circuit output signal, s = 1, 2, ..., M1;

[0121] Within the s-th signal region, the number of valid level pulses on the first reference reset clock signal line satisfies G3Num_s=H 2s-1 / N0+M0 / H 2s-1 N0 = 2H 2s-1 / Hmin, M0=Hmin*T / 2;

[0122] Within a display frame, the signals of the second reference reset clock signal line include: M2 signal areas; M2 is the number of even numbers in M, and the 2t-th reset drive circuit outputs a signal in the t-th signal area, where t = 1, 2, ..., M2;

[0123] Within the t-th signal region, the number of valid level pulses on the second reference reset clock signal line satisfies G3Num_t≥H 2t / N1+M0 / H 2t N1 = 2H 2t / Hmin.

[0124] Secondly, embodiments of this disclosure also provide a display device, including: the above-described display substrate.

[0125] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0126] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0127] Figure 1 This is a schematic diagram of the structure of a display device;

[0128] Figure 2 This is a schematic diagram of a planar structure of a display substrate;

[0129] Figure 3 This is a schematic diagram of a cross-sectional structure of a display substrate;

[0130] Figure 4 This is a schematic diagram of the equivalent circuit of a pixel circuit.

[0131] Figure 5 This is a timing diagram of a pixel circuit.

[0132] Figure 6 This is a schematic diagram of the partitioning of the display substrate;

[0133] Figure 7 This is a schematic diagram showing the connection between the light-emitting driving circuit group and the pixel circuits of different zones in the display substrate.

[0134] Figure 8 This is a schematic diagram showing the connection between the control drive circuit group and the pixel circuits of different zones in the display substrate.

[0135] Figure 9 This is a schematic diagram showing the connection between the reset drive circuit group and the pixel circuits of different zones in the display substrate.

[0136] Figure 10A schematic diagram of the structure of a shift register provided for an exemplary embodiment Figure 1 ;

[0137] Figure 11 A schematic diagram of the structure of a shift register provided for an exemplary embodiment Figure 2 ;

[0138] Figure 12 A schematic diagram of the structure of a shift register provided for an exemplary embodiment Figure 3 ;

[0139] Figure 13 A schematic diagram of the structure of a shift register provided for an exemplary embodiment Figure 4 ;

[0140] Figure 14 An equivalent circuit for a shift register Figure 1 ;

[0141] Figure 15 An equivalent circuit for a shift register Figure 2 ;

[0142] Figure 16 An equivalent circuit for a shift register Figure 3 ;

[0143] Figure 17 An equivalent circuit for a shift register Figure 4 ;

[0144] Figure 18 for Figures 14 to 17 The provided timing diagram for the shift register is shown.

[0145] Figure 19 Timing diagram of the signal lines connected to the light-emitting driver circuit group;

[0146] Figure 20 Timing diagram of the signal lines connected to the control drive circuit group;

[0147] Figure 21 The timing diagram shows the signal lines connected to the reset drive circuit group. Detailed Implementation

[0148] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be arbitrarily combined with each other.

[0149] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" encompass the elements or objects listed after the term and their equivalents, without excluding other elements or objects.

[0150] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0151] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection via an intermediate component; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure in light of the specific circumstances.

[0152] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (or drain terminal, drain connection region, or drain electrode) and the source electrode (or source terminal, source connection region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0153] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" can sometimes be interchanged. Therefore, in this disclosure, the "source electrode" and "drain electrode" can be interchanged. The gate electrode can also be called the control electrode.

[0154] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. The "component having a certain electrical function" can be, for example, an electrode or wiring, a switching element such as a transistor, or other functional elements such as a resistor, inductor, or capacitor.

[0155] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes a state in which the angle is greater than or equal to -5° and less than 5°. In addition, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes a state in which the angle is greater than or equal to 85° and less than 95°.

[0156] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0157] Figure 1This is a schematic diagram of a display device. The display substrate may include a timing controller, a data signal driver, a scan signal driver, a light-emitting signal driver, and a pixel array. The timing controller is connected to the data signal driver, scan signal driver, and light-emitting signal driver. The data signal driver is connected to multiple data signal lines D (D1 to Dn), the scan signal driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting signal driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line D, at least one light-emitting signal line, and pixel circuitry. In some exemplary embodiments, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data signal driver to the data signal driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan signal driver to the scan signal driver, and provide clock signals, emission stop signals, etc. of specifications suitable for the light-emitting signal driver to the light-emitting signal driver. The data signal driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data signal driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan signal driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan signal driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. The light emission signal driver can generate transmit signals to be provided to light emission signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0158] Figure 2 This is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P includes a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light. Each of the first, second, and third sub-pixels includes a pixel circuit and a light-emitting device. The pixel circuits in the first, second, and third sub-pixels are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel circuits are configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting devices in the first, second, and third sub-pixels are respectively connected to the pixel circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel circuit of their respective sub-pixels.

[0159] In some exemplary embodiments, a pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In some exemplary embodiments, the shape of the sub-pixels in the pixel unit may be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; this disclosure does not limit the specific arrangement.

[0160] Figure 3 This is a cross-sectional structural diagram of a display substrate, illustrating the structure of three sub-pixels in an OLED display substrate. Figure 3 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited herein.

[0161] In some exemplary embodiments, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 for each sub-pixel may include multiple transistors and storage capacitors constituting the pixel circuit. The light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via. The organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of a corresponding color under the drive of the anode 301 and the cathode 304. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first and third encapsulation layers 401 and 403 may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first and third encapsulation layers 401 and 403 to prevent external moisture from entering the light-emitting structure layer 103.

[0162] In some exemplary embodiments, the organic light-emitting layer 303 may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In some exemplary embodiments, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0163] The scan signal lines may include: a first scan signal line, a second scan signal line, and a third scan signal line.

[0164] In some exemplary embodiments, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. Figure 4 This is a schematic diagram of the equivalent circuit of a pixel circuit. For example... Figure 4As shown, the pixel circuit may include 5 transistors (first transistor T1 to fifth transistor T5) and 1 storage capacitor C. The pixel circuit may be connected to 9 signal lines (data signal line Data, first scan signal line G1, second scan signal line G2, third scan signal line G3, light emission signal line EM, initial signal line VIN1, reference voltage signal line VIN2, first power supply line VDD and second power supply line VSS).

[0165] In some exemplary embodiments, the pixel circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the second terminal of the first transistor T1, the second terminal of the third transistor T3, and the second terminal of the storage capacitor C. The second node N2 is connected to the second terminal of the second transistor T2, the control terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the first terminal of the storage capacitor C. The third node N3 is connected to the first terminal of the third transistor T3 and the second terminal of the fifth transistor T5.

[0166] In some exemplary embodiments, the first end of the storage capacitor C is connected to the second node N2, and the second end of the storage capacitor C is connected to the first node N1.

[0167] The control electrode of the first transistor T1 is connected to the third scan signal line G3, the first electrode of the first transistor T1 is connected to the initial signal line VIN1, and the second electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 can be called an anode reset transistor, etc. When the on-level scan signal is applied to the third scan signal line G3, the first transistor T1 resets the first node N1.

[0168] The control electrode of the second transistor T2 is connected to the second scan signal line G2, the first electrode of the second transistor T2 is connected to the reference voltage signal line VIN2, and the second electrode of the second transistor T2 is connected to the second node N2. The first transistor T1, which can be called a gate control transistor, etc., when the on-level scan signal is applied to the second scan signal line G2, the compensation voltage Vref of the reference voltage signal line VIN2 is written into the second node N2.

[0169] The control electrode of the third transistor T3 is connected to the second node N2, meaning the control electrode of the third transistor T3 is connected to the first terminal of the storage capacitor C. The first terminal of the third transistor T3 is connected to the third node N3, and the second terminal of the third transistor T3 is connected to the first node N1. The third transistor T3 can be called the driving transistor. The amount of driving current flowing between the first power line VDD and the second power line VSS is determined by the potential difference between its control electrode and its first terminal.

[0170] The control electrode of the fourth transistor T4 is connected to the first scan signal line G1, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the second node N2. The fourth transistor T4 can be called a write transistor, etc. When a conduction-level scan signal is applied to the first scan signal line G1, the fourth transistor T4 causes the data voltage of the data signal line Data to be input to the pixel circuit.

[0171] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the third node N3. The fifth transistor T5 can be called a light-emitting transistor.

[0172] In some exemplary embodiments, the first transistor T1 to the fifth transistor T5 can be P-type transistors or N-type transistors. Using the same type of transistor in the pixel circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the fifth transistor T5 may include both P-type and N-type transistors.

[0173] In some exemplary embodiments, the first scan signal line G1, the second scan signal line G2, the light emission signal line EM, the initial signal line VIN1, and the reference voltage signal line VIN2 extend in the horizontal direction, while the second power supply line VSS, the first power supply line VDD, and the data signal line Data extend in the vertical direction.

[0174] In some exemplary embodiments, the light-emitting device may include any one of organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (LEDs), and inorganic light-emitting diodes (OLEDs). For example, the light-emitting device L may be a micrometer-scale light-emitting device, such as a micro LED, a mini LED, or a micro OLED, etc., and this disclosure does not limit this. For example, taking an organic light-emitting diode (OLED) as an example, the light-emitting device may include a first electrode (e.g., as an anode), an organic light-emitting layer, and a second electrode (e.g., as a cathode) stacked together.

[0175] Figure 5 This is a timing diagram of a pixel circuit. The following is a breakdown of its operation. Figure 4 The operation of the example pixel circuit illustrates an exemplary embodiment. Figure 4The pixel circuit includes 5 transistors (first transistor T1 to fifth transistor T5), 1 storage capacitor C, and 9 signal lines (data signal line Data, first scan signal line G1, second scan signal line G2, third scan signal line G3, light emission signal line EM, initial signal line VIN1, reference voltage signal line VIN2, first power supply line VDD and second power supply line VSS). All 5 transistors are N-type transistors.

[0176] In some exemplary embodiments, the operation of the pixel circuit may include:

[0177] In the first stage A1, the signal of the first scan signal line G1 is low, while the signals of the second scan signal line G2, the third scan signal line G3, and the light-emitting signal line EM are high. With the first scan signal line G1 low, the fourth transistor T4 is off. With the second scan signal line G2 high, the second transistor T2 is on, and the reference voltage signal line VIN2 is supplied to the second node N2, writing the compensation voltage Vref into the second node N2. With the third scan signal line G3 high, the first transistor T1 is on, and the initial signal line VIN1 is supplied to the first node N1, resetting the first node N1. With the light-emitting signal line EM high, the fifth transistor T5 is on, and the first power supply line VDD charges the first node N1 via the third node N3 and the third transistor T3. Since the voltage of the first node N1 in this stage does not reach the voltage required to drive the OLED to emit light, the OLED does not emit light in this stage.

[0178] In the second stage A2, both the first scan signal line G1 and the third scan signal line G3 are low-level signals. Because these signals are low, both the first transistor T1 and the fourth transistor T4 are off. Based on the signals from the second scan signal line G2 and the light-emitting signal line EM, the second stage A2 can include the following three sub-stages:

[0179] In the first sub-stage A21, both the second scan signal line G2 and the light emission signal line EM are high-level signals. Because the second scan signal line G2 is high, the second transistor T2 is turned on, and the compensation voltage Vref from the reference voltage signal line VIN2 is continuously supplied to the second node N2, causing the third transistor T3 to remain on. Because the light emission signal line EM is high, the fifth transistor T5 is turned on, and the signal from the first power supply line VDD continuously charges the first node N1 via the third node N3 and the third transistor T3. Since the voltage at the first node N1 does not reach the voltage required to drive the OLED to emit light during this stage, the OLED does not emit light during this stage.

[0180] In the second sub-stage A22, the signal of the second scan signal line G2 is low, while the signal of the light emission signal line EM is high. Since the second scan signal line G2 is low, the second transistor T2 is off. Because the voltage across the storage capacitor C does not change abruptly, the second node N2 maintains the voltage of the previous frame, and the third transistor T3 remains on. Since the signal of the light emission signal line EM is high, the fifth transistor T5 remains on. The signal of the first power line VDD charges the first node N1 via the third node N3 and the third transistor T3 until the voltage of the first node N1 reaches Vref-Vth (Vth is the threshold voltage of the third transistor T3). Since the voltage of the first node N1 in this stage has not yet reached the voltage required to drive the OLED to emit light, the OLED does not emit light in this stage.

[0181] In the third sub-stage A23, both the second scan signal line G2 and the light emission signal line EM are at low levels. Since both the second scan signal line G2 and the light emission signal line EM are at low levels, the second transistor T2 and the fifth transistor T5 are both turned off. Because the voltage across the storage capacitor C will not change abruptly, the first node N1 maintains the voltage (Vref-Vth) of the previous frame.

[0182] In the third stage, A3, which is the data writing stage, the signal on the first scan signal line G1 is high, while the signals on the second scan signal line G2, the third scan signal line G3, and the light-emitting signal line EM are all low. Because the signal on the first scan signal line G1 is high, the fourth transistor T4 is turned on, and the data voltage output from the data signal line Data is written to the second node N2. Because the signals on the second scan signal line G2, the third scan signal line G3, and the light-emitting signal line EM are all low, the second transistor T2, the first transistor T1, and the fifth transistor T5 are all turned off, and the first node N1 maintains the voltage (Vref-Vth) of the previous frame.

[0183] In the fourth stage, A4, the transition stage, the signals of the first scan signal line G1, the second scan signal line G2, the third scan signal line G3, and the light emission signal line EM are all low-level signals. Because these signals are all low, all transistors except the third transistor T3 are turned off, and the first node N1 maintains the voltage (Vref-Vth) of the previous frame.

[0184] In the fifth stage, A5, the light-emitting stage, the signal of the light-emitting signal line EM is a high-level signal, while the signals of the first scan signal line G1, the second scan signal line G2, and the third scan signal line G3 are all low-level signals. Since the signals of the first scan signal line G1, the second scan signal line G2, the third scan signal line G3, and the light-emitting signal line EM are all low-level signals, the first transistor T1, the second transistor T2, and the fourth transistor T4 are all off. The signal of the light-emitting signal line EM is a high-level signal, and the third transistor T3 and the fifth transistor T5 are on. The high-level signal of the first power supply terminal VDD is written to the third node N3 through the fifth transistor T5. The third transistor T3 generates a driving current based on the voltage of the second node N2, and writes it to the first node N1, thereby driving the OLED connected to the first node N1 to emit light.

[0185] The scan signal driver in the display substrate may include: a scan signal driver that provides signals to the first scan signal line, a scan signal driver that provides signals to the second scan signal line, and a scan signal driver that provides signals to the third scan signal line. The scan signal driver and the light-emitting signal driver can also be called gate driving devices or gate drivers. Gate driving devices include separate gate driving integrated circuits or panel gate driving circuits. Since the pulse width of the gate driving signal provided by the gate driving circuit is related to the operating performance of the pixel circuits inside the display panel—for example, when the gate driving signal can be used as both a scan signal and a light-emitting signal, the pulse width of the scan signal and the light-emitting signal are related to the operating performance of the pixel circuits inside the display panel—a control circuit with pulse width modulation (PWM) functionality is needed to adjust the pulse width of the gate driving signal. The signal from the first scan signal line is used to control the writing of data signals during the data writing stage, while the signals from the second scan signal line, the third scan signal line, and the light-emitting signal line are mainly used for internal compensation during the compensation stage. Therefore, the scan signal driver that provides signals to the second scan signal line, the scan signal driver that provides signals to the third scan signal line, and the light-emitting signal driver that provides signals to the light-emitting signal line should use drive circuits with PWM function.

[0186] To reduce power consumption, the display substrate is partitioned. Different partitions can have the same or different resolutions and refresh rates. For example, the first partition uses a maximum resolution of 3840 (columns) * 240 (rows), and this highest resolution is also used for display. The corresponding PWM model clock cycle is 8 * H (ensuring a 4H shift per row for compensation timing). The second partition uses a 1920 * 120 resolution, so the corresponding PWM model clock cycle is 4 * H. Because the data writing time for two rows is combined, the shift time is halved, thus halving the cycle. The third partition uses a 960 * 60 resolution; according to the above explanation, the PWM model clock cycle needs to be set to 2H. A scan signal driver providing scan signals to one partition corresponds to a set of clock signal lines. Scan signal drivers providing scan signals to different partitions are connected to different sets of clock signal lines. A light-emitting signal driver providing light-emitting signals to one partition corresponds to a set of clock signal lines, and light-emitting signal drivers providing light-emitting signals to different partitions are connected to different clock signal lines. As the number of partitions increases, the number of clock signal lines connected to the PWM-enabled drive circuits used in the display substrate for the scan signal driver that provides signals to the second scan signal line, the scan signal driver that provides signals to the third scan signal line, and the light-emitting signal driver that provides signals to the light-emitting signal line also increases. This makes the structure of the display substrate more complex and prevents the realization of narrow bezels.

[0187] Figure 6 This is a schematic diagram of the partitioning of the display substrate. Figure 7 This is a schematic diagram showing the connection between the light-emitting driving circuit group and the pixel circuits in different zones of the display substrate. Figure 8 This is a schematic diagram showing the connection between the control drive circuit group and the pixel circuits of different zones in the display substrate. Figure 9 This is a schematic diagram showing the connection between the reset drive circuit group and the pixel circuits of different zones in the display substrate. (See diagram below.) Figures 6 to 9 As shown, the display substrate provided in this embodiment includes: a display area AA and a non-display area AA'. The display area AA is provided with an array of pixel circuits. The display area is divided into M partitions along a first direction, namely the first partition to the Mth partition. The pixel circuit includes: a write transistor, an anode reset transistor, a gate control transistor, a light-emitting transistor, and a first scan signal line, a second scan signal line, a third scan signal line, and a light-emitting signal line extending along a second direction. The first scan signal line is electrically connected to the write transistor, the second scan signal line is electrically connected to the gate control transistor, the third scan signal line is electrically connected to the anode reset transistor, and the light-emitting signal line is connected to the light-emitting transistor. M is a positive integer greater than or equal to 2.

[0188] like Figures 7 to 9As shown, the non-display area is equipped with a light-emitting driving circuit group, a control driving circuit group, a reset driving circuit group, a first light-emitting clock signal line EM_CLK1 to a fourth light-emitting clock signal line EM_CLK4, a first control clock signal line G2_CLK1 to a fourth control clock signal line G2_CLK4, and a first reset clock signal line G3_CLK1 to a fourth reset clock signal line G4_CLK1.

[0189] like Figure 7 As shown, the light-emitting driving circuit group may include: M light-emitting driving circuits EM GOA_1 to EM GOA_M, the i-th light-emitting driving circuit is connected to the light-emitting signal line in the pixel circuit of the i-th partition, the light-emitting shift register in the odd-numbered light-emitting driving circuit is electrically connected to the first light-emitting clock signal line EM_CLK1 and the second light-emitting clock signal line EM_CLK2, and the light-emitting shift register in the even-numbered light-emitting driving circuit is connected to the third light-emitting clock signal line EM_CLK3 and the fourth light-emitting clock signal line EM_CLK4, i = 1, 2, ..., M.

[0190] And / or, such as Figure 8 As shown, the control drive circuit group includes: M control drive circuits G2 GOA_1 to G2 GOA_M, the i-th control drive circuit is connected to the second scan signal line in the pixel circuit of the i-th partition, the odd-numbered control drive circuit is electrically connected to the first control clock signal line G2_CLK1 and the second control clock signal line G2_CLK2, and the even-numbered control drive circuit is connected to the third control clock signal line G2_CLK3 and the fourth control clock signal line G2_CLK4.

[0191] And / or, such as Figure 9 As shown, the reset drive circuit group includes: M reset drive circuits G3 GOA_1 to G3 GOA_M, the i-th reset drive circuit is connected to the third scan signal line in the pixel circuit of the i-th partition, the odd-numbered reset drive circuit is electrically connected to the first reset clock signal line G3_CLK1 and the second reset clock signal line G3_CLK2, and the even-numbered reset drive circuit is connected to the third reset clock signal line G3_CLK3 and the fourth reset clock signal line G3_CLK4.

[0192] This disclosure involves electrically connecting the light-emitting shift register in the odd-numbered light-emitting driving circuit to the first light-emitting clock signal line EM_CLK1 and the second light-emitting clock signal line EM_CLK2, connecting the light-emitting shift register in the even-numbered light-emitting driving circuit to the third light-emitting clock signal line EM_CLK3 and the fourth light-emitting clock signal line EM_CLK4, and / or connecting the i-th reset driving circuit to the third scan signal line in the pixel circuit of the i-th partition, and connecting the odd-numbered reset driving circuit to the first reset clock signal line G3_CLK1 and the second reset clock signal line G3_CLK2. The clock signal line G3_CLK2 is electrically connected, and the even-numbered reset drive circuit is connected to the third reset clock signal line G3_CLK3 and the fourth reset clock signal line G3_CLK4. And / or, the odd-numbered reset drive circuit is electrically connected to the first reset clock signal line G3_CLK1 and the second reset clock signal line G3_CLK2, and the even-numbered reset drive circuit is connected to the third reset clock signal line G3_CLK3 and the fourth reset clock signal line G3_CLK4. This simplifies the structure of the drive circuit group located in the non-display area and enables a narrow bezel.

[0193] In some exemplary embodiments, such as Figure 6 As shown, the first partition includes pixel circuits from the first row to the N1th row R(1) to R(N1), and the j-th partition includes: the Nth row... j-1 +1 row pixel circuit R(N) j-1 +1) to the Nth j Pixel circuit R(N) j ), j = 2, ..., M.

[0194] In some exemplary embodiments, such as Figure 7 As shown, the light-emitting driving circuit includes: a light-emitting shift register, which includes: a cascaded signal output terminal, a signal input terminal, a first signal output terminal, a second signal output terminal, a third signal output terminal, and a fourth signal output terminal.

[0195] In some exemplary embodiments, such as Figure 7As shown, the first light-emitting driving circuit EM GOA_1 includes: N1 / 4 cascaded light-emitting shift registers EM GOA_1(1) to EM GOA_1(N1 / 4). The cascaded signal output terminal of the x-th stage light-emitting shift register in the first light-emitting driving circuit is connected to the signal input terminal of the x+1-th stage light-emitting shift register. The first signal output terminal, the second signal output terminal, the third signal output terminal and the fourth signal output terminal of the x-th stage light-emitting shift register EM GOA_1(x) in the first light-emitting driving circuit are respectively connected to the light-emitting signal lines EM_4x-3, EM_4x-2, EM_4x-1, and EM_4x of the pixel circuit in the 4x-3 row, respectively, where x = 1, 2, ..., N1 / 4.

[0196] In some exemplary embodiments, such as Figure 7 As shown, the j-th light-emitting driving circuit EM GOA_j includes: (N j -N j-1 ) / 4 cascaded light-emitting shift registers EM GOA_j(1) to EM GOA_j((N j -N j-1 (4), the cascaded signal output terminal of the y-th stage light-emitting shift register in the j-th light-emitting driver circuit is connected to the signal input terminal of the (y+1)-th stage light-emitting shift register. The y-th stage light-emitting shift register EM GOA_j(y) in the j-th light-emitting driver circuit is connected to the N-th stage light-emitting shift register respectively. j-1 +4y-3 row pixel circuit light emission signal line EM_N j-1 +4y-3, the Nth j-1 +4y-2 row pixel circuit light emission signal line EM_N j-1 +4y-2, the Nth j-1 +4y-1 row pixel circuit light emission signal line EM_N j-1 +4y-1 and the Nth j-1 +4y row pixel circuit light emission signal line EM_N j-1 Connect +4y, y = 1, 2, ..., (N) j -N j-1 ) / 4.

[0197] In some exemplary embodiments, such as Figure 7 As shown, the light-emitting shift register also includes a first clock signal terminal and a second clock signal terminal.

[0198] The first clock signal terminal of the light-emitting shift register in the odd-numbered light-emitting driver circuit is connected to one of the first light-emitting clock signal lines EM_CLK1 and EM_CLK2, and the second clock signal terminal is connected to the other light-emitting clock signal line among the first light-emitting clock signal lines EM_CLK1 and EM_CLK2. Furthermore, the first clock signal terminals of adjacent light-emitting shift registers are connected to different light-emitting clock signal lines.

[0199] The first clock signal terminal of the light-emitting shift register in the even-numbered light-emitting driver circuit is connected to one of the light-emitting clock signal lines EM_CLK3 and EM_CLK4, and the second clock signal terminal is connected to the other of the light-emitting clock signal lines EM_CLK3 and EM_CLK4. The first clock signal terminal CKA in adjacent light-emitting shift registers is connected to different light-emitting clock signal lines.

[0200] In some exemplary embodiments, such as Figure 8 As shown, the control drive circuit includes a control shift register, which includes a cascaded signal output terminal OUTCR, a signal input terminal IN, a first signal output terminal, a second signal output terminal, a third signal output terminal, and a fourth signal output terminal.

[0201] In some exemplary embodiments, such as Figure 8 As shown, the first control drive circuit G2 GOA_1 includes: N1 / 4 cascaded control shift registers G2 GOA_1(1) to G2 GOA_1(N1 / 4). The cascaded signal output terminal of the x-th stage control shift register in the first control drive circuit is connected to the signal input terminal of the x+1-th stage control shift register. The first signal output terminal, the second signal output terminal, the third signal output terminal and the fourth signal output terminal of the x-th stage control shift register G2 GOA_1(x) in the first control drive circuit are respectively connected to the second scan signal line G2_4x-3 of the 4x-3 row pixel circuit, the second scan signal line G2_4x-3 of the 4x-2 row pixel circuit, the second scan signal line G2_4x-3 of the 4x-1 row pixel circuit and the second scan signal line G2_4x-3 of the 4x row pixel circuit, where x = 1, 2, ..., N1 / 4;

[0202] In some exemplary embodiments, such as Figure 8 As shown, the j-th control drive circuit G2 GOA_j includes: (N j -N j-1 ) / 4 cascaded control shift registers G2 GOA_j(1) to G2 GOA_j((N j-N j-1 (4), the cascaded signal output terminal OUTCR of the y-th stage control shift register in the j-th control drive circuit is connected to the signal input terminal IN of the (y+1)-th stage control shift register. The first, second, third, and fourth signal output terminals of the y-th stage control shift register G2 GOA_j(y) in the j-th control drive circuit are respectively connected to the N-th stage control shift register. j-1 The second scan signal line G2_N of the +4y-3 row pixel circuit j-1 +4y-3, the Nth j-1 The second scan signal line G2_N of the +4y-2 row pixel circuit j-1 +4y-2, the Nth j-1 The second scan signal line G2_N of the +4y-1 row pixel circuit j-1 +4y-` and the Nth j-1 The second scan signal line G2_N of the +4y row pixel circuit j-1 Connect +4y, y = 1, 2, ..., (N) j -N j-1 ) / 4.

[0203] In some exemplary embodiments, such as Figure 8 As shown, the control shift register further includes a first clock signal terminal and a second clock signal terminal.

[0204] The first clock signal terminal of the control shift register in the odd-numbered control drive circuit is connected to one of the first control clock signal lines G2_CLK1 and G2_CLK2, and the second clock signal terminal is connected to the other control clock signal line of the first control clock signal line G2_CLK1 and G2_CLK2. Furthermore, the first clock signal terminals CKA of adjacent control shift registers are connected to different control clock signal lines.

[0205] In the even-numbered control drive circuit, the first clock signal terminal CKA of the control shift register is connected to one of the control clock signal lines G2_CLK3 and G2_CLK4, and the second clock signal terminal is connected to the other control clock signal line of G2_CLK3 and G2_CLK4. Furthermore, the first clock signal terminal CKA of adjacent control shift registers is connected to different control clock signal lines.

[0206] In some exemplary embodiments, such as Figure 9As shown, the reset drive circuit includes a reset shift register, which includes a cascaded signal output terminal, a signal input terminal, a first signal output terminal, a second signal output terminal, a third signal output terminal, and a fourth signal output terminal.

[0207] In some exemplary embodiments, such as Figure 9 As shown, the first reset drive circuit G3 GOA_1 includes: N1 / 4 cascaded reset shift registers G3 GOA_1(1) to G3 GOA_1(N1 / 4). The cascaded signal output terminal OUTCR of the x-th stage reset shift register in the first reset drive circuit is connected to the signal input terminal IN of the x+1-th stage reset shift register. The first signal output terminal OUT1, the second signal output terminal OUT2, the third signal output terminal OUT3 and the fourth signal output terminal OUT4 of the x-th stage reset shift register G3 GOA_1(x) in the first reset drive circuit are respectively connected to the third scan signal line G3_4x-3 of the 4x-3 row pixel circuit, the third scan signal line G3_4x-3 of the 4x-2 row pixel circuit, the third scan signal line G3_4x-3 of the 4x-1 row pixel circuit and the third scan signal line G3_4x-3 of the 4x row pixel circuit, x=1,2,……,N1 / 4;

[0208] In some exemplary embodiments, such as Figure 9 As shown, the j-th reset drive circuit G3 GOA_j includes: (N j -N j-1 ) / 4 cascaded reset shift registers G3 GOA_j(1) to G3 GOA_j((N j -N j-1 (4) In the j-th reset drive circuit, the cascaded signal output terminal OUTCR of the y-th stage reset shift register is connected to the signal input terminal IN of the (y+1)-th stage reset shift register. The first signal output terminal OUT1, the second signal output terminal OUT2, the third signal output terminal OUT3, and the fourth signal output terminal OUT4 of the y-th stage reset shift register G3 GOA_j(y) in the j-th reset drive circuit are respectively connected to the N-th stage reset shift register. j-1 The third scan signal line G3_N of the +4y-3 row pixel circuit j-1 +4y-3, the Nth j-1 The third scan signal line G3_N of the +4y-2 row pixel circuit j-1 +4y-3, the Nth j-1 The third scan signal line G3_N of the +4y-1 row pixel circuit j-1 +4y-3 and the Nth j-1 The third scan signal line G3_N of the +4y row pixel circuit j-1Connect +4y-3, y = 1, 2, ..., (N) j -N j-1 ) / 4.

[0209] In some exemplary embodiments, the reset shift register further includes a first clock signal terminal and a second clock signal terminal.

[0210] In the odd-numbered reset drive circuit, the first clock signal terminal CKA of the reset shift register is connected to one of the first reset clock signal lines G3_CLK1 and G3_CLK2, and the second clock signal terminal is connected to the other of the first reset clock signal lines G3_CLK1 and G3_CLK2. Furthermore, the first clock signal terminals CKA of adjacent reset shift registers are connected to different reset clock signal lines.

[0211] In the even-numbered reset drive circuit, the first clock signal terminal CKA of the reset shift register is connected to one of the third reset clock signal lines G3_CLK3 and the fourth reset clock signal line G3_CLK4, and the second clock signal terminal is connected to the other of the third reset clock signal lines G3_CLK3 and the fourth reset clock signal line G3_CLK4. Furthermore, the first clock signal terminal CKA of adjacent reset shift registers is connected to different reset clock signal lines.

[0212] Figure 10 A schematic diagram of the structure of a shift register provided for an exemplary embodiment Figure 1 , Figure 11 A schematic diagram of the structure of a shift register provided for an exemplary embodiment Figure 2 .like Figure 10 and Figure 11 As shown, the shift register includes: a first node control sub-circuit, a second node control sub-circuit, a third node control word circuit, and an output control sub-circuit. The shift register also includes: an illumination shift register, a control shift register, and a reset shift register.

[0213] like Figure 10 As shown, the first node control sub-circuit is electrically connected to the first clock signal terminal CKA, the second clock signal terminal CKB, the first power supply terminal VDD, the signal input terminal IN, the first node Q, and the second node P, respectively. It is configured to provide the first power supply terminal VDD or the second clock signal terminal CKB to the first node Q under the control of the first clock signal terminal CKA, the signal input terminal IN, and the second node P.

[0214] like Figure 11As shown, the first node control sub-circuit can be electrically connected to the first clock signal terminal CKA, the second clock signal terminal CKB, the signal input terminal IN, the first node Q, and the second node P respectively. It is configured to provide the first clock signal terminal CKA or the second clock signal terminal CKB to the first node Q under the control of the first clock signal terminal CKA, the signal input terminal IN, and the second node P.

[0215] like Figure 10 and Figure 11 As shown, the second node control sub-circuit is electrically connected to the second clock signal terminal CKB, the first power supply terminal VDD, the signal input terminal IN, and the second node P, respectively. It is configured to provide the first power supply terminal VDD or the second clock signal terminal CKB to the second node P under the control of the signal input terminal IN and the second clock signal terminal CKB.

[0216] like Figure 10 and Figure 11 As shown, the third node control sub-circuit is electrically connected to the first node Q, the second node P, the third node QB and the first clock signal terminal CKA, respectively. It is configured to provide the first clock signal terminal CKA or the second power supply terminal VGL signal to the third node QB under the control of the first clock signal terminal CKA, the first node Q and the second node P.

[0217] like Figure 10 and Figure 11 As shown, the output control sub-circuit is electrically connected to the first node Q, the third node QB, the first power supply terminal VDD, the second power supply terminal VGL, the cascaded signal output terminal OUTCR, the first signal output terminal OUT1, the second signal output terminal OUT2, the third signal output terminal OUT3, and the fourth signal output terminal OUT4, respectively. It is configured to provide the first power supply terminal VDD or the second power supply terminal VGL signal to the cascaded signal output terminal OUTCR, the first signal output terminal OUT1, the second signal output terminal OUT2, the third signal output terminal OUT3, and the fourth signal output terminal OUT4 under the control of the first node Q, the third node QB, and the first power supply terminal VDD.

[0218] Figure 12 A schematic diagram of the structure of a shift register provided for an exemplary embodiment Figure 3 , Figure 13 A schematic diagram of the structure of a shift register provided for an exemplary embodiment Figure 4 The shift register also includes a noise reduction sub-circuit. This noise reduction sub-circuit is electrically connected to the noise reduction signal terminal TRST, the first clock signal terminal CKA, the first power supply terminal VDD, the first node Q, and the third node QB, respectively. It is configured to provide the first clock signal terminal CKA to the first node Q and the first power supply terminal VDD to the third node QB under the control of the noise reduction signal terminal TRST. Figure 12 The following explanation is based on the example of the first node control sub-circuit being electrically connected to the first clock signal terminal CKA, the second clock signal terminal CKB, the first power supply terminal VDD, the signal input terminal IN, the first node Q, and the second node P. Figure 13 This explanation will be based on the example of the first node control sub-circuit, which can be electrically connected to the first clock signal terminal CKA, the second clock signal terminal CKB, the signal input terminal IN, the first node Q, and the second node P.

[0219] This disclosure improves the reliability of the shift register by setting a noise reduction sub-circuit to ensure that the signals at the cascaded signal output terminals of the shift register and from the first signal output terminal to the fourth signal output terminal can be pulled low, thereby avoiding erroneous outputs.

[0220] Figure 14 An equivalent circuit for a shift register Figure 1 , Figure 15 An equivalent circuit for a shift register Figure 2 , Figure 16 An equivalent circuit for a shift register Figure 3 , Figure 17 An equivalent circuit for a shift register Figure 4 . Figure 14 and Figure 16 The following explanation is based on the example of the first node control sub-circuit being electrically connected to the first clock signal terminal CKA, the second clock signal terminal CKB, the first power supply terminal VDD, the signal input terminal IN, the first node Q, and the second node P. Figure 15 and Figure 17 The following explanation is based on the example of the first node control sub-circuit being electrically connected to the first clock signal terminal CKA, the second clock signal terminal CKB, the signal input terminal IN, the first node Q, and the second node P.

[0221] In some exemplary embodiments, such as Figure 14 and Figure 16As shown, the first node control sub-circuit may include: a first transistor T1, a second transistor T2, a tenth transistor T10, and an eleventh transistor T11. Specifically, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CKA, the first terminal of the first transistor T1 is electrically connected to the first power supply terminal VDD, and the second terminal of the first transistor T1 is electrically connected to the first terminal of the second transistor T2. The control electrode of the second transistor T2 is electrically connected to the signal input terminal IN, and the second terminal of the second transistor T2 is electrically connected to the first node Q. The control electrode of the tenth transistor T10 is electrically connected to the second node P, the first terminal of the tenth transistor T10 is electrically connected to the first node Q, and the second terminal of the tenth transistor T10 is electrically connected to the first terminal of the eleventh transistor T11. The control electrode of the eleventh transistor T11 is electrically connected to the first clock signal terminal CKA, and the second terminal of the eleventh transistor T11 is electrically connected to the second clock signal terminal CKB.

[0222] In some exemplary embodiments, such as Figure 15 and Figure 17 As shown, the first node control sub-circuit may include: a first transistor T1, a second transistor T2, a tenth transistor T10, and an eleventh transistor T11. Specifically, the control electrode and first electrode of the first transistor T1 are electrically connected to the first clock signal terminal CKA, and the second electrode of the first transistor T1 is electrically connected to the first electrode of the second transistor T2. The control electrode of the second transistor T2 is electrically connected to the signal input terminal IN, and the second electrode of the second transistor T2 is electrically connected to the first node Q. The control electrode of the tenth transistor T10 is electrically connected to the second node P, the first electrode of the tenth transistor T10 is electrically connected to the first node Q, and the second electrode of the tenth transistor T10 is electrically connected to the first electrode of the eleventh transistor T11. The control electrode of the eleventh transistor T11 is electrically connected to the first clock signal terminal CKA, and the second electrode of the eleventh transistor T11 is electrically connected to the second clock signal terminal CKB.

[0223] Figures 14 to 17 Two exemplary structures of the first node control sub-circuit are shown. It will be readily understood by those skilled in the art that the implementation of the first node control sub-circuit is not limited to these.

[0224] In some exemplary embodiments, Figures 14 to 17As shown, the second node control sub-circuit may include: a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. Specifically, the control electrode of the third transistor T3 is electrically connected to the second clock signal terminal CKB, the first electrode of the third transistor T3 is electrically connected to the first power supply terminal VDD, and the second electrode of the third transistor T3 is electrically connected to the second node P. The control electrode of the fourth transistor T4 is electrically connected to the signal input terminal IN, the first electrode of the fourth transistor T4 is electrically connected to the second node P, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the fifth transistor T5. The control electrode of the fifth transistor T5 is electrically connected to the signal input terminal IN, and the second electrode of the fifth transistor T5 is electrically connected to the second clock signal terminal CKB. The control electrode of the sixth transistor T6 is electrically connected to the second node P, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VDD, and the second electrode of the sixth transistor T6 is electrically connected to the second electrode of the fourth transistor T4.

[0225] Figures 14 to 17 Two exemplary structures of the second node control sub-circuit are shown. It will be readily understood by those skilled in the art that the implementation of the second node control sub-circuit is not limited to these.

[0226] In some exemplary embodiments, Figures 14 to 17 As shown, the third node control sub-circuit includes: a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a first capacitor C1. Specifically, the control electrode of the seventh transistor T7 is electrically connected to the second node P, the first electrode of the seventh transistor T7 is electrically connected to the first clock signal terminal CKA, and the second electrode of the seventh transistor T7 is electrically connected to the first electrode of the eighth transistor T8; the control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CKA, and the second electrode of the eighth transistor T8 is electrically connected to the third node QB; the control electrode of the ninth transistor T9 is electrically connected to the first node Q, the first electrode of the ninth transistor T9 is electrically connected to the third node QB, and the second electrode of the ninth transistor T9 is electrically connected to the second power supply terminal VGL; the first terminal of the first capacitor C1 is electrically connected to the second node P, and the second terminal of the first capacitor C1 is electrically connected to the second electrode of the seventh transistor T7.

[0227] Figures 14 to 17 Two exemplary structures of the third node control sub-circuit are shown. It will be readily understood by those skilled in the art that the implementation of the third node control sub-circuit is not limited to these.

[0228] In some exemplary embodiments, Figure 14 and Figure 15As shown, the output control sub-circuit includes: the twelfth transistor T12 to the twenty-second transistor T22, as well as the second capacitor C2 and the third capacitor C3.Specifically, the control electrode of the twelfth transistor T12 is electrically connected to the first power supply terminal VDD, the first electrode of the twelfth transistor T12 is electrically connected to the first node Q, and the second electrode of the twelfth transistor T12 is electrically connected to the fourth node D; the control electrode of the thirteenth transistor T13 is electrically connected to the fourth node D, the first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal VDD, and the second electrode of the thirteenth transistor T13 is electrically connected to the cascaded signal output terminal OUTCR; the control electrode of the fourteenth transistor T14 is electrically connected to the third node QB, the first electrode of the fourteenth transistor T14 is electrically connected to the second power supply terminal VGL, and the second electrode of the fourteenth transistor T14 is electrically connected to the cascaded signal output terminal OUTCR; the fifteenth crystal... The control electrode of transistor T15 is electrically connected to the fourth node D; the first electrode of the fifteenth transistor T15 is electrically connected to the first power supply terminal VDD; and the second electrode of the fifteenth transistor T15 is electrically connected to the first signal output terminal OUT1. The control electrode of the sixteenth transistor T16 is electrically connected to the third node QB; the first electrode of the sixteenth transistor T16 is electrically connected to the second power supply terminal VGL; and the second electrode of the sixteenth transistor T16 is electrically connected to the first signal output terminal OUT1. The control electrode of the seventeenth transistor T17 is electrically connected to the fourth node D; the first electrode of the seventeenth transistor T17 is electrically connected to the first power supply terminal VDD; and the second electrode of the seventeenth transistor T17 is electrically connected to the second signal output terminal OUT2. The eighteenth transistor T18… The control electrode of transistor T18 is electrically connected to the third node QB. The first electrode of transistor T18 is electrically connected to the second power supply terminal VGL, and the second electrode of transistor T18 is electrically connected to the second signal output terminal OUT2. The control electrode of transistor T19 is electrically connected to the fourth node D. The first electrode of transistor T19 is electrically connected to the first power supply terminal VDD, and the second electrode of transistor T19 is electrically connected to the third signal output terminal OUT3. The control electrode of transistor T20 is electrically connected to the third node QB. The first electrode of transistor T20 is electrically connected to the second power supply terminal VGL, and the second electrode of transistor T20 is electrically connected to the third signal output terminal OUT3. The control electrode of transistor T21 is electrically connected to the third node QB. The first electrode of transistor T20 is electrically connected to the second power supply terminal VGL, and the second electrode of transistor T20 is electrically connected to the third signal output terminal OUT3. The first terminal of the twenty-first transistor T21 is electrically connected to the fourth node D; the second terminal of the twenty-first transistor T21 is electrically connected to the first power supply terminal VDD; the second terminal of the twenty-first transistor T21 is electrically connected to the fourth signal output terminal OUT4; the control terminal of the twenty-second transistor T22 is electrically connected to the third node QB; the first terminal of the twenty-second transistor T22 is electrically connected to the second power supply terminal VGL; the second terminal of the twenty-second transistor T22 is electrically connected to the fourth signal output terminal OUT4; the first terminal of the second capacitor C2 is electrically connected to the fourth node D; the second terminal of the second capacitor C2 is electrically connected to the first signal output terminal OUT1; the first terminal of the third capacitor C3 is electrically connected to the third node QB; the second terminal of the third capacitor C3 is electrically connected to the second power supply terminal VGL.

[0229] In some exemplary embodiments, Figure 16 and Figure 17As shown, the output control sub-circuit includes: twelfth transistor T12 to twenty-eighth transistor T28, a second capacitor C2, and a third capacitor C3. Specifically, the control electrode of the twelfth transistor T12 is electrically connected to the first power supply terminal VDD, the first electrode of the twelfth transistor T12 is electrically connected to the first node Q, and the second electrode of the twelfth transistor T12 is electrically connected to the fourth node D; the control electrode of the thirteenth transistor T13 is electrically connected to the fourth node D, the first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal VDD, and the second electrode of the thirteenth transistor T13 is electrically connected to the cascaded signal output terminal OUTCR; the control electrode of the fourteenth transistor T14 is electrically connected to the third node QB, the first electrode of the fourteenth transistor T14 is electrically connected to the fifth node ND, and the second electrode of the fourteenth transistor T14 is electrically connected to the cascaded signal output terminal OUTCR; The control electrode of transistor T15 is electrically connected to the fourth node D; the first electrode of transistor T15 is electrically connected to the first power supply terminal VDD; and the second electrode of transistor T15 is electrically connected to the first signal output terminal OUT1. The control electrode of transistor T16 is electrically connected to the third node QB; the first electrode of transistor T16 is electrically connected to the fifth node ND; and the second electrode of transistor T16 is electrically connected to the first signal output terminal OUT1. The control electrode of transistor T17 is electrically connected to the fourth node D; the first electrode of transistor T17 is electrically connected to the first power supply terminal VDD; and the second electrode of transistor T17 is electrically connected to the second signal output terminal OUT2. The tenth... The control electrode of transistor T18 is electrically connected to the third node QB; the first electrode of transistor T18 is electrically connected to the fifth node ND; and the second electrode of transistor T18 is electrically connected to the second signal output terminal OUT2. The control electrode of transistor T19 is electrically connected to the fourth node D; the first electrode of transistor T19 is electrically connected to the first power supply terminal VDD; and the second electrode of transistor T19 is electrically connected to the third signal output terminal OUT3. The control electrode of transistor T20 is electrically connected to the third node QB; the first electrode of transistor T20 is electrically connected to the fifth node ND; and the second electrode of transistor T20 is electrically connected to the third signal output terminal OUT3. The twenty-first... The control electrode of transistor T21 is electrically connected to the fourth node D; the first electrode of the twenty-first transistor T21 is electrically connected to the first power supply terminal VDD; and the second electrode of the twenty-first transistor T21 is electrically connected to the fourth signal output terminal OUT4. The control electrode of the twenty-second transistor T22 is electrically connected to the third node QB; the first electrode of the twenty-second transistor T22 is electrically connected to the fifth node ND; and the second electrode of the twenty-second transistor T22 is electrically connected to the fourth signal output terminal OUT4. The control electrode of the twenty-third transistor T23 is electrically connected to the third node QB; the first electrode of the twenty-second transistor T22 is electrically connected to the second power supply terminal VGL; and the second electrode of the twenty-second transistor T22 is electrically connected to the fifth node ND.The control electrode of transistor T24 is electrically connected to the third node QB, and the first electrode of transistor T24 is electrically connected to the second power supply terminal VGL. The second electrode of transistor T22 is electrically connected to the fifth node ND. The control electrode of transistor T25 is electrically connected to the third node QB, and the first electrode of transistor T25 is electrically connected to the second power supply terminal VGL. The second electrode of transistor T25 is electrically connected to the fifth node ND. The control electrode of transistor T26 is electrically connected to the third node QB, and the first electrode of transistor T26 is electrically connected to the second power supply terminal VGL. The second electrode of transistor T26 is electrically connected to the fifth node ND. The twenty-seventh crystal... The control electrode of transistor T27 is electrically connected to the third node QB; the first electrode of the twenty-seventh transistor T27 is electrically connected to the second power supply terminal VGL; and the second electrode of the twenty-seventh transistor T27 is electrically connected to the fifth node ND. The control electrode of the twenty-eighth transistor T28 is electrically connected to the third node QB; the first electrode of the twenty-eighth transistor T28 is electrically connected to the second power supply terminal VGL; and the second electrode of the twenty-eighth transistor T28 is electrically connected to the fifth node ND. The first terminal of the second capacitor C2 is electrically connected to the fourth node D; and the second terminal of the second capacitor C2 is electrically connected to the first signal output terminal OUT1. The first terminal of the third capacitor C3 is electrically connected to the third node QB; and the second terminal of the third capacitor C3 is electrically connected to the second power supply terminal VGL.

[0230] Figures 14 to 17 Two exemplary structures of the output control sub-circuit are shown. It will be readily understood by those skilled in the art that the implementation of the output control sub-circuit is not limited to these.

[0231] In some exemplary embodiments, Figures 14 to 17 As shown, the noise reduction sub-circuit may include: a twenty-ninth transistor T29 and a thirtieth transistor T30. Specifically, the control electrode of the twenty-ninth transistor T29 is electrically connected to the noise reduction signal terminal TRST, its first electrode is electrically connected to the first clock signal terminal CKA, and its second electrode is electrically connected to the first node Q. Similarly, the control electrode of the thirtieth transistor T30 is electrically connected to the noise reduction signal terminal TRST, its first electrode is electrically connected to the first power supply terminal VDD, and its second electrode is electrically connected to the third node QB.

[0232] Figures 14 to 17 Two exemplary structures of the noise reduction sub-circuit are shown. It will be readily understood by those skilled in the art that the implementation of the noise reduction sub-circuit is not limited to these.

[0233] In one exemplary embodiment, the noise reduction signal terminal TRST is an active level signal before all shift registers start working, so that the signal of the first node Q is a low level signal and the signal of the third node Q3 is a high level signal.

[0234] Figure 14 and Figure 15 The difference and Figure 16 and Figure 17 The difference lies in the connection method of the first electrode of the first transistor. When the first electrode of the first transistor is electrically connected to the first clock signal line, it is more advantageous to utilize the narrow bezel design of medium and large-sized display substrates.

[0235] In one exemplary embodiment, transistors can be classified into N-type transistors and P-type transistors based on their characteristics. When a transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0236] In some exemplary embodiments, the first transistor T1 to the thirtieth transistor T30 can be either P-type or N-type transistors. Using the same type of transistor in the pixel circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the fifth transistor T5 can include both P-type and N-type transistors.

[0237] In some exemplary embodiments, when the transistor is an N-type transistor, the transistor can be an oxide transistor. Oxide transistors can reduce leakage current, improve the performance of the shift register, and reduce the power consumption of the shift register.

[0238] Figure 18 for Figures 14 to 17 The provided timing diagram for the shift register is shown. Figure 18 This explanation is based on the example that all transistors in the shift register are N-type transistors.

[0239] Figures 14 to 17 In the shift register shown, the twelfth transistor T12 is continuously turned on under the control of the first power supply terminal VGH.

[0240] The following is combined Figure 14 and Figure 18 Detailed description Figure 14 The operation of the multiple transistors and capacitors in the provided shift register from stage P1 to stage P6 is as follows:

[0241] In the first stage P1, the signal input at the signal input terminal IN is a high-level signal, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned on. Based on the signals input at the first clock signal terminal CKA and the second clock signal terminal CKB, the first stage P1 can include the following four sub-stages:

[0242] In the first sub-stage P11, the signal input to the first clock signal terminal CKA is a high-level signal, and the signal input to the second clock signal terminal CKB is a low-level signal. Because the signal input to the second clock signal terminal CKB is low, the third transistor T3 is cut off, and the signal at the first power supply terminal VGH cannot be written into the second node P. However, because the fourth transistor T4 and the fifth transistor T5 are turned on, the low-level signal at the second clock signal terminal CKB is written into the second node P, making the signal at the second node P low. Therefore, the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are cut off. Since the signal input to the first clock signal terminal CKA is a high-level signal, the first transistor T1, the eighth transistor T8, and the eleventh transistor T11 are turned on. Since the second transistor T2 is also turned on, the high-level signal of the first power supply terminal VGH is written into the first node Q, and the signal of the first node Q is a high-level signal. The ninth transistor T9 is turned on. The signal of the third node QB is pulled low by the low-level signal of the second power supply terminal VGL, and the signal of the third node QB is a low-level signal. The fourteenth transistor T14, the sixteenth transistor T16, the eighteenth transistor T18, the twentieth transistor T20, and the twenty-second transistor T22 are all turned off. The signals of the cascaded output terminal and the four signal output terminals are not pulled low by the low-level signal of the second power supply terminal VGL. Since the twelfth transistor T12 is turned on, the signal of the fourth node D is a high-level signal. The thirteenth transistor T13, the fifteenth transistor T15, the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are all turned on. The signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all high-level signals. During this stage, the signals of the second node P and the third node QB are low-level signals, the signals of the first node Q and the fourth node D are high-level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all high-level signals.

[0243] In the second sub-stage P12, the signals input to the first clock signal terminal CKA and the second clock signal terminal CKB are low-level signals. Because the signal input to the second clock signal terminal CKB is low-level, the third transistor T3 is turned off, and the high-level signal at the first power supply terminal VGH cannot be written into the second node P. However, because the fourth transistor T4 and the fifth transistor T5 are turned on, the low-level signal at the second clock signal terminal CKB is written into the second node P through the turned-on fourth transistor T4 and fifth transistor T5. The signal at the second node P remains low-level, and the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are turned off. Since the input signal at the first clock signal terminal CKA is a low-level signal, the first transistor T1, the eighth transistor T8, and the eleventh transistor T11 are cut off, and the first node Q maintains the high-level signal of the previous stage. The ninth transistor T9 remains on, and the signal of the third node QB is pulled low by the low-level signal of the second power supply terminal VGL. The signal of the third node QB remains a low-level signal. The fourteenth transistor T14, the sixteenth transistor T16, the eighteenth transistor T18, the twentieth transistor T20, and the twenty-second transistor T22 are all cut off, so that the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 will not be pulled low. Since the twelfth transistor T12 is on, the signal of the fourth node D remains a high-level signal. The thirteenth transistor T13, the fifteenth transistor T15, the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are all on, and the signals of the cascaded output terminal and the four signal output terminals are all high-level signals. During this stage, the signals of the second node P and the third node QB are low-level signals, the signals of the first node Q and the fourth node D are high-level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all high-level signals.

[0244] In the third sub-stage P13, the signal input to the first clock signal terminal CKA is a low-level signal, and the signal input to the second clock signal terminal CKB is a high-level signal. Because the signal input to the second clock signal terminal CKB is a high-level signal, the third transistor T3 is turned on, and the high-level signal of the first power supply terminal VGH is written into the second node P. The signal of the second node P is a high-level signal, and the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are all turned on. Since the input signal at the first clock signal terminal CKA is a low-level signal, the first transistor T1, the eighth transistor T8, and the eleventh transistor T11 are all turned off, and the first node Q maintains the high-level signal of the previous stage. The ninth transistor T9 continues to be turned on, and the signal of the third node QB is pulled low by the low-level signal of the second power supply terminal VGL. The signal of the third node QB continues to be a low-level signal. The fourteenth transistor T14, the sixteenth transistor T16, the eighteenth transistor T18, the twentieth transistor T20, and the twenty-second transistor T22 are all turned off, so that the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 will not be pulled low. Since the twelfth transistor T12 is turned on, the signal of the fourth node D continues to be a high-level signal. The thirteenth transistor T13, the fifteenth transistor T15, the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are all turned on, and the signals of the cascaded output terminal and the four signal output terminals are all high-level signals. In this stage, the signal of the third node QB is a low-level signal, the signals of the second node P, the first node Q and the fourth node D are all high-level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all high-level signals.

[0245] In the fourth sub-stage P14, the signals input to the first clock signal terminal CKA and the second clock signal terminal CKB are low-level signals. Because the signal input to the second clock signal terminal CKB is low-level, the third transistor T3 is turned off, and the high-level signal at the first power supply terminal VGH cannot be written into the second node P. However, because the fourth transistor T4 and the fifth transistor T5 are turned on, the low-level signal at the second clock signal terminal CKB is written into the second node P through the turned-on fourth transistor T4 and fifth transistor T5. The signal at the second node P is then low-level, and the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are turned off. Since the input signal at the first clock signal terminal CKA is a low-level signal, the first transistor T1, the eighth transistor T8, and the eleventh transistor T11 are cut off, the first node Q maintains the high-level signal of the previous stage, the ninth transistor T9 continues to conduct, the signal of the third node QB is pulled low by the low-level signal of the second power supply terminal VGL, the signal of the third node QB continues to be a low-level signal, the fourteenth transistor T14, the sixteenth transistor T16, the eighteenth transistor T18, the twentieth transistor T20, and the twenty-second transistor T22 are all cut off, so that the signals of the cascaded output terminal and the four signal output terminals will not be pulled low. Since the twelfth transistor T12 is conducting, the signal of the fourth node D continues to be a high-level signal, the thirteenth transistor T13, the fifteenth transistor T15, the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are all conducting, the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all high-level signals. During this stage, the signals of the second node P and the third node QB are low-level signals, the signals of the first node Q and the fourth node D are high-level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all high-level signals.

[0246] In the fifth sub-stage P15, the signal input to the first clock signal terminal CKA is a high-level signal, and the signal input to the second clock signal terminal CKB is a low-level signal. Because the signal input to the second clock signal terminal CKB is low, the third transistor T3 is cut off, and the high-level signal at the first power supply terminal VGH cannot be written into the second node P. However, because the fourth transistor T4 and the fifth transistor T5 are turned on, the low-level signal at the second clock signal terminal CKB is written into the second node P, making the signal at the second node P low. Therefore, the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are cut off. Since the input signal at the first clock signal terminal CKA is a high-level signal, the first transistor T1, the eighth transistor T8, and the eleventh transistor T11 are turned on. Since the second transistor T2 is also turned on, the high-level signal at the first power supply terminal VGH is written into the first node Q. The signal at the first node Q remains a high-level signal. The ninth transistor T9 is turned on. The signal at the third node QB is pulled low by the low-level signal at the second power supply terminal VGL. The signal at the third node QB is a low-level signal. The fourteenth transistor T14, the sixteenth transistor T16, the eighteenth transistor T18, the twentieth transistor T20, and the twenty-second transistor T22 are all turned off, so that the cascaded output terminal OUTCR and the signals at the four signal output terminals OUT1 to OUT4 are not pulled low. Since the twelfth transistor T12 is turned on, the signal at the fourth node D is a high-level signal. The thirteenth transistor T13, the fifteenth transistor T15, the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are all turned on. The cascaded output terminal OUTCR and the signals at the four signal output terminals OUT1 to OUT4 are all high-level signals. During this stage, the signals of the second node P and the third node QB are low-level signals, the signals of the first node Q and the fourth node D are high-level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all high-level signals.

[0247] In the sixth sub-stage P16, the signals input to the first clock signal terminal CKA and the second clock signal terminal CKB are low-level signals. Because the signal input to the second clock signal terminal CKB is low-level, the third transistor T3 is turned off, and the high-level signal at the first power supply terminal VGH cannot be written into the second node P. However, because the fourth transistor T4 and the fifth transistor T5 are turned on, the low-level signal at the second clock signal terminal CKB is written into the second node P through the turned-on fourth transistor T4 and fifth transistor T5. The signal at the second node P remains low-level, and the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are turned off. Since the input signal at the first clock signal terminal CKA is a low-level signal, the first transistor T1, the eighth transistor T8, and the eleventh transistor T11 are cut off, the first node Q maintains the high-level signal of the previous stage, the ninth transistor T9 continues to conduct, the signal of the third node QB is pulled low by the low-level signal of the second power supply terminal VGL, the signal of the third node QB continues to be a low-level signal, the fourteenth transistor T14, the sixteenth transistor T16, the eighteenth transistor T18, the twentieth transistor T20, and the twenty-second transistor T22 are all cut off, so that the signals of the cascaded output terminal and the four signal output terminals will not be pulled low. Since the twelfth transistor T12 is conducting, the signal of the fourth node D continues to be a high-level signal, the thirteenth transistor T13, the fifteenth transistor T15, the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are all conducting, the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all high-level signals. During this stage, the signals of the second node P and the third node QB are low-level signals, the signals of the first node Q and the fourth node D are high-level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all high-level signals.

[0248] Therefore, in the first stage, the signal of the second node P changes according to the signal of the second clock signal terminal CKB, the signal of the third node QB is always a low level signal, the signals of the first node Q and the fourth node D are always high level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are always high level signals.

[0249] In the second stage P2, both the signal input terminal IN and the first clock signal terminal CKA are low-level signals. Because the signal input terminal IN is low-level, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are all off. Similarly, because the signal input terminal CKA is low-level, the first transistor T1, the eighth transistor T8, and the eleventh transistor T11 are all off. Based on the signal input at the second clock signal terminal CKA, the second stage P2 can include the following two sub-stages:

[0250] In the first sub-stage P21, the signal input to the second clock signal terminal CKB is a high-level signal. Since the signal input to the second clock signal terminal CKB is a high-level signal, the third transistor T3 is turned on, and the high-level signal of the first power supply terminal VGH is written into the second node P. The signal of the second node P is a high-level signal, and the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are all turned on. Since both the first transistor T1 and the eleventh transistor T11 are off, the first node Q maintains the high-level signal of the previous stage. The ninth transistor T9 remains on. The signal of the third node QB is pulled low by the low-level signal of the second power supply terminal VGL, and the signal of the third node QB remains low. The fourteenth transistor T14, the sixteenth transistor T16, the eighteenth transistor T18, the twentieth transistor T20, and the twenty-second transistor T22 are all off, so that the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 will not be pulled low. Since the twelfth transistor T12 is on, the signal of the fourth node D remains high. The thirteenth transistor T13, the fifteenth transistor T15, the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are all on, and the signals of the cascaded output terminal and the four signal output terminals are all high. In this stage, the signal of the third node QB is a low-level signal, the signals of the second node P, the first node Q and the fourth node D are all high-level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all high-level signals.

[0251] In the second sub-stage H22, the signal input to the second clock signal terminal CKB is a low-level signal. Because the signal input to the second clock signal terminal CKB is a low-level signal, although the third transistor T3 is turned off, the fourth transistor T4 and the fifth transistor T5 are also turned off. Therefore, the low-level signal of the second clock signal terminal CKB cannot be written to the second node P. The second node P maintains the high-level signal of the previous stage, and the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are all turned on. Since both the first transistor T1 and the eleventh transistor T11 are off, the first node Q maintains the high-level signal of the previous stage. The ninth transistor T9 remains on. The signal of the third node QB is pulled low by the low-level signal of the second power supply terminal VGL, and the signal of the third node QB remains low. The fourteenth transistor T14, the sixteenth transistor T16, the eighteenth transistor T18, the twentieth transistor T20, and the twenty-second transistor T22 are all off, so that the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 will not be pulled low. Since the twelfth transistor T12 is on, the signal of the fourth node D remains high. The thirteenth transistor T13, the fifteenth transistor T15, the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are all on, and the signals of the cascaded output terminal and the four signal output terminals are all high. In this stage, the signal of the third node QB is a low-level signal, the signals of the second node P, the first node Q and the fourth node D are all high-level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all high-level signals.

[0252] Therefore, in the second stage, the signal of the third node QB is always a low level signal, the signals of the second node P, the first node Q and the fourth node D are always high level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are always high level signals.

[0253] In the third stage P3, both the signal input terminal IN and the second clock signal terminal CKB are low-level signals. Because the signal input terminal IN is low-level, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are all cut off. Because the signal input terminal CKB is low-level, the third transistor T3 is cut off. Based on the signal input at the first clock signal terminal CKA, the third stage P3 can include the following two sub-stages:

[0254] In the first sub-stage P31, the signal input to the first clock signal terminal CKA is a high-level signal. Because the signal input to the first clock signal terminal CKA is high, the first transistor T1, the eighth transistor T8, and the eleventh transistor T11 are turned on. Since the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all turned off, the second node P maintains the high-level signal from the previous stage, and the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are turned on. Because the tenth transistor T10 and the eleventh transistor T11 are turned on, the low-level signal of the second clock signal terminal CKB is written to the first node Q, and the signal of the first node Q is a low-level signal. Because the twelfth transistor T12 is turned on, the signal of the fourth node D is also a low-level signal. The thirteenth transistor T13, the fifteenth transistor T15, the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are all turned off. The ninth transistor T9 is turned off, and the signal of the third node QB will not be pulled low by the low-level signal of the second power supply terminal VGL. Because the seventh transistor T7 and the eighth transistor T8 are turned on, the high-level signal of the first clock signal terminal CKA is written to the third node QB, and the signal of the third node QB is a high-level signal. The fourteenth transistor T14, the sixteenth transistor T16, the eighteenth transistor T18, the twentieth transistor T20, and the twenty-second transistor T22 are all turned on. The cascaded output terminal OUTCR and the signals of the four signal output terminals OUT1 to OUT4 are pulled low by the low-level signal of the second power supply terminal VGL. During this stage, the signals of the second node P and the third node QB are high-level signals, the signals of the first node Q and the fourth node D are low-level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all low-level signals.

[0255] In the second sub-stage P32: the signal input to the first clock signal terminal CKA is a low-level signal. Because the signal input to the first clock signal terminal CKA is low, the first transistor T1, the eighth transistor T8, and the eleventh transistor T11 are turned off. Since the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all turned off, the second node P maintains the high-level signal from the previous stage, and the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are turned on. The signal at the first node Q remains at the low level of the previous stage. Since the twelfth transistor T12 is turned on, the signal at the fourth node D is also at a low level. The thirteenth transistor T13, the fifteenth transistor T15, the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are all turned off. The ninth transistor T9 is turned off. The signal at the third node QB will not be pulled low by the low level signal at the second power supply terminal VGL. Since the eighth transistor T8 is turned off, the low level signal at the first clock signal terminal CKA cannot be written to the third node QB. The third node QB remains at the high level of the previous stage. The fourteenth transistor T14, the sixteenth transistor T16, the eighteenth transistor T18, the twentieth transistor T20, and the twenty-second transistor T22 are all turned on. The signals at the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are pulled low by the low level signal at the second power supply terminal VGL. During this stage, the signals of the second node P and the third node QB are high-level signals, the signals of the first node Q and the fourth node D are low-level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all low-level signals.

[0256] Therefore, in the third stage, the signals of the second node P and the third node QB are continuously high-level signals, the signals of the first node Q and the fourth node D are continuously low-level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are continuously low-level signals.

[0257] In the fourth stage P4, the input signal at the signal input terminal IN is a high-level signal, while the input signal at the first clock signal terminal CKA is a low-level signal. Because the signal at the signal input terminal IN is high, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are all turned on. Because the signal at the first clock signal terminal CKA is low, the first transistor T1, the eighth transistor T8, and the eleventh transistor T11 are all turned off. Based on the signal input at the second clock signal terminal CKB, the fourth stage P4 can include the following two sub-stages:

[0258] In the first sub-stage P41, the signal input to the second clock signal terminal CKB is a high-level signal. Since the signal input to the second clock signal terminal CKB is a high-level signal, the third transistor T3 is turned on, and the high-level signal of the first power supply terminal VGH is written into the second node P. The signal of the second node P is a high-level signal, and the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are all turned on. Since both the first transistor T1 and the eleventh transistor T11 are off, the first node Q maintains the low-level signal of the previous stage. Since the twelfth transistor T12 is on, the signal of the fourth node D is also a low-level signal. The thirteenth transistor T13, the fifteenth transistor T15, the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are all off. The ninth transistor T9 is off, so the signal of the third node QB will not be pulled low by the low-level signal of the second power supply terminal VGL. Since the eighth transistor T8 is off, the low-level signal of the first clock signal terminal CKA cannot be written to the third node QB, so the third node QB maintains the high-level signal of the previous stage. The fourteenth transistor T14, the sixteenth transistor T16, the eighteenth transistor T18, the twentieth transistor T20, and the twenty-second transistor T22 are all on. The signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are pulled low by the low-level signal of the second power supply terminal VGL. During this stage, the signals of the second node P and the third node QB are high-level signals, the signals of the first node Q and the fourth node D are low-level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all low-level signals.

[0259] In the second sub-stage P42, the signal input to the second clock signal terminal CKB is a low-level signal. Because the signal input to the second clock signal terminal CKB is a low-level signal, the third transistor T3 is turned off. However, because the fourth transistor T4 and the fifth transistor T5 are turned on, the low-level signal of the second clock signal terminal CKB is written to the second node P. The signal of the second node P is a low-level signal, and the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are turned off. Since the first transistor T1, the tenth transistor T10, and the eleventh transistor T11 are all off, the first node Q maintains the low-level signal of the previous stage. Since the twelfth transistor T12 is on, the signal of the fourth node D is also a low-level signal. The thirteenth transistor T13, the fifteenth transistor T15, the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are all off. The ninth transistor T9 is off, so the signal of the third node QB will not be pulled low by the low-level signal of the second power supply terminal VGL. Since the eighth transistor T8 is off, the low-level signal of the first clock signal terminal CKA cannot be written to the third node QB, so the third node QB maintains the high-level signal of the previous stage. The fourteenth transistor T14, the sixteenth transistor T16, the eighteenth transistor T18, the twentieth transistor T20, and the twenty-second transistor T22 are all on. The signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are pulled low by the low-level signal of the second power supply terminal VGL. In this stage, the signal of the third node QB is a high-level signal, the signals of the second node P, the first node Q and the fourth node D are low-level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all low-level signals.

[0260] Therefore, in the fourth stage, the signal of the second node P changes according to the signal of the second clock signal terminal CKB, the signal of the third node QB remains high, the signals of the first node Q and the fourth node D remain low, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 remain low.

[0261] In stage P5, the input signal at signal input terminal IN is high, while the input signal at the second clock signal terminal CKB is low. Because the input signal at signal input terminal IN is high, transistors T2, T4, and T5 are all turned on. Because the input signal at the second clock signal terminal CKB is low, transistor T3 is turned off. Based on the signal input at the first clock signal terminal CKB, stage P5 can include the following two sub-stages:

[0262] In the first sub-stage P51, the signal input to the first clock signal terminal CKA is a high-level signal. Because the signal input to the first clock signal terminal CKA is high, the first transistor T1, the eighth transistor T8, and the eleventh transistor T11 are turned on. Because the fourth transistor T4 and the fifth transistor T5 are turned on, the low-level signal at the second clock signal terminal CKB is written to the second node P. The signal at the second node P is then low, and the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are turned off. Because the first transistor T1 and the second transistor T2 are turned on, the high-level signal of the first power supply terminal VGH is written to the first node Q, and the signal of the first node Q is a high-level signal. The ninth transistor T9 is continuously turned on, and the signal of the third node QB is pulled low by the low-level signal of the second power supply terminal VGL, so the signal of the third node QB is a low-level signal. The fourteenth transistor T14, the sixteenth transistor T16, the eighteenth transistor T18, the twentieth transistor T20, and the twenty-second transistor T22 are all turned off, so that the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 will not be pulled low. Because the twelfth transistor T12 is turned on, the signal of the fourth node D is continuously a high-level signal. The thirteenth transistor T13, the fifteenth transistor T15, the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are all turned on, and the signals of the cascaded output terminal and the four signal output terminals are all high-level signals. During this stage, the signals of the second node P and the third node QB are low-level signals, the signals of the first node Q and the fourth node D are high-level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all high-level signals.

[0263] In the second sub-stage P52, the signal input to the first clock signal terminal CKA is a low-level signal. Because the signal input to the first clock signal terminal CKA is low, the first transistor T1, the eighth transistor T8, and the eleventh transistor T11 are turned off. Because the fourth transistor T4 and the fifth transistor T5 are turned on, the low-level signal at the second clock signal terminal CKB is continuously written to the second node P, and the signal at the second node P remains low. Therefore, the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are turned off. Because the first transistor T1 is off, the low-level signal of the first clock signal terminal CKA cannot be written to the first node Q. The first node Q maintains the high-level signal of the previous stage. The ninth transistor T9 continues to be turned on. The signal of the third node QB is pulled low by the low-level signal of the second power supply terminal VGL. The signal of the third node QB is a low-level signal. The fourteenth transistor T14, the sixteenth transistor T16, the eighteenth transistor T18, the twentieth transistor T20, and the twenty-second transistor T22 are all off, so that the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 will not be pulled low. Because the twelfth transistor T12 is turned on, the signal of the fourth node D is a high-level signal. The thirteenth transistor T13, the fifteenth transistor T15, the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are all turned on. The signals of the cascaded output terminal and the four signal output terminals are all high-level signals. During this stage, the signals of the second node P and the third node QB are low-level signals, the signals of the first node Q and the fourth node D are high-level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all high-level signals.

[0264] Therefore, in the fifth stage, the signals of the second node P and the third node QB are low-level signals, the signals of the first node Q and the fourth node D are high-level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all high-level signals.

[0265] In stage P6, the input signal at signal input terminal IN is high, and the input signal at the first clock signal terminal CKA is low. Because the input signal at signal input terminal IN is high, transistors T2, T4, and T5 are all turned on. Because the input signal at the first clock signal terminal CKA is low, transistors T1, T8, and T11 are all turned off. Based on the signal input at the second clock signal terminal CKB, stage P6 can include the following two sub-stages:

[0266] In the first sub-stage P61, the signal input to the second clock signal terminal CKB is a high-level signal. Because the signal input to the second clock signal terminal CKB is high, the third transistor T3 is turned on, and the high-level signal at the first power supply terminal VGH is written into the second node P. Furthermore, because the fourth transistor T4 and the fifth transistor T5 are turned on, the high-level signal at the second clock signal terminal CKB is written into the second node P, making the signal at the second node P high. Therefore, the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are all turned on. Because the first transistor T1 and the eleventh transistor T11 are off, the first node Q maintains the high-level signal from the previous stage. The ninth transistor T9 remains on. The signal of the third node QB is pulled low by the low-level signal of the second power supply terminal VGL, making the signal of the third node QB a low-level signal. The fourteenth transistor T14, the sixteenth transistor T16, the eighteenth transistor T18, the twentieth transistor T20, and the twenty-second transistor T22 are all off, preventing the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 from being pulled low. Because the twelfth transistor T12 is on, the signal of the fourth node D remains a high-level signal. The thirteenth transistor T13, the fifteenth transistor T15, the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are all on, making the signals of the cascaded output terminal and the four signal output terminals high-level signals. In this stage, the signal of the third node QB is a low-level signal, the signals of the second node P, the first node Q, and the fourth node D are high-level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all high-level signals.

[0267] In the second sub-stage P62, the signal input to the second clock signal terminal CKB is a low-level signal. Because the signal input to the second clock signal terminal CKB is low, the third transistor T3 is turned off, and the high-level signal at the first power supply terminal VGH cannot be written into the second node P. Since the fourth transistor T4 and the fifth transistor T5 are turned on, the low-level signal at the second clock signal terminal CKB is written into the second node P, and the signal at the second node P is low. Therefore, the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are all turned off. Because the first transistor T1 and the eleventh transistor T11 are off, the first node Q maintains the high-level signal from the previous stage. The ninth transistor T9 remains on. The signal of the third node QB is pulled low by the low-level signal of the second power supply terminal VGL, making the signal of the third node QB a low-level signal. The fourteenth transistor T14, the sixteenth transistor T16, the eighteenth transistor T18, the twentieth transistor T20, and the twenty-second transistor T22 are all off, preventing the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 from being pulled low. Because the twelfth transistor T12 is on, the signal of the fourth node D remains a high-level signal. The thirteenth transistor T13, the fifteenth transistor T15, the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are all on, making the signals of the cascaded output terminal and the four signal output terminals high-level signals. In this stage, the signals of the second node P and the third node QB are low-level signals, the signals of the first node Q and the fourth node D are high-level signals, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 are all high-level signals.

[0268] Therefore, in the sixth stage, the signal of the second node P changes according to the signal of the second clock signal terminal CKB, the signal of the third node QB remains low, the signals of the first node Q and the fourth node D remain high, and the signals of the cascaded output terminal OUTCR and the four signal output terminals OUT1 to OUT4 remain high.

[0269] After the sixth phase, the fifth and sixth phases will be executed in sequence.

[0270] Combination Figure 15 and Figure 18 , Figure 15 The working process of the provided shift register and Figure 14 The difference in the operation of the shift register is that when the first transistor T1 and the second transistor T2 are turned on, the high-level signal written to the first node N1 is the high-level signal of the first clock signal terminal CKA.

[0271] Combination Figure 16 and Figure 18 As shown, Figure 16The working process of the provided shift register and Figure 14 The difference in the provided working process is that when the third node N3 is a high-level signal, all of the twenty-third transistor T23 to the twenty-eighth transistor T28 are turned on. Even if the signal of the first power supply terminal VGH is written into the fifth node ND, the signal of the fifth node ND is pulled low because the twenty-fourth transistor T24 to the twenty-eighth transistor T28 are turned on. The signal of the second power supply terminal VGL is written into the cascaded signal output terminal OUTCR and the first signal output terminal OUT1 to the fourth signal output terminal OUT4.

[0272] Combination Figure 17 and Figure 18 As shown, Figure 17 The working process of the provided shift register and Figure 15 The difference in the provided working process is that when the third node N3 is a high-level signal, all of the twenty-third transistor T23 to the twenty-eighth transistor T28 are turned on. Even if the signal of the first power supply terminal VGH is written into the fifth node ND, the signal of the fifth node ND is pulled low because the twenty-fourth transistor T24 to the twenty-eighth transistor T28 are turned on. The signal of the second power supply terminal VGL is written into the cascaded signal output terminal OUTCR and the first signal output terminal OUT1 to the fourth signal output terminal OUT4.

[0273] Figure 19 This is a timing diagram of the signal lines connected to the LED driver circuit group. (Example:) Figure 19 As shown, the display substrate may further include: an initial light emission signal line EM_STV; the signal input terminal of the first-stage light emission shift register in the M light emission driving circuits is electrically connected to the initial light emission signal line. Figure 19 This explanation uses M=4 as an example, and this disclosure does not impose any limitations on it.

[0274] In some exemplary embodiments, such as Figure 19 As shown, the initial light-emitting signal line EM_STV consists of M valid level pulse signals, and the i-th valid level pulse signal is the signal input terminal of the first-stage light-emitting shift register in the i-th light-emitting driving circuit.

[0275] In some exemplary embodiments, such as Figure 19 As shown, the time difference between the start time of the i-th effective level pulse signal of the initial light emission signal line and the start time of the (i+1)-th effective level pulse signal of the initial light emission signal line is Hi*H, where Hi is the row number corresponding to the resolution of the i-th partition, and H is the data writing time of a row of pixel circuits.

[0276] In some exemplary embodiments, such as Figure 19As shown, the data write time Hmin*H of the lowest resolution partition is greater than the duration T of the effective level pulse signal of the initial emission signal line, and Hmin is the number of rows corresponding to the resolution of the lowest resolution partition. For example, Hmin can be 60. Figure 19 This explanation will be based on the example of T=40H.

[0277] In some exemplary embodiments, such as Figure 19 As shown, the content displayed on the display substrate includes: multiple display frames. When the end time of the first valid level pulse signal of the first light-emitting clock signal line EM_CLK 1 is earlier than the start time of the first valid level pulse signal of the second light-emitting clock signal line EM_CLK 2, the first light-emitting clock signal line EM_CLK 1 is the first reference light-emitting clock signal line. When the end time of the first valid level pulse signal of the second light-emitting clock signal line EM_CLK 2 is earlier than the start time of the first valid level pulse signal of the first light-emitting clock signal line EM_CLK 1, the second light-emitting clock signal line EM_CLK 2 is the first reference light-emitting clock signal line. Figure 19 The explanation is based on the example of the first light-emitting clock signal line being the first reference light-emitting clock signal line.

[0278] In some exemplary embodiments, such as Figure 19 As shown, within a display frame, the signals of the first reference light-emitting clock signal line include: M1 signal areas, where M1 is the number of odd numbers in M, and within the s-th signal area, the output signal of the 2s-1-th light-emitting driving circuit, where s = 1, 2, ..., M1. Figure 19 This explanation uses M1=2 as an example.

[0279] In some exemplary embodiments, such as Figure 19 As shown, within the s-th signal region, the number of valid level pulse signals on the first reference light-emitting clock signal line satisfies EMNum_s=H 2s-1 / N0+M0 / H 2s-1 N0 = 2H 2s-1 / Hmin, M0 = Hmin * T / 2. For example, when H 2s-1 When Hmin = 60, EMNum_s = 240 / 8 + 1200 / 240 = 35, where 240 / 8 H are used for shifting, and 1200 / 240 H are used to compensate for the duration T of the effective level pulse signal of the initial light-emitting signal line.

[0280] Figure 19 Therefore, within the s-th signal region, the period of the signal on the first reference emission clock line is H. 2s-1The following explanation uses *H / 30 as an example, where the duration of the effective level pulse signal on the first reference light-emitting clock signal line is 3H / 4.

[0281] In some exemplary embodiments, such as Figure 19 As shown, when the end time of the first valid level pulse signal of the third light-emitting clock signal line EM_CLK3 is earlier than the start time of the first valid level pulse signal of the fourth light-emitting clock signal line EM_CLK4, the third light-emitting clock signal line EM_CLK3 is the second reference light-emitting clock signal line. When the end time of the first valid level pulse signal of the fourth light-emitting clock signal line EM_CLK4 is earlier than the start time of the first valid level pulse signal of the third light-emitting clock signal line EM_CLK3, the fourth light-emitting clock signal line EM_CLK4 is the second reference light-emitting clock signal line. Figure 19 This explanation uses the third luminous clock signal line EM_CLK 3 as the first reference luminous clock signal line as an example.

[0282] In some exemplary embodiments, such as Figure 19 As shown, within a display frame, the signals of the second reference light-emitting clock signal line include: M2 signal areas; M2 is the number of even numbers in M, and the 2t-th light-emitting driving circuit outputs a signal in the t-th signal area, where t = 1, 2, ..., M2. Figure 19 This explanation uses M1=2 as an example.

[0283] In some exemplary embodiments, such as Figure 19 As shown, within the t-th signal region, the number of valid level pulse signals on the second reference light-emitting clock signal line satisfies EMNum_t≥H 2t / N1+M0 / H 2t N1 = 2H 2t / Hmin. For example, when H 2t When Hmin = 60, EMNum_t = 240 / 8 + 1200 / 240 = 35, where 240 / 8 H are used for shifting, and 1200 / 240 H are used to compensate for the duration T of the effective level pulse signal of the initial light-emitting signal line.

[0284] Figure 19 Therefore, within the t-th signal region, the period of the signal on the second reference emission clock line is H. 2t The following explanation uses *H / 30 as an example, where the duration of the effective level pulse signal on the second reference light-emitting clock signal line is 3H / 4.

[0285] Figure 20 This is a timing diagram of the signal lines connected to the control drive circuit group. (Example:) Figure 20As shown, the display substrate may further include: a control initial signal line G2_STV; the signal input terminal of the first-stage control shift register in the M control drive circuits is electrically connected to the control initial signal line. Figure 20 This explanation uses M=4 as an example, and this disclosure does not impose any limitations on it.

[0286] In some exemplary embodiments, such as Figure 20 As shown, the signal controlling the initial signal line G2_STV consists of M valid level pulse signals, and the i-th valid level pulse signal is the signal input terminal of the first-stage control shift register in the i-th control drive circuit.

[0287] In some exemplary embodiments, such as Figure 20 As shown, the time difference between the start time of the i-th valid level pulse signal of the control initial signal line and the start time of the (i+1)-th valid level pulse signal of the control initial signal line is Hi*H, where Hi is the row number corresponding to the resolution of the i-th partition. For example, if the resolution of the i-th partition is 1920 (columns) * 120 (rows), then Hi = 120, and H is the data writing time of one row of pixel circuit.

[0288] In some exemplary embodiments, such as Figure 20 As shown, the data write time Hmin*H of the lowest resolution partition is greater than the duration T of the effective level pulse signal of the control initial signal line. Hmin is the number of rows corresponding to the resolution of the lowest resolution partition. For example, if the resolution of the lowest resolution partition is 1920 (columns) * 40 (rows), then Hmin = 40. For example, Hmin can be 60. Figure 20 This explanation will be based on the example of T=40H.

[0289] In some exemplary embodiments, such as Figure 20 As shown, the content displayed on the display substrate includes: multiple display frames. When the end time of the first valid level pulse signal of the first control clock signal line G2_CLK 1 is earlier than the start time of the first valid level pulse signal of the second control clock signal line G2_CLK 2, the first control clock signal line G2_CLK 1 is the first reference control clock signal line. When the end time of the first valid level pulse signal of the second control clock signal line G2_CLK 2 is earlier than the start time of the first valid level pulse signal of the first control clock signal line G2_CLK 1, the second control clock signal line G2_CLK 2 is the first reference control clock signal line. Figure 20 The explanation will be based on the example of the first control clock signal line being the first reference control clock signal line.

[0290] In some exemplary embodiments, such as Figure 20As shown, within a display frame, the signals of the first reference control clock signal line include: M1 signal areas, where M1 is the number of odd numbers in M, and within the s-th signal area, the 2s-1-th control drive circuit output signal, where s = 1, 2, ..., M1. Figure 20 This explanation uses M1=2 as an example.

[0291] In some exemplary embodiments, such as Figure 20 As shown, within the s-th signal region, the number of valid level pulse signals on the first reference control clock signal line satisfies G2Num_s=H 2s-1 / N0+M0 / H 2s-1 N0 = 2H 2s-1 / Hmin, M0 = Hmin * T / 2. For example, when H 2s-1 When Hmin = 60, G2Num_s = 240 / 8 + 1200 / 240 = 35, where 240 / 8 H are used for shifting, and 1200 / 240 H are used to compensate for the duration T of the effective level pulse signal of the control initial signal line.

[0292] Figure 20 Therefore, within the s-th signal region, the period of the first reference control clock signal line is H. 2s-1 The following explanation uses *H / 30 as an example, where the duration of the effective level pulse signal on the first reference control clock signal line is 3H / 4.

[0293] In some exemplary embodiments, such as Figure 20 As shown, when the end time of the first valid level pulse signal of the third control clock signal line G2_CLK3 is earlier than the start time of the first valid level pulse signal of the fourth control clock signal line G2_CLK4, the third control clock signal line G2_CLK3 is the second reference control clock signal line. When the end time of the first valid level pulse signal of the fourth control clock signal line G2_CLK4 is earlier than the start time of the first valid level pulse signal of the third control clock signal line G2_CLK3, the fourth control clock signal line G2_CLK4 is the second reference control clock signal line. Figure 20 This explanation uses the third control clock signal line G2_CLK 3 as the first reference control clock signal line as an example.

[0294] In some exemplary embodiments, such as Figure 20 As shown, within a display frame, the signals of the second reference control clock signal line include: M2 signal areas; M2 is the number of even numbers in M, and the 2tth control drive circuit output signal in the t-th signal area, t = 1, 2, ..., M2. Figure 20 This explanation uses M1=2 as an example.

[0295] In some exemplary embodiments, such as Figure 20 As shown, within the t-th signal region, the number of valid level pulse signals on the second reference control clock signal line satisfies G2Num_t≥H 2t / N1+M0 / H 2t N1 = 2H 2t / Hmin. For example, when H 2t When Hmin = 60, G2Num_t = 240 / 8 + 1200 / 240 = 35, where 240 / 8 H are used for shifting, and 1200 / 240 H are used to compensate for the duration T of the effective level pulse signal of the control initial signal line.

[0296] Figure 20 Therefore, within the t-th signal region, the period of the second reference control clock signal line is H. 2t The following explanation uses *H / 30 as an example, where the duration of the effective level pulse signal on the second reference light-emitting clock signal line is 3H / 4.

[0297] Figure 21 This is a timing diagram of the signal lines connected to the reset drive circuit group. (Example:) Figure 21 As shown, the display substrate may further include: a reset initial signal line G3_STV; the signal input terminal of the first-stage reset shift register in the M reset drive circuits is electrically connected to the reset initial signal line. Figure 21 This explanation uses M=4 as an example, and this disclosure does not impose any limitations on it.

[0298] In some exemplary embodiments, such as Figure 21 As shown, the reset initial signal line G3_STV consists of M valid level pulse signals, and the i-th valid level pulse signal is the signal input terminal of the first-stage reset shift register in the i-th reset drive circuit.

[0299] In some exemplary embodiments, such as Figure 21 As shown, the time difference between the start time of the i-th valid level pulse signal of the reset initial signal line and the start time of the (i+1)-th valid level pulse signal of the reset initial signal line is Hi*H, where Hi is the row number corresponding to the resolution of the i-th partition, and H is the data writing time of a row of pixel circuits.

[0300] In some exemplary embodiments, such as Figure 21 As shown, the data write time Hmin*H of the lowest resolution partition is greater than the duration T of the effective level pulse signal of the reset initial signal line, where Hmin is the number of rows corresponding to the resolution of the lowest resolution partition. For example, Hmin can be 60. Figure 21This explanation will be based on the example of T=40H.

[0301] In some exemplary embodiments, such as Figure 21 As shown, the content displayed on the display substrate includes: multiple display frames. When the end time of the first valid level pulse signal of the first reset clock signal line G3_CLK 1 is earlier than the start time of the first valid level pulse signal of the second reset clock signal line G3_CLK 2, the first reset clock signal line G3_CLK 1 is the first reference reset clock signal line. When the end time of the first valid level pulse signal of the second reset clock signal line G3_CLK 2 is earlier than the start time of the first valid level pulse signal of the first reset clock signal line G3_CLK 1, the second reset clock signal line G3_CLK 2 is the first reference reset clock signal line. Figure 21 This explanation uses the first reset clock signal line as the first reference reset clock signal line as an example.

[0302] In some exemplary embodiments, such as Figure 21 As shown, within a display frame, the signals of the first reference reset clock signal line include: M1 signal areas, where M1 is the number of odd numbers in M, and the 2s-1th reset drive circuit output signal in the s-th signal area, where s = 1, 2, ..., M1. Figure 21 This explanation uses M1=2 as an example.

[0303] In some exemplary embodiments, such as Figure 21 As shown, within the s-th signal region, the number of valid level pulse signals on the first reference reset clock signal line satisfies G3Num_s=H 2s-1 / N0+M0 / H 2s-1 N0 = 2H 2s-1 / Hmin, M0 = Hmin * T / 2. For example, when H 2s-1 When Hmin = 60, G3Num_s = 240 / 8 + 1200 / 240 = 35, where 240 / 8 H are used for shifting, and 1200 / 240 H are used to compensate for the duration T of the effective level pulse signal of the reset initial signal line.

[0304] Figure 21 Therefore, within the s-th signal region, the period of the first reference reset clock signal line is H. 2s-1 The following explanation uses *H / 30 as an example, where the duration of the effective level pulse signal on the first reference reset clock signal line is 3H / 4.

[0305] In some exemplary embodiments, such as Figure 21As shown, when the end time of the first valid level pulse signal of the third reset clock signal line G3_CLK 3 is earlier than the start time of the first valid level pulse signal of the fourth reset clock signal line G3_CLK 4, the third reset clock signal line G3_CLK 3 is the second reference reset clock signal line. When the end time of the first valid level pulse signal of the fourth reset clock signal line G3_CLK 4 is earlier than the start time of the first valid level pulse signal of the third reset clock signal line G3_CLK 3, the fourth reset clock signal line G3_CLK 4 is the second reference reset clock signal line. Figure 21 This explanation uses the third reset clock signal line G3_CLK 3 as the first reference reset clock signal line as an example.

[0306] In some exemplary embodiments, such as Figure 21 As shown, within a display frame, the signals of the second reference reset clock signal line include: M2 signal areas; M2 is the number of even numbers in M, and the 2tth reset drive circuit output signal in the t-th signal area, t = 1, 2, ..., M2. Figure 21 This explanation uses M1=2 as an example.

[0307] In some exemplary embodiments, such as Figure 21 As shown, within the t-th signal region, the number of valid level pulses on the second reference reset clock signal line satisfies G3Num_t≥H 2t / N1+M0 / H 2t N1 = 2H 2t / Hmin. For example, when H 2t When Hmin = 60, G3Num_t = 240 / 8 + 1200 / 240 = 35, where 240 / 8 H are used for shifting, and 1200 / 240 H are used to compensate for the duration T of the effective level pulse signal of the reset initial signal line.

[0308] Figure 21 Therefore, within the t-th signal region, the period of the second reference reset clock signal line is H. 2t The following explanation uses *H / 30 as an example, where the duration of the effective level pulse signal on the second reference reset clock signal line is 3H / 4.

[0309] like Figures 19 to 21This disclosure utilizes the data writing time of the pixel circuit in the first partition and the data writing time of the pixel circuit in the second partition to ensure that the first signal area of ​​the first reference clock signal line (the first reference light emission clock signal line, the first reference control clock signal line, and the first reference reset clock signal line) can realize the internal compensation of the pixel circuit in the first partition. It also utilizes the data writing time of the pixel circuit in the third partition and the data writing time of the pixel circuit in the fourth partition to ensure that the second signal area of ​​the first reference clock signal line can realize the internal compensation of the pixel circuit in the third partition. The same principle applies to other odd-numbered partitions.

[0310] like Figures 19 to 21 This disclosure utilizes the data writing time of the pixel circuit in the second partition and the data writing time of the pixel circuit in the third partition to ensure that the first signal area of ​​the second reference clock signal line (second reference light emission clock signal line, second reference control clock signal line and second reference reset clock signal line) can realize the internal compensation of the pixel circuit in the second partition. It also utilizes the data writing time of the pixel circuit in the fourth partition and the data writing time of the pixel circuit in the fifth partition to ensure that the second signal area of ​​the second reference clock signal line can realize the internal compensation of the pixel circuit in the fourth partition. The same principle applies to other even-numbered partitions.

[0311] This disclosure also provides a display device, including: such as a display substrate.

[0312] The display substrate is the same as the display substrate provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0313] In one exemplary embodiment, the display device can be a liquid crystal display (LCD) or an organic light-emitting diode (OLED) display device. The display device can be any product or component with display functionality, such as a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light-emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0314] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0315] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0316] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: Display area and non-display area, the display area is provided with an array of pixel circuits, and the display area is divided into M partitions along a first direction; The pixel circuit includes: a write transistor, an anode reset transistor, a gate control transistor, a light-emitting transistor, and a first scan signal line, a second scan signal line, a third scan signal line, and a light-emitting signal line extending along a second direction. The display substrate includes: a light-emitting initial signal line, a control initial signal line, and a reset initial signal line. The first scan signal line is electrically connected to the write transistor, the second scan signal line is electrically connected to the gate control transistor, the third scan signal line is electrically connected to the anode reset transistor, and the light-emitting signal line is connected to the light-emitting transistor. M is a positive integer greater than or equal to 2. The non-display area is provided with a light-emitting driving circuit group, a control driving circuit group, a reset driving circuit group, a first light-emitting clock signal line to a fourth light-emitting clock signal line, a first control clock signal line to a fourth control clock signal line, and a first reset clock signal line to a fourth reset clock signal line. The light-emitting driving circuit group includes: M light-emitting driving circuits, the i-th light-emitting driving circuit is connected to the light-emitting signal line in the pixel circuit of the i-th partition, the odd-numbered light-emitting driving circuits are electrically connected to the first light-emitting clock signal line and the second light-emitting clock signal line, and the even-numbered light-emitting driving circuits are connected to the third light-emitting clock signal line and the fourth light-emitting clock signal line, i=1,2,...,M. The light-emitting driving circuit includes: a light-emitting shift register, the light-emitting shift register includes: a signal input terminal; the signal input terminal of the first-stage light-emitting shift register in the M light-emitting driving circuits is electrically connected to the initial light-emitting signal line; the signal of the initial light-emitting signal line is M valid level pulse signals, and the i-th valid level pulse signal is the signal of the signal input terminal of the first-stage light-emitting shift register in the i-th light-emitting driving circuit; And / or, the control drive circuit group includes: M control drive circuits, the i-th control drive circuit being connected to the second scan signal line in the pixel circuit of the i-th partition, the odd-numbered control drive circuits being electrically connected to the first control clock signal line and the second control clock signal line, and the even-numbered control drive circuits being connected to the third control clock signal line and the fourth control clock signal line; the control drive circuit includes: a control shift register, the control shift register including: a signal input terminal, the signal input terminal of the first-stage control shift register in the M control drive circuits being electrically connected to the control initial signal line; the signal of the control initial signal line is M valid level pulse signals, and the i-th valid level pulse signal is the signal of the signal input terminal of the first-stage control shift register in the i-th control drive circuit; And / or, the reset drive circuit group includes: M reset drive circuits, the i-th reset drive circuit is connected to the third scan signal line in the pixel circuit of the i-th partition, the odd-numbered reset drive circuits are electrically connected to the first reset clock signal line and the second reset clock signal line, and the even-numbered reset drive circuits are connected to the third reset clock signal line and the fourth reset clock signal line. The reset drive circuit includes: a reset shift register, the reset shift register includes: a signal input terminal, the signal input terminal of the first-stage reset shift register in the M reset drive circuits is electrically connected to the reset initial signal line; the signal of the reset initial signal line is M valid level pulse signals, and the i-th valid level pulse signal is the signal of the signal input terminal of the first-stage reset shift register in the i-th reset drive circuit.

2. The display substrate according to claim 1, wherein, The first partition includes pixel circuits from the first row to the N1st row, and the j-th partition includes: the Nth row... j-1 +1 row pixel circuit to the Nth j Pixel circuit, j=2, ...,M; The light-emitting shift register further includes: a cascaded signal output terminal, a first signal output terminal, a second signal output terminal, a third signal output terminal, and a fourth signal output terminal; The first light-emitting driving circuit includes: N1 / 4 cascaded light-emitting shift registers. The cascaded signal output terminal of the x-th stage light-emitting shift register in the first light-emitting driving circuit is connected to the signal input terminal of the (x+1)-th stage light-emitting shift register. The first, second, third, and fourth signal output terminals of the x-th stage light-emitting shift register in the first light-emitting driving circuit are respectively connected to the light-emitting signal lines of the 4x-3 row pixel circuit, the 4x-2 row pixel circuit, the 4x-1 row pixel circuit, and the 4x row pixel circuit, where x = 1, 2, ..., N1 / 4. The j-th light-emitting driving circuit includes: (N) j -N j-1 The j-th cascaded light-emitting shift register consists of four cascaded light-emitting shift registers. The cascaded signal output of the y-th stage light-emitting shift register in the j-th light-emitting driver circuit is connected to the signal input of the (y+1)-th stage light-emitting shift register. The first, second, third, and fourth signal outputs of the y-th stage light-emitting shift register in the j-th light-emitting driver circuit are respectively connected to the N-th stage light-emitting shift register. j-1 +4y-3 row pixel circuit light-emitting signal line, Nth j-1 +4y-2 row pixel circuit light-emitting signal line, Nth j-1 +4y-1 row pixel circuit light-emitting signal line and Nth j-1 The light-emitting signal lines of the +4y row pixel circuit are connected, y=1,2,..., (N) j -N j-1 ) / 4.

3. The display substrate according to claim 2, wherein, The light-emitting shift register further includes: a first clock signal terminal and a second clock signal terminal; The first clock signal terminal of the light-emitting shift register in the odd-numbered light-emitting driving circuit is connected to one of the first light-emitting clock signal line and the second light-emitting clock signal line, and the second clock signal terminal is connected to the other light-emitting clock signal line among the first light-emitting clock signal line and the second light-emitting clock signal line. Furthermore, the first clock signal terminals of adjacent light-emitting shift registers are connected to different light-emitting clock signal lines. In the even-numbered light-emitting driver circuit, the first clock signal terminal of the light-emitting shift register is connected to one of the third and fourth light-emitting clock signal lines, and the second clock signal terminal is connected to the other of the third and fourth light-emitting clock signal lines. Furthermore, the first clock signal terminals of adjacent light-emitting shift registers are connected to different light-emitting clock signal lines.

4. The display substrate according to claim 2, wherein, The control shift register further includes: a cascaded signal output terminal, a first signal output terminal, a second signal output terminal, a third signal output terminal, and a fourth signal output terminal; The first control drive circuit includes: N1 / 4 cascaded control shift registers. The cascaded signal output terminal of the x-th stage control shift register in the first control drive circuit is connected to the signal input terminal of the (x+1)-th stage control shift register. The first, second, third, and fourth signal output terminals of the x-th stage control shift register in the first control drive circuit are respectively connected to the second scan signal lines of the 4x-3 row pixel circuit, the 4x-2 row pixel circuit, the 4x-1 row pixel circuit, and the 4x row pixel circuit, where x = 1, 2, ..., N1 / 4. The j-th control drive circuit includes: (N) j -N j-1 (4 cascaded control shift registers, the cascaded signal output terminal of the y-th stage control shift register in the j-th control drive circuit is connected to the signal input terminal of the (y+1)-th stage control shift register, and the first, second, third, and fourth signal output terminals of the y-th stage control shift register in the j-th control drive circuit are respectively connected to the N-th stage control shift register.) j-1 The second scan signal line of the +4y-3 row pixel circuit, the Nth j-1 The second scan signal line of the +4y-2 row pixel circuit, the Nth... j-1 The second scan signal line and the Nth row pixel circuit of +4y-1 j-1 The second scan signal line of the +4y row pixel circuit is connected, y=1,2,..., (N) j -N j-1 ) / 4.

5. The display substrate according to claim 4, wherein, The control shift register further includes: a first clock signal terminal and a second clock signal terminal; The first clock signal terminal of the control shift register in the odd-numbered control drive circuit is connected to one of the first control clock signal lines and the second control clock signal line, and the second clock signal terminal is connected to the other control clock signal line among the first and second control clock signal lines. Furthermore, the first clock signal terminals of adjacent control shift registers are connected to different control clock signal lines. In the even-numbered control drive circuit, the first clock signal terminal of the control shift register is connected to one of the third and fourth control clock signal lines, and the second clock signal terminal is connected to the other of the third and fourth control clock signal lines. Furthermore, the first clock signal terminals of adjacent control shift registers are connected to different control clock signal lines.

6. The display substrate according to claim 2, wherein, The reset shift register further includes: a cascaded signal output terminal, a first signal output terminal, a second signal output terminal, a third signal output terminal, and a fourth signal output terminal; The first reset drive circuit includes: N1 / 4 cascaded reset shift registers. The cascaded signal output terminal of the x-th stage reset shift register in the first reset drive circuit is connected to the signal input terminal of the (x+1)-th stage reset shift register. The first, second, third, and fourth signal output terminals of the x-th stage reset shift register in the first reset drive circuit are respectively connected to the third scan signal lines of the 4x-3 row pixel circuit, the 4x-2 row pixel circuit, the 4x-1 row pixel circuit, and the 4x row pixel circuit, where x = 1, 2, ..., N1 / 4. The j-th reset drive circuit includes: (N j -N j-1 A cascaded reset shift register system consists of four stages. The cascaded signal output of the y-th stage reset shift register in the j-th reset driver circuit is connected to the signal input of the (y+1)-th stage reset shift register. The first, second, third, and fourth signal outputs of the y-th stage reset shift register in the j-th reset driver circuit are respectively connected to the N-th stage reset shift register. j-1 The third scan signal line of the +4y-3 row pixel circuit, the Nth j-1 The third scan signal line of the +4y-2 row pixel circuit, the Nth j-1 The third scan signal line and the Nth line of the +4y-1 row pixel circuit j-1 The third scan signal line of the +4y row pixel circuit is connected, y=1,2,……,(N j -N j-1 ) / 4.

7. The display substrate according to claim 6, wherein, The reset shift register further includes: a first clock signal terminal and a second clock signal terminal; The first clock signal terminal of the reset shift register in the odd-numbered reset drive circuit is connected to one of the first reset clock signal lines and the second reset clock signal line, and the second clock signal terminal is connected to the other of the first reset clock signal lines and the second reset clock signal line. Furthermore, the first clock signal terminals of adjacent reset shift registers are connected to different reset clock signal lines. In the even-numbered reset drive circuit, the first clock signal terminal of the reset shift register is connected to one of the third and fourth reset clock signal lines, and the second clock signal terminal is connected to the other of the third and fourth reset clock signal lines. Furthermore, the first clock signal terminals of adjacent reset shift registers are connected to different reset clock signal lines.

8. The display substrate according to claim 1, wherein, The shift register includes: a first node control sub-circuit, a second node control sub-circuit, a third node control sub-circuit, and an output control sub-circuit. The shift register also includes: an illumination shift register, a control shift register, and a reset shift register. The first node control sub-circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the signal input terminal, the first node, and the second node, respectively, and is configured to provide the first power supply terminal or the second clock signal terminal to the first node under the control of the first clock signal terminal, the signal input terminal, and the second node; The second node control sub-circuit is electrically connected to the second clock signal terminal, the first power supply terminal, the signal input terminal, and the second node, respectively, and is configured to provide the first power supply terminal or the second clock signal terminal to the second node under the control of the signal input terminal and the second clock signal terminal; The third node control sub-circuit is electrically connected to the first node, the second node, the third node and the first clock signal terminal respectively, and is configured to provide the third node with a signal from the first clock signal terminal or the second power supply terminal under the control of the first clock signal terminal, the first node and the second node. The output control sub-circuit is electrically connected to the first node, the third node, the first power supply terminal, the second power supply terminal, the cascaded signal output terminal, the first signal output terminal, the second signal output terminal, the third signal output terminal, and the fourth signal output terminal, respectively. It is configured to provide the first power supply terminal or the second power supply terminal signal to the cascaded signal output terminal, the first signal output terminal, the second signal output terminal, the third signal output terminal, and the fourth signal output terminal under the control of the first node, the third node, and the first power supply terminal.

9. The display substrate according to claim 1, wherein, The shift register includes: a first node control sub-circuit, a second node control sub-circuit, a third node control sub-circuit, and an output control sub-circuit. The shift register also includes: an illumination shift register, a control shift register, and a reset shift register. The first node control sub-circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the signal input terminal, the first node, and the second node, respectively, and is configured to provide the first node with a signal from the first clock signal terminal or the second clock signal terminal under the control of the first clock signal terminal, the signal input terminal, and the second node. The second node control sub-circuit is electrically connected to the second clock signal terminal, the first power supply terminal, the signal input terminal, and the second node, respectively, and is configured to provide the first power supply terminal or the second clock signal terminal to the second node under the control of the signal input terminal and the second clock signal terminal; The third node control sub-circuit is electrically connected to the first node, the second node, the third node and the first clock signal terminal respectively, and is configured to provide the third node with a signal from the first clock signal terminal or the second power supply terminal under the control of the first clock signal terminal, the first node and the second node. The output control sub-circuit is electrically connected to the first node, the third node, the first power supply terminal, the second power supply terminal, the cascaded signal output terminal, the first signal output terminal, the second signal output terminal, the third signal output terminal, and the fourth signal output terminal, respectively. It is configured to provide the first power supply terminal or the second power supply terminal signal to the cascaded signal output terminal, the first signal output terminal, the second signal output terminal, the third signal output terminal, and the fourth signal output terminal under the control of the first node, the third node, and the first power supply terminal.

10. The display substrate according to claim 8 or 9, wherein, The shift register further includes: a noise reduction sub-circuit; The noise reduction sub-circuit is electrically connected to the noise reduction signal terminal, the first clock signal terminal, the first power supply terminal, the first node, and the third node, respectively, and is configured to provide the first clock signal terminal to the first node and the first power supply terminal to the third node under the control of the noise reduction signal terminal.

11. The display substrate according to claim 8, wherein, The first node control sub-circuit includes: a first transistor, a second transistor, a tenth transistor, and an eleventh transistor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the first power supply terminal, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor. The control electrode of the second transistor is electrically connected to the signal input terminal, and the second electrode of the second transistor is electrically connected to the first node. The control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor. The control terminal of the eleventh transistor is electrically connected to the first clock signal terminal, and the second terminal of the eleventh transistor is electrically connected to the second clock signal terminal.

12. The display substrate according to claim 9, wherein, The first node control sub-circuit includes: a first transistor, a second transistor, a tenth transistor, and an eleventh transistor; The control electrode and the first electrode of the first transistor are electrically connected to the first clock signal terminal, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor. The control electrode of the second transistor is electrically connected to the signal input terminal, and the second electrode of the second transistor is electrically connected to the first node. The control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor. The control terminal of the eleventh transistor is electrically connected to the first clock signal terminal, and the second terminal of the eleventh transistor is electrically connected to the second clock signal terminal.

13. The display substrate according to claim 11 or 12, wherein, The second node control sub-circuit includes: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; The control electrode of the third transistor is electrically connected to the second clock signal terminal, the first electrode of the third transistor is electrically connected to the first power supply terminal, and the second electrode of the third transistor is electrically connected to the second node. The control electrode of the fourth transistor is electrically connected to the signal input terminal, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor. The control electrode of the fifth transistor is electrically connected to the signal input terminal, and the second electrode of the fifth transistor is electrically connected to the second clock signal terminal; The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the second electrode of the fourth transistor.

14. The display substrate according to claim 13, wherein, The third node control sub-circuit includes: a seventh transistor, an eighth transistor, a ninth transistor, and a first capacitor; The control electrode of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the first clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor. The control terminal of the eighth transistor is electrically connected to the first clock signal terminal, and the second terminal of the eighth transistor is electrically connected to the third node. The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the third node, and the second electrode of the ninth transistor is electrically connected to the second power supply terminal. The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the second electrode of the seventh transistor.

15. The display substrate according to claim 14, wherein, The output control sub-circuit includes: the twelfth transistor to the twenty-second transistor, as well as a second capacitor and a third capacitor; The control electrode of the twelfth transistor is electrically connected to the first power supply terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the fourth node. The control electrode of the thirteenth transistor is electrically connected to the fourth node, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the cascaded signal output terminal. The control electrode of the fourteenth transistor is electrically connected to the third node, the first electrode of the fourteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourteenth transistor is electrically connected to the cascaded signal output terminal. The control electrode of the fifteenth transistor is electrically connected to the fourth node, the first electrode of the fifteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifteenth transistor is electrically connected to the first signal output terminal. The control electrode of the sixteenth transistor is electrically connected to the third node, the first electrode of the sixteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the sixteenth transistor is electrically connected to the first signal output terminal. The control electrode of the seventeenth transistor is electrically connected to the fourth node, the first electrode of the seventeenth transistor is electrically connected to the first power supply terminal, and the second electrode of the seventeenth transistor is electrically connected to the second signal output terminal. The control electrode of the eighteenth transistor is electrically connected to the third node, the first electrode of the eighteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the eighteenth transistor is electrically connected to the second signal output terminal. The control electrode of the nineteenth transistor is electrically connected to the fourth node, the first electrode of the nineteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the nineteenth transistor is electrically connected to the third signal output terminal. The control electrode of the twentieth transistor is electrically connected to the third node, the first electrode of the twentieth transistor is electrically connected to the second power supply terminal, and the second electrode of the twentieth transistor is electrically connected to the third signal output terminal. The control electrode of the 21st transistor is electrically connected to the fourth node, the first electrode of the 21st transistor is electrically connected to the first power supply terminal, and the second electrode of the 21st transistor is electrically connected to the fourth signal output terminal. The control electrode of the 22nd transistor is electrically connected to the third node, the first electrode of the 22nd transistor is electrically connected to the second power supply terminal, and the second electrode of the 22nd transistor is electrically connected to the fourth signal output terminal. The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the first signal output terminal. The first terminal of the third capacitor is electrically connected to the third node, and the second terminal of the third capacitor is electrically connected to the second power supply terminal.

16. The display substrate according to claim 14, wherein, The output control sub-circuit includes: the twelfth to twenty-eighth transistors, as well as a second capacitor and a third capacitor; The control electrode of the twelfth transistor is electrically connected to the first power supply terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the fourth node. The control electrode of the thirteenth transistor is electrically connected to the fourth node, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the cascaded signal output terminal. The control electrode of the fourteenth transistor is electrically connected to the third node, the first electrode of the fourteenth transistor is electrically connected to the fifth node, and the second electrode of the fourteenth transistor is electrically connected to the cascaded signal output terminal. The control electrode of the fifteenth transistor is electrically connected to the fourth node, the first electrode of the fifteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifteenth transistor is electrically connected to the first signal output terminal. The control electrode of the sixteenth transistor is electrically connected to the third node, the first electrode of the sixteenth transistor is electrically connected to the fifth node, and the second electrode of the sixteenth transistor is electrically connected to the first signal output terminal. The control electrode of the seventeenth transistor is electrically connected to the fourth node, the first electrode of the seventeenth transistor is electrically connected to the first power supply terminal, and the second electrode of the seventeenth transistor is electrically connected to the second signal output terminal. The control electrode of the eighteenth transistor is electrically connected to the third node, the first electrode of the eighteenth transistor is electrically connected to the fifth node, and the second electrode of the eighteenth transistor is electrically connected to the second signal output terminal. The control electrode of the nineteenth transistor is electrically connected to the fourth node, the first electrode of the nineteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the nineteenth transistor is electrically connected to the third signal output terminal. The control electrode of the twentieth transistor is electrically connected to the third node, the first electrode of the twentieth transistor is electrically connected to the fifth node, and the second electrode of the twentieth transistor is electrically connected to the third signal output terminal. The control electrode of the 21st transistor is electrically connected to the fourth node, the first electrode of the 21st transistor is electrically connected to the first power supply terminal, and the second electrode of the 21st transistor is electrically connected to the fourth signal output terminal. The control electrode of the 22nd transistor is electrically connected to the third node, the first electrode of the 22nd transistor is electrically connected to the fifth node, and the second electrode of the 22nd transistor is electrically connected to the fourth signal output terminal. The control electrode of the 23rd transistor is electrically connected to the third node, the first electrode of the 22nd transistor is electrically connected to the second power supply terminal, and the second electrode of the 22nd transistor is electrically connected to the fifth node. The control electrode of the 24th transistor is electrically connected to the third node, the first electrode of the 24th transistor is electrically connected to the second power supply terminal, and the second electrode of the 22nd transistor is electrically connected to the fifth node. The control electrode of the 25th transistor is electrically connected to the third node, the first electrode of the 25th transistor is electrically connected to the second power supply terminal, and the second electrode of the 25th transistor is electrically connected to the fifth node. The control electrode of the 26th transistor is electrically connected to the third node, the first electrode of the 26th transistor is electrically connected to the second power supply terminal, and the second electrode of the 26th transistor is electrically connected to the fifth node. The control electrode of the 27th transistor is electrically connected to the third node, the first electrode of the 27th transistor is electrically connected to the second power supply terminal, and the second electrode of the 27th transistor is electrically connected to the fifth node. The control electrode of the 28th transistor is electrically connected to the third node, the first electrode of the 28th transistor is electrically connected to the second power supply terminal, and the second electrode of the 28th transistor is electrically connected to the fifth node. The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the first signal output terminal. The first terminal of the third capacitor is electrically connected to the third node, and the second terminal of the third capacitor is electrically connected to the second power supply terminal.

17. The display substrate according to claim 10, wherein, The noise reduction sub-circuit includes: the twenty-ninth transistor and the thirtieth transistor; The control electrode of the 29th transistor is electrically connected to the noise reduction signal terminal, the first electrode of the 29th transistor is electrically connected to the first clock signal terminal, and the second electrode of the 29th transistor is electrically connected to the first node. The control electrode of the thirtieth transistor is electrically connected to the noise reduction signal terminal, the first electrode of the thirtieth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirtieth transistor is electrically connected to the third node.

18. The display substrate according to claim 2, wherein, The time difference between the start time of the i-th effective level pulse signal of the initial light emission signal line and the start time of the (i+1)-th effective level pulse signal of the initial light emission signal line is Hi. H, where Hi is the row number corresponding to the resolution of the i-th partition, and H is the data writing time of a row of pixel circuits; Data write time Hmin for the lowest resolution partition H is greater than the duration T of the effective level pulse signal of the initial emission signal line, and Hmin is the number of rows corresponding to the resolution of the lowest resolution partition.

19. The display substrate according to claim 18, wherein, The content displayed on the display substrate includes: multiple display frames. When the end time of the first valid level pulse signal of the first light-emitting clock signal line is earlier than the start time of the first valid level pulse signal of the second light-emitting clock signal line, the first light-emitting clock signal line is a first reference light-emitting clock signal line. When the end time of the first valid level pulse signal of the second light-emitting clock signal line is earlier than the start time of the first valid level pulse signal of the first light-emitting clock signal line, the second light-emitting clock signal line is a first reference light-emitting clock signal line. When the end time of the first valid level pulse signal of the third light-emitting clock signal line is earlier than the start time of the first valid level pulse signal of the fourth light-emitting clock signal line, the third light-emitting clock signal line is a second reference light-emitting clock signal line. When the end time of the first valid level pulse signal of the fourth light-emitting clock signal line is earlier than the start time of the first valid level pulse signal of the third light-emitting clock signal line, the fourth light-emitting clock signal line is a second reference light-emitting clock signal line. Within a display frame, the signals of the first reference light-emitting clock signal line include: M1 signal areas, where M1 is the number of odd numbers in M, and within the s-th signal area, the output signal of the 2s-1-th light-emitting driving circuit, where s = 1, 2, ..., M1; Within the s-th signal region, the number of valid level pulse signals on the first reference light-emitting clock signal line satisfies EMNum_s=H 2s-1 / N0+M0 / H 2s-1 N0 = 2H 2s-1 / Hmin, M0 = Hmin T / 2; Within a display frame, the signals of the second reference light-emitting clock signal line include: M2 signal areas; M2 is the number of even numbers in M; within the t-th signal area, the 2t-th light-emitting driving circuit outputs a signal, t=1,2,...,M2; Within the t-th signal region, the number of valid level pulse signals on the second reference light-emitting clock signal line satisfies EMNum_t. H 2t / N1+M0 / H 2t N1=2H 2t / Hmin.

20. The display substrate according to claim 2, wherein, The time difference between the start time of the i-th valid level pulse signal of the control initial signal line and the start time of the (i+1)-th valid level pulse signal of the control initial signal line is Hi. H, where Hi is the row number corresponding to the resolution of the i-th partition, and H is the data writing time of a row of pixel circuits; Data write time Hmin for the lowest resolution partition H is greater than the duration T of the effective level pulse signal of the control initial signal line, and Hmin is the number of rows corresponding to the resolution of the lowest resolution partition.

21. The display substrate according to claim 20, wherein, The content displayed on the display substrate includes: multiple display frames. When the end time of the first valid level pulse signal of the first control clock signal line is earlier than the start time of the first valid level pulse signal of the second control clock signal line, the first control clock signal line is a first reference control clock signal line. When the end time of the first valid level pulse signal of the second control clock signal line is earlier than the start time of the first valid level pulse signal of the first control clock signal line, the second control clock signal line is a first reference control clock signal line. When the end time of the first valid level pulse signal of the third control clock signal line is earlier than the start time of the first valid level pulse signal of the fourth control clock signal line, the third control clock signal line is a second reference control clock signal line. When the end time of the first valid level pulse signal of the fourth control clock signal line is earlier than the start time of the first valid level pulse signal of the third control clock signal line, the fourth control clock signal line is a second reference control clock signal line. Within a display frame, the signals of the first reference control clock signal line include: M1 signal areas, where M1 is the number of odd numbers in M, and within the s-th signal area, the output signal of the 2s-1-th control drive circuit, where s = 1, 2, ..., M1; Within the s-th signal region, the number of valid level pulse signals on the first reference control clock signal line satisfies G2Num_s=H 2s-1 / N0+M0 / H 2s-1 N0 = 2H 2s-1 / Hmin, M0 = Hmin T / 2; Within a display frame, the signals of the second reference control clock signal line include: M2 signal areas; M2 is the number of even numbers in M, and within the t-th signal area, the 2t-th control drive circuit outputs a signal, t=1,2,...,M2; Within the t-th signal region, the number of valid level pulse signals on the second reference control clock signal line satisfies G2Num_t. H 2t / N1+M0 / H 2t N1=2H 2t / Hmin.

22. The display substrate according to claim 2, wherein, The time difference between the start time of the i-th valid level pulse signal of the reset initial signal line and the start time of the (i+1)-th valid level pulse signal of the reset initial signal line is Hi. H, where Hi is the row number corresponding to the resolution of the i-th partition, and H is the data writing time of a row of pixel circuits; Data write time Hmin for the lowest resolution partition H is greater than the duration T of the effective level pulse signal of the reset initial signal line, and Hmin is the number of rows corresponding to the resolution of the lowest resolution partition.

23. The display substrate according to claim 22, wherein, The content displayed on the display substrate includes: multiple display frames. When the end time of the first valid level pulse signal of the first reset clock signal line is earlier than the start time of the first valid level pulse signal of the second reset clock signal line, the first reset clock signal line is the first reference reset clock signal line. When the end time of the first valid level pulse signal of the second reset clock signal line is earlier than the start time of the first valid level pulse signal of the first reset clock signal line, the second reset clock signal line is the first reference reset clock signal line. When the end time of the first valid level pulse signal of the third reset clock signal line is earlier than the start time of the first valid level pulse signal of the fourth reset clock signal line, the third reset clock signal line is the second reference reset clock signal line. When the end time of the first valid level pulse signal of the fourth reset clock signal line is earlier than the start time of the first valid level pulse signal of the third reset clock signal line, the fourth reset clock signal line is the second reference reset clock signal line. Within a display frame, the signals of the first reference reset clock signal line include: M1 signal areas, where M1 is the number of odd numbers in M, and within the s-th signal area, the 2s-1-th reset drive circuit output signal, s=1,2,...,M1; Within the s-th signal region, the number of valid level pulses on the first reference reset clock signal line satisfies G3Num_s=H 2s-1 / N0+M0 / H 2s-1 N0 = 2H 2s-1 / Hmin, M0 = Hmin T / 2; Within a display frame, the signals of the second reference reset clock signal line include: M2 signal areas; M2 is the number of even numbers in M, and the 2t-th reset drive circuit outputs a signal in the t-th signal area, t=1,2,...,M2; Within the t-th signal region, the number of valid level pulses on the second reference reset clock signal line satisfies G3Num_t. H 2t / N1+M0 / H 2t N1=2H 2t / Hmin.

24. A display device, comprising: The display substrate as described in any one of claims 1 to 23.

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