Gate driving circuit and display panel
By optimizing the channel length ratio of the pull-up control transistor and the scan signal output transistor, as well as the pull-down module design, the problem of the transistor being affected by parasitic capacitance was solved, improving the stability of the gate drive circuit and the display effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD
- Filing Date
- 2023-12-14
- Publication Date
- 2026-05-12
Smart Images
Figure CN117809546B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, specifically to a gate driving circuit and a display panel. Background Technology
[0002] Gate-driver-on-Array (GOA) technology utilizes the fabrication process of thin-film transistor arrays (TFT arrays) to fabricate gate driver circuitry on a TFT array substrate, enabling a row-by-row scanning driving method. The gate driver circuitry comprises multiple cascaded gate driver units.
[0003] Transistors in existing gate drive units are susceptible to parasitic capacitance and other factors, which can affect the potential of the pull-up node and result in poor stability of existing gate drive circuits. Summary of the Invention
[0004] The purpose of embodiments of this application is to provide a gate driving circuit and a display panel, wherein the gate driving circuit in the display panel has high stability.
[0005] On one hand, embodiments of this application provide a gate driving circuit, including a multi-stage cascaded gate driving unit. Each gate driving unit includes a pull-up control module, an output module, a pull-down module, a pull-down sustaining module, a first reference low-level signal input terminal, a second reference low-level signal input terminal, and a pull-up node located in the line between the pull-up control module and the output module. The pull-up control module includes a pull-up control transistor electrically connected to the pull-up node, and the pull-up control transistor is used to pull up the potential of the pull-up node. The output module includes a scan signal output transistor electrically connected to the pull-up node, and the scan signal output transistor is used to pull up the potential of the pull-up node. The current scanning signal is output under the control of the voltage level; the pull-down module is electrically connected to the pull-up node, the first reference low-level signal input terminal, and the pull-down sustaining module. The pull-down module is used to pull down the voltage of the pull-up node to the voltage of the first reference low-level signal input terminal; the pull-down sustaining module is electrically connected to the pull-up node and the second reference low-level signal input terminal. The pull-down sustaining module is used to keep the voltage of the pull-up node at the voltage of the second reference low-level signal input terminal; wherein, the ratio of the channel length of the pull-up control transistor to the channel length of the scanning signal output transistor is between 1:8 and 1:12.
[0006] Optionally, in some embodiments of this application, the channel length of the scan signal output transistor is between 12,000 micrometers and 33,000 micrometers.
[0007] Optionally, in some embodiments of this application, the pull-down module includes a first pull-down transistor and a second pull-down transistor; the first electrode of the first pull-down transistor is electrically connected to the first electrode of the second pull-down transistor and the pull-up node; the second electrode of the first pull-down transistor is electrically connected to the second electrode of the second pull-down transistor and a first reference low-level signal input terminal; the gate of the first pull-down transistor is electrically connected to a first control signal input terminal; the gate of the second pull-down transistor is electrically connected to a second control signal terminal; the first pull-down transistor and the second pull-down transistor are used to pull down the potential of the pull-up node; the sum of the channel length of the first pull-down transistor and the channel length of the second pull-down transistor is greater than or equal to the channel length of the pull-up control transistor.
[0008] Optionally, in some embodiments of this application, the pull-down module includes a third pull-down transistor, the first electrode of the third pull-down transistor is electrically connected to the first electrode of the second pull-down transistor and the pull-up node, the second electrode of the third pull-down transistor is electrically connected to the second electrode of the second pull-down transistor and the first reference low-level signal input terminal; the sum of the channel length of the third pull-down transistor, the channel length of the first pull-down transistor, and the channel length of the second pull-down transistor is greater than or equal to the channel length of the pull-up control transistor.
[0009] Optionally, in some embodiments of this application, the ratio of the sum of the channel lengths of the first pull-down transistor and the second pull-down transistor to the channel length of the pull-up control transistor is between 1:1 and 1.4:1; or, the ratio of the sum of the channel lengths of the first pull-down transistor and the third pull-down transistor to the channel length of the pull-up control transistor is between 1:1 and 1.4:1.
[0010] Optionally, in some embodiments of this application, the pull-down sustaining module includes a first pull-down sustaining transistor, a second pull-down sustaining transistor, a third pull-down sustaining transistor, and a fourth pull-down sustaining transistor; the gate and first electrode of the first pull-down sustaining transistor are electrically connected to a first clock signal input terminal, and the second electrode of the first pull-down sustaining transistor is electrically connected to the first electrode of the second pull-down sustaining transistor; the gate of the second pull-down sustaining transistor is electrically connected to the pull-up node, and the second electrode of the second pull-down sustaining transistor is electrically connected to a second reference low-level signal input terminal; the first electrode of the third pull-down sustaining transistor is electrically connected to the first clock signal input terminal, and the third pull-down sustaining transistor... The gate of the body transistor is electrically connected to the second electrode of the third pull-down transistor, and the second electrode of the third pull-down sustaining transistor is electrically connected to the first electrode of the fourth pull-down sustaining transistor; the gate of the fourth pull-down sustaining transistor is electrically connected to the pull-up node, and the second electrode of the fourth pull-down sustaining transistor is electrically connected to the second reference low-level signal input terminal; the first pull-down sustaining transistor, the second pull-down sustaining transistor, the third pull-down sustaining transistor, and the fourth pull-down sustaining transistor are used to maintain the potential of the pull-up node at a low potential; the ratio of the channel length of the first pull-down sustaining transistor to the channel length of the second pull-down sustaining transistor is between 1:4 and 1:8.
[0011] Optionally, in some embodiments of this application, the ratio of the current value flowing through the second electrode of the fourth pull-down sustaining transistor to the current value flowing through the second electrode of the third pull-down sustaining transistor is equal to M times the ratio of the difference between the voltage applied to the gate of the fourth pull-down sustaining transistor and the voltage applied to the second electrode of the fourth pull-down sustaining transistor and the difference between the voltage applied to the gate of the third pull-down sustaining transistor and the voltage applied to the second electrode of the third pull-down sustaining transistor, where M is a positive integer greater than 4.
[0012] Optionally, in some embodiments of this application, the pull-down sustaining module includes a fifth pull-down sustaining transistor and a sixth pull-down sustaining transistor; the gate of the fifth pull-down sustaining transistor is electrically connected to the pull-up node of the upper X-stage gate driving unit, the first electrode of the fifth pull-down sustaining transistor is electrically connected to the second electrode of the first pull-down sustaining transistor, and the second electrode of the fifth pull-down sustaining transistor is electrically connected to the second reference low-level signal input terminal, where X is a positive integer greater than or equal to 1; the gate of the sixth pull-down sustaining transistor is electrically connected to the pull-up node of the upper X-stage gate driving unit, the first electrode of the sixth pull-down sustaining transistor is electrically connected to the second electrode of the third pull-down sustaining transistor, and the second electrode of the sixth pull-down sustaining transistor is electrically connected to the second reference low-level signal input terminal; the channel length of the first pull-down sustaining transistor is equal to the channel length of the fifth pull-down sustaining transistor, and the channel length of the second pull-down sustaining transistor is equal to the channel length of the sixth pull-down sustaining transistor.
[0013] Optionally, in some embodiments of this application, during the conduction of the first pull-down sustaining transistor and the third pull-down sustaining transistor, the voltage values of the gate of the third pull-down sustaining transistor and the second electrode of the third pull-down sustaining transistor are between 24.52 volts and 26.84 volts.
[0014] On the other hand, this application provides a display panel including a plurality of pixel units and a gate driving circuit as described above, wherein the gate driving circuit is electrically connected to the plurality of pixel units.
[0015] In the gate driving circuit and display panel provided in the embodiments of this application, by setting the ratio of the channel length of the pull-up control transistor to the channel length of the scan signal output transistor to be between 1:8 and 1:12, the potential of the pull-up node, the time required for the scan signal to switch from a high potential to a low potential, the pixel charging rate, and the capacitor and resistance values in the gate driving unit are all in the optimal range, thereby improving the stability of the gate driving circuit. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the gate drive circuit provided in this application;
[0017] Figure 2 yes Figure 1 The circuit diagrams of the pull-up control module and output module of the gate drive unit provided in the document;
[0018] Figure 3 yes Figure 2 The simulation diagram shows the optimal ratio range of the channel length of the scanning signal output transistor to that of a conventional transistor.
[0019] Figure 4a yes Figure 2 The simulation diagram shows the optimal ratio range of the channel length of the pull-up control transistor to the channel length of the scan signal output transistor under normal temperature conditions.
[0020] Figure 4b yes Figure 2 The simulation diagram shows the optimal ratio range of the pull-up control transistor channel length to the scan signal output transistor under high temperature and high humidity conditions.
[0021] Figure 5 yes Figure 1 The first circuit diagram of the pull-down sustaining module of the gate drive unit provided in the document;
[0022] Figure 6 yes Figure 1 The first circuit diagram of the pull-down module of the gate drive unit provided in the document;
[0023] Figure 7 yes Figure 1 The second circuit diagram of the pull-down module of the gate drive unit provided in the document;
[0024] Figure 8 yes Figure 7 The simulation diagram shows the optimal ratio range of the channel length of the pull-down transistor to the channel length of the pull-up control transistor.
[0025] Figure 9 yes Figure 1 The second circuit diagram of the pull-down sustaining module of the gate drive unit provided in the diagram. Detailed Implementation
[0026] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.
[0027] The various embodiments provided in this application are similar, and features in different embodiments can be combined with each other.
[0028] An embodiment of this application provides a display panel including a plurality of pixel units and at least one gate driving circuit, wherein the gate driving circuit is electrically connected to the plurality of pixel units.
[0029] Specifically, the display panel includes multiple pixel units arranged in an array and multiple scan lines. Each scan line is electrically connected to a row of pixel units. The gate driving circuit includes multiple cascaded gate driving units. Each gate driving unit is electrically connected to at least one scan line, and the gate driving unit is used to provide a scan signal to the corresponding scan line to control the thin-film transistors in the pixel units of the corresponding row to turn on or off.
[0030] The gate drive unit includes at least one pull-up control transistor, at least one scan signal output transistor, at least one pull-down transistor, at least one pull-down sustaining transistor, and a pull-up node in the line between the pull-up control transistor and the scan signal output transistor. The pull-up control transistor is electrically connected to the pull-up node and is used to pull the potential of the pull-up node high. The scan signal output transistor is electrically connected to the pull-up node and is used to output the scan signal of this stage under the control of the potential of the pull-up node. The pull-down transistor is electrically connected to the pull-up node and is used to pull the potential of the pull-up node low. The pull-down sustaining transistor is electrically connected to the pull-up node and is used to maintain the potential of the pull-up node at a low level. The ratio of the channel length of the pull-up control transistor to the channel length of the scan signal output transistor is between 1:8 and 1:12.
[0031] The channel width of the pull-up control transistor is equal to the channel width of the scan signal output transistor.
[0032] In the embodiments of this application, the number of pull-up control transistor, scan signal output transistor, pull-down transistor, and pull-down sustaining transistor may each include one or more. Those skilled in the art can select according to actual needs. This application does not specifically limit the number of transistors.
[0033] The gate driving circuit in the display panel provided in the embodiments of this application sets the ratio of the channel length of the pull-up control transistor to the channel length of the scan signal output transistor to be between 1:8 and 1:12, so that the potential of the pull-up node, the time required for the scan signal to switch from a high potential to a low potential, the pixel charging rate, and the capacitor and resistance values in the gate driving unit are all in the optimal range, thereby improving the stability of the gate driving circuit.
[0034] The transistors used in all embodiments of this application can be thin-film transistors or other devices with similar characteristics. To distinguish the two terminals of a transistor other than the gate, one of the source and drain is referred to as the first electrode, and the other of the source and drain is referred to as the second electrode. According to the configuration shown in the accompanying drawings, the middle input terminal of the transistor is the gate, the signal input terminal is the first electrode, and the signal output terminal is the second electrode. Furthermore, the transistors used in the embodiments of this application are P-type transistors or N-type transistors. A P-type transistor conducts when the gate is at a low potential and is cut off when the gate is at a high potential; an N-type transistor conducts when the gate is at a high potential and is cut off when the gate is at a low potential.
[0035] like Figure 1 As shown, the gate driving circuit provided in the embodiments of this application includes multiple cascaded gate driving units. Figure 1 Take the cascaded gate drive unit GOA(NX), the Nth gate drive unit GOA(N), and the N+Xth gate drive unit GOA(N+X) as an example.
[0036] Specifically, the NX-level gate driving unit GOA(NX), the N-level gate driving unit GOA(N), and the N+X-level gate driving unit GOA(N+X) are connected to scan lines G(NX), G(N), and G(N+X), respectively. The gate of at least one pull-down transistor of the N-level gate driving unit GOA(N) is electrically connected to the pull-up node of the NX-level gate driving unit GOA(NX), and the gate of at least one pull-down transistor of the N+X-level gate driving unit GOA(N+X) is electrically connected to the pull-up node of the N-level gate driving unit GOA(N), and so on. Simultaneously, the NX-th level gate driving unit GOA(NX) transmits the scan signal to the scan line G(NX) connected to the NX-th level gate driving unit GOA(NX), the N-th level gate driving unit GOA(N) transmits the scan signal to the scan line G(N) connected to the N-th level gate driving unit GOA(N), the N+X-th level gate driving unit GOA(N+X) transmits the scan signal to the scan line G(N+X) connected to the N+X-th level gate driving unit GOA(N+X), and so on. The values of X and Y can be equal or unequal. Both X and Y are positive integers greater than 1; preferably, both X and Y are 2.
[0037] In this system, the first-stage gate driving unit transmits the scan signal to the first scan line connected to it in response to the start signal STV. It should be noted that the Nth-stage gate driving unit (where N is a positive integer greater than 1) can transmit the scan signal to the Nth scan line G(N).
[0038] Specifically, the scan drive control signal input terminal includes a first clock signal input terminal CK1 and a second clock signal input terminal CK2.
[0039] When the Nth gate driving unit is working, the scan signal output by the Nth gate driving unit GOA(N) is at a high potential, which is used to turn on the transistor switch of each pixel in a row of the display panel and charge the pixel electrode in each pixel through the data signal.
[0040] like Figure 2 As shown, an embodiment of this application provides a gate driving circuit, including a multi-stage cascaded gate driving unit. The gate driving unit includes a pull-up control module 101, an output module 102, a pull-down module 103, a pull-down sustaining module 104, a first reference low-level signal input terminal VSST, a second reference low-level signal input terminal VSSQ, and a pull-up node Q(N) in the line between the pull-up control module 101 and the output module 102.
[0041] The pull-up control module 101 includes a pull-up control transistor T1, which is electrically connected to the pull-up node Q(N). The pull-up control transistor T1 is used to pull up the potential of the pull-up node Q(N). Specifically, the gate of the pull-up control transistor T1 is electrically connected to the X-stage cascade signal output terminal ST(NX). The first electrode of the pull-up control transistor T1 is electrically connected to one of the following: the reference high-level input terminal VGH (not shown in the figure), the X-stage scan signal output terminal G(NX), and the X-stage cascade signal output terminal ST(NX). The second electrode of the pull-up control transistor T1 is electrically connected to the pull-up node Q(N). The pull-up control transistor T1 pulls up the potential of the pull-up node Q(N) under the control of the X-stage cascade signal input to the X-stage cascade signal output terminal ST(NX). Here, X is a positive integer greater than or equal to 1.
[0042] Output module 102 includes a scan signal output transistor T2, which is electrically connected to a pull-up node Q(N). The scan signal output transistor T2 is used to output the scan signal of this stage under the control of the potential of the pull-up node Q(N). Specifically, the gate of the scan signal output transistor T2 is electrically connected to the pull-up node Q(N), the first electrode of the scan signal output transistor T2 is electrically connected to the second clock signal input terminal CK(N), and the second electrode of the scan signal output transistor T2 is electrically connected to the scan signal output terminal G(N) of this stage. The scan signal output transistor T2 is used to output the scan signal of this stage through the scan signal output terminal G(N) of this stage under the control of the potential of the pull-up node Q(N).
[0043] The output module 102 also includes a stage signal output transistor T3. The gate of the stage signal output transistor T3 is electrically connected to the pull-up node Q(N). The first electrode of the stage signal output transistor T3 is electrically connected to the second clock signal input terminal CK(N). The second electrode of the stage signal output transistor T3 is electrically connected to the stage signal output terminal ST(N). The stage signal output transistor T3 is used to output the stage signal through the stage signal output terminal ST(N) under the potential control of the pull-up node Q(N).
[0044] The output module 102 also includes a first capacitor C1. The first plate of the first capacitor C1 is electrically connected to the pull-up node Q(N), and the second plate of the first capacitor C1 is electrically connected to the scan signal output terminal G(N) of this stage. The first capacitor C1 is used to stabilize the potential of the first node.
[0045] The pull-down module 103 is electrically connected to the pull-up node Q(N), the first reference low-level signal input terminal VSST, and the pull-down sustaining module 104. The pull-down module 103 is used to pull down the potential of the pull-up node Q(N) to the potential of the first reference low-level signal input terminal VSST.
[0046] The pull-down sustaining module 104 is electrically connected to the pull-up node Q(N) and the second reference low-level signal input terminal VSSQ. The pull-down sustaining module 104 is used to maintain the potential of the pull-up node Q(N) at the potential of the second reference low-level signal input terminal VSSQ. The ratio of the channel length of the pull-up control transistor T1 to the channel length of the scan signal output transistor T2 is between 1:8 and 1:12.
[0047] The channel width of the pull-up control transistor T1 is equal to the channel width of the scan signal output transistor T2.
[0048] The gate driving unit provided in this application sets the ratio of the channel length of the pull-up control transistor T1 to the channel length of the scan signal output transistor T2 to be between 1:8 and 1:12, so that the potential of the pull-up node Q(N), the time required for the scan signal to switch from a high potential to a low potential, the pixel charging rate, and the capacitor and resistance values in the gate driving unit are all in the optimal range, thereby improving the stability of the gate driving circuit.
[0049] In the embodiments of this application, the channel length of the scan signal output transistor T2 is 1.2 to 2.2 times that of the channel length of a conventional transistor, that is, the ratio of the channel length of the conventional transistor to the channel length of the scan signal output transistor T2 is between 1:1.2 and 1:2.2. The channel width of the scan signal output transistor T2 is equal to the channel width of the conventional transistor.
[0050] The channel length of a conventional transistor is typically between 10,000 and 15,000 micrometers. For example, the channel length of a conventional transistor can be 10,000 micrometers, 11,000 micrometers, 12,000 micrometers, 13,000 micrometers, 14,000 micrometers, or 15,000 micrometers. The channel of a conventional transistor comprises the product of the channels of multiple sub-transistors. For instance, if a conventional transistor includes 10 sub-transistors, then the channel length of the conventional transistor is equal to the channel length of each sub-transistor multiplied by 10. The channel length of the scan signal output transistor T2 is between 12,000 micrometers and 33,000 micrometers. For example, the channel length of the scan signal output transistor T2 can be 12,000 micrometers, 13,000 micrometers, 14,000 micrometers, 15,000 micrometers, 16,000 micrometers, 17,000 micrometers, 18,000 micrometers, 19,000 micrometers, 20,000 micrometers, 21,000 micrometers, 22,000 micrometers, 23,000 micrometers, 24,000 micrometers, 25,000 micrometers, 26,000 micrometers, 27,000 micrometers, 28,000 micrometers, 29,000 micrometers, 30,000 micrometers, 31,000 micrometers, 32,000 micrometers, or 33,000 micrometers. The channel length of the pull-up control transistor T1 is between 1,000 micrometers and 2,750 micrometers. Specifically, the channel length of the pull-up control transistor T1 is one-eighth or one-twelfth of the channel length of the scan signal output transistor T2.
[0051] Specifically, a conventional transistor includes multiple sub-transistors, and each sub-transistor includes a sub-channel. For example, if a conventional transistor includes 10 sub-transistors, then the channel length of the conventional transistor is equal to the sum of the channel lengths of the 10 sub-channels, and the channel width of the conventional transistor is equal to the sum of the channel widths of the 10 sub-channels.
[0052] like Figure 3As shown, it has been verified that when the channel length of the scan signal output transistor T2 is between 1.2 and 2.2 times that of a conventional transistor, the time t1 required for the scan signal output terminal G(N) of this stage to switch from a high potential to a low potential is less than the time t2 required when the channel length of the scan signal output transistor T2 is less than 1.2 times that of a conventional transistor, i.e., t1 < t2. Alternatively, the time t1 required for the scan signal output terminal G(N) of this stage to switch from a high potential to a low potential is less than the time t3 required when the channel length of the scan signal output transistor T2 is greater than 2.2 times that of a conventional transistor, i.e., t1 < t3. Meanwhile, when the channel length of the scan signal output transistor T2 is between 1.2 and 2.2 times that of a conventional transistor, the corresponding pixel charging rate is higher than when the channel length of the scan signal output transistor T2 is less than 1.2 times that of a conventional transistor. Furthermore, when the channel length of the scan signal output transistor T2 is between 1.2 and 2.2 times that of a conventional transistor, the capacitor-resistor load value on the second clock signal input terminal CK(N) electrically connected to the scan signal output transistor T2 is less than when the channel length of the scan signal output transistor T2 is greater than 2.2 times that of a conventional transistor.
[0053] like Figure 4a and Figure 4b As shown, the parasitic capacitance between the gate of the pull-up control transistor and the first electrode, and the imbalance of the parasitic capacitance between the gate of the pull-up control transistor and the second electrode, affect the pull-up control transistor's ability to raise the potential of the pull-up node. In this application, the pull-up control transistor's ability to raise the potential of the pull-up node is improved by adjusting the ratio of the channel length of the pull-up control transistor to that of the scan signal output transistor. Figure 4a As shown under normal temperature (T0) conditions and as Figure 4bUnder the high temperature and high humidity (RA) conditions shown, when the ratio of the channel length of the pull-up control transistor T1 to the channel length of the scan signal output transistor T2 is between 1:12 and 1:8, the potential V1 of the pull-up node Q(N) is higher than the potential V2 of the pull-up node Q(N) when the ratio of the channel length of the pull-up control transistor T1 to the channel length of the scan signal output transistor T2 is less than 1:12, i.e., V1 > V2. When the ratio of the channel length of the pull-up control transistor T1 to the channel length of the scan signal output transistor T2 is between 1:12 and 1:8, the potential V1 of the pull-up node Q(N) is higher than the potential V3 of the pull-up node Q(N) when the ratio of the channel length of the pull-up control transistor T1 to the channel length of the scan signal output transistor T2 is greater than 1:8, i.e., V1 > V3. Meanwhile, the time t4 required for the scan signal output from the local stage's output terminal G(N) to switch from a high potential to a low potential is less than the time t5 required for the scan signal to switch from a high potential to a low potential when the ratio of the channel length of the pull-up control transistor T1 to the channel length of the scan signal output transistor T2 is less than 1:12, i.e., t4 < t5. Alternatively, the time t4 required for the scan signal output from the local stage's output terminal G(N) to switch from a high potential to a low potential is less than the time t6 required for the scan signal to switch from a high potential to a low potential when the ratio of the channel length of the pull-up control transistor T1 to the channel length of the scan signal output transistor T2 is greater than 1:8, i.e., t4 < t6.
[0054] like Figure 5 As shown, the pull-down sustaining module 104 includes a first pull-down sustaining transistor T4, a second pull-down sustaining transistor T5, a third pull-down sustaining transistor T6, and a fourth pull-down sustaining transistor T7.
[0055] The gate and first electrode of the first pull-down sustaining transistor T4 are electrically connected to the first clock signal input terminal LC, and the second electrode of the first pull-down sustaining transistor T4 is electrically connected to the first electrode of the second pull-down sustaining transistor T5.
[0056] The gate of the second pull-down sustaining transistor T5 is electrically connected to the pull-up node Q(N), and the second electrode of the second pull-down sustaining transistor T5 is electrically connected to the second reference low-level signal input terminal VSSQ.
[0057] The first electrode of the third pull-down sustaining transistor T6 is electrically connected to the first clock signal input terminal LC. The gate of the third pull-down sustaining transistor T6 is electrically connected to the second electrode of the first pull-down sustaining transistor T4. The second electrode of the third pull-down sustaining transistor T6 is electrically connected to the first electrode of the fourth pull-down sustaining transistor T7.
[0058] The gate of the fourth pull-down sustaining transistor T7 is electrically connected to the pull-up node Q(N), and the second electrode of the fourth pull-down sustaining transistor T7 is electrically connected to the second reference low-level signal input terminal VSSQ.
[0059] Among them, the first pull-down sustaining transistor T4, the second pull-down sustaining transistor T5, the third pull-down sustaining transistor T6, and the fourth pull-down sustaining transistor T7 are used to keep the potential of the pull-up node Q(N) at a low potential.
[0060] The first clock signal input at the first clock signal input terminal LC is out of phase with the second clock signal input at the second clock signal input terminal CK(N).
[0061] The ratio of the channel length of the first pull-down sustaining transistor T4 to the channel length of the second pull-down sustaining transistor T5 is between 1:4 and 1:8. The channel width of the first pull-down sustaining transistor T4 is equal to the channel width of the second pull-down sustaining transistor T5. Specifically, the ratio of the channel length of the first pull-down sustaining transistor T4 to the channel length of the second pull-down sustaining transistor T5 includes 1:4, 1:5, 1:6, 1:7, or 1:8.
[0062] In the embodiments of this application, during the conduction of the first pull-down sustaining transistor T4 and the third pull-down sustaining transistor T6, the voltage between the gate and the second electrode of the third pull-down sustaining transistor T6 is between 24.52 volts and 26.84 volts. Specifically, when the ratio of the channel length of the first pull-down sustaining transistor T4 to the channel length of the second pull-down sustaining transistor T5 is 1:4, the voltage between the gate and the second electrode of the third pull-down sustaining transistor T6 is 26.84 volts during the conduction of the first pull-down sustaining transistor T4 and the third pull-down sustaining transistor T6. When the ratio of the channel length of the first pull-down sustaining transistor T4 to the channel length of the second pull-down sustaining transistor T5 is 1:6, the voltage between the gate and the second electrode of the third pull-down sustaining transistor T6 is 25.75 volts during the conduction of the first pull-down sustaining transistor T4 and the third pull-down sustaining transistor T6. When the ratio of the channel length of the first pull-down sustaining transistor T4 to the channel length of the second pull-down sustaining transistor T5 is 1:8, during the conduction period of the first pull-down sustaining transistor T4 and the third pull-down sustaining transistor T6, the voltage between the gate of the third pull-down sustaining transistor T6 and the second electrode of the third pull-down sustaining transistor T6 is 24.52 volts.
[0063] In the embodiments of this application, the ratio of the current value of the second electrode of the fourth pull-down sustaining transistor T7 to the current value of the second electrode of the third pull-down sustaining transistor T6 is equal to M times the ratio of the difference between the gate voltage value of the fourth pull-down sustaining transistor T7 and the voltage value of the second electrode of the fourth pull-down sustaining transistor T7 and the difference between the gate voltage value of the third pull-down sustaining transistor T6 and the voltage value of the second electrode of the third pull-down sustaining transistor T6, where M is a positive integer greater than 4.
[0064] That is, a slight change in the difference between the gate voltage of the fourth pull-down sustaining transistor T7 and the voltage of its second electrode, and a slight change in the difference between the gate voltage of the third pull-down sustaining transistor T6 and the voltage of its second electrode, will cause an exponential change in the current value of the second electrode of the fourth pull-down sustaining transistor T7 and the current value of the second electrode of the third pull-down sustaining transistor T6.
[0065] Among them, the ratio of the current value of the second electrode of the fourth pull-down sustaining transistor T7 to the current value of the second electrode of the third pull-down sustaining transistor T6 is much greater than the ratio of the difference between the gate voltage value of the fourth pull-down sustaining transistor T7 and the voltage value of the second electrode of the fourth pull-down sustaining transistor T7 and the ratio of the difference between the gate voltage value of the third pull-down sustaining transistor T6 and the voltage value of the second electrode of the third pull-down sustaining transistor T6.
[0066] In the gate driving circuit provided in the embodiments of this application, by setting the ratio of the channel length of the first pull-down sustaining transistor T4 to the channel length of the second pull-down sustaining transistor T5 to be between 1:4 and 1:8, the potential of the pull-up node, the time required for the scan signal to switch from a high potential to a low potential, the pixel charging rate, and the capacitor and resistance values in the gate driving unit are all in the optimal range, thereby improving the stability of the gate driving circuit.
[0067] like Figure 6As shown, the pull-down module 103 includes a first pull-down transistor T8 and a second pull-down transistor T9. The first electrode of the first pull-down transistor T8 is electrically connected to the first electrode of the second pull-down transistor T9 and the pull-up node Q(N). The second electrode of the first pull-down transistor T8 is electrically connected to the second electrode of the second pull-down transistor T9 and the first reference low-level signal input terminal VSST. The gate of the first pull-down transistor T8 is electrically connected to the first control signal input terminal, and the gate of the second pull-down transistor T9 is electrically connected to the second control signal terminal. The first pull-down transistor T8 and the second pull-down transistor T9 are used to pull down the potential of the pull-up node Q(N). The sum of the channel length of the first pull-down transistor T8 and the channel length of the second pull-down transistor T9 is greater than or equal to the channel length of the pull-up control transistor T1. The first control signal input terminal is the second electrode of the third pull-down sustaining transistor T6, that is, the potential of the second electrode of the third pull-down sustaining transistor T6 controls the conduction and shutdown of the first pull-down transistor T8. The second control signal input terminal is the X-stage cascade signal output terminal ST(N+X).
[0068] like Figure 7 As shown, the pull-down module 103 includes a third pull-down transistor T10. The first electrode of the third pull-down transistor T10 is electrically connected to the first electrode of the second pull-down transistor T9 and the pull-up node Q(N). The second electrode of the third pull-down transistor T10 is electrically connected to the second electrode of the second pull-down transistor T9 and the first reference low-level signal input terminal VSST. The sum of the channel length of the third pull-down transistor T10, the channel length of the first pull-down transistor T8, and the channel length of the second pull-down transistor T9 is greater than or equal to the channel length of the pull-up control transistor T1. The sum of the channel width of the third pull-down transistor T10 and the channel width of the second pull-down transistor T9 is equal to the channel width of the pull-up control transistor T1.
[0069] In embodiments of this application, the ratio of the sum of the channel lengths of the first pull-down transistor T8 and the second pull-down transistor T9 to the channel length of the pull-up control transistor T1 is between 1:1 and 1.4:1. Alternatively, the ratio of the sum of the channel lengths of the first pull-down transistor T8 and the third pull-down transistor T10 to the channel length of the pull-up control transistor T1 is between 1:1 and 1.4:1. The sum of the channel widths of the first pull-down transistor T8 and the second pull-down transistor T9 is equal to the channel width of the pull-up control transistor T1.
[0070] like Figure 8As shown, verification shows that when the ratio of the sum of the channel lengths of the first pull-down transistor T8 and the second pull-down transistor T9 to the channel length of the pull-up control transistor T1 is between 1:1 and 1.4:1, during the conduction period of the first pull-down transistor T8 and the second pull-down transistor T9, the potential of the pull-up node Q(N) is significantly lower than the potential of the pull-up node Q(N) when the ratio of the sum of the channel lengths of the first pull-down transistor T8 and the second pull-down transistor T9 to the channel length of the pull-up control transistor T1 is less than 1:1. This indicates a better pull-down effect on the potential of the pull-up node Q(N). Furthermore, the amplitude of the potential change of the pull-up node Q(N) is higher than the amplitude of the potential change of the pull-up node Q(N) when the ratio of the sum of the channel lengths of the first pull-down transistor T8 and the second pull-down transistor T9 to the channel length of the pull-up control transistor T1 is greater than 1:1.4.
[0071] In the gate driving circuit provided in the embodiments of this application, the ratio of the sum of the channel lengths of the first pull-down transistor T8 and the second pull-down transistor T9 to the channel length of the pull-up control transistor T1 is set to be between 1:1 and 1.4:1. Alternatively, the ratio of the sum of the channel lengths of the first pull-down transistor T8 and the third pull-down transistor T10 to the channel length of the pull-up control transistor T1 is set to be between 1:1 and 1.4:1. This ensures that the potential of the pull-up node, the time required for the scan signal to switch from a high potential to a low potential, the pixel charging rate, and the capacitor and resistance values in the gate driving unit are all within the optimal range, thereby improving the stability of the gate driving circuit.
[0072] like Figure 9 As shown, the pull-down sustaining module 104 also includes a fifth pull-down sustaining transistor T11 and a sixth pull-down sustaining transistor T12. The gate of the fifth pull-down sustaining transistor T11 is electrically connected to the pull-up node Q(N) of the upper X-stage gate driving unit. The first electrode of the fifth pull-down sustaining transistor T11 is electrically connected to the second electrode of the first pull-down sustaining transistor T4. The second electrode of the fifth pull-down sustaining transistor T11 is electrically connected to the second reference low-level signal input terminal VSSQ, where X is a positive integer greater than or equal to 1. The gate of the sixth pull-down sustaining transistor T12 is electrically connected to the pull-up node Q(N) of the upper X-stage gate driving unit. The first electrode of the sixth pull-down sustaining transistor T12 is electrically connected to the second electrode of the third pull-down sustaining transistor T6. The second electrode of the sixth pull-down sustaining transistor T12 is electrically connected to the second reference low-level signal input terminal VSSQ. The channel length of the first pull-down sustaining transistor T4 is equal to the channel length of the fifth pull-down sustaining transistor T11, and the channel length of the second pull-down sustaining transistor T5 is equal to the channel length of the sixth pull-down sustaining transistor T12. Preferably, the gate of the fifth pull-down sustaining transistor T11 is electrically connected to the pull-up node Q(N) of the two-stage gate drive unit above.
[0073] The first reference low-level signal input terminal VSST and the second reference low-level signal input terminal VSSQ can be the same signal terminal. Alternatively, the potential of the first reference low-level signal input at the first reference low-level signal input terminal VSST is not equal to the potential of the second reference low-level signal input at the second reference low-level signal input terminal VSSQ.
[0074] In the gate driving circuit provided in this application embodiment, by setting the ratio of the channel length of the first pull-down sustaining transistor T4 to the channel length of the second pull-down sustaining transistor T5 to be between 1:4 and 1:8, and setting the channel length of the first pull-down sustaining transistor T4 to be equal to the channel length of the fifth pull-down sustaining transistor T11, and the channel length of the second pull-down sustaining transistor T5 to be equal to the channel length of the sixth pull-down sustaining transistor T12, the potential of the pull-up node Q(N), the time required for the scan signal to switch from a high potential to a low potential, the pixel charging rate, and the capacitance and resistance values in the gate driving unit are all in the optimal range, thereby improving the stability of the gate driving circuit.
[0075] The above provides a detailed description of a gate driving circuit and a display panel provided in the embodiments of this application. The description of the above embodiments is only for the purpose of helping to understand the core idea of this application, and the above description should not be construed as a limitation on the scope of protection of this application.
Claims
1. A gate drive circuit characterized by comprising: The device includes a multi-stage cascaded gate driving unit, which includes a pull-up control module, an output module, a pull-down module, a pull-down sustaining module, a first reference low-level signal input terminal, a second reference low-level signal input terminal, and a pull-up node in the line between the pull-up control module and the output module. The pull-up control module includes a pull-up control transistor, which is electrically connected to the pull-up node and is used to pull up the potential of the pull-up node. The output module includes a scan signal output transistor, which is electrically connected to the pull-up node. The scan signal output transistor is used to output the scan signal of this stage under the control of the potential of the pull-up node. The pull-down module is electrically connected to the pull-up node, the first reference low-level signal input terminal, and the pull-down sustaining module. The pull-down module is used to pull the potential of the pull-up node down to the potential of the first reference low-level signal input to the first reference low-level signal input terminal. The pull-down sustaining module is electrically connected to the pull-up node and the second reference low-level signal input terminal. The pull-down sustaining module is used to keep the potential of the pull-up node at the potential of the second reference low-level signal input terminal. The ratio of the channel length of the pull-up control transistor to the channel length of the scan signal output transistor is between 1:8 and 1:
12.
2. The gate drive circuit according to claim 1, characterized by The channel length of the scan signal output transistor is between 12,000 micrometers and 33,000 micrometers.
3. The gate driving circuit according to claim 1, characterized in that, The pull-down module includes a first pull-down transistor and a second pull-down transistor; The first electrode of the first pull-down transistor is electrically connected to the first electrode of the second pull-down transistor and the pull-up node. The second electrode of the first pull-down transistor is electrically connected to the second electrode of the second pull-down transistor and the first reference low-level signal input terminal. The gate of the first pull-down transistor is electrically connected to the first control signal input terminal. The gate of the second pull-down transistor is electrically connected to the second control signal terminal. The first pull-down transistor and the second pull-down transistor are used to pull down the potential of the pull-up node. The sum of the channel length of the first pull-down transistor and the channel length of the second pull-down transistor is greater than or equal to the channel length of the pull-up control transistor.
4. The gate driving circuit according to claim 3, characterized in that, The pull-down module includes a third pull-down transistor, the first electrode of the third pull-down transistor is electrically connected to the first electrode of the second pull-down transistor and the pull-up node, and the second electrode of the third pull-down transistor is electrically connected to the second electrode of the second pull-down transistor and the first reference low-level signal input terminal. The sum of the channel length of the third pull-down transistor, the channel length of the first pull-down transistor, and the channel length of the second pull-down transistor is greater than or equal to the channel length of the pull-up control transistor.
5. The gate driving circuit according to claim 3 or 4, characterized in that, The ratio of the sum of the channel lengths of the first pull-down transistor and the second pull-down transistor to the channel length of the pull-up control transistor is between 1:1 and 1.4:
1.
6. The gate driving circuit according to claim 4, characterized in that, The ratio of the sum of the channel lengths of the first pull-down transistor and the third pull-down transistor to the channel length of the pull-up control transistor is between 1:1 and 1.4:
1.
7. The gate driving circuit according to claim 1, characterized in that, The pull-down sustaining module includes a first pull-down sustaining transistor, a second pull-down sustaining transistor, a third pull-down sustaining transistor, and a fourth pull-down sustaining transistor; The gate and first electrode of the first pull-down sustaining transistor are electrically connected to the first clock signal input terminal, and the second electrode of the first pull-down sustaining transistor is electrically connected to the first electrode of the second pull-down sustaining transistor. The gate of the second pull-down sustaining transistor is electrically connected to the pull-up node, and the second electrode of the second pull-down sustaining transistor is electrically connected to the second reference low-level signal input terminal. The first electrode of the third pull-down sustaining transistor is electrically connected to the first clock signal input terminal, the gate of the third pull-down sustaining transistor is electrically connected to the second electrode of the first pull-down sustaining transistor, and the second electrode of the third pull-down sustaining transistor is electrically connected to the first electrode of the fourth pull-down sustaining transistor. The gate of the fourth pull-down sustaining transistor is electrically connected to the pull-up node, and the second electrode of the fourth pull-down sustaining transistor is electrically connected to the second reference low-level signal input terminal. The first pull-down sustaining transistor, the second pull-down sustaining transistor, the third pull-down sustaining transistor, and the fourth pull-down sustaining transistor are used to keep the potential of the pull-up node at a low potential. The ratio of the channel length of the first pull-down sustaining transistor to the channel length of the second pull-down sustaining transistor is between 1:4 and 1:
8.
8. The gate driving circuit according to claim 7, characterized in that, The ratio of the current flowing through the second electrode of the fourth pull-down sustaining transistor to the current flowing through the second electrode of the third pull-down sustaining transistor is equal to M times the ratio of the difference between the voltage applied to the gate of the fourth pull-down sustaining transistor and the voltage applied to the second electrode of the fourth pull-down sustaining transistor and the difference between the voltage applied to the gate of the third pull-down sustaining transistor and the voltage applied to the second electrode of the third pull-down sustaining transistor, where M is a positive integer greater than 4.
9. The gate driving circuit according to claim 7, characterized in that, The pull-down sustaining module includes a fifth pull-down sustaining transistor and a sixth pull-down sustaining transistor; The gate of the fifth pull-down sustaining transistor is electrically connected to the pull-up node of the upper X-level gate driving unit, the first electrode of the fifth pull-down sustaining transistor is electrically connected to the second electrode of the first pull-down sustaining transistor, and the second electrode of the fifth pull-down sustaining transistor is electrically connected to the second reference low-level signal input terminal, where X is a positive integer greater than or equal to 1. The gate of the sixth pull-down sustaining transistor is electrically connected to the pull-up node of the upper X-level gate driving unit, the first electrode of the sixth pull-down sustaining transistor is electrically connected to the second electrode of the third pull-down sustaining transistor, and the second electrode of the sixth pull-down sustaining transistor is electrically connected to the second reference low-level signal input terminal. The channel length of the first pull-down sustaining transistor is equal to the channel length of the fifth pull-down sustaining transistor, and the channel length of the second pull-down sustaining transistor is equal to the channel length of the sixth pull-down sustaining transistor.
10. The gate driving circuit according to claim 7, characterized in that, During the conduction of the first pull-down sustaining transistor and the third pull-down sustaining transistor, the voltage between the gate of the third pull-down sustaining transistor and the second electrode of the third pull-down sustaining transistor is between 24.52 volts and 26.84 volts.
11. A display panel, characterized in that, It includes a plurality of pixel units and a gate driving circuit as described in any one of claims 1-10, wherein the gate driving circuit is electrically connected to the plurality of pixel units.