A fast differential protection method and device based on different sampling interruptions

Abstract

The application discloses a kind of fast differential protection method and device based on different sampling interruption, and wherein method includes: after starting element action, start timing, simultaneously execute high sampling rate and low sampling rate differential protection algorithm during preset time period, the differential protection of transformer is carried out;The high sampling rate differential protection algorithm is sampling value differential speed break protection algorithm, and the low sampling rate differential protection algorithm is conventional ratio differential protection algorithm and phasor differential speed break protection algorithm;When timing reaches preset time period, the low sampling rate conventional ratio differential protection algorithm and phasor differential speed break protection algorithm are executed, and the differential protection of transformer is carried out.The technical scheme of the application realizes that protection acts with faster speed when serious fault occurs in transformer.

Description

Technical Field

[0001] The present invention relates to the field of electrical technology, and more particularly to a fast differential protection method and device based on different sampling interruptions. Background Art

[0002] As a key component of the power system, the safe and reliable operation of power transformers is crucial. When an internal fault occurs in a transformer, the transformer's relay protection device detects and clears the fault, ensuring both transformer safety and the stable operation of the power system.

[0003] Current differential protection, the primary protection for transformers, is widely used due to its simple principle and excellent selectivity. Conventional differential protection is equipped with corresponding blocking elements to prevent false operation due to abnormal conditions other than internal faults, such as magnetizing inrush current. Therefore, the operating time of conventional differential protection is closely related to the performance of these blocking elements. Furthermore, to prevent the protection from operating too quickly due to these blocking elements in the event of a serious internal transformer fault, transformer protection devices are often equipped with differential quick-tripping protection elements that do not require any blocking. According to relevant technical standards, the operating time of differential protection should not exceed 30ms, and the differential tripping time should not exceed 20ms. However, in recent years, severe faults have caused the fault current to rise extremely rapidly, rapidly accumulating energy in a short period of time. This prevents heat from being released in a timely manner, ultimately leading to transformer explosions and combustion. Therefore, to overcome this problem, it is necessary to further improve the operating speed of protective devices for severe faults. This shortens the time it takes to clear a severe fault, thereby reducing the risk of equipment explosions and combustion.

[0004] Therefore, a technology is needed to realize transformer differential protection based on variable sampling rate and improve the action speed of transformer differential protection under severe fault conditions. Summary of the Invention

[0005] The technical solution of the present invention provides a fast differential protection method based on different sampling interruptions, the method comprising:

[0006] After the start element is activated, the timing starts, and during a preset time period, high sampling rate and low sampling rate differential protection algorithms are simultaneously executed to perform differential protection of the transformer; the high sampling rate differential protection algorithm is a sampled value differential quick-trip protection algorithm, and the low sampling rate differential protection algorithm is a conventional ratio differential protection algorithm and a phasor differential quick-trip protection algorithm;

[0007] When the timing reaches a preset time period, the conventional ratio differential protection algorithm and the phasor differential quick-break protection algorithm with a low sampling rate are executed to perform differential protection of the transformer.

[0008] Preferably, the sampled value differential quick-trip protection algorithm is implemented based on original high-frequency sampling data;

[0009] The conventional ratio differential protection algorithm and the phasor differential quick-break protection algorithm are implemented based on the sampled data in the original high-frequency sampling data.

[0010] Preferably, the simultaneous execution of the high sampling rate and low sampling rate differential protection algorithms within a preset time period includes:

[0011] Set multiple main interrupts based on the preset interrupt execution sequence, and set multiple sub-interrupts under each main interrupt;

[0012] Encoding the sub-interrupts, wherein each sub-interrupt corresponds to a calculation module in the sampling rate algorithm; the calculation module includes a normal sampling algorithm submodule and a high sampling rate differential fast interrupt submodule;

[0013] Executing the algorithms of the various calculation modules according to the codes of the multiple sub-interrupts in the main interrupt during the execution period of the main interrupt set in the interrupt execution sequence;

[0014] In each sub-interrupt, based on the sampling value differential quick-break protection algorithm of the high sampling rate differential quick-break submodule, it is judged whether the sampling point meets the judgment conditions of the sampling value differential quick-break protection algorithm;

[0015] In the last numbered sub-interrupt in each main interrupt, based on the conventional ratio differential protection algorithm and phasor differential quick-trip protection algorithm of the normal sampling algorithm submodule, it is judged whether the sampling point meets the criteria of the conventional ratio differential protection algorithm and the phasor differential quick-trip protection algorithm.

[0016] Preferably, the criterion of the sampling value differential quick-trip protection algorithm is:

[0017]

[0018] Where n is the ratio of the differential quick-break setting value to the rated current, which is 6-10; k is the ratio braking coefficient, which is 0.3-0.5; Δi cdφ is the differential current of the Φth phase variation sampling value; I e is the rated current of the transformer; Δi zdφ is the braking current of the sampling value of the variation of the Φth phase; j is the side of the transformer; m is the total number of sides of the transformer, usually 2 or 3; Δi jφ is the current variation sampling value of the Φth phase on the jth side;

[0019] In the above formula, Δi jφ Specifically for the kth sampling point:

[0020] Δi jφk =i jφk-i jφ(k-N) (2)

[0021] Among them, Δi jφk is the current variation sampling value of the kth sampling point of the Φth phase on the jth side; i jφk为 The current sampling value of the kth sampling point of the Φth phase on the jth side; i jφ(k-N) is the current sampling value of the kNth sampling point of the Φth phase on the jth side; N is the number of sampling points in one cycle.

[0022] Preferably, the time period is 8-12 ms.

[0023] According to another aspect of the present invention, the present invention provides a fast differential protection device based on different sampling interruptions, the device comprising:

[0024] The first protection unit is configured to start timing after the activation element is activated and simultaneously execute high-sampling rate and low-sampling rate differential protection algorithms within a preset time period to perform differential protection of the transformer; the high-sampling rate differential protection algorithm is a sampled value differential quick-trip protection algorithm, and the low-sampling rate differential protection algorithm is a conventional ratio differential protection algorithm and a phasor differential quick-trip protection algorithm;

[0025] The second protection unit is used to execute the conventional ratio differential protection algorithm and the phasor differential quick-break protection algorithm with a low sampling rate to perform differential protection of the transformer when the timing reaches a preset time period.

[0026] Preferably, the sampled value differential quick-trip protection algorithm is implemented based on original high-frequency sampling data;

[0027] The conventional ratio differential protection algorithm and the phasor differential quick-break protection algorithm are implemented based on the sampled data in the original high-frequency sampling data.

[0028] Preferably, the first protection unit is configured to simultaneously execute a high sampling rate and a low sampling rate differential protection algorithm within a preset time period, and is further configured to:

[0029] Set multiple main interrupts based on the preset interrupt execution sequence, and set multiple sub-interrupts under each main interrupt;

[0030] Encoding the sub-interrupts, wherein each sub-interrupt corresponds to a calculation module in the sampling rate algorithm; the calculation module includes a normal sampling algorithm submodule and a high sampling rate differential fast interrupt submodule;

[0031] Executing the algorithms of the various calculation modules according to the codes of the multiple sub-interrupts in the main interrupt during the execution period of the main interrupt set in the interrupt execution sequence;

[0032] In each sub-interrupt, based on the sampling value differential quick-break protection algorithm of the high sampling rate differential quick-break submodule, it is judged whether the sampling point meets the judgment conditions of the sampling value differential quick-break protection algorithm;

[0033] In the last numbered sub-interrupt in each main interrupt, based on the conventional ratio differential protection algorithm and phasor differential quick-trip protection algorithm of the normal sampling algorithm submodule, it is judged whether the sampling point meets the criteria of the conventional ratio differential protection algorithm and the phasor differential quick-trip protection algorithm.

[0034] Preferably, the criterion of the sampling value differential quick-trip protection algorithm is:

[0035]

[0036] Where n is the ratio of the differential quick-break setting value to the rated current, which is 6-10; k is the ratio braking coefficient, which is 0.3-0.5; Δi cdφ is the differential current of the Φth phase variation sampling value; I e is the rated current of the transformer; Δi zdφ is the braking current of the sampling value of the variation of the Φth phase; j is the side of the transformer; m is the total number of sides of the transformer, usually 2 or 3; Δ ijφ is the current variation sampling value of the Φth phase on the jth side;

[0037] In the above formula, Δ ijφ Specifically for the kth sampling point:

[0038] Δi jφk =i jφk -i jφ(k-N) (2)

[0039] Among them, Δi jφk is the current variation sampling value of the kth sampling point of the Φth phase on the jth side; i jφk is the current sampling value of the kth sampling point of the Φth phase on the jth side; i jφ(k-N) is the current sampling value of the kNth sampling point of the Φth phase on the jth side; N is the number of sampling points in one cycle.

[0040] Preferably, the time period is 8-12 ms.

[0041] The present invention provides a computer-readable storage medium storing a computer program for executing a transformer differential protection method based on a variable sampling rate.

[0042] The present invention provides an electronic device, which includes: a processor and a memory; wherein,

[0043] Memory for storing processor-executable instructions;

[0044] The processor is used for reading executable instructions from a memory and executing the instructions to implement a transformer differential protection method based on a variable sampling rate.

[0045] The technical solution of the present invention provides a fast differential protection method and device based on different sampling interruptions. The method includes: starting a timer after the activation of a starting element, and simultaneously executing high-sampling rate and low-sampling rate differential protection algorithms within a preset time period to perform differential protection for the transformer; the high-sampling rate differential protection algorithm is a sampled value differential fast-trip protection algorithm, and the low-sampling rate differential protection algorithm is a conventional ratio differential protection algorithm and a phasor differential fast-trip protection algorithm; when the timer reaches the preset time period, the low-sampling rate conventional ratio differential protection algorithm and the phasor differential fast-trip protection algorithm are executed to perform differential protection for the transformer. The technical solution of the present invention enables faster protection when a serious fault occurs within the transformer. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] A more complete understanding of exemplary embodiments of the present invention may be obtained by referring to the following drawings:

[0047] Figure 1 Flowchart of a fast differential protection method based on different sampling interruptions according to a preferred embodiment of the present invention;

[0048] Figure 2 2. A timing diagram of a variable sampling rate differential protection according to a preferred embodiment of the present invention;

[0049] Figure 3 1. A schematic diagram of a data processing flow for a variable sampling rate differential protection according to a preferred embodiment of the present invention;

[0050] Figure 4 A schematic diagram of a program interrupt execution sequence according to a preferred embodiment of the present invention;

[0051] Figure 5 Schematic diagram of phasor differential action characteristic curve according to a preferred embodiment of the present invention;

[0052] Figure 6 1. A schematic diagram of a flow chart of a variable sampling rate differential protection program according to a preferred embodiment of the present invention;

[0053] Figure 7 Schematic diagram of differential protection according to a preferred embodiment of the present invention;

[0054] Figure 8 A is a schematic diagram of a program flow according to a preferred embodiment of the present invention, and b is a schematic diagram of an interrupt service program;

[0055] Figure 9Schematic diagram of the original current waveform for the simulation verification of severe faults within the zone using RTDS according to the preferred embodiment of the present invention;

[0056] Figure 10 Schematic diagram of the following simulation calculations performed at a sampling rate of f1kHz according to a preferred embodiment of the present invention;

[0057] Figure 11 Schematic diagram of the output of the B-phase differential speed breaking criterion according to a preferred embodiment of the present invention;

[0058] Figure 12 Schematic diagram of output of phase C differential speed breaking criterion according to a preferred embodiment of the present invention;

[0059] Figure 13 Schematic diagram of the differential breaking action of phase A according to a preferred embodiment of the present invention;

[0060] Figure 14 Schematic diagram of the B-phase differential breaking action according to a preferred embodiment of the present invention;

[0061] Figure 15 Schematic diagram of the C-phase differential breaking action according to a preferred embodiment of the present invention;

[0062] Figure 16 Schematic diagram of output of phase A differential speed breaking criterion according to a preferred embodiment of the present invention;

[0063] Figure 17 Schematic diagram of the output of the B-phase differential speed breaking criterion according to a preferred embodiment of the present invention;

[0064] Figure 18 Schematic diagram of output of phase C differential speed breaking criterion according to a preferred embodiment of the present invention;

[0065] Figure 19 Schematic diagram of the differential breaking action of phase A according to a preferred embodiment of the present invention;

[0066] Figure 20 Schematic diagram of the B-phase differential breaking action according to a preferred embodiment of the present invention;

[0067] Figure 21 Schematic diagram of the C-phase differential breaking action according to a preferred embodiment of the present invention;

[0068] Figure 22 Schematic diagram of the output of the A-phase ratio differential criterion according to a preferred embodiment of the present invention;

[0069] Figure 23 Schematic diagram of the output of the B-phase ratio differential criterion according to a preferred embodiment of the present invention;

[0070] Figure 24 Schematic diagram of the output of the C-phase ratio differential criterion according to a preferred embodiment of the present invention;

[0071] Figure 25 Schematic diagram of analysis of the second harmonic proportion of conventional phasor ratio differential protection according to a preferred embodiment of the present invention;

[0072] Figure 26 Schematic diagram of the operation of phase A of the ratio differential protection according to a preferred embodiment of the present invention;

[0073] Figure 27 Schematic diagram of the operation of phase B of the ratio differential protection according to a preferred embodiment of the present invention;

[0074] Figure 28 A schematic diagram of analyzing the operation of conventional phasor ratio differential protection according to a preferred embodiment of the present invention; and

[0075] Figure 29 2 is a structural diagram of a fast differential protection device based on different sampling interruptions according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0076] Exemplary embodiments of the present invention will now be described with reference to the accompanying drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided to provide a thorough and complete disclosure of the present invention and to fully convey the scope of the present invention to those skilled in the art. The terminology used in the exemplary embodiments shown in the accompanying drawings is not intended to limit the present invention. In the accompanying drawings, identical elements are denoted by the same reference numerals.

[0077] Unless otherwise specified, the terms used herein (including technical terms) have the meanings commonly understood by those skilled in the art. In addition, it is understood that terms defined in commonly used dictionaries should be understood to have the same meanings as those in the context of the relevant fields, and should not be understood as idealized or overly formal meanings.

[0078] Figure 1 The figure is a flow chart of a fast differential protection method based on different sampling interruptions according to a preferred embodiment of the present invention.

[0079] Aiming at the problem that the transformer action speed needs to be further optimized and improved under severe fault conditions, the present invention proposes a transformer differential protection method based on variable sampling rate.

[0080] In order to improve the differential tripping speed of the protection under severe fault conditions and take into account the computational load of the entire protection system, different algorithms in the same protection device use different sampling rates in different time periods. Figure 2As shown in the figure, within the half cycle after the start element is activated, the original high-sampling rate data is used to implement the sampling point-based differential trip protection algorithm. For conventional phasor differential trip and phasor differential, the sampled low-sampling rate data is used to implement Fourier phasor calculation. In this way, conventional phasor differential and differential trip protection can serve as a backup for high-sampling rate differential trip.

[0081] The sampling rate of raw data from protection devices is relatively high (e.g., f1kHz), often exceeding the sampling rate of data actually used in phasor calculations (e.g., f2kHz). This means that the sampled data from existing protection devices is derived from the raw data after subtracting it. To fully utilize the raw, high-frequency sampled data, a sample value differential algorithm is implemented on this data, thereby improving protection operation speed.

[0082] like Figure 1 As shown, the present invention provides a fast differential protection method based on different sampling interruptions, the method comprising:

[0083] Step 101: Start timing after the starting element is activated, and execute high sampling rate and low sampling rate differential protection algorithms simultaneously within a preset time period to perform differential protection of the transformer; the high sampling rate differential protection algorithm is a sampling value differential quick-trip protection algorithm, and the low sampling rate differential protection algorithm is a Fu conventional ratio differential protection algorithm and a phasor differential quick-trip protection algorithm; preferably, the time period is 10ms.

[0084] Step 102: When the timing reaches a preset time period, a conventional ratio differential protection algorithm and a phasor differential quick-break protection algorithm with a low sampling rate are executed to perform differential protection of the transformer.

[0085] Preferably, the sampling value differential quick-trip protection algorithm is implemented based on the original high-frequency sampling data;

[0086] Conventional ratio differential protection algorithm and phasor differential quick-trip protection algorithm are implemented based on the sampling data in the original high-frequency sampling data.

[0087] Preferably, the high sampling rate and low sampling rate differential protection algorithms are executed simultaneously within a preset time period, including:

[0088] Set multiple main interrupts based on the preset interrupt execution sequence, and set multiple sub-interrupts under each main interrupt;

[0089] Encoding the sub-interrupts, wherein each sub-interrupt corresponds to a calculation module in the sampling rate algorithm; the calculation module includes a normal sampling algorithm submodule and a high sampling rate differential fast interrupt submodule;

[0090] During the execution period of the main interrupt set in the interrupt execution sequence, the algorithms of each calculation module are executed according to the codes of multiple sub-interrupts in the main interrupt, wherein the last coded sub-interrupt in each main interrupt performs a normal sampling rate exit logic judgment;

[0091] In each sub-interrupt, based on the sampling value differential quick-break protection algorithm of the high sampling rate differential quick-break submodule, it is judged whether the sampling point meets the judgment conditions of the sampling value differential quick-break protection algorithm;

[0092] In the last numbered sub-interrupt in each main interrupt, based on the conventional ratio differential protection algorithm and phasor differential quick-trip protection algorithm of the normal sampling algorithm submodule, it is judged whether the sampling point meets the criteria of the conventional ratio differential protection algorithm and the phasor differential quick-trip protection algorithm.

[0093] Figure 5 Interrupt 1, Interrupt 2, etc. indicate interrupts corresponding to low sampling rates, which can be called main interrupts. Interrupt 1-1, Interrupt 1-2, etc. indicate interrupts corresponding to high sampling rates, which can be called sub-interrupts.

[0094] In each sub-interrupt, a high sampling rate differential interrupt algorithm is performed, and whether the criterion conditions are met is determined point by point.

[0095] In each main interrupt, a conventional low sampling rate differential interrupt and differential algorithm are performed to determine whether the action conditions are met.

[0096] In order to balance the computing efficiency and load rate of the device hardware, the amount of calculation in the sub-interrupt is much smaller than that in the main interrupt.

[0097] The calculation and action logic judgment of high sampling rate differential interrupt are performed in each sub-interrupt, and each S sub-interrupt corresponds to a main interrupt. Each sub-interrupt is numbered cyclically, and each numbered sub-interrupt corresponds to a calculation module of the normal sampling rate algorithm. Each S is a group, that is, the sub-module algorithms of the normal sampling rate are completed within the time of a main interrupt, and the normal sampling rate exit logic judgment is performed in the Sth sub-interrupt of each main interrupt. In the above manner, the protection algorithms of different sampling rates can be realized to correspond to different interruption times. Among them, each normal sampling rate algorithm sub-module in the S sub-interrupts uses the sampling data of the sub-interrupt numbered 1 for calculation. The high sampling rate differential action algorithm in the S sub-interrupts is calculated using the sampling data of each sub-interrupt.

[0098] Preferably, the criterion of the sampling value differential quick-trip protection algorithm is:

[0099]

[0100] Where n is the ratio of the differential quick-break setting value to the rated current, which is 6-10; k is the ratio braking coefficient, which is 0.3-0.5; Δicdφ is the differential current of the Φth phase variation sampling value; I e is the rated current of the transformer; Δi zdφ is the braking current of the sampling value of the variation of the Φth phase; j is the side of the transformer; m is the total number of sides of the transformer, usually 2 or 3; Δi jφ is the current variation sampling value of the Φth phase on the jth side;

[0101] In the above formula, Δi jφ Specifically for the kth sampling point:

[0102] Δi jφk =i jφk -i jφ(k-N) (2)

[0103] Among them, Δi jφk is the current variation sampling value of the kth sampling point of the Φth phase on the jth side; i jφk is the current sampling value of the kth sampling point of the Φth phase on the jth side; i jφ(k-N) is the current sampling value of the kNth sampling point of the Φth phase on the jth side; N is the number of sampling points in one cycle.

[0104] The present invention is based on the sampling value differential protection method of high sampling rate:

[0105]

[0106] Among them, n is usually 6 to 10 times, and k can be 0.3 to 0.5.

[0107] Δi cdφ The differential current is obtained by subtracting the current sampling point from the sampling point corresponding to the cycle before startup.

[0108] Δi jφk =i jφk -i jφ(k-N) (2)

[0109] In the above formula, N represents the number of sampling points in one cycle. When the sampling rate is f1kHz, N=0.02*f1.

[0110] When there are 10 consecutive points in any phase that meet the above condition (1), the differential interruption of the change sampling value will be activated.

[0111] Preferably, the conventional phasor differential and differential quick-trip criteria of the conventional ratio differential protection algorithm and the phasor differential quick-trip protection algorithm are:

[0112]

[0113] Among them, I e is the rated current; Ij is the current on each side of the transformer; I qd is the starting value; I r is the braking current; I d is the differential current; K is the ratio braking coefficient; j is the jth side of the transformer; m is the total number of sides of the transformer;

[0114] The differential quick-break action equation is:

[0115] I d >kI e

[0116] Where k is the ratio of the differential trip setting value to the rated current Ie.

[0117] The conventional phasor differential and differential switching of the present invention are as follows:

[0118]

[0119] Among them, I e is the rated current, I j is the current on each side of the transformer, I qd is the starting value, I r is the braking current, I d is the differential current, K is the ratio braking coefficient (0.2~0.7, 0.5 is recommended).

[0120] The differential breaking action equation in the present invention is:

[0121] I d >kI e

[0122] Among them, k is usually set to 6 to 8.

[0123] Phase differential and differential breaking and characteristics see Figure 5 .

[0124] The overall process of the variable sampling rate solution proposed in this invention is simple. After the start element is activated, the high sampling rate and low sampling rate differential protection algorithms are implemented simultaneously within 10ms. After 10ms, the high sampling rate algorithm exits and only the conventional low sampling rate algorithm remains. This can take into account the rapidity of protection and the overall calculation load level of the device. Figure 6 shown.

[0125] The present invention takes the occurrence of a phase A grounding fault on the YΔ commutation transformer grid side lead as an example to illustrate the implementation manner of the present invention.

[0126] (1) Using RTDS to carry out simulation verification of severe faults in the area, the original current waveform is as follows Figure 9 shown.

[0127] like Figure 9As shown, time 0 is the start time of the fault. After the fault, the maximum instantaneous value of the differential current of the faulty phase can reach 46.11kA, which is a serious internal fault.

[0128] (2) The calculation results using the high sampling rate phase differential algorithm are as follows:

[0129] The following simulation calculations are performed with a sampling rate of f1kHz.

[0130] In the embodiment of the present invention, the protection is activated at time 0. After the fault, the differential current of phase A is always greater than the braking current and quickly exceeds the differential tripping threshold value. The non-fault phases B and C do not reach the differential tripping threshold value and are less than the braking current. Figure 10 , as shown in 11 and 12.

[0131] High sampling rate differential breaking action requires 10 sampling points to be satisfied continuously, such as Figure 13 As shown in Figures 14 and 15, time 0 is the start time of the protection. 1.04ms after the fault, the high sampling rate differential circuit breaker meets the action requirement, and the action signal changes from low level to high level. Adding the start time of 0.31ms, the high sampling rate differential circuit breaker operates 1.35ms after the fault. The non-fault phases B and C do not operate.

[0132] (3) The results of phase differential calculation under conventional low sampling rate are as follows Figure 16 , 17, 18. Figure 16 , 17, 18, where time 0 is the start time of protection. 11.67ms after the fault, the differential current of phase A is greater than the differential breaking threshold, and the non-fault phases B and C do not reach the differential breaking threshold.

[0133] The low sampling rate differential interruption action requires 3 sampling points to be satisfied continuously, such as Figure 19 As shown in Figures 20 and 21, time 0 is the start time of the protection. 14.2ms after the fault, the low-sampling-rate differential breaker meets the action requirement, and the action signal changes from low level to high level. Adding the start time of 0.31ms, the high-sampling-rate differential breaker operates 14.5ms after the fault. The non-fault phases B and C do not operate.

[0134] (4) The results of the phasor ratio differential calculation under conventional low sampling rate are as follows Figure 22 , 23, 24, where time 0 is the start time of protection. After the fault, the differential current of phase A is greater than the braking current, and the non-fault phases B and C are both less than the braking current.

[0135] like Figure 25As shown in the figure, time 0 is the start time of the protection. The second harmonic proportion of the differential current of phase A is greater than the second harmonic braking threshold within 15.8ms. After 15.8ms, it decays to below the second harmonic braking threshold. The second harmonic proportions of the differential current of phases B and C, which are not fault phases, do not exceed the second harmonic braking threshold.

[0136] The low sampling rate conventional phasor ratio differential protection action requires three sampling points to be satisfied continuously, such as Figure 26 As shown in Figures 27 and 28, time 0 is the start time of the protection. After 15.8ms, the low-sampling-rate conventional phasor ratio differential protection meets the action requirement, and the action signal changes from low level to high level. Adding the start time of 0.31ms, the low-sampling-rate conventional phasor ratio differential protection action output is 16.1ms after the fault. The non-fault phases B and C do not act.

[0137] The present invention proposes a transformer differential protection method based on variable sampling rate, which can effectively solve the problem of improving the protection action speed under severe fault conditions.

[0138] Figure 29 2 is a structural diagram of a fast differential protection device based on different sampling interruptions according to a preferred embodiment of the present invention.

[0139] like Figure 29 As shown, the present invention provides a fast differential protection device based on different sampling interruptions, the device comprising:

[0140] The first protection unit 201 is configured to start timing after the activation element is activated and simultaneously execute high-sampling rate and low-sampling rate differential protection algorithms within a preset time period to perform differential protection of the transformer; the high-sampling rate differential protection algorithm is a sampled value differential quick-trip protection algorithm, and the low-sampling rate differential protection algorithm is a conventional ratio differential protection algorithm and a phasor differential quick-trip protection algorithm;

[0141] The second protection unit 202 is configured to execute a conventional ratio differential protection algorithm and a phasor differential quick-break protection algorithm with a low sampling rate to perform differential protection of the transformer when the timing reaches a preset time period.

[0142] Preferably, the sampling value differential quick-trip protection algorithm is implemented based on the original high-frequency sampling data;

[0143] Conventional ratio differential protection algorithm and phasor differential quick-trip protection algorithm are implemented based on the sampling data in the original high-frequency sampling data.

[0144] Preferably, the first protection unit 201 is configured to simultaneously execute the high sampling rate and low sampling rate differential protection algorithms within a preset time period, and further configured to:

[0145] Set multiple main interrupts based on the preset interrupt execution sequence, and set multiple sub-interrupts under each main interrupt;

[0146] Encoding the sub-interrupts, wherein each sub-interrupt corresponds to a calculation module in the sampling rate algorithm; the calculation module includes a normal sampling algorithm submodule and a high sampling rate differential fast interrupt submodule;

[0147] During the execution period of the main interrupt set in the interrupt execution sequence, the algorithms of each calculation module are executed according to the codes of multiple sub-interrupts in the main interrupt, wherein the last coded sub-interrupt in each main interrupt performs a normal sampling rate exit logic judgment;

[0148] In each sub-interrupt, based on the sampling value differential quick-break protection algorithm of the high sampling rate differential quick-break submodule, it is judged whether the sampling point meets the judgment conditions of the sampling value differential quick-break protection algorithm;

[0149] In the last numbered sub-interrupt in each main interrupt, based on the conventional ratio differential protection algorithm and phasor differential quick-trip protection algorithm of the normal sampling algorithm submodule, it is judged whether the sampling point meets the criteria of the conventional ratio differential protection algorithm and the phasor differential quick-trip protection algorithm.

[0150] Preferably, the criterion of the sampling value differential quick-trip protection algorithm is:

[0151]

[0152] Where n is the ratio of the differential quick-break setting value to the rated current, which is 6-10; k is the ratio braking coefficient, which is 0.3-0.5; Δi cdφ is the differential current of the Φth phase variation sampling value; I e is the rated current of the transformer; Δi zdφ is the braking current of the sampling value of the variation of the Φth phase; j is the side of the transformer; m is the total number of sides of the transformer, usually 2 or 3; Δi jφ is the current variation sampling value of the Φth phase on the jth side;

[0153] In the above formula, Δi jφ Specifically for the kth sampling point:

[0154] Δi jφk =i jφk -i jφ(k-N) (2)

[0155] Among them, Δi jφk is the current variation sampling value of the kth sampling point of the Φth phase on the jth side; i jφk is the current sampling value of the kth sampling point of the Φth phase on the jth side; i jφ(k-N)is the current sampling value of the kNth sampling point of the Φth phase on the jth side; N is the number of sampling points in one cycle.

[0156] Preferably, the conventional phasor differential and differential quick-trip criteria of the conventional ratio differential protection algorithm and the phasor differential quick-trip protection algorithm are:

[0157]

[0158] Among them, I e is the rated current; I j is the current on each side of the transformer; I qd is the starting value; I r is the braking current; I d is the differential current; K is the ratio braking coefficient; j is the jth side of the transformer; m is the total number of sides of the transformer;

[0159] The differential quick-break action equation is:

[0160] I d >kI e

[0161] Where k is the ratio of the differential trip setting value to the rated current Ie.

[0162] Preferably, the time period is 10 ms.

[0163] The present invention provides a fast differential protection device based on different sampling interruptions, which corresponds to the present invention provides a fast differential protection method based on different sampling interruptions, and will not be described in detail here.

[0164] The present invention provides a computer-readable storage medium storing a computer program for executing a transformer differential protection method based on a variable sampling rate.

[0165] The present invention provides an electronic device, which includes: a processor and a memory; wherein,

[0166] Memory for storing processor-executable instructions;

[0167] The processor is used for reading executable instructions from a memory and executing the instructions to implement a transformer differential protection method based on a variable sampling rate.

[0168] It will be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of the present invention may be implemented in various computer languages, for example, the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0169] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0170] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0171] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0172] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0173] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

[0174] The invention has been described above with reference to a few embodiments. However, it is readily apparent to a person skilled in the art that other embodiments than the ones disclosed above are equally within the scope of the invention, as defined by the appended patent claims.

[0175] Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise herein. All references to "a / the [means, component, etc.]" are to be interpreted openly as referring to at least one instance of the means, component, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not necessarily need to be performed in the exact order disclosed, unless explicitly stated otherwise.

Claims

1. A fast differential protection method based on different sampling interruptions, the method comprising: After the start element is activated, the high sampling rate and low sampling rate differential protection algorithms are simultaneously executed within a preset time period to perform differential protection of the transformer; the high sampling rate differential protection algorithm is a sampled value differential quick-trip protection algorithm, and the low sampling rate differential protection algorithm is a conventional ratio differential protection algorithm and a phasor differential quick-trip protection algorithm; the criterion for the sampled value differential quick-trip protection algorithm is: Where n is the ratio of the differential quick-break setting value to the rated current, which is 6-10; k is the ratio braking coefficient, which is 0.3-0.5; Δi cdφ is the differential current of the Φth phase variation sampling value; I e is the rated current of the transformer; Δi zdφ is the braking current of the sampling value of the variation of the Φth phase; j is the side of the transformer; m is the total number of sides of the transformer, usually 2 or 3; Δi jφ is the current variation sampling value of the Φth phase on the jth side; In the above formula, Δi jφ Specifically for the kth sampling point: Δi jφk =i jφk -i jφ(k-N) (2) Among them, Δi jφk is the current variation sampling value of the kth sampling point of the Φth phase on the jth side; i jφk is the current sampling value of the kth sampling point of the Φth phase on the jth side; i jφ(k-N) is the current sampling value of the kNth sampling point of the Φth phase on the jth side; N is the number of sampling points in one cycle; When the timing reaches a preset time period, the conventional ratio differential protection algorithm and the phasor differential quick-break protection algorithm with a low sampling rate are executed to perform differential protection of the transformer.

2. The method according to claim 1, wherein the sampling value differential quick-trip protection algorithm is implemented based on the original high-frequency sampling data; The conventional ratio differential protection algorithm and the phasor differential quick-break protection algorithm are implemented based on the sampled data in the original high-frequency sampling data.

3. The method according to claim 1, wherein the simultaneously executing the high sampling rate and low sampling rate differential protection algorithms within a preset time period comprises: Set multiple main interrupts based on the preset interrupt execution sequence, and set multiple sub-interrupts under each main interrupt; Encoding the sub-interrupts, wherein each sub-interrupt corresponds to a calculation module in the sampling rate algorithm; the calculation module includes a normal sampling algorithm submodule and a high sampling rate differential fast interrupt submodule; Executing the algorithms of the various calculation modules according to the codes of the multiple sub-interrupts in the main interrupt during the execution period of the main interrupt set in the interrupt execution sequence; In each sub-interrupt, based on the sampling value differential quick-break protection algorithm of the high sampling rate differential quick-break submodule, it is judged whether the sampling point meets the judgment conditions of the sampling value differential quick-break protection algorithm; In the last numbered sub-interrupt in each main interrupt, based on the conventional ratio differential protection algorithm and phasor differential quick-trip protection algorithm of the normal sampling algorithm submodule, it is judged whether the sampling point meets the criteria of the conventional ratio differential protection algorithm and the phasor differential quick-trip protection algorithm. The method according to claim 1 , wherein the time period is 8-12 ms.

5. A fast differential protection device based on different sampling interruptions, the device comprising: The first protection unit is configured to start timing after the activation element is activated, and to simultaneously execute high-sampling rate and low-sampling rate differential protection algorithms within a preset time period to perform differential protection of the transformer; the high-sampling rate differential protection algorithm is a sampled value differential quick-trip protection algorithm, and the low-sampling rate differential protection algorithm is a conventional ratio differential protection algorithm and a phasor differential quick-trip protection algorithm; the criterion for the sampled value differential quick-trip protection algorithm is: Where n is the ratio of the differential quick-break setting value to the rated current, which is 6-10; k is the ratio braking coefficient, which is 0.3-0.5; Δi cdφ is the differential current of the Φth phase variation sampling value; I e is the rated current of the transformer; Δi zdφ is the braking current of the sampling value of the variation of the Φth phase; j is the side of the transformer; m is the total number of sides of the transformer, usually 2 or 3; Δi jφ is the current variation sampling value of the Φth phase on the jth side; In the above formula, Δi jφ Specifically for the kth sampling point: Δi jφk =i jφk -i jφ(k-N) (2) Among them, Δi jφk is the current variation sampling value of the kth sampling point of the Φth phase on the jth side; i jφk is the current sampling value of the kth sampling point of the Φth phase on the jth side; i jφ(k-N) is the current sampling value of the kNth sampling point of the Φth phase on the jth side; N is the number of sampling points in one cycle; The second protection unit is used to execute the conventional ratio differential protection algorithm and the phasor differential quick-break protection algorithm with a low sampling rate to perform differential protection of the transformer when the timing reaches a preset time period.

6. The device according to claim 5, wherein the sampling value differential quick-trip protection algorithm is implemented based on the original high-frequency sampling data; The conventional ratio differential protection algorithm and the phasor differential quick-break protection algorithm are implemented based on the sampled data in the original high-frequency sampling data.

7. The apparatus according to claim 5, wherein the first protection unit is configured to simultaneously execute a high sampling rate and a low sampling rate differential protection algorithm within a preset time period, and further configured to: Set multiple main interrupts based on the preset interrupt execution sequence, and set multiple sub-interrupts under each main interrupt; Encoding the sub-interrupts, wherein each sub-interrupt corresponds to a calculation module in the sampling rate algorithm; the calculation module includes a normal sampling algorithm submodule and a high sampling rate differential fast interrupt submodule; Executing the algorithms of the various calculation modules according to the codes of the multiple sub-interrupts in the main interrupt during the execution period of the main interrupt set in the interrupt execution sequence; In each sub-interrupt, based on the sampling value differential quick-break protection algorithm of the high sampling rate differential quick-break submodule, it is judged whether the sampling point meets the judgment conditions of the sampling value differential quick-break protection algorithm; In the last numbered sub-interrupt in each main interrupt, based on the conventional ratio differential protection algorithm and phasor differential quick-trip protection algorithm of the normal sampling algorithm submodule, it is judged whether the sampling point meets the criteria of the conventional ratio differential protection algorithm and the phasor differential quick-trip protection algorithm. The apparatus according to claim 5 , wherein the time period is 8-12 ms.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and the computer program is used to execute the method according to any one of claims 1 to 4.

10. An electronic device, characterized in that: The electronic device includes: a processor and a memory; wherein, The memory is a memory for storing instructions executable by the processor; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the method according to any one of claims 1 to 4.

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