An op-amp input stage esd protection device and method with ultra-low leakage current

Abstract

The embodiment of the present application provides an ultra-low leakage current operational amplifier input stage ESD protection device and method, which comprises: a first-stage ESD protection circuit (101), a second-stage ESD protection circuit (103) and a voltage bias circuit (102); the first-stage ESD protection circuit (101) is connected in series with the second-stage ESD protection circuit (103); and the voltage bias circuit (102) sends control signals to the source and the gate of the first-stage ESD protection circuit (101) and the second-stage ESD protection circuit (103) respectively. The present application samples input voltage through the first-stage ESD protection circuit (101) and the second-stage ESD protection circuit (103), and controls the source and the gate of the ESD protection tube close to the input pin through the voltage bias circuit (102), so as to bias the drain and the source voltage of the ESD protection tube to be equal, and keep the gate voltage to be smaller than the input stage voltage, thereby completely turning off the ESD protection tube and realizing the low leakage function.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of protection devices, and more specifically, the embodiments of the present invention relate to an operational amplifier input stage ESD protection device and method with ultra-low leakage current. Background Technology

[0002] This section is intended to provide background or context for embodiments of the invention as set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section.

[0003] In high-precision acquisition systems, input sampling amplification is the most critical component, and operational amplifiers are commonly used analog chips essential for input stage sampling.

[0004] Figure 1 This illustrates a traditional input pin ESD protection scheme. The scheme includes primary ESD protection composed of R0 and M1, and secondary ESD protection composed of R8, R1, and M2. Since it is secondary protection, R8 provides protection. The size of M2 is typically 1 / 10 of M1. The pin leakage current is caused by the leakage currents of M1 and M2 respectively. In CMOS technology, this leakage current is significantly affected by temperature.

[0005] Some input signals have high internal resistance, requiring the preamplifier to have ultra-high input impedance (possibly on the order of 10G). Traditional operational amplifiers have ESD protection devices on their input pins, and large ESD protection devices all have leakage current. At room temperature, this leakage current is only on the order of pA, but when the temperature rises to 85°C, the leakage current begins to increase exponentially, and at 125°C it may reach the level of nA or even tens of nA. Figure 2 The diagram illustrates the leakage current variation with temperature in a single ESD solution. At 125°C, the leakage current reaches approximately 15nA, which is insufficient for ultra-high precision acquisition systems. However, removing the ESD protection device makes the chip susceptible to ESD damage and failure; therefore, leakage protection is necessary for traditional ESD devices. Summary of the Invention

[0006] In this context, embodiments of the present invention aim to provide an operational amplifier input stage ESD protection device and method with ultra-low leakage current.

[0007] In a first aspect of the present invention, an operational amplifier input stage ESD protection device with ultra-low leakage current is provided, comprising:

[0008] The circuit consists of a first-level ESD protection circuit (101), a second-level ESD protection circuit (103), and a voltage biasing circuit (102);

[0009] The first-stage EAD protection circuit (101) is connected in series with the second-stage ESD protection circuit (103);

[0010] The voltage bias circuit (102) sends control signals to the source and gate of the first-level EAD protection circuit (101) and the second-level ESD protection circuit (103), respectively.

[0011] In one embodiment of this implementation, the first-level EAD protection circuit (101) includes: transistor M1, transistor M2, a first control circuit, and a second control circuit;

[0012] The source of transistor M2 and the drain of transistor M1 are connected to form a series branch;

[0013] Both the first control circuit and the second control circuit are connected in parallel with the series branch;

[0014] The voltage bias circuit (102) is connected to the gate and source of the transistor M2, respectively.

[0015] In one embodiment of this implementation, the first control circuit includes: capacitor C0, resistor R2, and resistor R0;

[0016] One end of capacitor C0 is connected in series with one end of resistor R2 and one end of resistor R0 in sequence; the other end of capacitor C0 is connected to the drain of transistor M2; the other end of R0 is grounded.

[0017] The gate of the transistor M1 is connected between the resistor R2 and the capacitor C0.

[0018] In one embodiment of this implementation, the second control circuit includes: resistor R1, resistor R3, capacitor C1, and transistor M3;

[0019] One end of the capacitor C1 is connected in series with the resistor R3, the resistor R1, and the drain of the transistor M3; the source of the transistor M3 is grounded.

[0020] The other end of the capacitor C1 is connected to the drain of the transistor M2;

[0021] The gate of transistor M3 is connected to the gate of transistor M1;

[0022] The gate of the transistor M2 is connected between the resistor R3 and the resistor R1.

[0023] In one embodiment of this implementation, the second-level ESD protection circuit (103) includes: resistor R8, transistor M4, and transistor M5;

[0024] The resistor R8 is connected to the drain of transistor M4 and the internal circuit, respectively. The source of transistor M4 is connected to the drain of transistor M5. The source and gate of transistor M5 are both grounded.

[0025] The voltage bias circuit (102) is connected to the gate and source of the transistor M4, respectively.

[0026] In one embodiment of this implementation, the voltage bias circuit (102) includes: operational amplifier A0, resistor R4, resistor R5, resistor R6, and resistor R7;

[0027] The positive input terminal of the operational amplifier A0 is connected to the second-stage ESD protection circuit (103), the negative input terminal of the operational amplifier A0 is connected to the output terminal, and the output terminal of the operational amplifier A0 is connected to one end of the resistors R4, R5, R6 and R7.

[0028] The other end of resistor R4 and the other end of resistor R5 are both connected to the first-stage ESD protection circuit.

[0029] The other end of resistor R6 and the other end of resistor R7 are both connected to the second-stage ESD protection circuit.

[0030] In one embodiment of this implementation, the operational amplifier A0 includes: transistor MA3, transistor MA4, transistor MA5, transistor MA6, resistor RA0, resistor RA1, resistor RA2, resistor RA3, and resistor RA4;

[0031] The gates of transistors MA5 and MA6 are connected; the gate and drain of transistor MA5 are connected; the drain of transistor MA5 is connected to the drain of transistor MA3; the drain of transistor MA6 is connected to the drain of transistor MA4; the gate and drain of transistor MA4 are connected; and the source of transistor MA3, the source of transistor MA4, and the drain of transistor MA1 are connected.

[0032] The sources of transistors MA0, MA1, and MA2 are grounded, the gates of transistors MA0, MA1, and MA2 are connected, the drain and gate of transistor MA0 are connected, and the drain of transistor MA2 is connected to the source of transistor MA5, one end of resistor RA3, and one end of resistor RA4, respectively.

[0033] The gate of transistor MA5 is connected to the gate of transistor MA4, resistor RA1 and resistor RA2 respectively. The drain of transistor MA5 is connected to one end of resistor RA0, and the other end of resistor RA0 is connected to the source of transistors MA5 and MA6.

[0034] The other end of resistor RA1 is connected to one end of resistor R4, and the other end of resistor RA2 is connected to one end of resistor R6.

[0035] The other end of resistor RA3 is connected to one end of resistor R5, and the other end of resistor RA4 is connected to one end of resistor R7. In a second aspect of the present invention, an ESD protection method for an operational amplifier input stage with ultra-low leakage current is provided, comprising:

[0036] The first-stage ESD protection circuit (101) monitors ESD events, provides delay, and distinguishes them from normal power-on events;

[0037] The control signal sent by the voltage bias circuit (102) to the first-level ESD protection circuit (101) and the second-level ESD protection circuit (103) controls the gate of the transistor in the first-level ESD protection circuit (101) and the second-level ESD protection circuit (103).

[0038] The first-stage ESD protection circuit (101), the second-stage ESD protection circuit (103), and the voltage bias circuit (102) adopt the above-described ultra-low leakage current operational amplifier input stage ESD protection device.

[0039] In one embodiment of this implementation, the step of monitoring ESD events through a first-stage ESD protection circuit (101), providing delay and distinguishing normal power-on events, includes:

[0040] The gate of transistor M1 is controlled by a circuit consisting of resistor R0, resistor R2 and capacitor C0 connected in series in the first-stage ESD protection circuit (101), which detects ESD events, provides delay and distinguishes normal power-on events.

[0041] The circuit formed by resistors R1, R3, and capacitor C1 in the first-stage ESD protection circuit (101) and the drain connection of transistor M3 controls the gate of M1, detects ESD events, provides delay, and distinguishes normal power-on events.

[0042] In one embodiment of this implementation, a control signal sent by a voltage bias circuit (102) to a first-stage ESD protection circuit (101) and a second-stage ESD protection circuit (103) controls the gates of transistors in the first-stage ESD protection circuit (101) and the second-stage ESD protection circuit (103), including:

[0043] Control signals are sent to the first-stage ESD protection circuit through resistors R4 and R5 connected to the output terminal of A0 in the voltage bias circuit (102), and the control signals control the transistor M1 of the first-stage ESD protection circuit.

[0044] Control signals are sent to the second-stage ESD protection circuit through resistors R6 and R7 connected to the output terminal of A0 in the voltage bias circuit (102), and the control signals control the transistor M4 of the second-stage ESD protection circuit.

[0045] In a third aspect of the present invention, a computing device is provided, the computing device comprising: at least one processor, a memory, and an input / output unit; wherein the memory is used to store a computer program, and the processor is used to invoke the computer program stored in the memory to execute an operational amplifier input stage ESD protection method with ultra-low leakage current as described in any one aspect.

[0046] In a fourth aspect of the present invention, a computer-readable storage medium is provided, comprising instructions which, when executed on a computer, cause the computer to perform an operational amplifier input stage ESD protection method with ultra-low leakage current as described in any of the first aspects.

[0047] According to an embodiment of the present invention, an operational amplifier input stage ESD protection device and method with ultra-low leakage current is provided. By connecting two individual ESD protection transistors in series, sampling the input voltage and controlling the source and gate of the ESD protection transistors near the input pin through an input buffer, the drain and source voltages of the ESD protection transistors are biased to be equal, and the gate voltage is kept lower than the input stage voltage, thereby completely turning off the ESD protection transistors and achieving low leakage current function. Attached Figure Description

[0048] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated in the drawings by way of example and not limitation, wherein:

[0049] Figure 1 This is a traditional input pin ESD protection scheme;

[0050] Figure 2 This is a schematic diagram illustrating the change in leakage current with temperature in a single ESD solution provided in an embodiment of the present invention.

[0051] Figure 3 A schematic diagram of an operational amplifier input stage ESD protection device with ultra-low leakage current provided in an embodiment of the present invention;

[0052] Figure 4 This is a schematic diagram illustrating the implementation of the operational amplifier A0 proposed in an embodiment of the present invention;

[0053] Figure 5 The diagram illustrates the effect of achieving low leakage current in an embodiment of the present invention.

[0054] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0055] The principles and spirit of the invention will now be described with reference to several exemplary embodiments. It should be understood that these embodiments are given merely to enable those skilled in the art to better understand and implement the invention, and are not intended to limit the scope of the invention in any way. Rather, these embodiments are provided to make this disclosure more thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art.

[0056] Those skilled in the art will recognize that embodiments of the present invention can be implemented as a system, apparatus, device, method, or computer program product. Therefore, this disclosure can be specifically implemented in the following forms: entirely hardware, entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0057] According to an embodiment of the present invention, an operational amplifier input stage ESD protection device and method with ultra-low leakage current is proposed.

[0058] It should be noted that the number of any elements in the accompanying drawings is for illustrative purposes only and not as a limitation, and any naming is for distinction only and has no limiting meaning.

[0059] The principles and spirit of the present invention will be explained in detail below with reference to several representative embodiments.

[0060] Exemplary device

[0061] The following is for reference. Figure 3 , Figure 3 This diagram illustrates an ultra-low leakage current ESD protection device for the input stage of an operational amplifier, according to an embodiment of the present invention. It should be noted that the embodiments of the present invention can be applied to any applicable scenario. The objective of the present invention is to realize an ultra-low leakage current ESD protection device for the input pins of an operational amplifier using standard CMOS technology. This device ensures low leakage current under a wide input common-mode voltage range and low leakage current across the entire temperature range, while also achieving low current noise.

[0062] Figure 3 The embodiment of the present invention shown provides an ultra-low leakage current operational amplifier input stage ESD protection device, comprising:

[0063] The first-level ESD protection circuit 101, the second-level ESD protection circuit 103, and the voltage bias circuit 102;

[0064] The first-stage EAD protection circuit 101 is connected in series with the second-stage ESD protection circuit 103;

[0065] The voltage bias circuit 102 sends control signals to the source and gate of the first-stage EAD protection circuit 101 and the second-stage ESD protection circuit 103, respectively.

[0066] As an optional implementation, the first-level EAD protection circuit 101 includes: transistor M1, transistor M2, a first control circuit, and a second control circuit;

[0067] The source of transistor M2 and the drain of transistor M1 are connected to form a series branch;

[0068] Both the first control circuit and the second control circuit are connected in parallel with the series branch;

[0069] The voltage bias circuit 102 is connected to the gate and source of the transistor M2, respectively.

[0070] As an optional implementation, the first control circuit includes: capacitor C0, resistor R2, and resistor R0;

[0071] One end of capacitor C0 is connected in series with one end of resistor R2 and one end of resistor R0 in sequence; the other end of capacitor C0 is connected to the drain of transistor M2; the other end of R0 is grounded.

[0072] The gate of the transistor M1 is connected between the resistor R2 and the capacitor C0.

[0073] As an optional implementation, the second control circuit includes: resistor R1, resistor R3, capacitor C1, and transistor M3;

[0074] One end of the capacitor C1 is connected in series with the resistor R3, the resistor R1, and the drain of the transistor M3; the source of the transistor M3 is grounded.

[0075] The other end of the capacitor C1 is connected to the drain of the transistor M2;

[0076] The gate of transistor M3 is connected to the gate of transistor M1;

[0077] The gate of the transistor M2 is connected between the resistor R3 and the resistor R1.

[0078] The specific details of implementing this method are as follows:

[0079] In the first-level ESD protection circuit 101, the main ESD protection path is composed of transistors M1 and M2 connected in series; the circuit composed of resistors R0, R2 and capacitor C0 realizes gate control of transistor M1, detects ESD events, provides delay and distinguishes normal power-on events; the circuit composed of resistors R1, R3 and capacitor C1 and transistor M3 realizes gate control of transistor M1, detects ESD events, provides delay and distinguishes normal power-on events.

[0080] As an optional implementation, the second-level ESD protection circuit 103 includes: resistor R8, transistor M4, and transistor M5;

[0081] The resistor R8 is connected to the drain of transistor M4 and the internal circuit, respectively. The source of transistor M4 is connected to the drain of transistor M5. The source and gate of transistor M5 are both grounded.

[0082] The voltage bias circuit 102 is connected to the gate and source of the transistor M4, respectively.

[0083] The specific details of implementing this method are as follows:

[0084] The second-stage ESD protection circuit 103 consists of a resistor R8 and a circuit in which transistors M4 and M5 are connected in series. The source and gate of transistor M4 are controlled by the outputs NS1 and NG1 of the voltage bias circuit 102, respectively. Since it is the second-stage ESD protection circuit 103, the size of transistors M4 and M5 is generally 1 / 10 of that of transistors M1 and M2 in 101.

[0085] When an ESD event occurs, the input pulse is very fast. The circuit consisting of resistors R0, R2, and C0, as well as the circuit consisting of resistors R1, R3, C1, and transistor M3, are identified as ESD events. At this time, transistor M1, resistor R0, transistor M2, and resistor R1 form a GGNMOS to perform ESD protection, providing an ESD discharge path. Simultaneously, the circuit in the second-stage ESD protection circuit 103, in which transistors M4 and M5 are connected in series, triggers the second-stage ESD protection.

[0086] As an optional implementation, the voltage bias circuit 102 includes: operational amplifier A0, resistor R4, resistor R5, resistor R6, and resistor R7;

[0087] The positive input terminal of the operational amplifier A0 is connected to the second-stage ESD protection circuit 103, the negative input terminal of the operational amplifier A0 is connected to the output terminal, and the output terminal of the operational amplifier A0 is connected to one end of the resistors R4, R5, R6 and R7.

[0088] The other end of resistor R4 and the other end of resistor R5 are both connected to the first-stage ESD protection circuit.

[0089] The other end of resistor R6 and the other end of resistor R7 are both connected to the second-stage ESD protection circuit 103.

[0090] The specific details of implementing this method are as follows:

[0091] The input voltage buffer, also known as the voltage bias circuit 102, samples the input voltage and outputs two voltages NS0 and NS1 that are the same as the input voltage, and two output signals NG0 and NG1 that are smaller than the input voltage. NS0 and NS1 control the source of transistor M1 in the first-stage ESD protection circuit 101 and the source of transistor M4 in the second-stage ESD protection circuit 103, respectively; NG0 and NG1 control the gate of transistor M1 in the first-stage ESD protection circuit 101 and the gate of transistor M4 in the second-stage ESD protection circuit 103, respectively.

[0092] When an ESD event occurs, the input pulse is very fast. The circuit consisting of R0, R2, and C0, as well as the circuit consisting of R1, R3, C1, and M3, is identified as an ESD event. At this time, transistor M1, resistor R0, transistor M2, and resistor R1 form a GGNMOS to perform ESD protection and provide an ESD discharge path. Simultaneously, the circuit consisting of transistors M4 and M5 connected in series in the second-stage ESD protection circuit 103 triggers the second-stage ESD protection.

[0093] As an optional implementation, the operational amplifier A0 includes: transistor MA3, transistor MA4, transistor MA5, transistor MA6, resistor RA0, resistor RA1, resistor RA2, resistor RA3, and resistor RA4;

[0094] The gates of transistors MA5 and MA6 are connected; the gate and drain of transistor MA5 are connected; the drain of transistor MA5 is connected to the drain of transistor MA3; the drain of transistor MA6 is connected to the drain of transistor MA4; the gate and drain of transistor MA4 are connected; and the source of transistor MA3, the source of transistor MA4, and the drain of transistor MA1 are connected.

[0095] The sources of transistors MA0, MA1, and MA2 are grounded, the gates of transistors MA0, MA1, and MA2 are connected, the drain and gate of transistor MA0 are connected, and the drain of transistor MA2 is connected to the source of transistor MA5, one end of resistor RA3, and one end of resistor RA4, respectively.

[0096] The gate of transistor MA5 is connected to the gate of transistor MA4, resistor RA1 and resistor RA2 respectively. The drain of transistor MA5 is connected to one end of resistor RA0, and the other end of resistor RA0 is connected to the source of transistors MA5 and MA6.

[0097] The specific details of implementing this method are as follows:

[0098] The circuit design of operational amplifier A0, such as Figure 4 As shown, the design employs a traditional single op-amp structure. Transistors MA3 and MA4 form the input pair, while transistors MA5 and MA6 form the load transistors. Transistors MA0, MA1, and MA2 provide the input bias current. The gate and drain of transistor M4 are connected, and its output voltage is approximately equal to the input voltage. This signal is then reduced by the threshold voltage of transistor MA5 before being output to NG0 and NG1. Resistors RA0 to RA4 serve as current limiting in ESD events.

[0099] This invention uses two individual ESD protection transistors connected in series to sample the input voltage and control the source and gate of the ESD protection transistor closest to the input pin through an input buffer. The drain and source voltages of the ESD protection transistor are biased to be equal, and the gate voltage is kept lower than the input stage voltage, thereby completely turning off the ESD protection transistor and achieving a low leakage current function.

[0100] The present invention, under SMIC's 0.18um BCD process, typically achieves a maximum input leakage current of less than 20pA when the temperature range is from -55℃ to 125℃ and the input signal voltage is 0-5V.

[0101] Exemplary methods

[0102] After introducing the method of exemplary embodiments of the present invention, the following references are made. Figure 5 An exemplary embodiment of the present invention provides an operational amplifier input stage ESD protection method with ultra-low leakage current, comprising:

[0103] The first-stage ESD protection circuit 101 monitors ESD events, provides delay, and distinguishes them from normal power-on events.

[0104] The control signal sent by the voltage bias circuit 102 to the first-level ESD protection circuit 101 and the second-level ESD protection circuit 103 controls the gate of the transistor in the first-level ESD protection circuit 101 and the second-level ESD protection circuit 103.

[0105] The first-stage ESD protection circuit 101, the second-stage ESD protection circuit 103, and the voltage bias circuit 102 employ the aforementioned ultra-low leakage current operational amplifier input stage ESD protection device.

[0106] In another embodiment of the present invention, the step of monitoring ESD events through the first-stage ESD protection circuit 101, providing delay and distinguishing normal power-on events, includes:

[0107] The gate of transistor M1 is controlled by a circuit consisting of resistor R0, resistor R2 and capacitor C0 connected in series in the first-stage ESD protection circuit 101, which detects ESD events, provides delay and distinguishes normal power-on events.

[0108] The circuit formed by resistors R1 and R3, capacitor C1, and the drain connection of transistor M3 in the first-stage ESD protection circuit 101 controls the gate of M1, detects ESD events, provides delay, and distinguishes normal power-on events.

[0109] In another embodiment of the present invention, the control signals sent by the voltage bias circuit 102 to the first-stage ESD protection circuit 101 and the second-stage ESD protection circuit 103 control the gates of the transistors in the first-stage ESD protection circuit 101 and the second-stage ESD protection circuit 103, including:

[0110] Control signals are sent to the first-stage ESD protection circuit through resistors R4 and R5 connected to the output terminal of operational amplifier A0 in voltage bias circuit 102, and the control signals control the transistor M1 of the first-stage ESD protection circuit 101.

[0111] Control signals are sent to the second-stage ESD protection circuit 103 through resistors R6 and R7 connected to the output terminal of operational amplifier A0 in voltage bias circuit 102, and the control signals control the transistor M4 of the second-stage ESD protection circuit 103.

[0112] This invention provides an ESD protection method for the input stage of an operational amplifier with ultra-low leakage current, the details of which are as follows:

[0113] When the chip starts up normally, the circuit consisting of resistors R0, R2, and C0, as well as the circuit consisting of R1, R3, C1, and M3, determines that it is not an ESD event. The gate of transistor M1 is connected to ground through resistor R0, and transistor M1 is in the off state. The input voltage of the source of transistor M2 is controlled by the input stage AMPIN and the 102 input voltage buffer. At this time, the source voltage of transistor M2 is approximately equal to the drain voltage, i.e., the input stage voltage, meaning the source-drain voltage difference of transistor M2 is equal to 0, thus achieving low leakage current of transistor M2. At the same time, the source-drain voltage of transistor M4 in the second-stage protection circuit of 103 is controlled to be close to 0 by the 102 input buffer, thus achieving very low leakage current of transistor M4.

[0114] Figure 5The diagram illustrates the low leakage current achieved by this invention. Under typical conditions using SMIC's 0.18µm BCD process, the maximum input leakage current is less than 20pA within a temperature range of -55°C to 125°C and with an input signal voltage of 0-5V. The slight fluctuation in Iin_25 in the diagram due to testing errors does not affect the beneficial effects of this invention.

[0115] Exemplary media

[0116] After introducing the methods and apparatus of exemplary embodiments of the present invention, the computer-readable storage medium of the exemplary embodiments of the present invention will now be described. The computer-readable storage medium is an optical disc, on which a computer program (i.e., a program product) is stored. When the computer program is run by a processor, it implements the steps described in the above-described method embodiments. For example, it monitors ESD events through the first-level ESD protection circuit 101, provides a delay, and distinguishes normal power-on events; it controls the gates of transistors in the first-level ESD protection circuit 101 and the second-level ESD protection circuit 103 by sending control signals to the first-level ESD protection circuit 101 and the second-level ESD protection circuit 103 through the voltage bias circuit 102; wherein the first-level ESD protection circuit 101 and the second-level ESD protection circuit 103 are connected in series; the specific implementation of each step will not be repeated here.

[0117] It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical and magnetic storage media, which will not be elaborated here.

[0118] Exemplary computing device

[0119] After introducing the methods, apparatus, and media of exemplary embodiments of the present invention, the following describes a computing device for an operational amplifier input stage ESD protection method with ultra-low leakage current according to exemplary embodiments of the present invention.

[0120] The computing device may be a computer system or a server. This computing device is merely an example and should not be construed as limiting the functionality or scope of the embodiments of the present invention.

[0121] The components of a computing device may include, but are not limited to: one or more processors or processing units, system memory, and buses connecting different system components (including system memory and processing units).

[0122] Computing devices typically include a variety of computer system-readable media. These media can be any available media that can be accessed by the computing device, including volatile and non-volatile media, and removable and non-removable media.

[0123] The system memory may include computer system readable media in the form of volatile memory, such as random access memory (RAM) and / or cache memory. The computing device may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, ROM can be used to read and write non-removable, non-volatile magnetic media (commonly referred to as a "hard disk drive"). Disk drives for reading and writing to removable non-volatile disks (e.g., "floppy disks") and optical disk drives for reading and writing to removable non-volatile optical discs (e.g., CD-ROMs, DVD-ROMs, or other optical media) may be provided. In these cases, each drive may be connected to a bus via one or more data media interfaces. The system memory 9 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present invention.

[0124] A program / utility having a set (at least one) of program modules may be stored, for example, in system memory, and such program modules include, but are not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment. The program modules typically perform the functions and / or methods described in the embodiments of this invention.

[0125] The computing device can also communicate with one or more external devices (such as a keyboard, pointing device, display, etc.). This communication can be achieved through an input / output (I / O) interface. Furthermore, the computing device can communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter. The network adapter communicates with other modules of the computing device (such as a processing unit) via a bus. It should be understood that other hardware and / or software modules can be used in conjunction with the computing device.

[0126] The processing unit executes various functional applications and data processing by running programs stored in the system memory. For example, it monitors ESD events through the first-stage ESD protection circuit 101, provides delays, and distinguishes normal power-on events; it controls the gates of transistors in the first-stage ESD protection circuit 101 and the second-stage ESD protection circuit 103 by sending control signals to them via the voltage bias circuit 102; wherein the first-stage ESD protection circuit 101 and the second-stage ESD protection circuit 103 are connected in series. The specific implementation methods of each step will not be repeated here. It should be noted that although several units / modules or sub-units / sub-modules for implementing an op-amp input stage ESD protection method with ultra-low leakage current are mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of the present invention, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided and embodied by multiple units / modules.

[0127] In the description of this invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0128] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0129] In the several embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0130] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0131] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0132] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0133] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0134] Furthermore, although the operations of the method of the present invention are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

Claims

1. An operational amplifier input stage ESD protection device with ultra-low leakage current, characterized in that, include: The circuit consists of a first-level ESD protection circuit (101), a second-level ESD protection circuit (103), and a voltage biasing circuit (102). The first-stage ESD protection circuit (101) and the second-stage ESD protection circuit (103) are connected in series; The voltage bias circuit (102) sends control signals to the source and gate of the first-stage ESD protection circuit (101) and the second-stage ESD protection circuit (103), respectively. The first-level ESD protection circuit (101) includes: transistor M1, transistor M2, a first control circuit, and a second control circuit; The source of transistor M2 and the drain of transistor M1 are connected to form a series branch; Both the first control circuit and the second control circuit are connected in parallel with the series branch; The voltage bias circuit (102) is connected to the gate and source of the transistor M2, respectively; The second-level ESD protection circuit (103) includes: resistor R8, transistor M4 and transistor M5; The resistor R8 is connected to the drain of transistor M4 and the internal circuit, respectively. The source of transistor M4 is connected to the drain of transistor M5. The source and gate of transistor M5 are both grounded. The voltage bias circuit (102) is connected to the gate and source of the transistor M4, respectively; The voltage bias circuit (102) includes: operational amplifier A0, resistor R4, resistor R5, resistor R6, and resistor R7; The positive input terminal of the operational amplifier A0 is connected to the second-stage ESD protection circuit (103), the negative input terminal of the operational amplifier A0 is connected to the output terminal, and the output terminal of the operational amplifier A0 is connected to one end of the resistors R4, R5, R6 and R7. The other end of resistor R4 is connected to the source of the first-stage ESD protection circuit, and the other end of resistor R5 is connected to the gate of the first-stage ESD protection circuit. The other end of resistor R6 is connected to the source of the second-stage ESD protection circuit, and the other end of resistor R7 is connected to the gate of the second-stage ESD protection circuit. The operational amplifier A0 includes: transistor MA3, transistor MA4, transistor MA5, transistor MA6, resistor RA0, resistor RA1, resistor RA2, resistor RA3 and resistor RA4; The gates of transistors MA5 and MA6 are connected; the gate and drain of transistor MA5 are connected; the drain of transistor MA5 is connected to the drain of transistor MA3; the drain of transistor MA6 is connected to the drain of transistor MA4; the gate and drain of transistor MA4 are connected; and the source of transistor MA3, the source of transistor MA4, and the drain of transistor MA1 are connected. The sources of transistors MA0, MA1, and MA2 are grounded, the gates of transistors MA0, MA1, and MA2 are connected, the drain and gate of transistor MA0 are connected, and the drain of transistor MA2 is connected to the source of transistor MA5, one end of resistor RA3, and one end of resistor RA4, respectively. The gate of transistor MA5 is connected to the gate of transistor MA4, resistor RA1 and resistor RA2 respectively. The drain of transistor MA5 is connected to one end of resistor RA0, and the other end of resistor RA0 is connected to the source of transistors MA5 and MA6. The other end of resistor RA1 is connected to one end of resistor R4, and the other end of resistor RA2 is connected to one end of resistor R6. The other end of resistor RA3 is connected to one end of resistor R5, and the other end of resistor RA4 is connected to one end of resistor R7.

2. The apparatus as claimed in claim 1, characterized in that, The first control circuit includes: capacitor C0, resistor R2 and resistor R0; One end of capacitor C0 is connected in series with one end of resistor R2 and one end of resistor R0 in sequence; the other end of capacitor C0 is connected to the drain of transistor M2; the other end of R0 is grounded. The gate of the transistor M1 is connected between the resistor R2 and the resistor R0.

3. The apparatus as described in claim 1, characterized in that, The second control circuit includes: resistor R1, resistor R3, capacitor C1, and transistor M3; One end of the capacitor C1 is connected in series with the resistor R3, the resistor R1, and the drain of the transistor M3; the source of the transistor M3 is grounded. The other end of the capacitor C1 is connected to the drain of the transistor M2; The gate of transistor M3 is connected to the gate of transistor M1; The gate of the transistor M2 is connected between the resistor R3 and the resistor R1.

4. A method for ESD protection of an operational amplifier input stage with ultra-low leakage current, characterized in that, include: The first-stage ESD protection circuit (101) monitors ESD events, provides delay, and distinguishes them from normal power-on events; The control signal sent by the voltage bias circuit (102) to the first-level ESD protection circuit (101) and the second-level ESD protection circuit (103) controls the gate of the transistor in the first-level ESD protection circuit (101) and the second-level ESD protection circuit (103). The first-stage ESD protection circuit (101), the second-stage ESD protection circuit (103), and the voltage bias circuit (102) adopt an operational amplifier input stage ESD protection device with ultra-low leakage current as described in any one of claims 1 to 3.

5. The method as described in claim 4, characterized in that, The monitoring of ESD events through the first-stage ESD protection circuit (101), providing delay and distinguishing normal power-on events, includes: The gate of transistor M1 is controlled by a circuit consisting of resistor R0, resistor R2 and capacitor C0 connected in series in the first-stage ESD protection circuit (101), which detects ESD events, provides delay and distinguishes normal power-on events. The circuit formed by resistors R1, R3, and C1 in the first-stage ESD protection circuit (101) and the drain connection of transistor M3 controls the gate of M1, detects ESD events, provides delay, and distinguishes normal power-on events.

6. A computer device, the computer device comprising: At least one processor, memory, and input / output unit; The memory is used to store computer programs, and the processor is used to call the computer programs stored in the memory to execute an operational amplifier input stage ESD protection method with ultra-low leakage current as described in any one of claims 4-5.

7. A computer-readable storage medium comprising instructions that, when executed on a computer, cause the computer to perform an operational amplifier input stage ESD protection method with ultra-low leakage current as described in any one of claims 4-5.

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