A word-length split content addressable memory system

Abstract

The present invention provides a word-length-split content-addressable memory system, belonging to the field of microelectronics. A matchline partially activated content-addressable module is used to store data in blocks, implement partial searches, and output partial matching results to an AND gate module. The AND gate module is used to AND the partial matching results of multiple matchline partially activated content-addressable modules and output the final matching result to a main processor. The main processor is used to control the matchline partially activated content-addressable module and the AND gate module, and is used to output search data to the matchline partially activated content-addressable module and receive the final matching result. The data to be stored is segmented according to word length and stored in sub-blocks of different matchline partially activated content-addressable modules. The present invention can effectively reduce the number of matchline load units, improve the sensing margin, thereby reducing the area and power consumption of the sensing amplifier, and can also realize the storage and search of data of arbitrary word length.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronics technology, and more particularly, relates to a word-length split content addressable memory system. Background Art

[0002] Content-addressable memory (CAM) is a highly efficient memory for data retrieval. It enables highly parallel data searches and outputs matching results for all stored and searched data in a single search operation. Emerging non-volatile device-based CAMs are gaining attention due to their advantages such as non-volatility, low power consumption, and small size.

[0003] However, content-addressable memories based on non-volatile devices suffer from issues such as leakage current and resistance drift, limiting their array size. Furthermore, as the number of load cells on a match line increases, the sensing margin between match and mismatch decreases, increasing the area and power consumption of the sense amplifier, significantly diminishing the performance gains offered by non-volatile devices. Summary of the Invention

[0004] In response to the shortcomings of the prior art, the purpose of the present invention is to provide a word-length-split content-addressable memory system, which splits the stored data into sub-blocks of different content-addressable memory arrays for search, effectively reducing the number of load units on the match line and thus reducing the area and power consumption of the sensing amplifier, and realizing data storage and search of arbitrary word length.

[0005] To achieve the above object, the present invention provides a word-length split content addressable memory system, comprising: a match line partial activation content addressing module, an AND gate circuit module and a main processor;

[0006] The output end of the main processor is connected to the input end of the match line partial activation content addressing module; the output end of the match line partial activation content addressing module is connected to the input end of the AND gate circuit module; the AND gate circuit module is bidirectionally connected to the main processor;

[0007] The match line partially activated content addressing module is used to store data in blocks, implement partial search and output partial matching results to the AND gate circuit module;

[0008] The AND gate circuit module is used to perform AND operation on partial matching results of multiple match line partial activation content addressing modules and output the final matching result to the main processor;

[0009] The main processor is used to control the match line partial activation content addressing module and the AND gate circuit module; and is used to output search data to the match line partial activation content addressing module and receive the final matching result output by the AND gate circuit module;

[0010] The data to be stored are cut according to word length and stored in sub-blocks of different matching line partially activated content addressing modules respectively; the data stored in the same matching line partially activated content addressing module have the same word length, and the storage data stored in different sub-blocks of the same matching line partially activated content addressing module will not perform search operations at the same time; the word length of the search data is equal to the word length of the storage data of different sub-blocks.

[0011] It should be pointed out here that the "part" in the match line partially activated content addressing module, partial search and partial matching means that the storage data of different sub-blocks stored in the same match line partially activated content addressing module will not perform search operations at the same time, and all storage data will not perform search operations at the same time.

[0012] Further preferably, the match line partial activation content addressing module comprises: an input voltage driving unit, a multiplexer, a content addressable memory array based on a non-volatile device, and a voltage sensing unit;

[0013] The input end of the input voltage driving unit is connected to the output end of the main processor, and is used to convert the search data input by the main processor into paired complementary analog voltage signals and output them to the multiplexer;

[0014] The input end of the multiplexer is connected to the input voltage driving unit and the output end of the main processor, and the output end of the multiplexer is connected to the content addressable memory array based on the non-volatile device, and is used to output the paired complementary analog voltage signals input by the input voltage driving unit to the corresponding sub-blocks of the content addressable memory array based on the non-volatile device according to the multiplexing signal input by the main processor;

[0015] A content addressable memory array based on a non-volatile device is used to store multiple sub-blocks, and compares the data stored in the sub-blocks with the analog voltage signal input by the multiplexer, and outputs a high or low voltage to the voltage sensing unit through a match line to indicate whether there is a match;

[0016] The input end of the voltage sensing unit is connected to the output end of the content addressable memory array based on the non-volatile device, and its output end is connected to the AND gate circuit module, which is used to convert the high and low voltages on each row of matching lines into digital signals and transmit the digital signals to the AND gate circuit module.

[0017] Further preferably, the non-volatile device is a resistive random access memory, a ferroelectric memory, a phase change memory, a spin transfer torque-magnetic random access memory, a NOR Flash device or a NAND Flash device.

[0018] Further preferably, the content addressable memory array based on non-volatile devices is a two-dimensional crossbar structure or other two-dimensional planar structure array, a three-dimensional horizontal stacking structure, a three-dimensional vertical stacking structure or other three-dimensional stacking structure.

[0019] Further preferably, a discharge transistor is connected to the commonly connected match line of each row of content addressable memories in the non-volatile device-based content addressable memory array, for initializing before the search phase and discharging the match line to ground.

[0020] Further preferably, the voltage sensing unit includes a plurality of voltage sensing amplifiers, each voltage sensing amplifier is correspondingly connected to a matching line, and outputs a digital signal 1 or 0 when sensing a high voltage or a low voltage, respectively.

[0021] Further preferably, the AND gate circuit module includes multiple multi-input AND gates; the number of AND gates is equal to the number of voltage sensing amplifiers in the voltage sensing unit, and the number of input ports of each AND gate is equal to the number of matching line partial activation content addressing modules.

[0022] Further preferably, the sub-block word lengths between different match line partial activation content addressing modules are not necessarily equal.

[0023] Further preferably, when the search data is 1, the paired complementary analog voltage signals in the input voltage driving unit are voltages of VS and 0; when the search data is 0, the paired complementary analog voltage signals in the input voltage driving unit are voltages of 0 and VS; wherein VS is the search voltage of the content addressable memory array based on the non-volatile device.

[0024] In general, the above technical solutions conceived by the present invention have the following beneficial effects compared with the prior art:

[0025] The present invention provides a word-length-split content-addressable memory system, in which data to be stored is split according to word length and stored separately in sub-blocks of different match-line partially activated content-addressable modules. Data stored in the same match-line partially activated content-addressable module has the same word length, and data stored in different sub-blocks of the same match-line partially activated content-addressable module are not searched simultaneously. The word length of the searched data is equal to the word length of the data stored in different sub-blocks. This invention can effectively reduce the number of match-line load units and improve the sensing margin, thereby reducing the area and power consumption of the sense amplifier. It can also enable the storage and search of data of arbitrary word lengths. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 1 is a schematic structural diagram of a word-length split content-addressable memory system provided by an embodiment of the present invention;

[0027] Figure 2is a circuit structure diagram of a match line partial activation content addressing module provided by an embodiment of the present invention;

[0028] Figure 3 Schematic diagram of voltage input and data storage forms, as well as matching and mismatching conditions, of a content addressable memory based on a non-volatile device provided by an embodiment of the present invention;

[0029] Figure 4 This is a match and 1-bit mismatch search voltage distribution diagram of a content addressable memory array based on a non-volatile device provided by an embodiment of the present invention during a 64-bit parallel search;

[0030] Figure 5 The voltage distribution diagrams for matching and 1-bit mismatch searches of a content addressable memory array based on a non-volatile device provided by an embodiment of the present invention during 16-bit and 8-bit parallel searches are shown;

[0031] Figure 6 Schematic diagram of splitting the word length of stored data into sub-blocks of partially activated content addressable modules of different match lines according to an embodiment of the present invention;

[0032] Figure 7 Schematic diagram of searching after splitting the search data word length and obtaining the final matching result provided by an embodiment of the present invention;

[0033] Figure 8 This is an example of performing word length splitting and data search in the word length split content addressable memory system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] For ease of understanding, the English abbreviations and related technical terms involved in the embodiments of this application are explained and described below.

[0035] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0036] like Figure 1 As shown, the present invention provides a word-length split content addressable memory system, including a match line partial activation content addressing module 1, an AND gate circuit module 2 and a main processor 3;

[0037] The match line partial activation content addressing module 1 is used to store data in blocks, implement partial search and output partial matching results to the AND gate circuit module 2;

[0038] The AND gate circuit module 2 is used to perform AND on the partial matching results of the multiple match line partial activation content addressing modules 1 and output the final matching result to the main processor 3;

[0039] The main processor 3 is used to control the match line partial activation content addressing module 1 and the AND gate circuit module 2; and is used to output search data to the match line partial activation content addressing module 1 and receive the final matching result output by the AND gate circuit module 2.

[0040] Further preferably, the match line partial activation content addressing module 1 mentioned in this embodiment includes an input voltage driving unit 1-1, a multiplexer 1-2, a content addressable memory array 1-3 based on a non-volatile device, and a voltage sensing unit 1-4;

[0041] The input terminal of the input voltage driving unit 1-1 is connected to the output terminal of the main processor 3, and is used to convert the search data input by the main processor 3 into paired complementary analog voltage signals and output them to the multiplexer 1-2;

[0042] The input end of the multiplexer 1-2 is connected to the input voltage driving unit 1-1 and the main processor 3, and the output end of the multiplexer 1-2 is connected to the content addressable memory array 1-3 based on the non-volatile device; the multiplexer 1-2 is used to output the paired complementary analog voltage signals input by the input voltage driving unit 1-1 to the corresponding sub-blocks of the content addressable memory array 1-3 based on the non-volatile device according to the multiplexing signal input by the main processor 3;

[0043] The content addressable memory array 1-3 based on non-volatile devices is used to store multiple sub-blocks and compare the data stored in the sub-blocks with the analog voltage signal input in the form of analog voltage by the multiplexer 1-2, and outputs high and low voltages to the voltage sensing unit 1-4 through the match line to indicate whether there is a match;

[0044] The input end of the voltage sensing unit 1-4 is connected to the output end of the content addressable memory array 1-3 based on the non-volatile device, and its output end is connected to the AND gate circuit module, which is used to convert the high and low voltages on each row of matching lines into digital signals and transmit the digital signals to the AND gate circuit module.

[0045] It should be noted that the non-volatile device mentioned in this embodiment may be a resistive random access memory, a ferroelectric memory, a phase change memory, a spin transfer torque-magnetic random access memory, a NOR Flash device, or a NAND Flash device, and this embodiment does not limit this. The structure of the content addressable memory array 1-3 based on the non-volatile device mentioned in this embodiment may be a two-dimensional crossbar structure or other two-dimensional planar structure array, a three-dimensional horizontal stacking structure, a three-dimensional vertical stacking structure, or other three-dimensional stacking structure, and this embodiment does not limit this.

[0046] Furthermore, a discharge transistor is connected to the commonly connected match line of each row of content addressable memories in the non-volatile device-based content addressable memory array 1-3 provided in this embodiment, for initializing before the search phase and discharging the match line to ground.

[0047] The word-length split content-addressable memory system provided in this embodiment effectively reduces the matching line load unit, improves the sensing margin, reduces the area and power consumption of the sensing amplifier, and can realize the storage and search of data of arbitrary word length by storing the storage data in multiple different content-addressable memory arrays.

[0048] In one embodiment, the input voltage driving unit of the match line partially activated content addressing module provided by the present invention has a pair of complementary analog voltage signals corresponding to voltages of VS and 0 when the search data is "1"; and a pair of complementary analog voltage signals corresponding to voltages of 0 and VS when the search data is "0"; wherein VS is the search voltage of the content addressable memory array based on the non-volatile device;

[0049] In one embodiment, the voltage sensing unit of the match line partially activated content addressing module provided by the present invention includes a plurality of voltage sensing amplifiers, each of which is connected to a corresponding match line and outputs a digital signal 1 or 0 when sensing a high voltage or a low voltage, respectively;

[0050] In one embodiment, the AND gate circuit module provided by the present invention is composed of a plurality of multi-input AND gates, the number of AND gates being equal to the number of voltage sensing amplifiers in the voltage sensing unit of the match line partial activation content addressing module, and the number of input ports of each AND gate being equal to the number of the match line partial activation content addressing module 1;

[0051] Specifically, the match line partially activated content addressing module 1 provided in this embodiment stores a plurality of sub-blocks of equal word length, and the word lengths of the sub-blocks in different match line partially activated content addressing modules are not necessarily equal.

[0052] In one embodiment, the data to be stored provided by the present invention is cut according to word length and stored in sub-blocks of different matching line partial activation content addressing modules, and the storage data stored in different sub-blocks of the same matching line partial activation content addressing module will not perform search operations at the same time.

[0053] In one embodiment, the search data provided by the present invention is divided into multiple sub-data according to the same word length cutting method as the storage data and input into the corresponding matching line partial activation content addressing module, and multiple output results are ANDed through the multi-input AND gate of the AND gate circuit module to obtain the final matching result.

[0054] The present invention is described in detail below with reference to specific embodiments:

[0055] Example 1

[0056] like Figure 2 As shown in the figure, the circuit structure diagram of the match line partial activation content addressable module includes: an input voltage driving unit, a multiplexer, a content addressable memory array based on non-volatile devices, and a voltage sensing unit; wherein, the input voltage driving unit is composed of a 1-bit DAC; the multiplexer is composed of n t-way selection switches; the content addressable memory array based on non-volatile devices is composed of content addressable memory cells composed of two non-volatile devices, and each row also has a discharge transistor for initialization, with a total of t×n columns; the voltage sensing unit is composed of a sense amplifier (SA), which is used to compare the input voltage with the reference voltage to obtain a digital output result of "0" or "1".

[0057] Example 2

[0058] Figure 3 This is a schematic diagram of the storage and search methods, as well as the matching and mismatching conditions, of a content-addressable memory cell based on a non-volatile device provided by an embodiment of the present invention. A content-addressable memory is composed of two non-volatile devices R0 and R1. When storing "0", R0 and R1 are in high-impedance and low-impedance states, respectively; when storing "1", R0 and R1 are in low-impedance and high-impedance states, respectively. The search is implemented by two 1-bit DACs with complementary outputs. When searching for "0", voltages of 0 and VS are applied, respectively; when searching for "1", voltages of VS and 0 are applied, respectively, where VS is the search voltage of the content-addressable memory array. When the stored data and the search data match, the match line ML is a high voltage, and when there is a mismatch, it is a low voltage.

[0059] Example 3

[0060] Figure 4 This diagram shows the voltage distribution for a match and a one-bit mismatch during a 64-bit parallel search in a content-addressable memory array based on a nonvolatile device, as provided by an embodiment of the present invention. The diagram uses an on / off ratio of 20, a read voltage (VS) of 0.2V, and a device drift of 20%. Because the 64-bit data is not split, if the number of load cells on the same match line is too long, matches and mismatches overlap. In this case, the sensing margin is zero, making it impossible to accurately distinguish between matches and mismatches.

[0061] Figure 5This is a diagram of the voltage distribution for the match and 1-bit mismatch search of a content-addressable memory array based on a non-volatile device provided by an embodiment of the present invention during 16-bit and 8-bit parallel searches. At this time, the switching ratio is 20, the read voltage VS is 0.2V, and the device drift is 20%. By splitting the 64-bit data into [16bit, 16bit, 16bit, 8bit, 8bit] and searching separately, it is possible to accurately distinguish between mismatches and matches, and effectively improve the perception margin. After the split search, the perception margin of each search is relatively large, and the shorter the search data word length, the larger the perception margin, the easier it is to distinguish, and the lower the accuracy requirement for the perception circuit.

[0062] Example 4

[0063] The way to implement storage data splitting and searching is as follows:

[0064] Figure 6 Schematic diagram of splitting stored data into sub-blocks of different match-line partially activated content-addressable modules according to an embodiment of the present invention; wherein the stored data has a word length of N and is split into X0 pieces of data with a word length of n0, X1 pieces of data with a word length of n1, ..., and these pieces of data satisfy the condition N = n0*X0+n1*X1+...; after splitting, these pieces of data are respectively stored in the match-line partially activated content-addressable modules of the sub-blocks with word lengths of n0, n1, ...;

[0065] Figure 7 This is a schematic diagram of search data splitting and matching result acquisition provided by an embodiment of the present invention; wherein, search data having the same word length as the stored data is split in the same data manner to obtain multiple partial data, which are then input into the input voltage driving unit of the corresponding match line partially activated content addressing module to be compared and matched with the corresponding partial stored data; the partial matching results obtained after comparison by multiple match line partially activated content addressing modules are ANDed through a multi-input AND gate circuit to obtain the final matching result.

[0066] Example 5

[0067] Figure 8 This is an example of storage data splitting and data search provided by an embodiment of the present invention, wherein the storage data A are "01101001", "10010111", and "11000110", and the storage data B are "11011100", "00011011", and "01001000", respectively. The search data a used to search the storage data A is "10010111", and the search data b used to search the storage data B is "01001000". It should be noted that the storage data A and the storage data B cannot be searched at the same time.

[0068] After the storage data splitting in 4-2-2, the storage data A is split into three partial data blocks A0, A1 and A2, and the storage data B is split into three partial data blocks B0, B1 and B2; wherein, the partial storage data A0 are respectively "0110", "1001", and "1100", and A1 are respectively "10", "01", and "01"; A2 are respectively "01", "11", and "10", and B0 are respectively "1101", "0001", and "0100", and B1 are respectively "11", "10", and "10", and B2 are respectively "00", "11", and "00"; after splitting, different partial data of the same storage data are stored in the storage arrays of different match line partially activated content addressing modules, and partial data of the same word length of different storage data can be stored in the same storage array; based on this, the storage data A and the storage data B are stored together in the storage arrays 0-2, wherein the storage array 0 stores the partial data A0 and B0, the storage array 1 stores the partial data A1 and B1, and the storage array 2 stores the partial data A2 and B2;

[0069] When searching for stored data A, the search data a is also split into a0, a1 and a2 through 4-2-2, which are "1001", "01" and "11" respectively, and then input into the storage arrays 0-2 for searching. At this time, the multiplexers of each storage array are connected to the sub-blocks corresponding to A0-A2; after comparison matching and sense amplifier comparison, the partial matching results corresponding to each storage array are obtained; among which, the partial matching results 0-2 are "010", "011" and "010" respectively. The matching results of the same row are ANDed through three three-input AND gates to obtain the final matching result. The matching result is "010", so the first and third rows of data in storage data A do not match search data a, but the second row does. When searching for data b, it is split into "0100", "10", and "00" in the same way and then input. At this time, the multiplexers of each storage array are connected to the sub-blocks corresponding to B0-2. After comparison matching and sense amplifier comparison, the matching results are "001", "011", and "101" respectively. After passing through the AND gate, the final matching result is "001", so the first and second rows of data in storage data B do not match search data b, but the third row does.

[0070] The word-length-split content-addressable memory system provided by the present invention can realize highly parallel data search in the memory, reduce data transmission and processing processes, and improve search efficiency; it can also reduce the number of match line load units, improve search perception margin, reduce the power consumption and area of ​​the perception circuit, and realize data storage and search of arbitrary word length.

[0071] It should be understood that expressions such as "include" and "may include" used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as "include" and / or "have" may be interpreted as indicating specific characteristics, numbers, operations, constituent elements, components, or combinations thereof, but may not be interpreted as excluding the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0072] In addition, in this application, the expression "and / or" includes any and all combinations of the associated listed words. For example, the expression "A and / or B" may include A, may include B, or may include both A and B.

[0073] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. Among them, "fixed connection" means that the two are connected to each other and the relative position relationship after the connection remains unchanged. "Rotational connection" means that the two are connected to each other and can rotate relative to each other after the connection. "Sliding connection" means that the two are connected to each other and can slide relative to each other after the connection. The directional terms mentioned in the embodiments of the present application, such as "top", "bottom", "inside", "outside", "left", "right", etc., are only reference to the directions of the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0074] In addition, in the embodiments of the present application, the mathematical concepts mentioned include symmetry, equality, parallelism, and perpendicularity. These limitations are all for the current state of the art, rather than being absolutely strict definitions in a mathematical sense. A small amount of deviation is allowed, and it is possible to be approximately symmetric, approximately equal, approximately parallel, or approximately perpendicular. For example, A and B are parallel, which means that A and B are parallel or approximately parallel, and the angle between A and B can be between 0 and 10 degrees. A and B are perpendicular, which means that A and B are perpendicular or approximately perpendicular, and the angle between A and B can be between 80 and 100 degrees.

[0075] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A word-length split content addressable memory system, characterized in that: include: The match line section activates the content addressing module, the AND gate circuit module and the main processor; The output of the main processor is connected to the input of the match line partial activation content addressing module; the output of the match line partial activation content addressing module is connected to the input of the AND gate circuit module; the AND gate circuit module is bidirectionally connected to the main processor; The match line partial activation content addressing module is used to store data in blocks, implement partial search and output partial matching results to the AND gate circuit module; The AND gate circuit module is used to perform AND on the partial matching results of the multiple match line partial activation content addressing modules and output the final matching result to the main processor; The main processor is used to control the match line part to activate the content addressing module and the AND gate circuit module; and is used to output search data to the match line partial activation content addressing module and receive the final matching result output by the AND gate circuit module; The data to be stored are cut according to word length and stored in sub-blocks of different matching line partially activated content addressing modules respectively; the data stored in the same matching line partially activated content addressing module have the same word length, and the storage data stored in different sub-blocks of the same matching line partially activated content addressing module will not perform search operations at the same time; wherein the word length of the search data is equal to the word length of the storage data of different sub-blocks.

2. The word-length split content addressable memory system according to claim 1, wherein: The match line partial activation content addressing module includes: an input voltage driving unit, a multiplexer, a content addressable memory array based on a non-volatile device, and a voltage sensing unit; The input end of the input voltage driving unit is connected to the output end of the main processor, and is used to convert the search data input by the main processor into paired complementary analog voltage signals and input them into the multiplexer; The input end of the multiplexer is connected to the output end of the input voltage driving unit and the main processor, and the output end of the multiplexer is connected to the content addressable memory array based on the non-volatile device, and is used to output the paired complementary analog voltage signals input by the input voltage driving unit to the corresponding sub-blocks of the content addressable memory array based on the non-volatile device according to the multiplexing signal input by the main processor; The content addressable memory array based on non-volatile devices is used to store multiple sub-blocks, and compares the data stored in the sub-blocks with the analog voltage signal input by the multiplexer, and outputs high and low voltages to the voltage sensing unit through the match line to indicate whether there is a match; The input end of the voltage sensing unit is connected to the output end of the content addressable memory array based on the non-volatile device, and its output end is connected to the AND gate circuit module, which is used to convert the high and low voltages on each row of matching lines into digital signals and transmit the digital signals to the AND gate circuit module.

3. The word-length split content addressable memory system according to claim 2, wherein: The non-volatile device is a resistive random access memory, a ferroelectric memory, a phase change memory, a spin transfer torque-magnetic random access memory, a NOR Flash device or a NAND Flash device.

4. The word-length split content addressable memory system according to claim 2, wherein: The content addressable memory array based on non-volatile devices is a two-dimensional crossbar structure or other two-dimensional planar structure array, a three-dimensional horizontal stacking structure, a three-dimensional vertical stacking structure or other three-dimensional stacking structure.

5. The word-length split content addressable memory system according to claim 2 or 4, characterized in that: A discharge transistor is connected to the matching line commonly connected to each row of content addressable memory in the non-volatile device-based content addressable memory array, and is used for initialization before the search phase to discharge the matching line to the ground.

6. The word-length split content addressable memory system according to claim 2, wherein: The voltage sensing unit includes a plurality of voltage sensing amplifiers, each of which is connected to a corresponding matching line and outputs a digital signal 1 or 0 when sensing a high voltage or a low voltage, respectively.

7. The word-length split content addressable memory system according to claim 6, wherein: The AND gate circuit module includes multiple multi-input AND gates; the number of AND gates is equal to the number of voltage sensing amplifiers in the voltage sensing unit, and the number of input ports of each AND gate is equal to the number of matching line partial activation content addressing modules.

8. The word-length split content addressable memory system according to claim 1 or 2, characterized in that: The sub-block word lengths between different match line partially activated content addressable modules are not necessarily equal.

9. The word-length split content addressable memory system according to claim 2, wherein: When the search data is 1, the paired complementary analog voltage signals in the input voltage driving unit are voltages of VS and 0; when the search data is 0, the paired complementary analog voltage signals in the input voltage driving unit are voltages of 0 and VS; wherein VS is the search voltage of the content addressable memory array based on the non-volatile device.

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