Business processing method and device

Abstract

The invention discloses a business processing method and device, and relates to the field of computers. And the main processing core determines the processing core for processing the job according to the load information and the job attribute of each processing core. Thus, the main processing core schedules the operation included in the processing core processing service, a guarantee is provided for the low-power-consumption processing core to process complex services, the service processing range of the low-power-consumption processing core is expanded, the power consumption of the computing device is reduced, and the endurance time of the computing device is prolonged. And the master processing core schedules the master processing core and the slave processing core to process each job in the service so as to process the service, and the master processor and / or the slave processing core are / is adopted to schedule and process the service, so that the time required for processing the service is saved, and the scheduling efficiency of processing the service is improved.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to a business processing method and device. Background Art

[0002] Computing devices can use both application (AP) processing cores and microprocessor cores to handle services. Microprocessor cores consume less power than AP processing cores, reducing power consumption. Typically, computing devices use AP processing cores for complex services requiring higher processing power, and microprocessor cores for other services.

[0003] Before computing devices can use processing cores to process services, they must designate a processing core for that service and use that core to process the service. Microprocessor cores are limited in their processing power and cannot handle complex services. Complex services still need to be handled by the higher-powered AP processing cores, resulting in minimal power savings. Summary of the Invention

[0004] The present application provides a service processing method and apparatus for solving the problem that the scope of services processed by low-power processing cores is limited, resulting in insignificant reduction in power consumption of computing devices.

[0005] In a first aspect, the present application provides a business processing method. The method can be executed by a business processing device, which includes: a master processing core and a slave processing core. The master processing core is used to schedule the master processing core and the slave processing core to process the business. The master processing core and the slave processing core can be deployed on one processor or on multiple processors. The method includes: the master processing core receives a request message. The request message is used to request processing of a business, and the business includes multiple jobs. The master processing core determines the target processing core for processing the first job based on at least one of the job attributes of the first job, the load information of the master processing core, and the load information of the slave processing core. The first job is one of the multiple jobs. The target processing core includes the master processing core and / or the slave processing core. The job attributes of the first job are used to reflect the processing core that supports processing the first job. The target processing core processes the first job.

[0006] In this application, the main processing core determines the processing core that processes the job based on the load information and job attributes of each processing core. The main processing core schedules the jobs included in the processing core's business, which ensures that the low-power processing core can handle complex business, expands the scope of business that the low-power processing core can handle, reduces the power consumption of the computing device, and extends the battery life of the computing device. The main processing core also schedules the various jobs in the main processing core and the slave processing core to process the business to realize the processing of the business. The main processor and / or the slave processing core are used to schedule the processing business, which saves the time required to process the business and improves the efficiency of processing the business.

[0007] In one possible implementation, the master processing core determines a target processing core for processing the first job based on at least one of the job attributes of the first job, the load information of the master processing core, and the load information of the slave processing core. This includes: if the job attributes of the first job indicate that the processing core supporting processing the first job is a designated processing core, the master processing core determines the designated processing core as the target processing core for the first job. If the job attributes of the first job indicate that the processing core supporting processing the first job is not a designated processing core, the master processing core determines the target processing core for the first job based on the load information of the master processing core and the load information of the slave processing core. In this way, if a job in a service has a designated processing core, the service processing device uses the designated processing core as the target processing core for the job, reducing the number of jobs that need to be processed by processing cores with higher power consumption, thereby reducing power consumption. Furthermore, the service processing device uses a processing core that matches the job requirements to process the job, thereby improving job processing efficiency.

[0008] In another possible embodiment, the slave processing core includes at least one processing core. The master processing core determines the target processing core for the first job based on the load information of the master processing core and the load information of the slave processing core, including: the master processing core detects power-on information of at least one processing core; if the detection result indicates that the at least one processing core includes an unpowered processing core, the master processing core determines the target processing core for the first job based on the unpowered processing core. In this way, because the load of the unpowered processing core is lower than that of the powered processing core, the unpowered processing core can call upon more resources to process the job, thereby reducing the job processing time, shortening the processing core running time, reducing the power consumption of the processing core, and improving the processing efficiency of the job.

[0009] In another possible implementation, if the detection result indicates that the at least one processing core does not include an unpowered processing core, the master processing core detects load information for each of the at least one processing core. If the detection result indicates that the load information for each processing core is greater than or equal to a load threshold, the master processing core is determined as the target processing core for the first job. This avoids assigning jobs to processing cores with limited available resources, reduces the time required for processing cores to process jobs, shortens the processing core's runtime, and reduces power consumption.

[0010] In another possible implementation, if the detection result indicates that at least one processing core includes a processing core whose load information is less than a load threshold, the main processing core determines the target processing core for the first job based on the processing cores whose load information is less than the load threshold. In this way, the service processing device determines the target processing core for the job based on the processing core with the lower load. The target processing core can provide more available resources for the job, shortening the time required for the target processing core to process the job, reducing the target processing core's operating time, and lowering power consumption.

[0011] In another possible embodiment, the main processing core is determined based on the first information or the second information. The first information is used to indicate: the processing core identifier carried in the user instruction. The second information is used to indicate: the capability value of the processing core, and the capability value of the processing core is used to reflect: the processing capability of the processing core to process the job. In this way, the business processing device can specify the processing core to process the job according to the needs of the actual application, which provides a guarantee for using the processing core that matches the job to process the job, and the business processing device determines the main processing core based on the processing capability of the processing core, so that the main processing core can schedule the processing core that matches the job to process the job, thereby reducing the running time of the processing core, reducing power consumption, and improving processing efficiency.

[0012] In a second aspect, the present application provides a service processing device, which includes various units for executing the method in the first aspect or any possible design of the first aspect.

[0013] In a third aspect, the present application provides a processor comprising multiple processing cores, wherein the processor uses the multiple processing cores to cooperate in executing the operation steps of the method in the first aspect or any possible design of the first aspect.

[0014] In a fourth aspect, the present application provides a chip. The chip includes an interface circuit and a control circuit. The interface circuit is used to obtain services to be processed, and the interface circuit and the control circuit cooperate to perform the operating steps of the method described in the first aspect or any possible design of the first aspect.

[0015] In a fifth aspect, the present application provides a computing device. The computing device includes at least one processor and a memory, wherein the memory is configured to store a set of computer instructions; when the processor, acting as an execution device in the first aspect or any possible implementation of the first aspect, executes the set of computer instructions, the operating steps of the method in the first aspect or any possible implementation of the first aspect are performed.

[0016] In a sixth aspect, the present application provides a computer-readable storage medium comprising computer software instructions that, when executed in a computing device, cause the computing device to execute the operating steps of the method described in the first aspect or any possible implementation of the first aspect.

[0017] In a seventh aspect, the present application provides a computer program product. When the computer program product is executed on a computer, the computer device is caused to execute the operation steps of the method described in the first aspect or any possible implementation of the first aspect.

[0018] The beneficial effects of the second to seventh aspects above can be referred to the description of the first aspect or any implementation of the first aspect, and will not be repeated here. Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is an example diagram of a business process;

[0020] Figure 2 This is another example diagram for business processing;

[0021] Figure 3 A schematic diagram of the architecture of a business processing system provided for this application;

[0022] Figure 4 A schematic diagram of the structure of a chip provided in this application;

[0023] Figure 5 A flowchart of a business processing method provided for this application;

[0024] Figure 6 This is an example diagram for determining the main processing core provided by this application;

[0025] Figure 7 A schematic diagram of a process for determining a target processing core provided by this application;

[0026] Figure 8 An example diagram of a processing operation provided for this application;

[0027] Figure 9 This is a timing diagram of an example of a processing operation provided by this application;

[0028] Figure 10 A schematic diagram of the structure of a possible business processing device provided in this application;

[0029] Figure 11 A schematic structural diagram of a chip system provided in this application. DETAILED DESCRIPTION

[0030] With the increasing prevalence of electronic devices, they are required to have stronger service processing capabilities and longer battery life. Electronic devices can use application (AP) processing cores and microprocessor cores to process services. By leveraging the lower power consumption of microprocessor cores compared to AP processing cores, power consumption can be reduced. The following examples illustrate how electronic devices utilize AP processing cores and microprocessor cores to process services. In some cases, the AP processing core can also be referred to as the AP processor.

[0031] Example 1

[0032] Electronic devices process services through event-driven systems (such as Context Hub Runtime Environment, CHRE) AP processing cores and microprocessor cores. Figure 1 This is an example diagram of a business process, such as Figure 1 As shown in (a), the system includes hardware, system layer, development tools and software development kit (SDK). The hardware may include multiple chips with different chip architectures. CHRE can be used Figure 1 The process shown in (b) utilizes these multiple chips to process services, sensors to collect service data, and sensors to write service data into an event queue via interrupts. The EventLoop thread then polls the event queue to obtain service data and transmits the service data to the processing core corresponding to the sensor for processing.

[0033] In the above process, each processing core processes the business data generated by the corresponding sensor, and the processing cores cannot schedule the processing of business data, resulting in low processing efficiency. In addition, complex businesses require processing cores with high processing capabilities and high power consumption, which cannot effectively reduce the power consumption of electronic devices when processing business, thereby extending the battery life of electronic devices.

[0034] Example 2

[0035] Figure 2 This is another example diagram of business processing, such as Figure 2 As shown, by adding a sensor hub between the sensor and the processor, when the sensor data (or business data) stored in the sensor hub meets the requirements, the electronic device uses a receiving unit to receive the sensor data. The electronic device uses one of the multiple processing cores included in the processor to process the business data. In this process, the processing of business data cannot be scheduled between the various processing cores, the processing efficiency is low, and complex businesses require processing cores with high processing capabilities and high power consumption to process, which cannot effectively reduce the power consumption of the electronic device when processing the business, thereby extending the battery life of the electronic device.

[0036] Based on this, the present application provides a service processing method that can be performed by a service processing device. The service processing device includes a master processing core and a slave processing core. The master processing core is used to schedule the master and slave processing cores to process services. The master processing core receives a request message requesting the processing of a service, which includes multiple jobs. The master processing core determines a target processing core to process the multiple jobs based on the load information of the master processing core, the load information of the slave processing cores, and the job attributes. In this way, the master processing core determines the processing core to process the job based on the load information and job attributes of each processing core. The master processing core schedules the processing cores to process the jobs included in the service, ensuring that low-power processing cores can handle complex services, expanding the range of services that low-power processing cores can handle, reducing the power consumption of computing devices, and extending the battery life of computing devices. The master processing core schedules the master and slave processing cores to process each job in the service to process the service. Using the master processor and / or slave processing cores to schedule the service processing reduces the time required to process the service and improves the efficiency of service processing scheduling.

[0037] The business processing method provided by this application is exemplarily described below with reference to the accompanying drawings.

[0038] Figure 3 This is a schematic diagram of the architecture of a business processing system provided in this application. The business processing system includes a computing device 310. Computing device 310 receives business requests to be processed from a user and processes the requests using multiple processing cores to obtain processing results. Computing device 310 then outputs the processing results to the user.

[0039] The computing device 310 may include multiple processing cores. The multiple processing cores may be deployed on one processor or on multiple processors. It is understandable that when multiple processing cores are deployed on multiple processors, one or more processing cores may be deployed on one processor. The processing core may refer to an AP processing core, a microcontroller unit (MCU), or a dedicated accelerator, such as a sensor hub contexthub, an audio digital signal processor (audio-dsp), and an image signal processor (Image Signal Processing, ISP). In some possible examples, the AP processing core may also be referred to as an AP processor, and the MCU may also be referred to as a microprocessor core.

[0040] Figure 3 An example diagram of a computing device when multiple processing cores are deployed on a processor is given in Figure 3As shown, computing device 310 includes an input / output (I / O) interface 314, a processor 311, and a memory 312. I / O interface 314 is used to communicate with devices external to computing device 310. For example, computing device 310 receives user input of business to be processed (or input data) through I / O interface 314. After processing the input data, computing device 310 sends the processing results to the user through I / O interface 314.

[0041] The processor 311 is the computing core and control core of the computing device 310. It may include: a central processing unit (CPU), a specific integrated circuit, other general-purpose processors, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. In actual applications, the computing device 310 may also include multiple processors. The processor 311 may include one or more processing cores. An operating system and other software programs are installed in the processor 311, so that the processor 311 can access the memory 312 and various peripheral component interconnect express (PCIe) devices.

[0042] The processor 311 is connected to the memory 312 via a double data rate (DDR) bus or other type of bus. The memory 312 is the main memory of the computing device 310. Memory 312 is typically used to store various running software in the operating system, receive user input, and output results to be sent to the user in the future. To improve the access speed of the processor 311, the memory 312 needs to have a fast access speed. In traditional computer devices, dynamic random access memory (DRAM) is commonly used as the memory 312. In addition to DRAM, the memory 312 can also be other random access memories, such as static random access memory (SRAM). In addition, the memory 312 can also be read-only memory (ROM). For example, the read-only memory can be programmable read-only memory (PROM) or erasable programmable read-only memory (EPROM). This embodiment does not limit the number and type of memory 312.

[0043] Optionally, in order to store data persistently, the business processing system is further provided with a data storage system 313, which may be located outside the computing device 310 (e.g., Figure 3 310 ), exchanges data with the computing device 310 via the network. Optionally, the data storage system 313 may also be located inside the host, such as the data storage system 313 exchanging data with the processor 311 via the bus 315. In this case, the data storage system 313 is a hard disk.

[0044] Optionally, the business processing system may further include a client device 320. A user sends business to be processed to the computing device 310 via the client device 320, and the computing device 310 sends the processing results to the user via the client device 320. The client device 320 is a terminal device, including but not limited to a personal computer, server, mobile phone, tablet computer, or smart car.

[0045] For example, Figure 3 The processor 311 in the embodiment may be implemented by a chip, such as Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of a chip provided in the present application. For example, the chip 400 includes a core 401 , a CPU 402 , a system buffer 403 and a DDR 405 .

[0046] CPU 402 is used to accept business processing tasks and call core 401 to execute them. If chip 400 has multiple cores 401, CPU 402 is also responsible for scheduling tasks. For example, CPU 402 can be implemented by an ARM processor, which is compact, low-power, uses a 32-bit reduced instruction set, and has simple and flexible addressing. Of course, in some embodiments, CPU 402 can also be implemented by other processors.

[0047] Core 401 is used to provide the computing power required for business processing tasks. In an optional scenario, core 401 includes a load / store unit (LSU), a cube computing unit, a scalar computing unit, a vector computing unit and a buffer. Among them, the LSU is used to load the business to be processed and store the processing results. It can also be used for reading and writing internal data between different buffers in the core, and to complete some format conversion operations. The cube computing unit is used to provide the core computing power for matrix multiplication. The scalar computing unit is a single instruction single data (SISD) processor. This type of processor only processes one piece of data (usually an integer or floating point number) at the same time. The vector computing unit, also known as an array processor, is a processor that can directly operate a set of arrays or vectors for calculation. The number of buffers may be one or more. For example, the buffer mainly refers to the level 1 buffer (L1 buffer). The buffer is used to temporarily store some data that the core 401 needs to use repeatedly to reduce reading and writing from the bus. In addition, the implementation of certain data format conversion functions also requires that the source data is located in the buffer. In this embodiment, since the buffer is located in the core, the distance between the cube computing unit in the core and the storage area where the data is located is shortened, reducing the cube computing unit's access to DDR 405, thereby reducing data access latency and core data processing latency.

[0048] The system buffer 403 mainly refers to a level 2 buffer (L1 buffer or L2 cache), which is used to temporarily store input data, intermediate results or final results passing through the chip.

[0049] DDR 405 is an off-chip memory that can be replaced with high bandwidth memory (HBM) or other off-chip memory. DDR 405 is located between the chip and the external memory, overcoming the access speed limitations of shared memory reads and writes for computing resources.

[0050] The input / output (I / O) device 404 included in chip 400 refers to the hardware used for data transmission and can also be understood as a device that interfaces with an I / O interface. Common I / O devices include network cards, printers, keyboards, and mice. All external storage devices, such as hard drives, floppy disks, and optical disks, can also serve as I / O devices.

[0051] The core 401, the CPU 402, the system buffer 403, the I / O device 404, and the DDR 405 are connected via a bus. The bus may include a path for transmitting information between the above components (such as the CPU 402 and the system buffer 403). In addition to the data bus, the bus may also include a power bus, a control bus, and a status signal bus. However, for the sake of clarity, the bus may be a PCIe bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. For example, the core 401 can access these I / O devices 404 via the PCIe bus. The core 401 is connected to the system buffer 403 via the DDR bus. Here, different system buffers 403 may use different data buses to communicate with the core 401. Therefore, the DDR bus may also be replaced by other types of data buses. The embodiment of the present application does not limit the bus type.

[0052] For example, after CPU 402 loads a pending service into DDR 405, the LSU in core 401 reads (loads) the pending service from DDR 405, processes it, and obtains a processing result. Once the processing result is obtained, the LSU stores (stores) the processing result into DDR 405. The network interface card then sends the processing result to client device 320 or to data storage system 313 for persistent storage.

[0053] It should be understood that the structure illustrated in this embodiment does not constitute a specific limitation on the computing device. In other embodiments, the computing device and chip may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0054] The following combination Figure 3and Figure 4 The content shown provides a detailed description of the business processing method provided by this application.

[0055] Figure 5 This is a flow chart of a business processing method provided by the present application, which can be executed by a business processing device, processor or chip. The business processing device, processor or chip may include multiple processing cores. The multiple processing cores included in the business processing device or chip can be deployed on one processor or on multiple processors. The multiple processing cores include: a master processing core and a slave processing core, and the master processing core is used to schedule the master processing core and the slave processing core to process business. The business processing device may be Figure 3 The computing device 310 shown. In some optional examples, the business processing method can also be executed by other computing devices including multiple processing cores. For hardware implementation of other computing devices, please refer to the aforementioned Figure 3 The hardware implementation of the processor or chip can refer to the aforementioned Figure 4 The description is not repeated here.

[0056] The following uses a computing device including multiple processing cores to perform a business processing method as an example to illustrate the business processing method provided by this application. Figure 5 As shown, the service processing method provided in this embodiment includes the following S510 to S530.

[0057] S510: The main processing core receives a request message.

[0058] The request message is used to request the processing of a service, which includes multiple operations. Services may include but are not limited to message notification display, device connection management that supports the BT (Bit Torrent) protocol, etc. Devices that support the BT protocol may be referred to as BT devices, which may include but are not limited to mobile phones, computers, headphones, mice, printers, etc. In this case, the processing of the service may refer to displaying message notifications, managing BT devices, etc.

[0059] In one possible scenario, before executing S510 using the master processing core, the service processing device may determine the master processing core and the slave processing core from among multiple processing cores in various ways. For example, the service processing device determines the master processing core and the slave processing core by executing S510A.

[0060] S510A, the service processing device determines a main processing core according to the first information or the second information.

[0061] Both the master processing core and the slave processing core may refer to one or more processing cores. When the master processing core refers to multiple processing cores, the multiple processing cores have the same core architecture. When the slave processing core refers to multiple processing cores, the multiple processing cores may have the same core architecture or different core architectures. The core architecture may include, but is not limited to, ARM64, Cortex-A, Cortex-M, Cortex-R, RISC-V, DSP, and other architectures.

[0062] Among them, the first information is used to indicate: the processing core identifier carried in the user instruction. The second information is used to indicate: the capability value of the processing core, and the capability value of the processing core is used to reflect: the processing capability of the processing core to process the job. When the main processing core is determined according to the first information, it can also be said that the business processing device determines the main processing core according to preset information or static preset. When the main processing core is determined according to the second information, it can also be said that the business processing device dynamically determines the main processing core during the execution of the business processing method. The following describes the process of the business processing device determining the main processing core according to the first information or the second information according to different situations. In some possible examples, the core architecture of the processing core can also be called the chip architecture.

[0063] Scenario 1: The service processing device determines the main processing core according to the first information.

[0064] The processing core identifier carried in the user instruction indicated by the first information may be a processing core name, a processing core ID, etc. The first information may be preset or transmitted by the user to the service processing device during the process of the service processing device executing the service processing method. This application does not limit the timing of the service processing device obtaining the first information.

[0065] In this case, the service processing device selects a processing core that matches the processing core identifier carried in the first information from multiple processing cores based on the processing core identifier, and determines the matching processing core as the main processing core.

[0066] In some possible scenarios, the service processing device may also determine the secondary processing core according to preset information. Similarly, the service processing device may determine the secondary processing core in the manner described in scenario 1 above.

[0067] Scenario 2: The service processing device determines the main processing core according to the second information.

[0068] The business processing device can use the following ① and ② to determine the main processing core.

[0069] ① The service processing device obtains the capability value of each processing core among the multiple processing cores.

[0070] The service processing device can obtain the capability value of the processing core based on parameters such as the core architecture of the processing core and the historical CPU utilization (CPU-percentage, CPUP). This process may include the following steps 1 to 3.

[0071] Step 1: The service processing device allocates a shared storage space. Each processing core can read and write data from the shared storage space.

[0072] In step 2, each processing core writes its own parameters into the shared storage space. The parameters may include, but are not limited to, the core architecture of the processing core, historical CPU utilization, etc.

[0073] In step 3, the service processing device uses the first processing core to calculate the capability value of each processing core based on the parameters of each processing core.

[0074] The first processing core may refer to a preset processing core or a processing core that satisfies a first preset condition. The first preset condition may refer to the processing core that last writes its own parameters into the storage space. In this case, the first processing core may refer to the processing core that last writes its own parameters into the storage space among the multiple processing cores.

[0075] Before the first processing core calculates the processing core's capability value based on the processing core's parameters, the first processing core determines whether the processing core is designated as a slave processing core by preset information. If the processing core is designated as a slave processing core by preset information, the first processing core assigns the processing core's capability value to 0. If the processing core is not designated as a slave processing core by preset information, the first processing core may use numerical values ​​to represent each parameter and perform a weighted calculation on each parameter to obtain the processing core's capability value. Depending on the needs of the actual application, the first processing core may assign different weights to each parameter.

[0076] ② The business processing device determines the main processing core based on the capability values ​​of each processing core.

[0077] The service processing device selects a processing core that meets a second preset condition from the multiple processing cores to obtain a primary processing core. The second preset condition may include, but is not limited to, the following: the highest capability value, the capability value being a certain set value, the capability value being greater than a certain set value, the capability value being within a certain set range, and the like. For example, the service processing device selects the processing core with the highest capability value from the multiple processing cores as the primary processing core.

[0078] After the service processing device determines the master processing core, it can also write information about the master processing core and the slave processing cores into a shared storage space, and each processing core can read the master processing core information and the slave processing core information from the shared storage space. The master processing core information can include the master processing core's identifier, name, etc., and the slave processing core information can include the slave processing core's identifier, name, etc.

[0079] The following is an example of a service processing device determining a main processing core: Figure 6 This is an example diagram of determining the main processing core provided by this application, such as Figure 6 As shown, the business processing device includes processing core 1 (core1), processing core 2 (core2) and processing core 3 (core3). And the business processing device determines core3 as a slave processing core according to preset information. If the last processing core to write its own parameters into the shared space is core2, in this case, core2 calculates the capacity values ​​of core1 and core2 based on the parameters of core1 and core2. If the second preset condition is to determine that the processing core with the highest capacity value is the master processing core, and the capacity value of core1 is greater than the capacity value of core2. The business processing device determines core1 as the master processing core.

[0080] The above description uses the example of a service processing device determining the capacity value of a primary processing core based on the core architecture and historical CPUP utilization of the processing core to illustrate the process of determining the capacity value of the processing core. In some possible examples, the service processing device may also use the method described above to determine the primary processing core based on more or fewer parameters, which will not be detailed here.

[0081] S520 : The master processing core determines a target processing core for processing the first job based on at least one of a job attribute of the first job, load information of the master processing core, and load information of the slave processing cores.

[0082] The job attribute of the first job is used to reflect the processing core that supports processing the first job.

[0083] Figure 7 A flowchart of determining a target processing core provided by this application is shown as follows: Figure 7 As shown, the process of the master processing core determining the target processing core for processing the first job based on at least one of the job attributes of the first job, the load information of the master processing core, and the load information of the slave processing core may include the following ① to ③.

[0084] ① The main processing core determines whether there is a designated processing core for the first job based on the job attributes of the first job.

[0085] In some possible examples, the main processing core can obtain the job attributes of the first job from a designated field, and determine whether a designated processing core exists based on the job attributes of the first job. For example, if the job attribute of the first job is content 1, it indicates that the first job has a designated processing core, and if the job attribute of job 1 is content 2, it indicates that the first job has no designated processing core. And when the first job specifies a processing core, the main processing core obtains the designated processing core information (such as the designated processing core name, identifier, etc.). Depending on the needs of the actual application, the designated processing core can be the main processing core or the slave processing core, and this application does not limit this.

[0086] ② If the job attribute of the first job indicates that the processing core supporting processing of the first job is a designated processing core, the master processing core determines the designated processing core as the target processing core for the first job.

[0087] In this scenario, the main processing core determines the designated processing core as the target processing core for the first job and assigns the first job to the designated processing core. The designated processing core executes the first job, obtains an execution result, and sends a completion notification message to the main processing core. After receiving the notification message from the designated processing core, the main processing core obtains the execution result from the designated processing core. In this scenario, the main processing core can determine the target processing core for the first job based on the job attributes of the first job.

[0088] ③ If the job attributes of the first job indicate that the processing core supporting processing the first job is not the designated processing core, the master processing core determines the target processing core for the first job based on the load information of the master processing core and the load information of the slave processing core.

[0089] In one possible scenario, the slave processing core includes at least one processing core. The master processing core may determine a target processing core for the first job based on load information of the master processing core and load information of the slave processing core. The process includes the following steps 1 and 2.

[0090] In step 1, the master processing core detects power-on information of each processing core in at least one processing core included in the slave processing core.

[0091] The master processing core queries the power management unit for power-on information of at least one processing core included in the slave processing cores, and detects whether each processing core is powered on based on the power-on information of each processing core. The power-on information indicates the power-on status of the processing core. The power-on status may be powered on or powered off. If the power-on information of the processing core indicates that the power-on status is powered on, the processing core is powered on. If the power-on information of the processing core indicates that the power-on status is powered off, the processing core is not powered on.

[0092] In step 2, the main processing core determines the target processing core for the first operation based on the detection result.

[0093] Depending on whether the at least one processing core indicated by the detection result includes an unpowered processing core, the main processing core determines the target processing core for the first job in different ways, which are described below in different situations.

[0094] In scenario A, if the detection result indicates that at least one processing core includes an unpowered processing core, the master processing core determines the target processing core for the first job based on the unpowered processing core. In this scenario, the master processing core can determine the target processing core for the first job based on the load information of the slave processing cores.

[0095] The method for determining the target processing core varies depending on the number of unpowered processing cores. Two possible examples are given below.

[0096] In Example 1, one of the at least one processing cores is not powered on.

[0097] In this case, the main processing core directly determines the unpowered processing core as the target processing core for the first operation.

[0098] Example 2: There are multiple processing cores in at least one processing core that are not powered on.

[0099] In this case, the main processing core may determine the target processing core for the first operation from the multiple unpowered processing cores in various ways.

[0100] For example, the main processing core randomly selects a processing core from the multiple unpowered processing cores and uses the processing core as the target processing core for the first operation.

[0101] In another example, the main processing core selects a processing core from the multiple unpowered processing cores that meets a third preset condition, and uses the processing core as the target processing core for the first operation. The third preset condition may be one or more of the processing core's historical CPU usage, core architecture, and the like. For example, the main processing core selects a processing core from the multiple unpowered processing cores whose historical CPU usage is lower than a set threshold as the target processing core for the first operation. In another example, the main processing core selects a processing core from the multiple unpowered processing cores whose core architecture is a specified architecture as the target processing core for the first operation.

[0102] The above gives two possible ways for the main processing core to determine the target processing core for the first operation from multiple unpowered processing cores. In some possible situations, the main processing core can also use other methods to determine the target processing core for the first operation, such as using the historical usage rate of cpup and the core architecture to simultaneously determine the target processing core for the first operation. This application is not limited to this.

[0103] In scenario B, if the detection result indicates that the at least one processing core does not include an unpowered processing core, the master processing core detects the load information of each of the at least one processing core. The method for determining the target processing core varies depending on the load information of each of the at least one processing core, as described below for each scenario.

[0104] In case a, if the detection result indicates that the load information of each processing core is greater than or equal to the load threshold, the main processing core is determined as the target processing core of the first job.

[0105] The load information of the processing core may refer to the load of the processing core. The main processing core may obtain the load of the processing core based on the CPU utilization of the processing core. For example, when the CPU utilization of the processing core is 92%, the main processing core obtains the load of the processing core as 92%.

[0106] The load threshold can reflect the load that the processing core can bear, and when the load borne by the processing core is less than the load threshold, the processing core can use the required processing capacity to handle the load. Different load thresholds can be set according to the needs of the actual application. For example, the load threshold can be set to 95%. In this case, the master processing core uses the method described above to obtain the load of each processing core in the at least one processing core included in the slave processing core. If the load of each processing core is greater than 95%, the master processing core is the target processing core for the first job.

[0107] In case b, if the detection result indicates that at least one processing core includes a processing core whose load information is less than the load threshold, the main processing core determines the target processing core for the first operation based on the processing cores whose load information is less than the load threshold.

[0108] Depending on the number of processing cores whose load information is less than the load threshold, the main processing core determines the target processing core for the first job in different ways, which are described below in different situations.

[0109] In case b1, the at least one processing core includes a processing core whose load information is less than a load threshold.

[0110] In this case, the main processing core determines the processing core whose load information is less than the load threshold as the target processing core for the first job.

[0111] In case b2, the at least one processing core includes a plurality of processing cores whose load information is smaller than a load threshold.

[0112] The master processing core selects a processing core that meets a fourth preset condition from among the multiple processing cores whose load information is less than a load threshold, and uses the processing core as the target processing core for the first operation. The fourth preset condition may include, but is not limited to, one or more of: the processing core with the lowest load, the core architecture, and the like.

[0113] In the case where the fourth preset condition includes the processing core with the lowest load and multiple ones in the core architecture, a priority can also be set for each condition, and the main processing core can select a processing core from the multiple processing cores in order of priority from high to low as the target processing core for the first job.

[0114] S530: The service processing device uses the target processing core to process the first job.

[0115] The target processing core may use a thread to process the first job. For example, the target processing core may use a worker thread to process the first job and obtain a processing result. After obtaining the processing result of the first job, the target processing core may send a notification indicating the completion of execution of the first job to the main processing core, and the main processing core may obtain the processing result of the first job from the target processing core.

[0116] In some possible scenarios, the main processing core may use threads, queues, etc. to execute the above process to process jobs. Exemplarily, the main processing core uses business threads, all scheduling threads, job scheduling queues, and worker threads to schedule and process jobs. The process is specifically as follows: the business thread receives the job and submits the job to the global scheduling thread. The global scheduling thread receives the job and submits the job to the job scheduling queue. The job scheduling queue determines the target processing core for processing the job based on the job attributes and the processing core load information, and distributes the job to the target processing core. The target processing core receives the job and uses the worker thread to execute the job to obtain the processing result. After obtaining the processing result, the target processing core sends a notification to the global scheduling thread to indicate that the job has been executed. After receiving the notification sent by the target processing core, the global scheduling thread sends a notification to the business thread. The business thread receives the notification and obtains the processing result from the target processing core.

[0117] Figure 8 An example diagram of a processing operation provided for this application, such as Figure 8 As shown, the business processing device includes a main processing core and slave processing cores 1 to i. The main processing core runs a business thread, a global scheduling thread, and a job scheduling queue. The job scheduling queue may include scheduling queue 1 and scheduling queue 2. Scheduling queue 1 is used to store jobs designated for execution by the main processing core, and scheduling queue 2 is used to store jobs that can be executed by the main processing core or the slave processing core. Slave processing cores 1 and 2 may be processing cores with a first core architecture, and slave processing cores 3 to i may be processing cores with a second core architecture. The first and second core architectures may be core architectures such as RISC-V and ARM. For more information about the core architectures, please refer to the relevant description above and will not be repeated here. The main processing core runs worker thread 0 for executing jobs, slave processing core 1 runs worker thread 1 for executing jobs, slave processing core 2 runs worker thread 2 for executing jobs, and slave processing core i runs worker threads m and n for executing jobs. In some possible scenarios, worker threads may also be referred to as workers.

[0118] The main processing core's service thread receives jobs and submits them to the global scheduling thread. The global scheduling thread checks the job's attributes. Depending on the job's attributes, the main processing core handles the job differently, as described below.

[0119] In scenario 11, when the detection result indicates that the job has a designated processing core and the designated processing core is a primary processing core, all scheduling threads add the job to scheduling queue 1.

[0120] Depending on the number of processing cores included in the main processing core, the main processing core processes jobs in different ways, which are described below respectively.

[0121] In the case where the main processing core includes one processing core, the scheduling queue 1 uses the working thread in the processing core to process the job and obtain the processing result.

[0122] If the main processing core includes multiple processing cores, scheduling queue 1 determines the target processing core for the job from among the multiple processing cores and uses the worker thread of the target processing core to process the job and obtain a processing result. Scheduling queue 1 may determine the target processing core for the job based on load information of each of the multiple processing cores. For example, scheduling queue 1 uses worker thread 0 of the main processing core to process job 0 and obtain a processing result.

[0123] In case 12, when the detection result indicates that the job has a designated processing core and the designated processing core is a slave processing core, all scheduling threads add the job to scheduling queue 2.

[0124] In this case, scheduling queue 2 distributes the job to the designated slave processing core. The designated slave processing core executes the job to obtain the processing result, and sends a notification to the global scheduling thread indicating that the job has been completed. The global scheduling thread receives the notification and sends the notification to the business thread. The business thread receives the notification and obtains the processing result from the slave processing core. For example, scheduling queue 2 distributes job 1 to slave processing core 1, and slave processing core 1 uses worker thread 1 to execute job 1 to obtain the processing result. Slave processing core 1 sends notification 1 to the global scheduling thread indicating that the job has been completed. The global scheduling thread receives notification 1 and sends notification 1 to the business thread. The business thread receives notification 1 and obtains the processing result from slave processing core 1.

[0125] In Scenario 13, if the detection result indicates that the job does not have a designated processing core, the global scheduling thread places the job in scheduling queue 2. Scheduling queue 2 then determines the target processing core for processing the job based on the load information of the slave processing core. If the target processing core determined by scheduling queue 2 is the master processing core, scheduling queue 2 obtains the processing result of the job using the method described in Scenario 11. If the target processing core determined by scheduling queue 2 is a slave processing core, scheduling queue 2 obtains the processing result of the job using the method described in Scenario 12. For example, scheduling queue 2 distributes job 2 to slave processing core i, and slave processing core i uses worker thread n to execute job 2 and obtain the processing result.

[0126] Figure 8The process of processing services by a service processing device is described using an example in which the service processing device includes one master processing core and three slave processing cores. Similarly, if the service processing device has one or more of the following: more master processing cores, more slave processing cores, or fewer slave processing cores, the service processing device can still use the method described above to process services, and detailed description thereof is omitted here.

[0127] Figure 9 This is a timing diagram of a processing operation provided by this application, such as Figure 9 As shown, the service processing device includes a master processing core and two slave processing cores (e.g., slave processing core 1 and slave processing core 2). Services include jobs 1 and 2. In some possible scenarios, the master processing core can also be called a master, the slave processing cores can also be called slaves, and the jobs can be called jobs. In this scenario, slave processing cores 1 and 2 can be called slave 1 and slave 2, respectively, and jobs 1 and 2 can be called job 1 and job 2, respectively.

[0128] (1) The master determines the target processing core for job 1.

[0129] The master checks the job attributes of job1. If the check indicates that job1 has a designated processing core, and that the designated processing core is slave1, the master obtains the power status of slave1 from the power management unit. If slave1 is powered off, the master processing core sends a command to power on slave1 and distributes job1 to slave1. Slave1 executes job1, obtains the processing result, and sends a completion notification to the master. The master obtains the processing result of job1 from slave1.

[0130] (2) The master determines the target processing core for job2.

[0131] The master detects the job attributes of job2. If the detection result indicates that the designated processing core for job2 does not exist, the master obtains the power-on status of slave1 and slave2 from the power management unit. If both slave1 and slave2 are powered on, the master processing core obtains the load information of slave1 and slave2, and distributes job2 to slave2 based on the load information of slave1 and slave2. Similarly, the master can obtain the processing result of job2 using the method described in (1) above, which will not be repeated here.

[0132] Figure 9This example illustrates the timing of a business processing device processing two jobs, using a service processing device comprising one master processing core and two slave processing cores. Similarly, when a service processing device comprises one or more of the following: more master processing cores, more slave processing cores, or fewer slave processing cores, the method described above can also be used to obtain a timing diagram of a business processing device processing a job. This description is omitted here.

[0133] In this application, the main processing core determines the processing core that processes the job based on the load information and job attributes of each processing core. The main processing core schedules the jobs included in the processing core's business, which provides a guarantee for low-power processing cores to handle complex businesses, expands the scope of businesses that low-power processing cores can handle, reduces the power consumption of computing devices, and extends the battery life of computing devices. The main processing core also schedules the various jobs in the main processing core and slave processing core processing business to achieve the processing of the business. The main processor and / or slave processing core are used to schedule the processing business, which saves the time required to process the business and improves the efficiency of the business processing scheduling.

[0134] It is understood that in order to implement the functions in the above embodiments, the computing device includes hardware structures and / or software modules corresponding to the execution of each function. It should be readily apparent to those skilled in the art that, in combination with the units and method steps of each example described in the embodiments disclosed in this application, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in hardware or in a manner driven by computer software depends on the specific application scenario and design constraints of the technical solution.

[0135] Combined with the above Figures 1 to 8 , describes in detail the service processing method provided by this embodiment, and will now be combined with Figure 9 , describes the business processing device provided according to this embodiment.

[0136] Figure 10 This is a schematic diagram of the structure of a possible business processing device provided by this application. The business processing device can be used to implement the functions of the computing device in the above method embodiment, and thus can also achieve the beneficial effects of the above method embodiment. In this embodiment, the business processing device can be as follows Figure 4 The chip shown may also be a module used for service processing. In some possible situations, the service processing device may also be called a service processing apparatus.

[0137] like Figure 10 As shown, the service processing device 1000 includes a first processing unit 1010 and a second processing unit 1020. The first processing unit 1010 performs the function of the master processing core, and the second processing unit 1020 performs the function of the slave processing core.

[0138] Specifically, the first processing unit 1010 is configured to receive a request message. The request message is used to request processing of a business, where the business includes multiple jobs. The first processing unit 1010 is further configured to determine a target processing unit for processing the first job based on at least one of the job attributes of the first job, load information of the first processing unit 1010, and load information of the second processing unit 1020. The first job is one of the multiple jobs. The job attributes are used to reflect the processing unit that supports processing the job. The target processing unit processes the first job.

[0139] In one possible scenario, if the job attributes of the first job indicate that the processing unit supporting processing of the first job is a designated processing unit, the first processing unit 1010 is specifically configured to determine the designated processing unit as the target processing unit for the first job. If the job attributes of the first job indicate that the processing unit supporting processing of the first job is not the designated processing unit, the first processing unit 1010 is specifically configured to determine the target processing unit for the first job based on load information of the first processing unit 1010 and load information of the second processing unit 1020.

[0140] In one possible scenario, the second processing unit 1020 includes at least one processing unit. The first processing unit 1010 is specifically configured to detect power-on information of the at least one processing unit. If the detection result indicates that the at least one processing unit includes an unpowered processing unit, the first processing unit 1010 is specifically configured to determine a target processing unit for the first operation based on the unpowered processing unit.

[0141] In one possible scenario, if the detection result indicates that the at least one processing unit does not include a powered-off processing unit, the first processing unit 1010 is specifically configured to detect load information of each processing unit in the at least one processing unit. If the detection result indicates that the load information of each processing unit is greater than or equal to a load threshold, the first processing unit 1010 is specifically configured to determine the first processing unit 1010 as a target processing unit for the first job.

[0142] In one possible scenario, if the detection result indicates that at least one processing unit includes a processing unit whose load information is less than the load threshold, the first processing unit 1010 is specifically used to determine the target processing unit of the first operation based on the processing unit whose load information is less than the load threshold.

[0143] In one possible scenario, service processing device 1000 further includes a third processing unit 1030. Third processing unit 1030 is configured to determine first processing unit 1010 based on the first information or the second information. The first information indicates a processing unit identifier carried in a user instruction. The second information indicates a processing unit capability value, which reflects the processing unit's ability to process a job.

[0144] It should be understood that the business processing device 1000 of the embodiment of the present application can be implemented by a DPU. The business processing device 1000 according to the embodiment of the present application can correspond to executing the method described in the embodiment of the present application, and the above-mentioned and other operations and / or functions of each unit in the business processing device 1000 are respectively for implementing the corresponding processes of each method above. For more relevant content about the functions implemented by the first processing unit 1010, the second processing unit 1020 and the third processing unit 1030, please refer to the relevant description in the above method embodiment, which will not be repeated here.

[0145] The service processing device 1000 of the embodiment of the present application can be implemented as a software module. The service processing device 1000 according to the embodiment of the present application can be used to execute the method described in the embodiment of the present application. The above and other operations and / or functions of each module in the service processing device 1000 are respectively for implementing the method flow shown in the above figures. For the sake of brevity, they are not further described here.

[0146] It is worth noting that if the business processing device 1000 is implemented through a software module, for example, the software module can be provided to users through a cloud service subscription model, and users can choose different subscription levels according to their needs; for example, the software module can also provide enterprise-level customized services with professional domain customization, interface personalization and extended functions according to the needs of users or enterprises.

[0147] The service processing device 1000 of the embodiment of the present application can also be implemented by hardware. For example, the hardware can refer to a computing device, a processor, a chip, etc. For the specific implementation of the computing device, please refer to Figure 3 For details about the implementation of processors and chips, please refer to Figure 4 The description is not repeated here.

[0148] The method steps in this embodiment can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium can be located in an ASIC. In addition, the ASIC can be located in a computing device. Of course, the processor and storage medium can also exist as discrete components in a network device or a terminal device.

[0149] Figure 11 A schematic diagram of the structure of a chip system provided in this application is shown as follows: Figure 11 As shown in (a), the chip system 1100 includes multiple processing cores, such as processing core 1 to processing core i. The multiple processing cores can be deployed on one chip, which is not limited in this application. The multiple processing cores can communicate with each other using methods such as inter-processor communication (IPC). An OS can be run on each of the multiple processing cores, and the OSs running on the multiple processing cores can be the same or different, which is not limited in this application. An application can also be deployed on the OS of the processing core. The application can be used to sense the load information of the processing core, determine the master processing core and the slave processing core, manage jobs, schedule jobs, execute jobs, etc.

[0150] Figure 11 The chip system 1100 shown in (a) can be applied to various scenarios, such as system on chip (Soc). Figure 11 (b) shows an example diagram of the chip system 1100 being applied to the Soc of the terminal device, as shown in FIG. Figure 11As shown in (b), the Soc of the terminal includes hardware and software. The hardware may include multiple processing cores (such as processing core 1 to processing core i) and a bus. Bus communication can be used between processing core 1 to processing core i. The bus can support IPC communication. In this case, IPC communication can be used between each processing core. Other communication methods can also be used between each processing core, which is not limited in this application. The software may include an OS and an application running on the processing core. The OS running on each processing core may be the same or different. The operating system may be Android™, firmware, etc., which is not pre-defined in this application. The relevant content of the terminal device will not be repeated here.

[0151] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the process or function described in the embodiments of the present application is performed in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device or other programmable device. The computer program or instruction can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer program or instruction can be transmitted from one website, computer, server or data center to another website, computer, server or data center via wired or wireless means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, a hard disk, or a tape; it can also be an optical medium, such as a digital video disc (DVD); it can also be a semiconductor medium, such as a solid state drive (SSD).

[0152] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present application, and such modifications or substitutions should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A business processing method, characterized in that: The method is performed by a processing device, the processing device comprising: a master processing core and a slave processing core, the master processing core being used to schedule the master processing core and the slave processing core to process services, the method comprising: The main processing core receives a request message, where the request message is used to request processing of a service, where the service includes multiple jobs; determining, by the master processing core, a target processing core for processing the first job based on at least one of a job attribute of the first job, load information of the master processing core, and load information of the slave processing core, wherein the first job is one of the plurality of jobs, the target processing core includes a master processing core and / or a slave processing core, and the job attribute of the first job is used to reflect a processing core that supports processing the first job; The target processing core is used to process the first job.

2. The method according to claim 1, characterized in that The master processing core determines, based on at least one of a job attribute of the first job, load information of the master processing core, and load information of the slave processing core, a target processing core for processing the first job, including: If the job attribute of the first job indicates that the processing core supporting processing of the first job is a designated processing core, the main processing core determines the designated processing core as a target processing core for the first job; If the job attribute of the first job indicates that the processing core supporting processing of the first job is not the designated processing core, the master processing core determines the target processing core for the first job based on the load information of the master processing core and the load information of the slave processing core.

3. The method according to claim 2, characterized in that The slave processing core includes at least one processing core, The master processing core determines a target processing core for the first job according to the load information of the master processing core and the load information of the slave processing core, including: detecting power-on information of the at least one processing core; If the detection result indicates that the at least one processing core includes a non-powered processing core, a target processing core for the first operation is determined based on the non-powered processing core.

4. The method according to claim 3, characterized in that The method further comprises: If the detection result indicates that the at least one processing core does not include a non-powered processing core, detecting load information of each processing core in the at least one processing core; If the detection result indicates that the load information of each processing core is greater than or equal to a load threshold, the main processing core is determined as a target processing core for the first operation.

5. The method according to claim 4, characterized in that The method further comprises: If the detection result indicates that the at least one processing core includes a processing core whose load information is less than a load threshold, a target processing core for the first operation is determined based on the processing core whose load information is less than the load threshold.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: determining the main processing core according to the first information or the second information; The first information is used to indicate the processing core identifier carried in the user instruction; The second information is used to indicate a capability value of the processing core, and the capability value of the processing core is used to reflect a processing capability of the processing core for processing jobs.

7. A business processing device, characterized in that: The device comprises: a first processing unit and a second processing unit, The first processing unit is configured to: receive a request message; the request message is used to request processing of a service, wherein the service includes a plurality of jobs; The first processing unit is further used to determine a target processing unit for processing the first job based on at least one of the job attributes of the first job, the load information of the first processing unit, and the load information of the second processing unit; the first job is one of the multiple jobs, the target processing unit includes the first processing unit and / or the second processing unit, and the job attributes of the first job are used to reflect the processing unit that supports processing the first job.

8. The device according to claim 7, characterized in that If the job attribute of the first job indicates that the processing unit supporting processing of the first job is a designated processing unit, the first processing unit is specifically configured to: determine the designated processing unit as a target processing unit for the first job; If the job attribute of the first job indicates that the processing unit supporting processing the job is not the designated processing unit, the first processing unit is specifically used to: determine the target processing unit of the first job based on the load information of the first processing unit and the load information of the second processing unit.

9. The device according to claim 8, characterized in that The second processing unit includes at least one processing unit, The first processing unit is specifically configured to: detect power-on information of the at least one processing unit; If the detection result indicates that the at least one processing unit includes a non-powered processing unit, the first processing unit is specifically configured to determine a target processing unit for the first operation based on the non-powered processing unit.

10. The device according to claim 9, characterized in that If the detection result indicates that the at least one processing unit does not include a non-powered processing unit, the first processing unit is specifically configured to: detect load information of each processing unit in the at least one processing unit; If the detection result indicates that the load information of each processing unit is greater than or equal to a load threshold, the first processing unit is specifically configured to: determine the first processing unit as a target processing unit for the first job.

11. The device according to claim 10, characterized in that If the detection result indicates that the at least one processing unit includes a processing unit whose load information is less than the load threshold, the first processing unit is specifically used to: determine the target processing unit of the first job based on the processing unit whose load information is less than the load threshold.

12. The device according to any one of claims 7 to 11, characterized in that The apparatus further includes a third processing unit configured to: determine the first processing unit based on the first information or the second information; The first information is used to indicate: a processing unit identifier carried in a user instruction; The second information is used to indicate a capability value of the processing unit, and the capability value of the processing unit is used to reflect a processing capability of the processing unit for processing a job.

13. A processor, characterized in that: The processor includes a plurality of processing modules, and the processor uses the plurality of processing modules to schedule and execute the method according to any one of claims 1 to 6.

14. A chip, characterized in that: The chip includes an interface circuit and a control circuit; the interface circuit is used to obtain services to be processed and schedule with the control circuit to execute the method according to any one of claims 1 to 6.

15. A computing device, characterized in that The method comprises a memory and a processor, wherein the memory stores a program code, and when the processor executes the program code, the processor is configured to execute the method according to any one of claims 1 to 6.

16. A computer-readable storage medium, characterized in that The computer-readable storage medium includes computer instructions; when the computer instructions are executed in a computing device, the computing device executes the method according to any one of claims 1 to 6.

17. A computer program product, characterized in that When the computer program product is run in a computing device, the computing device performs the method according to any one of claims 1 to 6.

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